1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Freescale eSDHC controller driver. 4 * 5 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. 6 * Copyright (c) 2009 MontaVista Software, Inc. 7 * 8 * Authors: Xiaobo Xie <X.Xie@freescale.com> 9 * Anton Vorontsov <avorontsov@ru.mvista.com> 10 */ 11 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/delay.h> 17 #include <linux/module.h> 18 #include <linux/sys_soc.h> 19 #include <linux/clk.h> 20 #include <linux/ktime.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include "sdhci-pltfm.h" 25 #include "sdhci-esdhc.h" 26 27 #define VENDOR_V_22 0x12 28 #define VENDOR_V_23 0x13 29 30 #define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1) 31 32 struct esdhc_clk_fixup { 33 const unsigned int sd_dflt_max_clk; 34 const unsigned int max_clk[MMC_TIMING_NUM]; 35 }; 36 37 static const struct esdhc_clk_fixup ls1021a_esdhc_clk = { 38 .sd_dflt_max_clk = 25000000, 39 .max_clk[MMC_TIMING_MMC_HS] = 46500000, 40 .max_clk[MMC_TIMING_SD_HS] = 46500000, 41 }; 42 43 static const struct esdhc_clk_fixup ls1046a_esdhc_clk = { 44 .sd_dflt_max_clk = 25000000, 45 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000, 46 .max_clk[MMC_TIMING_MMC_HS200] = 167000000, 47 }; 48 49 static const struct esdhc_clk_fixup ls1012a_esdhc_clk = { 50 .sd_dflt_max_clk = 25000000, 51 .max_clk[MMC_TIMING_UHS_SDR104] = 125000000, 52 .max_clk[MMC_TIMING_MMC_HS200] = 125000000, 53 }; 54 55 static const struct esdhc_clk_fixup p1010_esdhc_clk = { 56 .sd_dflt_max_clk = 20000000, 57 .max_clk[MMC_TIMING_LEGACY] = 20000000, 58 .max_clk[MMC_TIMING_MMC_HS] = 42000000, 59 .max_clk[MMC_TIMING_SD_HS] = 40000000, 60 }; 61 62 static const struct of_device_id sdhci_esdhc_of_match[] = { 63 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk}, 64 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk}, 65 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk}, 66 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk}, 67 { .compatible = "fsl,mpc8379-esdhc" }, 68 { .compatible = "fsl,mpc8536-esdhc" }, 69 { .compatible = "fsl,esdhc" }, 70 { } 71 }; 72 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); 73 74 struct sdhci_esdhc { 75 u8 vendor_ver; 76 u8 spec_ver; 77 bool quirk_incorrect_hostver; 78 bool quirk_limited_clk_division; 79 bool quirk_unreliable_pulse_detection; 80 bool quirk_tuning_erratum_type1; 81 bool quirk_tuning_erratum_type2; 82 bool quirk_ignore_data_inhibit; 83 bool quirk_delay_before_data_reset; 84 bool quirk_trans_complete_erratum; 85 bool in_sw_tuning; 86 unsigned int peripheral_clock; 87 const struct esdhc_clk_fixup *clk_fixup; 88 u32 div_ratio; 89 }; 90 91 /** 92 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register 93 * to make it compatible with SD spec. 94 * 95 * @host: pointer to sdhci_host 96 * @spec_reg: SD spec register address 97 * @value: 32bit eSDHC register value on spec_reg address 98 * 99 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 100 * registers are 32 bits. There are differences in register size, register 101 * address, register function, bit position and function between eSDHC spec 102 * and SD spec. 103 * 104 * Return a fixed up register value 105 */ 106 static u32 esdhc_readl_fixup(struct sdhci_host *host, 107 int spec_reg, u32 value) 108 { 109 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 110 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 111 u32 ret; 112 113 /* 114 * The bit of ADMA flag in eSDHC is not compatible with standard 115 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is 116 * supported by eSDHC. 117 * And for many FSL eSDHC controller, the reset value of field 118 * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA, 119 * only these vendor version is greater than 2.2/0x12 support ADMA. 120 */ 121 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) { 122 if (esdhc->vendor_ver > VENDOR_V_22) { 123 ret = value | SDHCI_CAN_DO_ADMA2; 124 return ret; 125 } 126 } 127 /* 128 * The DAT[3:0] line signal levels and the CMD line signal level are 129 * not compatible with standard SDHC register. The line signal levels 130 * DAT[7:0] are at bits 31:24 and the command line signal level is at 131 * bit 23. All other bits are the same as in the standard SDHC 132 * register. 133 */ 134 if (spec_reg == SDHCI_PRESENT_STATE) { 135 ret = value & 0x000fffff; 136 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK; 137 ret |= (value << 1) & SDHCI_CMD_LVL; 138 return ret; 139 } 140 141 /* 142 * DTS properties of mmc host are used to enable each speed mode 143 * according to soc and board capability. So clean up 144 * SDR50/SDR104/DDR50 support bits here. 145 */ 146 if (spec_reg == SDHCI_CAPABILITIES_1) { 147 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 148 SDHCI_SUPPORT_DDR50); 149 return ret; 150 } 151 152 /* 153 * Some controllers have unreliable Data Line Active 154 * bit for commands with busy signal. This affects 155 * Command Inhibit (data) bit. Just ignore it since 156 * MMC core driver has already polled card status 157 * with CMD13 after any command with busy siganl. 158 */ 159 if ((spec_reg == SDHCI_PRESENT_STATE) && 160 (esdhc->quirk_ignore_data_inhibit == true)) { 161 ret = value & ~SDHCI_DATA_INHIBIT; 162 return ret; 163 } 164 165 ret = value; 166 return ret; 167 } 168 169 static u16 esdhc_readw_fixup(struct sdhci_host *host, 170 int spec_reg, u32 value) 171 { 172 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 173 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 174 u16 ret; 175 int shift = (spec_reg & 0x2) * 8; 176 177 if (spec_reg == SDHCI_TRANSFER_MODE) 178 return pltfm_host->xfer_mode_shadow; 179 180 if (spec_reg == SDHCI_HOST_VERSION) 181 ret = value & 0xffff; 182 else 183 ret = (value >> shift) & 0xffff; 184 /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect 185 * vendor version and spec version information. 186 */ 187 if ((spec_reg == SDHCI_HOST_VERSION) && 188 (esdhc->quirk_incorrect_hostver)) 189 ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200; 190 return ret; 191 } 192 193 static u8 esdhc_readb_fixup(struct sdhci_host *host, 194 int spec_reg, u32 value) 195 { 196 u8 ret; 197 u8 dma_bits; 198 int shift = (spec_reg & 0x3) * 8; 199 200 ret = (value >> shift) & 0xff; 201 202 /* 203 * "DMA select" locates at offset 0x28 in SD specification, but on 204 * P5020 or P3041, it locates at 0x29. 205 */ 206 if (spec_reg == SDHCI_HOST_CONTROL) { 207 /* DMA select is 22,23 bits in Protocol Control Register */ 208 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK; 209 /* fixup the result */ 210 ret &= ~SDHCI_CTRL_DMA_MASK; 211 ret |= dma_bits; 212 } 213 return ret; 214 } 215 216 /** 217 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be 218 * written into eSDHC register. 219 * 220 * @host: pointer to sdhci_host 221 * @spec_reg: SD spec register address 222 * @value: 8/16/32bit SD spec register value that would be written 223 * @old_value: 32bit eSDHC register value on spec_reg address 224 * 225 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 226 * registers are 32 bits. There are differences in register size, register 227 * address, register function, bit position and function between eSDHC spec 228 * and SD spec. 229 * 230 * Return a fixed up register value 231 */ 232 static u32 esdhc_writel_fixup(struct sdhci_host *host, 233 int spec_reg, u32 value, u32 old_value) 234 { 235 u32 ret; 236 237 /* 238 * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE] 239 * when SYSCTL[RSTD] is set for some special operations. 240 * No any impact on other operation. 241 */ 242 if (spec_reg == SDHCI_INT_ENABLE) 243 ret = value | SDHCI_INT_BLK_GAP; 244 else 245 ret = value; 246 247 return ret; 248 } 249 250 static u32 esdhc_writew_fixup(struct sdhci_host *host, 251 int spec_reg, u16 value, u32 old_value) 252 { 253 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 254 int shift = (spec_reg & 0x2) * 8; 255 u32 ret; 256 257 switch (spec_reg) { 258 case SDHCI_TRANSFER_MODE: 259 /* 260 * Postpone this write, we must do it together with a 261 * command write that is down below. Return old value. 262 */ 263 pltfm_host->xfer_mode_shadow = value; 264 return old_value; 265 case SDHCI_COMMAND: 266 ret = (value << 16) | pltfm_host->xfer_mode_shadow; 267 return ret; 268 } 269 270 ret = old_value & (~(0xffff << shift)); 271 ret |= (value << shift); 272 273 if (spec_reg == SDHCI_BLOCK_SIZE) { 274 /* 275 * Two last DMA bits are reserved, and first one is used for 276 * non-standard blksz of 4096 bytes that we don't support 277 * yet. So clear the DMA boundary bits. 278 */ 279 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0)); 280 } 281 return ret; 282 } 283 284 static u32 esdhc_writeb_fixup(struct sdhci_host *host, 285 int spec_reg, u8 value, u32 old_value) 286 { 287 u32 ret; 288 u32 dma_bits; 289 u8 tmp; 290 int shift = (spec_reg & 0x3) * 8; 291 292 /* 293 * eSDHC doesn't have a standard power control register, so we do 294 * nothing here to avoid incorrect operation. 295 */ 296 if (spec_reg == SDHCI_POWER_CONTROL) 297 return old_value; 298 /* 299 * "DMA select" location is offset 0x28 in SD specification, but on 300 * P5020 or P3041, it's located at 0x29. 301 */ 302 if (spec_reg == SDHCI_HOST_CONTROL) { 303 /* 304 * If host control register is not standard, exit 305 * this function 306 */ 307 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL) 308 return old_value; 309 310 /* DMA select is 22,23 bits in Protocol Control Register */ 311 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5; 312 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits; 313 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) | 314 (old_value & SDHCI_CTRL_DMA_MASK); 315 ret = (ret & (~0xff)) | tmp; 316 317 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */ 318 ret &= ~ESDHC_HOST_CONTROL_RES; 319 return ret; 320 } 321 322 ret = (old_value & (~(0xff << shift))) | (value << shift); 323 return ret; 324 } 325 326 static u32 esdhc_be_readl(struct sdhci_host *host, int reg) 327 { 328 u32 ret; 329 u32 value; 330 331 if (reg == SDHCI_CAPABILITIES_1) 332 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1); 333 else 334 value = ioread32be(host->ioaddr + reg); 335 336 ret = esdhc_readl_fixup(host, reg, value); 337 338 return ret; 339 } 340 341 static u32 esdhc_le_readl(struct sdhci_host *host, int reg) 342 { 343 u32 ret; 344 u32 value; 345 346 if (reg == SDHCI_CAPABILITIES_1) 347 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1); 348 else 349 value = ioread32(host->ioaddr + reg); 350 351 ret = esdhc_readl_fixup(host, reg, value); 352 353 return ret; 354 } 355 356 static u16 esdhc_be_readw(struct sdhci_host *host, int reg) 357 { 358 u16 ret; 359 u32 value; 360 int base = reg & ~0x3; 361 362 value = ioread32be(host->ioaddr + base); 363 ret = esdhc_readw_fixup(host, reg, value); 364 return ret; 365 } 366 367 static u16 esdhc_le_readw(struct sdhci_host *host, int reg) 368 { 369 u16 ret; 370 u32 value; 371 int base = reg & ~0x3; 372 373 value = ioread32(host->ioaddr + base); 374 ret = esdhc_readw_fixup(host, reg, value); 375 return ret; 376 } 377 378 static u8 esdhc_be_readb(struct sdhci_host *host, int reg) 379 { 380 u8 ret; 381 u32 value; 382 int base = reg & ~0x3; 383 384 value = ioread32be(host->ioaddr + base); 385 ret = esdhc_readb_fixup(host, reg, value); 386 return ret; 387 } 388 389 static u8 esdhc_le_readb(struct sdhci_host *host, int reg) 390 { 391 u8 ret; 392 u32 value; 393 int base = reg & ~0x3; 394 395 value = ioread32(host->ioaddr + base); 396 ret = esdhc_readb_fixup(host, reg, value); 397 return ret; 398 } 399 400 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) 401 { 402 u32 value; 403 404 value = esdhc_writel_fixup(host, reg, val, 0); 405 iowrite32be(value, host->ioaddr + reg); 406 } 407 408 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) 409 { 410 u32 value; 411 412 value = esdhc_writel_fixup(host, reg, val, 0); 413 iowrite32(value, host->ioaddr + reg); 414 } 415 416 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) 417 { 418 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 419 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 420 int base = reg & ~0x3; 421 u32 value; 422 u32 ret; 423 424 value = ioread32be(host->ioaddr + base); 425 ret = esdhc_writew_fixup(host, reg, val, value); 426 if (reg != SDHCI_TRANSFER_MODE) 427 iowrite32be(ret, host->ioaddr + base); 428 429 /* Starting SW tuning requires ESDHC_SMPCLKSEL to be set 430 * 1us later after ESDHC_EXTN is set. 431 */ 432 if (base == ESDHC_SYSTEM_CONTROL_2) { 433 if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) && 434 esdhc->in_sw_tuning) { 435 udelay(1); 436 ret |= ESDHC_SMPCLKSEL; 437 iowrite32be(ret, host->ioaddr + base); 438 } 439 } 440 } 441 442 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) 443 { 444 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 445 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 446 int base = reg & ~0x3; 447 u32 value; 448 u32 ret; 449 450 value = ioread32(host->ioaddr + base); 451 ret = esdhc_writew_fixup(host, reg, val, value); 452 if (reg != SDHCI_TRANSFER_MODE) 453 iowrite32(ret, host->ioaddr + base); 454 455 /* Starting SW tuning requires ESDHC_SMPCLKSEL to be set 456 * 1us later after ESDHC_EXTN is set. 457 */ 458 if (base == ESDHC_SYSTEM_CONTROL_2) { 459 if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) && 460 esdhc->in_sw_tuning) { 461 udelay(1); 462 ret |= ESDHC_SMPCLKSEL; 463 iowrite32(ret, host->ioaddr + base); 464 } 465 } 466 } 467 468 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) 469 { 470 int base = reg & ~0x3; 471 u32 value; 472 u32 ret; 473 474 value = ioread32be(host->ioaddr + base); 475 ret = esdhc_writeb_fixup(host, reg, val, value); 476 iowrite32be(ret, host->ioaddr + base); 477 } 478 479 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) 480 { 481 int base = reg & ~0x3; 482 u32 value; 483 u32 ret; 484 485 value = ioread32(host->ioaddr + base); 486 ret = esdhc_writeb_fixup(host, reg, val, value); 487 iowrite32(ret, host->ioaddr + base); 488 } 489 490 /* 491 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA 492 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC]) 493 * and Block Gap Event(IRQSTAT[BGE]) are also set. 494 * For Continue, apply soft reset for data(SYSCTL[RSTD]); 495 * and re-issue the entire read transaction from beginning. 496 */ 497 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask) 498 { 499 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 500 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 501 bool applicable; 502 dma_addr_t dmastart; 503 dma_addr_t dmanow; 504 505 applicable = (intmask & SDHCI_INT_DATA_END) && 506 (intmask & SDHCI_INT_BLK_GAP) && 507 (esdhc->vendor_ver == VENDOR_V_23); 508 if (!applicable) 509 return; 510 511 host->data->error = 0; 512 dmastart = sg_dma_address(host->data->sg); 513 dmanow = dmastart + host->data->bytes_xfered; 514 /* 515 * Force update to the next DMA block boundary. 516 */ 517 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 518 SDHCI_DEFAULT_BOUNDARY_SIZE; 519 host->data->bytes_xfered = dmanow - dmastart; 520 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 521 } 522 523 static int esdhc_of_enable_dma(struct sdhci_host *host) 524 { 525 u32 value; 526 struct device *dev = mmc_dev(host->mmc); 527 528 if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") || 529 of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) 530 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); 531 532 value = sdhci_readl(host, ESDHC_DMA_SYSCTL); 533 534 if (of_dma_is_coherent(dev->of_node)) 535 value |= ESDHC_DMA_SNOOP; 536 else 537 value &= ~ESDHC_DMA_SNOOP; 538 539 sdhci_writel(host, value, ESDHC_DMA_SYSCTL); 540 return 0; 541 } 542 543 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) 544 { 545 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 546 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 547 548 if (esdhc->peripheral_clock) 549 return esdhc->peripheral_clock; 550 else 551 return pltfm_host->clock; 552 } 553 554 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) 555 { 556 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 557 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 558 unsigned int clock; 559 560 if (esdhc->peripheral_clock) 561 clock = esdhc->peripheral_clock; 562 else 563 clock = pltfm_host->clock; 564 return clock / 256 / 16; 565 } 566 567 static void esdhc_clock_enable(struct sdhci_host *host, bool enable) 568 { 569 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 570 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 571 ktime_t timeout; 572 u32 val, clk_en; 573 574 clk_en = ESDHC_CLOCK_SDCLKEN; 575 576 /* 577 * IPGEN/HCKEN/PEREN bits exist on eSDHC whose vendor version 578 * is 2.2 or lower. 579 */ 580 if (esdhc->vendor_ver <= VENDOR_V_22) 581 clk_en |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | 582 ESDHC_CLOCK_PEREN); 583 584 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 585 586 if (enable) 587 val |= clk_en; 588 else 589 val &= ~clk_en; 590 591 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL); 592 593 /* 594 * Wait max 20 ms. If vendor version is 2.2 or lower, do not 595 * wait clock stable bit which does not exist. 596 */ 597 timeout = ktime_add_ms(ktime_get(), 20); 598 while (esdhc->vendor_ver > VENDOR_V_22) { 599 bool timedout = ktime_after(ktime_get(), timeout); 600 601 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE) 602 break; 603 if (timedout) { 604 pr_err("%s: Internal clock never stabilised.\n", 605 mmc_hostname(host->mmc)); 606 break; 607 } 608 usleep_range(10, 20); 609 } 610 } 611 612 static void esdhc_flush_async_fifo(struct sdhci_host *host) 613 { 614 ktime_t timeout; 615 u32 val; 616 617 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 618 val |= ESDHC_FLUSH_ASYNC_FIFO; 619 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 620 621 /* Wait max 20 ms */ 622 timeout = ktime_add_ms(ktime_get(), 20); 623 while (1) { 624 bool timedout = ktime_after(ktime_get(), timeout); 625 626 if (!(sdhci_readl(host, ESDHC_DMA_SYSCTL) & 627 ESDHC_FLUSH_ASYNC_FIFO)) 628 break; 629 if (timedout) { 630 pr_err("%s: flushing asynchronous FIFO timeout.\n", 631 mmc_hostname(host->mmc)); 632 break; 633 } 634 usleep_range(10, 20); 635 } 636 } 637 638 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) 639 { 640 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 641 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 642 unsigned int pre_div = 1, div = 1; 643 unsigned int clock_fixup = 0; 644 ktime_t timeout; 645 u32 temp; 646 647 if (clock == 0) { 648 host->mmc->actual_clock = 0; 649 esdhc_clock_enable(host, false); 650 return; 651 } 652 653 /* Start pre_div at 2 for vendor version < 2.3. */ 654 if (esdhc->vendor_ver < VENDOR_V_23) 655 pre_div = 2; 656 657 /* Fix clock value. */ 658 if (host->mmc->card && mmc_card_sd(host->mmc->card) && 659 esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY) 660 clock_fixup = esdhc->clk_fixup->sd_dflt_max_clk; 661 else if (esdhc->clk_fixup) 662 clock_fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing]; 663 664 if (clock_fixup == 0 || clock < clock_fixup) 665 clock_fixup = clock; 666 667 /* Calculate pre_div and div. */ 668 while (host->max_clk / pre_div / 16 > clock_fixup && pre_div < 256) 669 pre_div *= 2; 670 671 while (host->max_clk / pre_div / div > clock_fixup && div < 16) 672 div++; 673 674 esdhc->div_ratio = pre_div * div; 675 676 /* Limit clock division for HS400 200MHz clock for quirk. */ 677 if (esdhc->quirk_limited_clk_division && 678 clock == MMC_HS200_MAX_DTR && 679 (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 || 680 host->flags & SDHCI_HS400_TUNING)) { 681 if (esdhc->div_ratio <= 4) { 682 pre_div = 4; 683 div = 1; 684 } else if (esdhc->div_ratio <= 8) { 685 pre_div = 4; 686 div = 2; 687 } else if (esdhc->div_ratio <= 12) { 688 pre_div = 4; 689 div = 3; 690 } else { 691 pr_warn("%s: using unsupported clock division.\n", 692 mmc_hostname(host->mmc)); 693 } 694 esdhc->div_ratio = pre_div * div; 695 } 696 697 host->mmc->actual_clock = host->max_clk / esdhc->div_ratio; 698 699 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 700 clock, host->mmc->actual_clock); 701 702 /* Set clock division into register. */ 703 pre_div >>= 1; 704 div--; 705 706 esdhc_clock_enable(host, false); 707 708 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 709 temp &= ~ESDHC_CLOCK_MASK; 710 temp |= ((div << ESDHC_DIVIDER_SHIFT) | 711 (pre_div << ESDHC_PREDIV_SHIFT)); 712 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 713 714 /* 715 * Wait max 20 ms. If vendor version is 2.2 or lower, do not 716 * wait clock stable bit which does not exist. 717 */ 718 timeout = ktime_add_ms(ktime_get(), 20); 719 while (esdhc->vendor_ver > VENDOR_V_22) { 720 bool timedout = ktime_after(ktime_get(), timeout); 721 722 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE) 723 break; 724 if (timedout) { 725 pr_err("%s: Internal clock never stabilised.\n", 726 mmc_hostname(host->mmc)); 727 break; 728 } 729 usleep_range(10, 20); 730 } 731 732 /* Additional setting for HS400. */ 733 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && 734 clock == MMC_HS200_MAX_DTR) { 735 temp = sdhci_readl(host, ESDHC_TBCTL); 736 sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL); 737 temp = sdhci_readl(host, ESDHC_SDCLKCTL); 738 sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL); 739 esdhc_clock_enable(host, true); 740 741 temp = sdhci_readl(host, ESDHC_DLLCFG0); 742 temp |= ESDHC_DLL_ENABLE; 743 if (host->mmc->actual_clock == MMC_HS200_MAX_DTR) 744 temp |= ESDHC_DLL_FREQ_SEL; 745 sdhci_writel(host, temp, ESDHC_DLLCFG0); 746 temp = sdhci_readl(host, ESDHC_TBCTL); 747 sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL); 748 749 esdhc_clock_enable(host, false); 750 esdhc_flush_async_fifo(host); 751 } 752 esdhc_clock_enable(host, true); 753 } 754 755 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 756 { 757 u32 ctrl; 758 759 ctrl = sdhci_readl(host, ESDHC_PROCTL); 760 ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK); 761 switch (width) { 762 case MMC_BUS_WIDTH_8: 763 ctrl |= ESDHC_CTRL_8BITBUS; 764 break; 765 766 case MMC_BUS_WIDTH_4: 767 ctrl |= ESDHC_CTRL_4BITBUS; 768 break; 769 770 default: 771 break; 772 } 773 774 sdhci_writel(host, ctrl, ESDHC_PROCTL); 775 } 776 777 static void esdhc_reset(struct sdhci_host *host, u8 mask) 778 { 779 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 780 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 781 u32 val, bus_width = 0; 782 783 /* 784 * Add delay to make sure all the DMA transfers are finished 785 * for quirk. 786 */ 787 if (esdhc->quirk_delay_before_data_reset && 788 (mask & SDHCI_RESET_DATA) && 789 (host->flags & SDHCI_REQ_USE_DMA)) 790 mdelay(5); 791 792 /* 793 * Save bus-width for eSDHC whose vendor version is 2.2 794 * or lower for data reset. 795 */ 796 if ((mask & SDHCI_RESET_DATA) && 797 (esdhc->vendor_ver <= VENDOR_V_22)) { 798 val = sdhci_readl(host, ESDHC_PROCTL); 799 bus_width = val & ESDHC_CTRL_BUSWIDTH_MASK; 800 } 801 802 sdhci_reset(host, mask); 803 804 /* 805 * Restore bus-width setting and interrupt registers for eSDHC 806 * whose vendor version is 2.2 or lower for data reset. 807 */ 808 if ((mask & SDHCI_RESET_DATA) && 809 (esdhc->vendor_ver <= VENDOR_V_22)) { 810 val = sdhci_readl(host, ESDHC_PROCTL); 811 val &= ~ESDHC_CTRL_BUSWIDTH_MASK; 812 val |= bus_width; 813 sdhci_writel(host, val, ESDHC_PROCTL); 814 815 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 816 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 817 } 818 819 /* 820 * Some bits have to be cleaned manually for eSDHC whose spec 821 * version is higher than 3.0 for all reset. 822 */ 823 if ((mask & SDHCI_RESET_ALL) && 824 (esdhc->spec_ver >= SDHCI_SPEC_300)) { 825 val = sdhci_readl(host, ESDHC_TBCTL); 826 val &= ~ESDHC_TB_EN; 827 sdhci_writel(host, val, ESDHC_TBCTL); 828 829 /* 830 * Initialize eSDHC_DLLCFG1[DLL_PD_PULSE_STRETCH_SEL] to 831 * 0 for quirk. 832 */ 833 if (esdhc->quirk_unreliable_pulse_detection) { 834 val = sdhci_readl(host, ESDHC_DLLCFG1); 835 val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL; 836 sdhci_writel(host, val, ESDHC_DLLCFG1); 837 } 838 } 839 } 840 841 /* The SCFG, Supplemental Configuration Unit, provides SoC specific 842 * configuration and status registers for the device. There is a 843 * SDHC IO VSEL control register on SCFG for some platforms. It's 844 * used to support SDHC IO voltage switching. 845 */ 846 static const struct of_device_id scfg_device_ids[] = { 847 { .compatible = "fsl,t1040-scfg", }, 848 { .compatible = "fsl,ls1012a-scfg", }, 849 { .compatible = "fsl,ls1046a-scfg", }, 850 {} 851 }; 852 853 /* SDHC IO VSEL control register definition */ 854 #define SCFG_SDHCIOVSELCR 0x408 855 #define SDHCIOVSELCR_TGLEN 0x80000000 856 #define SDHCIOVSELCR_VSELVAL 0x60000000 857 #define SDHCIOVSELCR_SDHC_VS 0x00000001 858 859 static int esdhc_signal_voltage_switch(struct mmc_host *mmc, 860 struct mmc_ios *ios) 861 { 862 struct sdhci_host *host = mmc_priv(mmc); 863 struct device_node *scfg_node; 864 void __iomem *scfg_base = NULL; 865 u32 sdhciovselcr; 866 u32 val; 867 868 /* 869 * Signal Voltage Switching is only applicable for Host Controllers 870 * v3.00 and above. 871 */ 872 if (host->version < SDHCI_SPEC_300) 873 return 0; 874 875 val = sdhci_readl(host, ESDHC_PROCTL); 876 877 switch (ios->signal_voltage) { 878 case MMC_SIGNAL_VOLTAGE_330: 879 val &= ~ESDHC_VOLT_SEL; 880 sdhci_writel(host, val, ESDHC_PROCTL); 881 return 0; 882 case MMC_SIGNAL_VOLTAGE_180: 883 scfg_node = of_find_matching_node(NULL, scfg_device_ids); 884 if (scfg_node) 885 scfg_base = of_iomap(scfg_node, 0); 886 if (scfg_base) { 887 sdhciovselcr = SDHCIOVSELCR_TGLEN | 888 SDHCIOVSELCR_VSELVAL; 889 iowrite32be(sdhciovselcr, 890 scfg_base + SCFG_SDHCIOVSELCR); 891 892 val |= ESDHC_VOLT_SEL; 893 sdhci_writel(host, val, ESDHC_PROCTL); 894 mdelay(5); 895 896 sdhciovselcr = SDHCIOVSELCR_TGLEN | 897 SDHCIOVSELCR_SDHC_VS; 898 iowrite32be(sdhciovselcr, 899 scfg_base + SCFG_SDHCIOVSELCR); 900 iounmap(scfg_base); 901 } else { 902 val |= ESDHC_VOLT_SEL; 903 sdhci_writel(host, val, ESDHC_PROCTL); 904 } 905 return 0; 906 default: 907 return 0; 908 } 909 } 910 911 static struct soc_device_attribute soc_tuning_erratum_type1[] = { 912 { .family = "QorIQ T1023", }, 913 { .family = "QorIQ T1040", }, 914 { .family = "QorIQ T2080", }, 915 { .family = "QorIQ LS1021A", }, 916 { }, 917 }; 918 919 static struct soc_device_attribute soc_tuning_erratum_type2[] = { 920 { .family = "QorIQ LS1012A", }, 921 { .family = "QorIQ LS1043A", }, 922 { .family = "QorIQ LS1046A", }, 923 { .family = "QorIQ LS1080A", }, 924 { .family = "QorIQ LS2080A", }, 925 { .family = "QorIQ LA1575A", }, 926 { }, 927 }; 928 929 static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable) 930 { 931 u32 val; 932 933 esdhc_clock_enable(host, false); 934 esdhc_flush_async_fifo(host); 935 936 val = sdhci_readl(host, ESDHC_TBCTL); 937 if (enable) 938 val |= ESDHC_TB_EN; 939 else 940 val &= ~ESDHC_TB_EN; 941 sdhci_writel(host, val, ESDHC_TBCTL); 942 943 esdhc_clock_enable(host, true); 944 } 945 946 static void esdhc_tuning_window_ptr(struct sdhci_host *host, u8 *window_start, 947 u8 *window_end) 948 { 949 u32 val; 950 951 /* Write TBCTL[11:8]=4'h8 */ 952 val = sdhci_readl(host, ESDHC_TBCTL); 953 val &= ~(0xf << 8); 954 val |= 8 << 8; 955 sdhci_writel(host, val, ESDHC_TBCTL); 956 957 mdelay(1); 958 959 /* Read TBCTL[31:0] register and rewrite again */ 960 val = sdhci_readl(host, ESDHC_TBCTL); 961 sdhci_writel(host, val, ESDHC_TBCTL); 962 963 mdelay(1); 964 965 /* Read the TBSTAT[31:0] register twice */ 966 val = sdhci_readl(host, ESDHC_TBSTAT); 967 val = sdhci_readl(host, ESDHC_TBSTAT); 968 969 *window_end = val & 0xff; 970 *window_start = (val >> 8) & 0xff; 971 } 972 973 static void esdhc_prepare_sw_tuning(struct sdhci_host *host, u8 *window_start, 974 u8 *window_end) 975 { 976 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 977 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 978 u8 start_ptr, end_ptr; 979 980 if (esdhc->quirk_tuning_erratum_type1) { 981 *window_start = 5 * esdhc->div_ratio; 982 *window_end = 3 * esdhc->div_ratio; 983 return; 984 } 985 986 esdhc_tuning_window_ptr(host, &start_ptr, &end_ptr); 987 988 /* Reset data lines by setting ESDHCCTL[RSTD] */ 989 sdhci_reset(host, SDHCI_RESET_DATA); 990 /* Write 32'hFFFF_FFFF to IRQSTAT register */ 991 sdhci_writel(host, 0xFFFFFFFF, SDHCI_INT_STATUS); 992 993 /* If TBSTAT[15:8]-TBSTAT[7:0] > (4 * div_ratio) + 2 994 * or TBSTAT[7:0]-TBSTAT[15:8] > (4 * div_ratio) + 2, 995 * then program TBPTR[TB_WNDW_END_PTR] = 4 * div_ratio 996 * and program TBPTR[TB_WNDW_START_PTR] = 8 * div_ratio. 997 */ 998 999 if (abs(start_ptr - end_ptr) > (4 * esdhc->div_ratio + 2)) { 1000 *window_start = 8 * esdhc->div_ratio; 1001 *window_end = 4 * esdhc->div_ratio; 1002 } else { 1003 *window_start = 5 * esdhc->div_ratio; 1004 *window_end = 3 * esdhc->div_ratio; 1005 } 1006 } 1007 1008 static int esdhc_execute_sw_tuning(struct mmc_host *mmc, u32 opcode, 1009 u8 window_start, u8 window_end) 1010 { 1011 struct sdhci_host *host = mmc_priv(mmc); 1012 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1013 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 1014 u32 val; 1015 int ret; 1016 1017 /* Program TBPTR[TB_WNDW_END_PTR] and TBPTR[TB_WNDW_START_PTR] */ 1018 val = ((u32)window_start << ESDHC_WNDW_STRT_PTR_SHIFT) & 1019 ESDHC_WNDW_STRT_PTR_MASK; 1020 val |= window_end & ESDHC_WNDW_END_PTR_MASK; 1021 sdhci_writel(host, val, ESDHC_TBPTR); 1022 1023 /* Program the software tuning mode by setting TBCTL[TB_MODE]=2'h3 */ 1024 val = sdhci_readl(host, ESDHC_TBCTL); 1025 val &= ~ESDHC_TB_MODE_MASK; 1026 val |= ESDHC_TB_MODE_SW; 1027 sdhci_writel(host, val, ESDHC_TBCTL); 1028 1029 esdhc->in_sw_tuning = true; 1030 ret = sdhci_execute_tuning(mmc, opcode); 1031 esdhc->in_sw_tuning = false; 1032 return ret; 1033 } 1034 1035 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1036 { 1037 struct sdhci_host *host = mmc_priv(mmc); 1038 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1039 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 1040 u8 window_start, window_end; 1041 int ret, retries = 1; 1042 bool hs400_tuning; 1043 unsigned int clk; 1044 u32 val; 1045 1046 /* For tuning mode, the sd clock divisor value 1047 * must be larger than 3 according to reference manual. 1048 */ 1049 clk = esdhc->peripheral_clock / 3; 1050 if (host->clock > clk) 1051 esdhc_of_set_clock(host, clk); 1052 1053 esdhc_tuning_block_enable(host, true); 1054 1055 hs400_tuning = host->flags & SDHCI_HS400_TUNING; 1056 1057 do { 1058 if (esdhc->quirk_limited_clk_division && 1059 hs400_tuning) 1060 esdhc_of_set_clock(host, host->clock); 1061 1062 /* Do HW tuning */ 1063 val = sdhci_readl(host, ESDHC_TBCTL); 1064 val &= ~ESDHC_TB_MODE_MASK; 1065 val |= ESDHC_TB_MODE_3; 1066 sdhci_writel(host, val, ESDHC_TBCTL); 1067 1068 ret = sdhci_execute_tuning(mmc, opcode); 1069 if (ret) 1070 break; 1071 1072 /* For type2 affected platforms of the tuning erratum, 1073 * tuning may succeed although eSDHC might not have 1074 * tuned properly. Need to check tuning window. 1075 */ 1076 if (esdhc->quirk_tuning_erratum_type2 && 1077 !host->tuning_err) { 1078 esdhc_tuning_window_ptr(host, &window_start, 1079 &window_end); 1080 if (abs(window_start - window_end) > 1081 (4 * esdhc->div_ratio + 2)) 1082 host->tuning_err = -EAGAIN; 1083 } 1084 1085 /* If HW tuning fails and triggers erratum, 1086 * try workaround. 1087 */ 1088 ret = host->tuning_err; 1089 if (ret == -EAGAIN && 1090 (esdhc->quirk_tuning_erratum_type1 || 1091 esdhc->quirk_tuning_erratum_type2)) { 1092 /* Recover HS400 tuning flag */ 1093 if (hs400_tuning) 1094 host->flags |= SDHCI_HS400_TUNING; 1095 pr_info("%s: Hold on to use fixed sampling clock. Try SW tuning!\n", 1096 mmc_hostname(mmc)); 1097 /* Do SW tuning */ 1098 esdhc_prepare_sw_tuning(host, &window_start, 1099 &window_end); 1100 ret = esdhc_execute_sw_tuning(mmc, opcode, 1101 window_start, 1102 window_end); 1103 if (ret) 1104 break; 1105 1106 /* Retry both HW/SW tuning with reduced clock. */ 1107 ret = host->tuning_err; 1108 if (ret == -EAGAIN && retries) { 1109 /* Recover HS400 tuning flag */ 1110 if (hs400_tuning) 1111 host->flags |= SDHCI_HS400_TUNING; 1112 1113 clk = host->max_clk / (esdhc->div_ratio + 1); 1114 esdhc_of_set_clock(host, clk); 1115 pr_info("%s: Hold on to use fixed sampling clock. Try tuning with reduced clock!\n", 1116 mmc_hostname(mmc)); 1117 } else { 1118 break; 1119 } 1120 } else { 1121 break; 1122 } 1123 } while (retries--); 1124 1125 if (ret) { 1126 esdhc_tuning_block_enable(host, false); 1127 } else if (hs400_tuning) { 1128 val = sdhci_readl(host, ESDHC_SDTIMNGCTL); 1129 val |= ESDHC_FLW_CTL_BG; 1130 sdhci_writel(host, val, ESDHC_SDTIMNGCTL); 1131 } 1132 1133 return ret; 1134 } 1135 1136 static void esdhc_set_uhs_signaling(struct sdhci_host *host, 1137 unsigned int timing) 1138 { 1139 u32 val; 1140 1141 /* 1142 * There are specific registers setting for HS400 mode. 1143 * Clean all of them if controller is in HS400 mode to 1144 * exit HS400 mode before re-setting any speed mode. 1145 */ 1146 val = sdhci_readl(host, ESDHC_TBCTL); 1147 if (val & ESDHC_HS400_MODE) { 1148 val = sdhci_readl(host, ESDHC_SDTIMNGCTL); 1149 val &= ~ESDHC_FLW_CTL_BG; 1150 sdhci_writel(host, val, ESDHC_SDTIMNGCTL); 1151 1152 val = sdhci_readl(host, ESDHC_SDCLKCTL); 1153 val &= ~ESDHC_CMD_CLK_CTL; 1154 sdhci_writel(host, val, ESDHC_SDCLKCTL); 1155 1156 esdhc_clock_enable(host, false); 1157 val = sdhci_readl(host, ESDHC_TBCTL); 1158 val &= ~ESDHC_HS400_MODE; 1159 sdhci_writel(host, val, ESDHC_TBCTL); 1160 esdhc_clock_enable(host, true); 1161 1162 val = sdhci_readl(host, ESDHC_DLLCFG0); 1163 val &= ~(ESDHC_DLL_ENABLE | ESDHC_DLL_FREQ_SEL); 1164 sdhci_writel(host, val, ESDHC_DLLCFG0); 1165 1166 val = sdhci_readl(host, ESDHC_TBCTL); 1167 val &= ~ESDHC_HS400_WNDW_ADJUST; 1168 sdhci_writel(host, val, ESDHC_TBCTL); 1169 1170 esdhc_tuning_block_enable(host, false); 1171 } 1172 1173 if (timing == MMC_TIMING_MMC_HS400) 1174 esdhc_tuning_block_enable(host, true); 1175 else 1176 sdhci_set_uhs_signaling(host, timing); 1177 } 1178 1179 static u32 esdhc_irq(struct sdhci_host *host, u32 intmask) 1180 { 1181 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1182 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 1183 u32 command; 1184 1185 if (esdhc->quirk_trans_complete_erratum) { 1186 command = SDHCI_GET_CMD(sdhci_readw(host, 1187 SDHCI_COMMAND)); 1188 if (command == MMC_WRITE_MULTIPLE_BLOCK && 1189 sdhci_readw(host, SDHCI_BLOCK_COUNT) && 1190 intmask & SDHCI_INT_DATA_END) { 1191 intmask &= ~SDHCI_INT_DATA_END; 1192 sdhci_writel(host, SDHCI_INT_DATA_END, 1193 SDHCI_INT_STATUS); 1194 } 1195 } 1196 return intmask; 1197 } 1198 1199 #ifdef CONFIG_PM_SLEEP 1200 static u32 esdhc_proctl; 1201 static int esdhc_of_suspend(struct device *dev) 1202 { 1203 struct sdhci_host *host = dev_get_drvdata(dev); 1204 1205 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL); 1206 1207 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1208 mmc_retune_needed(host->mmc); 1209 1210 return sdhci_suspend_host(host); 1211 } 1212 1213 static int esdhc_of_resume(struct device *dev) 1214 { 1215 struct sdhci_host *host = dev_get_drvdata(dev); 1216 int ret = sdhci_resume_host(host); 1217 1218 if (ret == 0) { 1219 /* Isn't this already done by sdhci_resume_host() ? --rmk */ 1220 esdhc_of_enable_dma(host); 1221 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); 1222 } 1223 return ret; 1224 } 1225 #endif 1226 1227 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops, 1228 esdhc_of_suspend, 1229 esdhc_of_resume); 1230 1231 static const struct sdhci_ops sdhci_esdhc_be_ops = { 1232 .read_l = esdhc_be_readl, 1233 .read_w = esdhc_be_readw, 1234 .read_b = esdhc_be_readb, 1235 .write_l = esdhc_be_writel, 1236 .write_w = esdhc_be_writew, 1237 .write_b = esdhc_be_writeb, 1238 .set_clock = esdhc_of_set_clock, 1239 .enable_dma = esdhc_of_enable_dma, 1240 .get_max_clock = esdhc_of_get_max_clock, 1241 .get_min_clock = esdhc_of_get_min_clock, 1242 .adma_workaround = esdhc_of_adma_workaround, 1243 .set_bus_width = esdhc_pltfm_set_bus_width, 1244 .reset = esdhc_reset, 1245 .set_uhs_signaling = esdhc_set_uhs_signaling, 1246 .irq = esdhc_irq, 1247 }; 1248 1249 static const struct sdhci_ops sdhci_esdhc_le_ops = { 1250 .read_l = esdhc_le_readl, 1251 .read_w = esdhc_le_readw, 1252 .read_b = esdhc_le_readb, 1253 .write_l = esdhc_le_writel, 1254 .write_w = esdhc_le_writew, 1255 .write_b = esdhc_le_writeb, 1256 .set_clock = esdhc_of_set_clock, 1257 .enable_dma = esdhc_of_enable_dma, 1258 .get_max_clock = esdhc_of_get_max_clock, 1259 .get_min_clock = esdhc_of_get_min_clock, 1260 .adma_workaround = esdhc_of_adma_workaround, 1261 .set_bus_width = esdhc_pltfm_set_bus_width, 1262 .reset = esdhc_reset, 1263 .set_uhs_signaling = esdhc_set_uhs_signaling, 1264 .irq = esdhc_irq, 1265 }; 1266 1267 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = { 1268 .quirks = ESDHC_DEFAULT_QUIRKS | 1269 #ifdef CONFIG_PPC 1270 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 1271 #endif 1272 SDHCI_QUIRK_NO_CARD_NO_RESET | 1273 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1274 .ops = &sdhci_esdhc_be_ops, 1275 }; 1276 1277 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = { 1278 .quirks = ESDHC_DEFAULT_QUIRKS | 1279 SDHCI_QUIRK_NO_CARD_NO_RESET | 1280 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1281 .ops = &sdhci_esdhc_le_ops, 1282 }; 1283 1284 static struct soc_device_attribute soc_incorrect_hostver[] = { 1285 { .family = "QorIQ T4240", .revision = "1.0", }, 1286 { .family = "QorIQ T4240", .revision = "2.0", }, 1287 { }, 1288 }; 1289 1290 static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = { 1291 { .family = "QorIQ LX2160A", .revision = "1.0", }, 1292 { .family = "QorIQ LX2160A", .revision = "2.0", }, 1293 { .family = "QorIQ LS1028A", .revision = "1.0", }, 1294 { }, 1295 }; 1296 1297 static struct soc_device_attribute soc_unreliable_pulse_detection[] = { 1298 { .family = "QorIQ LX2160A", .revision = "1.0", }, 1299 { }, 1300 }; 1301 1302 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host) 1303 { 1304 const struct of_device_id *match; 1305 struct sdhci_pltfm_host *pltfm_host; 1306 struct sdhci_esdhc *esdhc; 1307 struct device_node *np; 1308 struct clk *clk; 1309 u32 val; 1310 u16 host_ver; 1311 1312 pltfm_host = sdhci_priv(host); 1313 esdhc = sdhci_pltfm_priv(pltfm_host); 1314 1315 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); 1316 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >> 1317 SDHCI_VENDOR_VER_SHIFT; 1318 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK; 1319 if (soc_device_match(soc_incorrect_hostver)) 1320 esdhc->quirk_incorrect_hostver = true; 1321 else 1322 esdhc->quirk_incorrect_hostver = false; 1323 1324 if (soc_device_match(soc_fixup_sdhc_clkdivs)) 1325 esdhc->quirk_limited_clk_division = true; 1326 else 1327 esdhc->quirk_limited_clk_division = false; 1328 1329 if (soc_device_match(soc_unreliable_pulse_detection)) 1330 esdhc->quirk_unreliable_pulse_detection = true; 1331 else 1332 esdhc->quirk_unreliable_pulse_detection = false; 1333 1334 match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node); 1335 if (match) 1336 esdhc->clk_fixup = match->data; 1337 np = pdev->dev.of_node; 1338 1339 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { 1340 esdhc->quirk_delay_before_data_reset = true; 1341 esdhc->quirk_trans_complete_erratum = true; 1342 } 1343 1344 clk = of_clk_get(np, 0); 1345 if (!IS_ERR(clk)) { 1346 /* 1347 * esdhc->peripheral_clock would be assigned with a value 1348 * which is eSDHC base clock when use periperal clock. 1349 * For some platforms, the clock value got by common clk 1350 * API is peripheral clock while the eSDHC base clock is 1351 * 1/2 peripheral clock. 1352 */ 1353 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc") || 1354 of_device_is_compatible(np, "fsl,ls1028a-esdhc") || 1355 of_device_is_compatible(np, "fsl,ls1088a-esdhc")) 1356 esdhc->peripheral_clock = clk_get_rate(clk) / 2; 1357 else 1358 esdhc->peripheral_clock = clk_get_rate(clk); 1359 1360 clk_put(clk); 1361 } 1362 1363 esdhc_clock_enable(host, false); 1364 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 1365 /* 1366 * This bit is not able to be reset by SDHCI_RESET_ALL. Need to 1367 * initialize it as 1 or 0 once, to override the different value 1368 * which may be configured in bootloader. 1369 */ 1370 if (esdhc->peripheral_clock) 1371 val |= ESDHC_PERIPHERAL_CLK_SEL; 1372 else 1373 val &= ~ESDHC_PERIPHERAL_CLK_SEL; 1374 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 1375 esdhc_clock_enable(host, true); 1376 } 1377 1378 static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc) 1379 { 1380 esdhc_tuning_block_enable(mmc_priv(mmc), false); 1381 return 0; 1382 } 1383 1384 static int sdhci_esdhc_probe(struct platform_device *pdev) 1385 { 1386 struct sdhci_host *host; 1387 struct device_node *np; 1388 struct sdhci_pltfm_host *pltfm_host; 1389 struct sdhci_esdhc *esdhc; 1390 int ret; 1391 1392 np = pdev->dev.of_node; 1393 1394 if (of_property_read_bool(np, "little-endian")) 1395 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata, 1396 sizeof(struct sdhci_esdhc)); 1397 else 1398 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata, 1399 sizeof(struct sdhci_esdhc)); 1400 1401 if (IS_ERR(host)) 1402 return PTR_ERR(host); 1403 1404 host->mmc_host_ops.start_signal_voltage_switch = 1405 esdhc_signal_voltage_switch; 1406 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning; 1407 host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr; 1408 host->tuning_delay = 1; 1409 1410 esdhc_init(pdev, host); 1411 1412 sdhci_get_of_property(pdev); 1413 1414 pltfm_host = sdhci_priv(host); 1415 esdhc = sdhci_pltfm_priv(pltfm_host); 1416 if (soc_device_match(soc_tuning_erratum_type1)) 1417 esdhc->quirk_tuning_erratum_type1 = true; 1418 else 1419 esdhc->quirk_tuning_erratum_type1 = false; 1420 1421 if (soc_device_match(soc_tuning_erratum_type2)) 1422 esdhc->quirk_tuning_erratum_type2 = true; 1423 else 1424 esdhc->quirk_tuning_erratum_type2 = false; 1425 1426 if (esdhc->vendor_ver == VENDOR_V_22) 1427 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; 1428 1429 if (esdhc->vendor_ver > VENDOR_V_22) 1430 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1431 1432 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) { 1433 host->quirks |= SDHCI_QUIRK_RESET_AFTER_REQUEST; 1434 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1435 } 1436 1437 if (of_device_is_compatible(np, "fsl,p5040-esdhc") || 1438 of_device_is_compatible(np, "fsl,p5020-esdhc") || 1439 of_device_is_compatible(np, "fsl,p4080-esdhc") || 1440 of_device_is_compatible(np, "fsl,p1020-esdhc") || 1441 of_device_is_compatible(np, "fsl,t1040-esdhc")) 1442 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1443 1444 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc")) 1445 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1446 1447 esdhc->quirk_ignore_data_inhibit = false; 1448 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { 1449 /* 1450 * Freescale messed up with P2020 as it has a non-standard 1451 * host control register 1452 */ 1453 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL; 1454 esdhc->quirk_ignore_data_inhibit = true; 1455 } 1456 1457 /* call to generic mmc_of_parse to support additional capabilities */ 1458 ret = mmc_of_parse(host->mmc); 1459 if (ret) 1460 goto err; 1461 1462 mmc_of_parse_voltage(np, &host->ocr_mask); 1463 1464 ret = sdhci_add_host(host); 1465 if (ret) 1466 goto err; 1467 1468 return 0; 1469 err: 1470 sdhci_pltfm_free(pdev); 1471 return ret; 1472 } 1473 1474 static struct platform_driver sdhci_esdhc_driver = { 1475 .driver = { 1476 .name = "sdhci-esdhc", 1477 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1478 .of_match_table = sdhci_esdhc_of_match, 1479 .pm = &esdhc_of_dev_pm_ops, 1480 }, 1481 .probe = sdhci_esdhc_probe, 1482 .remove = sdhci_pltfm_unregister, 1483 }; 1484 1485 module_platform_driver(sdhci_esdhc_driver); 1486 1487 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC"); 1488 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, " 1489 "Anton Vorontsov <avorontsov@ru.mvista.com>"); 1490 MODULE_LICENSE("GPL v2"); 1491