1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Freescale eSDHC controller driver. 4 * 5 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. 6 * Copyright (c) 2009 MontaVista Software, Inc. 7 * 8 * Authors: Xiaobo Xie <X.Xie@freescale.com> 9 * Anton Vorontsov <avorontsov@ru.mvista.com> 10 */ 11 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/delay.h> 17 #include <linux/module.h> 18 #include <linux/sys_soc.h> 19 #include <linux/clk.h> 20 #include <linux/ktime.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include "sdhci-pltfm.h" 25 #include "sdhci-esdhc.h" 26 27 #define VENDOR_V_22 0x12 28 #define VENDOR_V_23 0x13 29 30 #define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1) 31 32 struct esdhc_clk_fixup { 33 const unsigned int sd_dflt_max_clk; 34 const unsigned int max_clk[MMC_TIMING_NUM]; 35 }; 36 37 static const struct esdhc_clk_fixup ls1021a_esdhc_clk = { 38 .sd_dflt_max_clk = 25000000, 39 .max_clk[MMC_TIMING_MMC_HS] = 46500000, 40 .max_clk[MMC_TIMING_SD_HS] = 46500000, 41 }; 42 43 static const struct esdhc_clk_fixup ls1046a_esdhc_clk = { 44 .sd_dflt_max_clk = 25000000, 45 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000, 46 .max_clk[MMC_TIMING_MMC_HS200] = 167000000, 47 }; 48 49 static const struct esdhc_clk_fixup ls1012a_esdhc_clk = { 50 .sd_dflt_max_clk = 25000000, 51 .max_clk[MMC_TIMING_UHS_SDR104] = 125000000, 52 .max_clk[MMC_TIMING_MMC_HS200] = 125000000, 53 }; 54 55 static const struct esdhc_clk_fixup p1010_esdhc_clk = { 56 .sd_dflt_max_clk = 20000000, 57 .max_clk[MMC_TIMING_LEGACY] = 20000000, 58 .max_clk[MMC_TIMING_MMC_HS] = 42000000, 59 .max_clk[MMC_TIMING_SD_HS] = 40000000, 60 }; 61 62 static const struct of_device_id sdhci_esdhc_of_match[] = { 63 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk}, 64 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk}, 65 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk}, 66 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk}, 67 { .compatible = "fsl,mpc8379-esdhc" }, 68 { .compatible = "fsl,mpc8536-esdhc" }, 69 { .compatible = "fsl,esdhc" }, 70 { } 71 }; 72 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); 73 74 struct sdhci_esdhc { 75 u8 vendor_ver; 76 u8 spec_ver; 77 bool quirk_incorrect_hostver; 78 bool quirk_limited_clk_division; 79 bool quirk_unreliable_pulse_detection; 80 bool quirk_fixup_tuning; 81 bool quirk_ignore_data_inhibit; 82 unsigned int peripheral_clock; 83 const struct esdhc_clk_fixup *clk_fixup; 84 u32 div_ratio; 85 }; 86 87 /** 88 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register 89 * to make it compatible with SD spec. 90 * 91 * @host: pointer to sdhci_host 92 * @spec_reg: SD spec register address 93 * @value: 32bit eSDHC register value on spec_reg address 94 * 95 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 96 * registers are 32 bits. There are differences in register size, register 97 * address, register function, bit position and function between eSDHC spec 98 * and SD spec. 99 * 100 * Return a fixed up register value 101 */ 102 static u32 esdhc_readl_fixup(struct sdhci_host *host, 103 int spec_reg, u32 value) 104 { 105 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 106 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 107 u32 ret; 108 109 /* 110 * The bit of ADMA flag in eSDHC is not compatible with standard 111 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is 112 * supported by eSDHC. 113 * And for many FSL eSDHC controller, the reset value of field 114 * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA, 115 * only these vendor version is greater than 2.2/0x12 support ADMA. 116 */ 117 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) { 118 if (esdhc->vendor_ver > VENDOR_V_22) { 119 ret = value | SDHCI_CAN_DO_ADMA2; 120 return ret; 121 } 122 } 123 /* 124 * The DAT[3:0] line signal levels and the CMD line signal level are 125 * not compatible with standard SDHC register. The line signal levels 126 * DAT[7:0] are at bits 31:24 and the command line signal level is at 127 * bit 23. All other bits are the same as in the standard SDHC 128 * register. 129 */ 130 if (spec_reg == SDHCI_PRESENT_STATE) { 131 ret = value & 0x000fffff; 132 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK; 133 ret |= (value << 1) & SDHCI_CMD_LVL; 134 return ret; 135 } 136 137 /* 138 * DTS properties of mmc host are used to enable each speed mode 139 * according to soc and board capability. So clean up 140 * SDR50/SDR104/DDR50 support bits here. 141 */ 142 if (spec_reg == SDHCI_CAPABILITIES_1) { 143 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 144 SDHCI_SUPPORT_DDR50); 145 return ret; 146 } 147 148 /* 149 * Some controllers have unreliable Data Line Active 150 * bit for commands with busy signal. This affects 151 * Command Inhibit (data) bit. Just ignore it since 152 * MMC core driver has already polled card status 153 * with CMD13 after any command with busy siganl. 154 */ 155 if ((spec_reg == SDHCI_PRESENT_STATE) && 156 (esdhc->quirk_ignore_data_inhibit == true)) { 157 ret = value & ~SDHCI_DATA_INHIBIT; 158 return ret; 159 } 160 161 ret = value; 162 return ret; 163 } 164 165 static u16 esdhc_readw_fixup(struct sdhci_host *host, 166 int spec_reg, u32 value) 167 { 168 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 169 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 170 u16 ret; 171 int shift = (spec_reg & 0x2) * 8; 172 173 if (spec_reg == SDHCI_HOST_VERSION) 174 ret = value & 0xffff; 175 else 176 ret = (value >> shift) & 0xffff; 177 /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect 178 * vendor version and spec version information. 179 */ 180 if ((spec_reg == SDHCI_HOST_VERSION) && 181 (esdhc->quirk_incorrect_hostver)) 182 ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200; 183 return ret; 184 } 185 186 static u8 esdhc_readb_fixup(struct sdhci_host *host, 187 int spec_reg, u32 value) 188 { 189 u8 ret; 190 u8 dma_bits; 191 int shift = (spec_reg & 0x3) * 8; 192 193 ret = (value >> shift) & 0xff; 194 195 /* 196 * "DMA select" locates at offset 0x28 in SD specification, but on 197 * P5020 or P3041, it locates at 0x29. 198 */ 199 if (spec_reg == SDHCI_HOST_CONTROL) { 200 /* DMA select is 22,23 bits in Protocol Control Register */ 201 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK; 202 /* fixup the result */ 203 ret &= ~SDHCI_CTRL_DMA_MASK; 204 ret |= dma_bits; 205 } 206 return ret; 207 } 208 209 /** 210 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be 211 * written into eSDHC register. 212 * 213 * @host: pointer to sdhci_host 214 * @spec_reg: SD spec register address 215 * @value: 8/16/32bit SD spec register value that would be written 216 * @old_value: 32bit eSDHC register value on spec_reg address 217 * 218 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 219 * registers are 32 bits. There are differences in register size, register 220 * address, register function, bit position and function between eSDHC spec 221 * and SD spec. 222 * 223 * Return a fixed up register value 224 */ 225 static u32 esdhc_writel_fixup(struct sdhci_host *host, 226 int spec_reg, u32 value, u32 old_value) 227 { 228 u32 ret; 229 230 /* 231 * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE] 232 * when SYSCTL[RSTD] is set for some special operations. 233 * No any impact on other operation. 234 */ 235 if (spec_reg == SDHCI_INT_ENABLE) 236 ret = value | SDHCI_INT_BLK_GAP; 237 else 238 ret = value; 239 240 return ret; 241 } 242 243 static u32 esdhc_writew_fixup(struct sdhci_host *host, 244 int spec_reg, u16 value, u32 old_value) 245 { 246 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 247 int shift = (spec_reg & 0x2) * 8; 248 u32 ret; 249 250 switch (spec_reg) { 251 case SDHCI_TRANSFER_MODE: 252 /* 253 * Postpone this write, we must do it together with a 254 * command write that is down below. Return old value. 255 */ 256 pltfm_host->xfer_mode_shadow = value; 257 return old_value; 258 case SDHCI_COMMAND: 259 ret = (value << 16) | pltfm_host->xfer_mode_shadow; 260 return ret; 261 } 262 263 ret = old_value & (~(0xffff << shift)); 264 ret |= (value << shift); 265 266 if (spec_reg == SDHCI_BLOCK_SIZE) { 267 /* 268 * Two last DMA bits are reserved, and first one is used for 269 * non-standard blksz of 4096 bytes that we don't support 270 * yet. So clear the DMA boundary bits. 271 */ 272 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0)); 273 } 274 return ret; 275 } 276 277 static u32 esdhc_writeb_fixup(struct sdhci_host *host, 278 int spec_reg, u8 value, u32 old_value) 279 { 280 u32 ret; 281 u32 dma_bits; 282 u8 tmp; 283 int shift = (spec_reg & 0x3) * 8; 284 285 /* 286 * eSDHC doesn't have a standard power control register, so we do 287 * nothing here to avoid incorrect operation. 288 */ 289 if (spec_reg == SDHCI_POWER_CONTROL) 290 return old_value; 291 /* 292 * "DMA select" location is offset 0x28 in SD specification, but on 293 * P5020 or P3041, it's located at 0x29. 294 */ 295 if (spec_reg == SDHCI_HOST_CONTROL) { 296 /* 297 * If host control register is not standard, exit 298 * this function 299 */ 300 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL) 301 return old_value; 302 303 /* DMA select is 22,23 bits in Protocol Control Register */ 304 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5; 305 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits; 306 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) | 307 (old_value & SDHCI_CTRL_DMA_MASK); 308 ret = (ret & (~0xff)) | tmp; 309 310 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */ 311 ret &= ~ESDHC_HOST_CONTROL_RES; 312 return ret; 313 } 314 315 ret = (old_value & (~(0xff << shift))) | (value << shift); 316 return ret; 317 } 318 319 static u32 esdhc_be_readl(struct sdhci_host *host, int reg) 320 { 321 u32 ret; 322 u32 value; 323 324 if (reg == SDHCI_CAPABILITIES_1) 325 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1); 326 else 327 value = ioread32be(host->ioaddr + reg); 328 329 ret = esdhc_readl_fixup(host, reg, value); 330 331 return ret; 332 } 333 334 static u32 esdhc_le_readl(struct sdhci_host *host, int reg) 335 { 336 u32 ret; 337 u32 value; 338 339 if (reg == SDHCI_CAPABILITIES_1) 340 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1); 341 else 342 value = ioread32(host->ioaddr + reg); 343 344 ret = esdhc_readl_fixup(host, reg, value); 345 346 return ret; 347 } 348 349 static u16 esdhc_be_readw(struct sdhci_host *host, int reg) 350 { 351 u16 ret; 352 u32 value; 353 int base = reg & ~0x3; 354 355 value = ioread32be(host->ioaddr + base); 356 ret = esdhc_readw_fixup(host, reg, value); 357 return ret; 358 } 359 360 static u16 esdhc_le_readw(struct sdhci_host *host, int reg) 361 { 362 u16 ret; 363 u32 value; 364 int base = reg & ~0x3; 365 366 value = ioread32(host->ioaddr + base); 367 ret = esdhc_readw_fixup(host, reg, value); 368 return ret; 369 } 370 371 static u8 esdhc_be_readb(struct sdhci_host *host, int reg) 372 { 373 u8 ret; 374 u32 value; 375 int base = reg & ~0x3; 376 377 value = ioread32be(host->ioaddr + base); 378 ret = esdhc_readb_fixup(host, reg, value); 379 return ret; 380 } 381 382 static u8 esdhc_le_readb(struct sdhci_host *host, int reg) 383 { 384 u8 ret; 385 u32 value; 386 int base = reg & ~0x3; 387 388 value = ioread32(host->ioaddr + base); 389 ret = esdhc_readb_fixup(host, reg, value); 390 return ret; 391 } 392 393 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) 394 { 395 u32 value; 396 397 value = esdhc_writel_fixup(host, reg, val, 0); 398 iowrite32be(value, host->ioaddr + reg); 399 } 400 401 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) 402 { 403 u32 value; 404 405 value = esdhc_writel_fixup(host, reg, val, 0); 406 iowrite32(value, host->ioaddr + reg); 407 } 408 409 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) 410 { 411 int base = reg & ~0x3; 412 u32 value; 413 u32 ret; 414 415 value = ioread32be(host->ioaddr + base); 416 ret = esdhc_writew_fixup(host, reg, val, value); 417 if (reg != SDHCI_TRANSFER_MODE) 418 iowrite32be(ret, host->ioaddr + base); 419 } 420 421 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) 422 { 423 int base = reg & ~0x3; 424 u32 value; 425 u32 ret; 426 427 value = ioread32(host->ioaddr + base); 428 ret = esdhc_writew_fixup(host, reg, val, value); 429 if (reg != SDHCI_TRANSFER_MODE) 430 iowrite32(ret, host->ioaddr + base); 431 } 432 433 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) 434 { 435 int base = reg & ~0x3; 436 u32 value; 437 u32 ret; 438 439 value = ioread32be(host->ioaddr + base); 440 ret = esdhc_writeb_fixup(host, reg, val, value); 441 iowrite32be(ret, host->ioaddr + base); 442 } 443 444 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) 445 { 446 int base = reg & ~0x3; 447 u32 value; 448 u32 ret; 449 450 value = ioread32(host->ioaddr + base); 451 ret = esdhc_writeb_fixup(host, reg, val, value); 452 iowrite32(ret, host->ioaddr + base); 453 } 454 455 /* 456 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA 457 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC]) 458 * and Block Gap Event(IRQSTAT[BGE]) are also set. 459 * For Continue, apply soft reset for data(SYSCTL[RSTD]); 460 * and re-issue the entire read transaction from beginning. 461 */ 462 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask) 463 { 464 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 465 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 466 bool applicable; 467 dma_addr_t dmastart; 468 dma_addr_t dmanow; 469 470 applicable = (intmask & SDHCI_INT_DATA_END) && 471 (intmask & SDHCI_INT_BLK_GAP) && 472 (esdhc->vendor_ver == VENDOR_V_23); 473 if (!applicable) 474 return; 475 476 host->data->error = 0; 477 dmastart = sg_dma_address(host->data->sg); 478 dmanow = dmastart + host->data->bytes_xfered; 479 /* 480 * Force update to the next DMA block boundary. 481 */ 482 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 483 SDHCI_DEFAULT_BOUNDARY_SIZE; 484 host->data->bytes_xfered = dmanow - dmastart; 485 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 486 } 487 488 static int esdhc_of_enable_dma(struct sdhci_host *host) 489 { 490 u32 value; 491 struct device *dev = mmc_dev(host->mmc); 492 493 if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") || 494 of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) 495 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); 496 497 value = sdhci_readl(host, ESDHC_DMA_SYSCTL); 498 value |= ESDHC_DMA_SNOOP; 499 sdhci_writel(host, value, ESDHC_DMA_SYSCTL); 500 return 0; 501 } 502 503 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) 504 { 505 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 506 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 507 508 if (esdhc->peripheral_clock) 509 return esdhc->peripheral_clock; 510 else 511 return pltfm_host->clock; 512 } 513 514 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) 515 { 516 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 517 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 518 unsigned int clock; 519 520 if (esdhc->peripheral_clock) 521 clock = esdhc->peripheral_clock; 522 else 523 clock = pltfm_host->clock; 524 return clock / 256 / 16; 525 } 526 527 static void esdhc_clock_enable(struct sdhci_host *host, bool enable) 528 { 529 u32 val; 530 ktime_t timeout; 531 532 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 533 534 if (enable) 535 val |= ESDHC_CLOCK_SDCLKEN; 536 else 537 val &= ~ESDHC_CLOCK_SDCLKEN; 538 539 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL); 540 541 /* Wait max 20 ms */ 542 timeout = ktime_add_ms(ktime_get(), 20); 543 val = ESDHC_CLOCK_STABLE; 544 while (1) { 545 bool timedout = ktime_after(ktime_get(), timeout); 546 547 if (sdhci_readl(host, ESDHC_PRSSTAT) & val) 548 break; 549 if (timedout) { 550 pr_err("%s: Internal clock never stabilised.\n", 551 mmc_hostname(host->mmc)); 552 break; 553 } 554 udelay(10); 555 } 556 } 557 558 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) 559 { 560 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 561 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 562 int pre_div = 1; 563 int div = 1; 564 int division; 565 ktime_t timeout; 566 long fixup = 0; 567 u32 temp; 568 569 host->mmc->actual_clock = 0; 570 571 if (clock == 0) { 572 esdhc_clock_enable(host, false); 573 return; 574 } 575 576 /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */ 577 if (esdhc->vendor_ver < VENDOR_V_23) 578 pre_div = 2; 579 580 if (host->mmc->card && mmc_card_sd(host->mmc->card) && 581 esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY) 582 fixup = esdhc->clk_fixup->sd_dflt_max_clk; 583 else if (esdhc->clk_fixup) 584 fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing]; 585 586 if (fixup && clock > fixup) 587 clock = fixup; 588 589 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 590 temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | 591 ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK); 592 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 593 594 while (host->max_clk / pre_div / 16 > clock && pre_div < 256) 595 pre_div *= 2; 596 597 while (host->max_clk / pre_div / div > clock && div < 16) 598 div++; 599 600 if (esdhc->quirk_limited_clk_division && 601 clock == MMC_HS200_MAX_DTR && 602 (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 || 603 host->flags & SDHCI_HS400_TUNING)) { 604 division = pre_div * div; 605 if (division <= 4) { 606 pre_div = 4; 607 div = 1; 608 } else if (division <= 8) { 609 pre_div = 4; 610 div = 2; 611 } else if (division <= 12) { 612 pre_div = 4; 613 div = 3; 614 } else { 615 pr_warn("%s: using unsupported clock division.\n", 616 mmc_hostname(host->mmc)); 617 } 618 } 619 620 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 621 clock, host->max_clk / pre_div / div); 622 host->mmc->actual_clock = host->max_clk / pre_div / div; 623 esdhc->div_ratio = pre_div * div; 624 pre_div >>= 1; 625 div--; 626 627 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 628 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 629 | (div << ESDHC_DIVIDER_SHIFT) 630 | (pre_div << ESDHC_PREDIV_SHIFT)); 631 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 632 633 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && 634 clock == MMC_HS200_MAX_DTR) { 635 temp = sdhci_readl(host, ESDHC_TBCTL); 636 sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL); 637 temp = sdhci_readl(host, ESDHC_SDCLKCTL); 638 sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL); 639 esdhc_clock_enable(host, true); 640 641 temp = sdhci_readl(host, ESDHC_DLLCFG0); 642 temp |= ESDHC_DLL_ENABLE; 643 if (host->mmc->actual_clock == MMC_HS200_MAX_DTR) 644 temp |= ESDHC_DLL_FREQ_SEL; 645 sdhci_writel(host, temp, ESDHC_DLLCFG0); 646 temp = sdhci_readl(host, ESDHC_TBCTL); 647 sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL); 648 649 esdhc_clock_enable(host, false); 650 temp = sdhci_readl(host, ESDHC_DMA_SYSCTL); 651 temp |= ESDHC_FLUSH_ASYNC_FIFO; 652 sdhci_writel(host, temp, ESDHC_DMA_SYSCTL); 653 } 654 655 /* Wait max 20 ms */ 656 timeout = ktime_add_ms(ktime_get(), 20); 657 while (1) { 658 bool timedout = ktime_after(ktime_get(), timeout); 659 660 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE) 661 break; 662 if (timedout) { 663 pr_err("%s: Internal clock never stabilised.\n", 664 mmc_hostname(host->mmc)); 665 return; 666 } 667 udelay(10); 668 } 669 670 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 671 temp |= ESDHC_CLOCK_SDCLKEN; 672 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 673 } 674 675 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 676 { 677 u32 ctrl; 678 679 ctrl = sdhci_readl(host, ESDHC_PROCTL); 680 ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK); 681 switch (width) { 682 case MMC_BUS_WIDTH_8: 683 ctrl |= ESDHC_CTRL_8BITBUS; 684 break; 685 686 case MMC_BUS_WIDTH_4: 687 ctrl |= ESDHC_CTRL_4BITBUS; 688 break; 689 690 default: 691 break; 692 } 693 694 sdhci_writel(host, ctrl, ESDHC_PROCTL); 695 } 696 697 static void esdhc_reset(struct sdhci_host *host, u8 mask) 698 { 699 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 700 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 701 u32 val; 702 703 sdhci_reset(host, mask); 704 705 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 706 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 707 708 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) 709 mdelay(5); 710 711 if (mask & SDHCI_RESET_ALL) { 712 val = sdhci_readl(host, ESDHC_TBCTL); 713 val &= ~ESDHC_TB_EN; 714 sdhci_writel(host, val, ESDHC_TBCTL); 715 716 if (esdhc->quirk_unreliable_pulse_detection) { 717 val = sdhci_readl(host, ESDHC_DLLCFG1); 718 val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL; 719 sdhci_writel(host, val, ESDHC_DLLCFG1); 720 } 721 } 722 } 723 724 /* The SCFG, Supplemental Configuration Unit, provides SoC specific 725 * configuration and status registers for the device. There is a 726 * SDHC IO VSEL control register on SCFG for some platforms. It's 727 * used to support SDHC IO voltage switching. 728 */ 729 static const struct of_device_id scfg_device_ids[] = { 730 { .compatible = "fsl,t1040-scfg", }, 731 { .compatible = "fsl,ls1012a-scfg", }, 732 { .compatible = "fsl,ls1046a-scfg", }, 733 {} 734 }; 735 736 /* SDHC IO VSEL control register definition */ 737 #define SCFG_SDHCIOVSELCR 0x408 738 #define SDHCIOVSELCR_TGLEN 0x80000000 739 #define SDHCIOVSELCR_VSELVAL 0x60000000 740 #define SDHCIOVSELCR_SDHC_VS 0x00000001 741 742 static int esdhc_signal_voltage_switch(struct mmc_host *mmc, 743 struct mmc_ios *ios) 744 { 745 struct sdhci_host *host = mmc_priv(mmc); 746 struct device_node *scfg_node; 747 void __iomem *scfg_base = NULL; 748 u32 sdhciovselcr; 749 u32 val; 750 751 /* 752 * Signal Voltage Switching is only applicable for Host Controllers 753 * v3.00 and above. 754 */ 755 if (host->version < SDHCI_SPEC_300) 756 return 0; 757 758 val = sdhci_readl(host, ESDHC_PROCTL); 759 760 switch (ios->signal_voltage) { 761 case MMC_SIGNAL_VOLTAGE_330: 762 val &= ~ESDHC_VOLT_SEL; 763 sdhci_writel(host, val, ESDHC_PROCTL); 764 return 0; 765 case MMC_SIGNAL_VOLTAGE_180: 766 scfg_node = of_find_matching_node(NULL, scfg_device_ids); 767 if (scfg_node) 768 scfg_base = of_iomap(scfg_node, 0); 769 if (scfg_base) { 770 sdhciovselcr = SDHCIOVSELCR_TGLEN | 771 SDHCIOVSELCR_VSELVAL; 772 iowrite32be(sdhciovselcr, 773 scfg_base + SCFG_SDHCIOVSELCR); 774 775 val |= ESDHC_VOLT_SEL; 776 sdhci_writel(host, val, ESDHC_PROCTL); 777 mdelay(5); 778 779 sdhciovselcr = SDHCIOVSELCR_TGLEN | 780 SDHCIOVSELCR_SDHC_VS; 781 iowrite32be(sdhciovselcr, 782 scfg_base + SCFG_SDHCIOVSELCR); 783 iounmap(scfg_base); 784 } else { 785 val |= ESDHC_VOLT_SEL; 786 sdhci_writel(host, val, ESDHC_PROCTL); 787 } 788 return 0; 789 default: 790 return 0; 791 } 792 } 793 794 static struct soc_device_attribute soc_fixup_tuning[] = { 795 { .family = "QorIQ T1040", .revision = "1.0", }, 796 { .family = "QorIQ T2080", .revision = "1.0", }, 797 { .family = "QorIQ T1023", .revision = "1.0", }, 798 { .family = "QorIQ LS1021A", .revision = "1.0", }, 799 { .family = "QorIQ LS1080A", .revision = "1.0", }, 800 { .family = "QorIQ LS2080A", .revision = "1.0", }, 801 { .family = "QorIQ LS1012A", .revision = "1.0", }, 802 { .family = "QorIQ LS1043A", .revision = "1.*", }, 803 { .family = "QorIQ LS1046A", .revision = "1.0", }, 804 { }, 805 }; 806 807 static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable) 808 { 809 u32 val; 810 811 esdhc_clock_enable(host, false); 812 813 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 814 val |= ESDHC_FLUSH_ASYNC_FIFO; 815 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 816 817 val = sdhci_readl(host, ESDHC_TBCTL); 818 if (enable) 819 val |= ESDHC_TB_EN; 820 else 821 val &= ~ESDHC_TB_EN; 822 sdhci_writel(host, val, ESDHC_TBCTL); 823 824 esdhc_clock_enable(host, true); 825 } 826 827 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 828 { 829 struct sdhci_host *host = mmc_priv(mmc); 830 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 831 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 832 bool hs400_tuning; 833 u32 val; 834 int ret; 835 836 if (esdhc->quirk_limited_clk_division && 837 host->flags & SDHCI_HS400_TUNING) 838 esdhc_of_set_clock(host, host->clock); 839 840 esdhc_tuning_block_enable(host, true); 841 842 hs400_tuning = host->flags & SDHCI_HS400_TUNING; 843 ret = sdhci_execute_tuning(mmc, opcode); 844 845 if (hs400_tuning) { 846 val = sdhci_readl(host, ESDHC_SDTIMNGCTL); 847 val |= ESDHC_FLW_CTL_BG; 848 sdhci_writel(host, val, ESDHC_SDTIMNGCTL); 849 } 850 851 if (host->tuning_err == -EAGAIN && esdhc->quirk_fixup_tuning) { 852 853 /* program TBPTR[TB_WNDW_END_PTR] = 3*DIV_RATIO and 854 * program TBPTR[TB_WNDW_START_PTR] = 5*DIV_RATIO 855 */ 856 val = sdhci_readl(host, ESDHC_TBPTR); 857 val = (val & ~((0x7f << 8) | 0x7f)) | 858 (3 * esdhc->div_ratio) | ((5 * esdhc->div_ratio) << 8); 859 sdhci_writel(host, val, ESDHC_TBPTR); 860 861 /* program the software tuning mode by setting 862 * TBCTL[TB_MODE]=2'h3 863 */ 864 val = sdhci_readl(host, ESDHC_TBCTL); 865 val |= 0x3; 866 sdhci_writel(host, val, ESDHC_TBCTL); 867 sdhci_execute_tuning(mmc, opcode); 868 } 869 return ret; 870 } 871 872 static void esdhc_set_uhs_signaling(struct sdhci_host *host, 873 unsigned int timing) 874 { 875 if (timing == MMC_TIMING_MMC_HS400) 876 esdhc_tuning_block_enable(host, true); 877 else 878 sdhci_set_uhs_signaling(host, timing); 879 } 880 881 static u32 esdhc_irq(struct sdhci_host *host, u32 intmask) 882 { 883 u32 command; 884 885 if (of_find_compatible_node(NULL, NULL, 886 "fsl,p2020-esdhc")) { 887 command = SDHCI_GET_CMD(sdhci_readw(host, 888 SDHCI_COMMAND)); 889 if (command == MMC_WRITE_MULTIPLE_BLOCK && 890 sdhci_readw(host, SDHCI_BLOCK_COUNT) && 891 intmask & SDHCI_INT_DATA_END) { 892 intmask &= ~SDHCI_INT_DATA_END; 893 sdhci_writel(host, SDHCI_INT_DATA_END, 894 SDHCI_INT_STATUS); 895 } 896 } 897 return intmask; 898 } 899 900 #ifdef CONFIG_PM_SLEEP 901 static u32 esdhc_proctl; 902 static int esdhc_of_suspend(struct device *dev) 903 { 904 struct sdhci_host *host = dev_get_drvdata(dev); 905 906 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL); 907 908 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 909 mmc_retune_needed(host->mmc); 910 911 return sdhci_suspend_host(host); 912 } 913 914 static int esdhc_of_resume(struct device *dev) 915 { 916 struct sdhci_host *host = dev_get_drvdata(dev); 917 int ret = sdhci_resume_host(host); 918 919 if (ret == 0) { 920 /* Isn't this already done by sdhci_resume_host() ? --rmk */ 921 esdhc_of_enable_dma(host); 922 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); 923 } 924 return ret; 925 } 926 #endif 927 928 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops, 929 esdhc_of_suspend, 930 esdhc_of_resume); 931 932 static const struct sdhci_ops sdhci_esdhc_be_ops = { 933 .read_l = esdhc_be_readl, 934 .read_w = esdhc_be_readw, 935 .read_b = esdhc_be_readb, 936 .write_l = esdhc_be_writel, 937 .write_w = esdhc_be_writew, 938 .write_b = esdhc_be_writeb, 939 .set_clock = esdhc_of_set_clock, 940 .enable_dma = esdhc_of_enable_dma, 941 .get_max_clock = esdhc_of_get_max_clock, 942 .get_min_clock = esdhc_of_get_min_clock, 943 .adma_workaround = esdhc_of_adma_workaround, 944 .set_bus_width = esdhc_pltfm_set_bus_width, 945 .reset = esdhc_reset, 946 .set_uhs_signaling = esdhc_set_uhs_signaling, 947 .irq = esdhc_irq, 948 }; 949 950 static const struct sdhci_ops sdhci_esdhc_le_ops = { 951 .read_l = esdhc_le_readl, 952 .read_w = esdhc_le_readw, 953 .read_b = esdhc_le_readb, 954 .write_l = esdhc_le_writel, 955 .write_w = esdhc_le_writew, 956 .write_b = esdhc_le_writeb, 957 .set_clock = esdhc_of_set_clock, 958 .enable_dma = esdhc_of_enable_dma, 959 .get_max_clock = esdhc_of_get_max_clock, 960 .get_min_clock = esdhc_of_get_min_clock, 961 .adma_workaround = esdhc_of_adma_workaround, 962 .set_bus_width = esdhc_pltfm_set_bus_width, 963 .reset = esdhc_reset, 964 .set_uhs_signaling = esdhc_set_uhs_signaling, 965 .irq = esdhc_irq, 966 }; 967 968 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = { 969 .quirks = ESDHC_DEFAULT_QUIRKS | 970 #ifdef CONFIG_PPC 971 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 972 #endif 973 SDHCI_QUIRK_NO_CARD_NO_RESET | 974 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 975 .ops = &sdhci_esdhc_be_ops, 976 }; 977 978 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = { 979 .quirks = ESDHC_DEFAULT_QUIRKS | 980 SDHCI_QUIRK_NO_CARD_NO_RESET | 981 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 982 .ops = &sdhci_esdhc_le_ops, 983 }; 984 985 static struct soc_device_attribute soc_incorrect_hostver[] = { 986 { .family = "QorIQ T4240", .revision = "1.0", }, 987 { .family = "QorIQ T4240", .revision = "2.0", }, 988 { }, 989 }; 990 991 static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = { 992 { .family = "QorIQ LX2160A", .revision = "1.0", }, 993 { .family = "QorIQ LX2160A", .revision = "2.0", }, 994 { }, 995 }; 996 997 static struct soc_device_attribute soc_unreliable_pulse_detection[] = { 998 { .family = "QorIQ LX2160A", .revision = "1.0", }, 999 { }, 1000 }; 1001 1002 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host) 1003 { 1004 const struct of_device_id *match; 1005 struct sdhci_pltfm_host *pltfm_host; 1006 struct sdhci_esdhc *esdhc; 1007 struct device_node *np; 1008 struct clk *clk; 1009 u32 val; 1010 u16 host_ver; 1011 1012 pltfm_host = sdhci_priv(host); 1013 esdhc = sdhci_pltfm_priv(pltfm_host); 1014 1015 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); 1016 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >> 1017 SDHCI_VENDOR_VER_SHIFT; 1018 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK; 1019 if (soc_device_match(soc_incorrect_hostver)) 1020 esdhc->quirk_incorrect_hostver = true; 1021 else 1022 esdhc->quirk_incorrect_hostver = false; 1023 1024 if (soc_device_match(soc_fixup_sdhc_clkdivs)) 1025 esdhc->quirk_limited_clk_division = true; 1026 else 1027 esdhc->quirk_limited_clk_division = false; 1028 1029 if (soc_device_match(soc_unreliable_pulse_detection)) 1030 esdhc->quirk_unreliable_pulse_detection = true; 1031 else 1032 esdhc->quirk_unreliable_pulse_detection = false; 1033 1034 match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node); 1035 if (match) 1036 esdhc->clk_fixup = match->data; 1037 np = pdev->dev.of_node; 1038 clk = of_clk_get(np, 0); 1039 if (!IS_ERR(clk)) { 1040 /* 1041 * esdhc->peripheral_clock would be assigned with a value 1042 * which is eSDHC base clock when use periperal clock. 1043 * For ls1046a, the clock value got by common clk API is 1044 * peripheral clock while the eSDHC base clock is 1/2 1045 * peripheral clock. 1046 */ 1047 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc")) 1048 esdhc->peripheral_clock = clk_get_rate(clk) / 2; 1049 else 1050 esdhc->peripheral_clock = clk_get_rate(clk); 1051 1052 clk_put(clk); 1053 } 1054 1055 if (esdhc->peripheral_clock) { 1056 esdhc_clock_enable(host, false); 1057 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 1058 val |= ESDHC_PERIPHERAL_CLK_SEL; 1059 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 1060 esdhc_clock_enable(host, true); 1061 } 1062 } 1063 1064 static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc) 1065 { 1066 esdhc_tuning_block_enable(mmc_priv(mmc), false); 1067 return 0; 1068 } 1069 1070 static int sdhci_esdhc_probe(struct platform_device *pdev) 1071 { 1072 struct sdhci_host *host; 1073 struct device_node *np; 1074 struct sdhci_pltfm_host *pltfm_host; 1075 struct sdhci_esdhc *esdhc; 1076 int ret; 1077 1078 np = pdev->dev.of_node; 1079 1080 if (of_property_read_bool(np, "little-endian")) 1081 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata, 1082 sizeof(struct sdhci_esdhc)); 1083 else 1084 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata, 1085 sizeof(struct sdhci_esdhc)); 1086 1087 if (IS_ERR(host)) 1088 return PTR_ERR(host); 1089 1090 host->mmc_host_ops.start_signal_voltage_switch = 1091 esdhc_signal_voltage_switch; 1092 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning; 1093 host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr; 1094 host->tuning_delay = 1; 1095 1096 esdhc_init(pdev, host); 1097 1098 sdhci_get_of_property(pdev); 1099 1100 pltfm_host = sdhci_priv(host); 1101 esdhc = sdhci_pltfm_priv(pltfm_host); 1102 if (soc_device_match(soc_fixup_tuning)) 1103 esdhc->quirk_fixup_tuning = true; 1104 else 1105 esdhc->quirk_fixup_tuning = false; 1106 1107 if (esdhc->vendor_ver == VENDOR_V_22) 1108 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; 1109 1110 if (esdhc->vendor_ver > VENDOR_V_22) 1111 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1112 1113 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) { 1114 host->quirks2 |= SDHCI_QUIRK_RESET_AFTER_REQUEST; 1115 host->quirks2 |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1116 } 1117 1118 if (of_device_is_compatible(np, "fsl,p5040-esdhc") || 1119 of_device_is_compatible(np, "fsl,p5020-esdhc") || 1120 of_device_is_compatible(np, "fsl,p4080-esdhc") || 1121 of_device_is_compatible(np, "fsl,p1020-esdhc") || 1122 of_device_is_compatible(np, "fsl,t1040-esdhc")) 1123 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1124 1125 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc")) 1126 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1127 1128 esdhc->quirk_ignore_data_inhibit = false; 1129 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { 1130 /* 1131 * Freescale messed up with P2020 as it has a non-standard 1132 * host control register 1133 */ 1134 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL; 1135 esdhc->quirk_ignore_data_inhibit = true; 1136 } 1137 1138 /* call to generic mmc_of_parse to support additional capabilities */ 1139 ret = mmc_of_parse(host->mmc); 1140 if (ret) 1141 goto err; 1142 1143 mmc_of_parse_voltage(np, &host->ocr_mask); 1144 1145 ret = sdhci_add_host(host); 1146 if (ret) 1147 goto err; 1148 1149 return 0; 1150 err: 1151 sdhci_pltfm_free(pdev); 1152 return ret; 1153 } 1154 1155 static struct platform_driver sdhci_esdhc_driver = { 1156 .driver = { 1157 .name = "sdhci-esdhc", 1158 .of_match_table = sdhci_esdhc_of_match, 1159 .pm = &esdhc_of_dev_pm_ops, 1160 }, 1161 .probe = sdhci_esdhc_probe, 1162 .remove = sdhci_pltfm_unregister, 1163 }; 1164 1165 module_platform_driver(sdhci_esdhc_driver); 1166 1167 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC"); 1168 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, " 1169 "Anton Vorontsov <avorontsov@ru.mvista.com>"); 1170 MODULE_LICENSE("GPL v2"); 1171