1 /* 2 * Freescale eSDHC controller driver. 3 * 4 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. 5 * Copyright (c) 2009 MontaVista Software, Inc. 6 * 7 * Authors: Xiaobo Xie <X.Xie@freescale.com> 8 * Anton Vorontsov <avorontsov@ru.mvista.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or (at 13 * your option) any later version. 14 */ 15 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/delay.h> 21 #include <linux/module.h> 22 #include <linux/sys_soc.h> 23 #include <linux/clk.h> 24 #include <linux/ktime.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/mmc/host.h> 27 #include "sdhci-pltfm.h" 28 #include "sdhci-esdhc.h" 29 30 #define VENDOR_V_22 0x12 31 #define VENDOR_V_23 0x13 32 33 #define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1) 34 35 struct esdhc_clk_fixup { 36 const unsigned int sd_dflt_max_clk; 37 const unsigned int max_clk[MMC_TIMING_NUM]; 38 }; 39 40 static const struct esdhc_clk_fixup ls1021a_esdhc_clk = { 41 .sd_dflt_max_clk = 25000000, 42 .max_clk[MMC_TIMING_MMC_HS] = 46500000, 43 .max_clk[MMC_TIMING_SD_HS] = 46500000, 44 }; 45 46 static const struct esdhc_clk_fixup ls1046a_esdhc_clk = { 47 .sd_dflt_max_clk = 25000000, 48 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000, 49 .max_clk[MMC_TIMING_MMC_HS200] = 167000000, 50 }; 51 52 static const struct esdhc_clk_fixup ls1012a_esdhc_clk = { 53 .sd_dflt_max_clk = 25000000, 54 .max_clk[MMC_TIMING_UHS_SDR104] = 125000000, 55 .max_clk[MMC_TIMING_MMC_HS200] = 125000000, 56 }; 57 58 static const struct esdhc_clk_fixup p1010_esdhc_clk = { 59 .sd_dflt_max_clk = 20000000, 60 .max_clk[MMC_TIMING_LEGACY] = 20000000, 61 .max_clk[MMC_TIMING_MMC_HS] = 42000000, 62 .max_clk[MMC_TIMING_SD_HS] = 40000000, 63 }; 64 65 static const struct of_device_id sdhci_esdhc_of_match[] = { 66 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk}, 67 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk}, 68 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk}, 69 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk}, 70 { .compatible = "fsl,mpc8379-esdhc" }, 71 { .compatible = "fsl,mpc8536-esdhc" }, 72 { .compatible = "fsl,esdhc" }, 73 { } 74 }; 75 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); 76 77 struct sdhci_esdhc { 78 u8 vendor_ver; 79 u8 spec_ver; 80 bool quirk_incorrect_hostver; 81 bool quirk_fixup_tuning; 82 unsigned int peripheral_clock; 83 const struct esdhc_clk_fixup *clk_fixup; 84 u32 div_ratio; 85 }; 86 87 /** 88 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register 89 * to make it compatible with SD spec. 90 * 91 * @host: pointer to sdhci_host 92 * @spec_reg: SD spec register address 93 * @value: 32bit eSDHC register value on spec_reg address 94 * 95 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 96 * registers are 32 bits. There are differences in register size, register 97 * address, register function, bit position and function between eSDHC spec 98 * and SD spec. 99 * 100 * Return a fixed up register value 101 */ 102 static u32 esdhc_readl_fixup(struct sdhci_host *host, 103 int spec_reg, u32 value) 104 { 105 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 106 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 107 u32 ret; 108 109 /* 110 * The bit of ADMA flag in eSDHC is not compatible with standard 111 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is 112 * supported by eSDHC. 113 * And for many FSL eSDHC controller, the reset value of field 114 * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA, 115 * only these vendor version is greater than 2.2/0x12 support ADMA. 116 */ 117 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) { 118 if (esdhc->vendor_ver > VENDOR_V_22) { 119 ret = value | SDHCI_CAN_DO_ADMA2; 120 return ret; 121 } 122 } 123 /* 124 * The DAT[3:0] line signal levels and the CMD line signal level are 125 * not compatible with standard SDHC register. The line signal levels 126 * DAT[7:0] are at bits 31:24 and the command line signal level is at 127 * bit 23. All other bits are the same as in the standard SDHC 128 * register. 129 */ 130 if (spec_reg == SDHCI_PRESENT_STATE) { 131 ret = value & 0x000fffff; 132 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK; 133 ret |= (value << 1) & SDHCI_CMD_LVL; 134 return ret; 135 } 136 137 /* 138 * DTS properties of mmc host are used to enable each speed mode 139 * according to soc and board capability. So clean up 140 * SDR50/SDR104/DDR50 support bits here. 141 */ 142 if (spec_reg == SDHCI_CAPABILITIES_1) { 143 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 144 SDHCI_SUPPORT_DDR50); 145 return ret; 146 } 147 148 ret = value; 149 return ret; 150 } 151 152 static u16 esdhc_readw_fixup(struct sdhci_host *host, 153 int spec_reg, u32 value) 154 { 155 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 156 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 157 u16 ret; 158 int shift = (spec_reg & 0x2) * 8; 159 160 if (spec_reg == SDHCI_HOST_VERSION) 161 ret = value & 0xffff; 162 else 163 ret = (value >> shift) & 0xffff; 164 /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect 165 * vendor version and spec version information. 166 */ 167 if ((spec_reg == SDHCI_HOST_VERSION) && 168 (esdhc->quirk_incorrect_hostver)) 169 ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200; 170 return ret; 171 } 172 173 static u8 esdhc_readb_fixup(struct sdhci_host *host, 174 int spec_reg, u32 value) 175 { 176 u8 ret; 177 u8 dma_bits; 178 int shift = (spec_reg & 0x3) * 8; 179 180 ret = (value >> shift) & 0xff; 181 182 /* 183 * "DMA select" locates at offset 0x28 in SD specification, but on 184 * P5020 or P3041, it locates at 0x29. 185 */ 186 if (spec_reg == SDHCI_HOST_CONTROL) { 187 /* DMA select is 22,23 bits in Protocol Control Register */ 188 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK; 189 /* fixup the result */ 190 ret &= ~SDHCI_CTRL_DMA_MASK; 191 ret |= dma_bits; 192 } 193 return ret; 194 } 195 196 /** 197 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be 198 * written into eSDHC register. 199 * 200 * @host: pointer to sdhci_host 201 * @spec_reg: SD spec register address 202 * @value: 8/16/32bit SD spec register value that would be written 203 * @old_value: 32bit eSDHC register value on spec_reg address 204 * 205 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 206 * registers are 32 bits. There are differences in register size, register 207 * address, register function, bit position and function between eSDHC spec 208 * and SD spec. 209 * 210 * Return a fixed up register value 211 */ 212 static u32 esdhc_writel_fixup(struct sdhci_host *host, 213 int spec_reg, u32 value, u32 old_value) 214 { 215 u32 ret; 216 217 /* 218 * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE] 219 * when SYSCTL[RSTD] is set for some special operations. 220 * No any impact on other operation. 221 */ 222 if (spec_reg == SDHCI_INT_ENABLE) 223 ret = value | SDHCI_INT_BLK_GAP; 224 else 225 ret = value; 226 227 return ret; 228 } 229 230 static u32 esdhc_writew_fixup(struct sdhci_host *host, 231 int spec_reg, u16 value, u32 old_value) 232 { 233 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 234 int shift = (spec_reg & 0x2) * 8; 235 u32 ret; 236 237 switch (spec_reg) { 238 case SDHCI_TRANSFER_MODE: 239 /* 240 * Postpone this write, we must do it together with a 241 * command write that is down below. Return old value. 242 */ 243 pltfm_host->xfer_mode_shadow = value; 244 return old_value; 245 case SDHCI_COMMAND: 246 ret = (value << 16) | pltfm_host->xfer_mode_shadow; 247 return ret; 248 } 249 250 ret = old_value & (~(0xffff << shift)); 251 ret |= (value << shift); 252 253 if (spec_reg == SDHCI_BLOCK_SIZE) { 254 /* 255 * Two last DMA bits are reserved, and first one is used for 256 * non-standard blksz of 4096 bytes that we don't support 257 * yet. So clear the DMA boundary bits. 258 */ 259 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0)); 260 } 261 return ret; 262 } 263 264 static u32 esdhc_writeb_fixup(struct sdhci_host *host, 265 int spec_reg, u8 value, u32 old_value) 266 { 267 u32 ret; 268 u32 dma_bits; 269 u8 tmp; 270 int shift = (spec_reg & 0x3) * 8; 271 272 /* 273 * eSDHC doesn't have a standard power control register, so we do 274 * nothing here to avoid incorrect operation. 275 */ 276 if (spec_reg == SDHCI_POWER_CONTROL) 277 return old_value; 278 /* 279 * "DMA select" location is offset 0x28 in SD specification, but on 280 * P5020 or P3041, it's located at 0x29. 281 */ 282 if (spec_reg == SDHCI_HOST_CONTROL) { 283 /* 284 * If host control register is not standard, exit 285 * this function 286 */ 287 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL) 288 return old_value; 289 290 /* DMA select is 22,23 bits in Protocol Control Register */ 291 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5; 292 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits; 293 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) | 294 (old_value & SDHCI_CTRL_DMA_MASK); 295 ret = (ret & (~0xff)) | tmp; 296 297 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */ 298 ret &= ~ESDHC_HOST_CONTROL_RES; 299 return ret; 300 } 301 302 ret = (old_value & (~(0xff << shift))) | (value << shift); 303 return ret; 304 } 305 306 static u32 esdhc_be_readl(struct sdhci_host *host, int reg) 307 { 308 u32 ret; 309 u32 value; 310 311 if (reg == SDHCI_CAPABILITIES_1) 312 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1); 313 else 314 value = ioread32be(host->ioaddr + reg); 315 316 ret = esdhc_readl_fixup(host, reg, value); 317 318 return ret; 319 } 320 321 static u32 esdhc_le_readl(struct sdhci_host *host, int reg) 322 { 323 u32 ret; 324 u32 value; 325 326 if (reg == SDHCI_CAPABILITIES_1) 327 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1); 328 else 329 value = ioread32(host->ioaddr + reg); 330 331 ret = esdhc_readl_fixup(host, reg, value); 332 333 return ret; 334 } 335 336 static u16 esdhc_be_readw(struct sdhci_host *host, int reg) 337 { 338 u16 ret; 339 u32 value; 340 int base = reg & ~0x3; 341 342 value = ioread32be(host->ioaddr + base); 343 ret = esdhc_readw_fixup(host, reg, value); 344 return ret; 345 } 346 347 static u16 esdhc_le_readw(struct sdhci_host *host, int reg) 348 { 349 u16 ret; 350 u32 value; 351 int base = reg & ~0x3; 352 353 value = ioread32(host->ioaddr + base); 354 ret = esdhc_readw_fixup(host, reg, value); 355 return ret; 356 } 357 358 static u8 esdhc_be_readb(struct sdhci_host *host, int reg) 359 { 360 u8 ret; 361 u32 value; 362 int base = reg & ~0x3; 363 364 value = ioread32be(host->ioaddr + base); 365 ret = esdhc_readb_fixup(host, reg, value); 366 return ret; 367 } 368 369 static u8 esdhc_le_readb(struct sdhci_host *host, int reg) 370 { 371 u8 ret; 372 u32 value; 373 int base = reg & ~0x3; 374 375 value = ioread32(host->ioaddr + base); 376 ret = esdhc_readb_fixup(host, reg, value); 377 return ret; 378 } 379 380 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) 381 { 382 u32 value; 383 384 value = esdhc_writel_fixup(host, reg, val, 0); 385 iowrite32be(value, host->ioaddr + reg); 386 } 387 388 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) 389 { 390 u32 value; 391 392 value = esdhc_writel_fixup(host, reg, val, 0); 393 iowrite32(value, host->ioaddr + reg); 394 } 395 396 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) 397 { 398 int base = reg & ~0x3; 399 u32 value; 400 u32 ret; 401 402 value = ioread32be(host->ioaddr + base); 403 ret = esdhc_writew_fixup(host, reg, val, value); 404 if (reg != SDHCI_TRANSFER_MODE) 405 iowrite32be(ret, host->ioaddr + base); 406 } 407 408 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) 409 { 410 int base = reg & ~0x3; 411 u32 value; 412 u32 ret; 413 414 value = ioread32(host->ioaddr + base); 415 ret = esdhc_writew_fixup(host, reg, val, value); 416 if (reg != SDHCI_TRANSFER_MODE) 417 iowrite32(ret, host->ioaddr + base); 418 } 419 420 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) 421 { 422 int base = reg & ~0x3; 423 u32 value; 424 u32 ret; 425 426 value = ioread32be(host->ioaddr + base); 427 ret = esdhc_writeb_fixup(host, reg, val, value); 428 iowrite32be(ret, host->ioaddr + base); 429 } 430 431 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) 432 { 433 int base = reg & ~0x3; 434 u32 value; 435 u32 ret; 436 437 value = ioread32(host->ioaddr + base); 438 ret = esdhc_writeb_fixup(host, reg, val, value); 439 iowrite32(ret, host->ioaddr + base); 440 } 441 442 /* 443 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA 444 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC]) 445 * and Block Gap Event(IRQSTAT[BGE]) are also set. 446 * For Continue, apply soft reset for data(SYSCTL[RSTD]); 447 * and re-issue the entire read transaction from beginning. 448 */ 449 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask) 450 { 451 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 452 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 453 bool applicable; 454 dma_addr_t dmastart; 455 dma_addr_t dmanow; 456 457 applicable = (intmask & SDHCI_INT_DATA_END) && 458 (intmask & SDHCI_INT_BLK_GAP) && 459 (esdhc->vendor_ver == VENDOR_V_23); 460 if (!applicable) 461 return; 462 463 host->data->error = 0; 464 dmastart = sg_dma_address(host->data->sg); 465 dmanow = dmastart + host->data->bytes_xfered; 466 /* 467 * Force update to the next DMA block boundary. 468 */ 469 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 470 SDHCI_DEFAULT_BOUNDARY_SIZE; 471 host->data->bytes_xfered = dmanow - dmastart; 472 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 473 } 474 475 static int esdhc_of_enable_dma(struct sdhci_host *host) 476 { 477 u32 value; 478 struct device *dev = mmc_dev(host->mmc); 479 480 if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") || 481 of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) 482 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); 483 484 value = sdhci_readl(host, ESDHC_DMA_SYSCTL); 485 value |= ESDHC_DMA_SNOOP; 486 sdhci_writel(host, value, ESDHC_DMA_SYSCTL); 487 return 0; 488 } 489 490 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) 491 { 492 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 493 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 494 495 if (esdhc->peripheral_clock) 496 return esdhc->peripheral_clock; 497 else 498 return pltfm_host->clock; 499 } 500 501 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) 502 { 503 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 504 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 505 unsigned int clock; 506 507 if (esdhc->peripheral_clock) 508 clock = esdhc->peripheral_clock; 509 else 510 clock = pltfm_host->clock; 511 return clock / 256 / 16; 512 } 513 514 static void esdhc_clock_enable(struct sdhci_host *host, bool enable) 515 { 516 u32 val; 517 ktime_t timeout; 518 519 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 520 521 if (enable) 522 val |= ESDHC_CLOCK_SDCLKEN; 523 else 524 val &= ~ESDHC_CLOCK_SDCLKEN; 525 526 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL); 527 528 /* Wait max 20 ms */ 529 timeout = ktime_add_ms(ktime_get(), 20); 530 val = ESDHC_CLOCK_STABLE; 531 while (!(sdhci_readl(host, ESDHC_PRSSTAT) & val)) { 532 if (ktime_after(ktime_get(), timeout)) { 533 pr_err("%s: Internal clock never stabilised.\n", 534 mmc_hostname(host->mmc)); 535 break; 536 } 537 udelay(10); 538 } 539 } 540 541 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) 542 { 543 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 544 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 545 int pre_div = 1; 546 int div = 1; 547 ktime_t timeout; 548 long fixup = 0; 549 u32 temp; 550 551 host->mmc->actual_clock = 0; 552 553 if (clock == 0) { 554 esdhc_clock_enable(host, false); 555 return; 556 } 557 558 /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */ 559 if (esdhc->vendor_ver < VENDOR_V_23) 560 pre_div = 2; 561 562 if (host->mmc->card && mmc_card_sd(host->mmc->card) && 563 esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY) 564 fixup = esdhc->clk_fixup->sd_dflt_max_clk; 565 else if (esdhc->clk_fixup) 566 fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing]; 567 568 if (fixup && clock > fixup) 569 clock = fixup; 570 571 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 572 temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | 573 ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK); 574 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 575 576 while (host->max_clk / pre_div / 16 > clock && pre_div < 256) 577 pre_div *= 2; 578 579 while (host->max_clk / pre_div / div > clock && div < 16) 580 div++; 581 582 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 583 clock, host->max_clk / pre_div / div); 584 host->mmc->actual_clock = host->max_clk / pre_div / div; 585 esdhc->div_ratio = pre_div * div; 586 pre_div >>= 1; 587 div--; 588 589 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 590 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 591 | (div << ESDHC_DIVIDER_SHIFT) 592 | (pre_div << ESDHC_PREDIV_SHIFT)); 593 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 594 595 /* Wait max 20 ms */ 596 timeout = ktime_add_ms(ktime_get(), 20); 597 while (!(sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)) { 598 if (ktime_after(ktime_get(), timeout)) { 599 pr_err("%s: Internal clock never stabilised.\n", 600 mmc_hostname(host->mmc)); 601 return; 602 } 603 udelay(10); 604 } 605 606 temp |= ESDHC_CLOCK_SDCLKEN; 607 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 608 } 609 610 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 611 { 612 u32 ctrl; 613 614 ctrl = sdhci_readl(host, ESDHC_PROCTL); 615 ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK); 616 switch (width) { 617 case MMC_BUS_WIDTH_8: 618 ctrl |= ESDHC_CTRL_8BITBUS; 619 break; 620 621 case MMC_BUS_WIDTH_4: 622 ctrl |= ESDHC_CTRL_4BITBUS; 623 break; 624 625 default: 626 break; 627 } 628 629 sdhci_writel(host, ctrl, ESDHC_PROCTL); 630 } 631 632 static void esdhc_reset(struct sdhci_host *host, u8 mask) 633 { 634 u32 val; 635 636 sdhci_reset(host, mask); 637 638 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 639 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 640 641 if (mask & SDHCI_RESET_ALL) { 642 val = sdhci_readl(host, ESDHC_TBCTL); 643 val &= ~ESDHC_TB_EN; 644 sdhci_writel(host, val, ESDHC_TBCTL); 645 } 646 } 647 648 /* The SCFG, Supplemental Configuration Unit, provides SoC specific 649 * configuration and status registers for the device. There is a 650 * SDHC IO VSEL control register on SCFG for some platforms. It's 651 * used to support SDHC IO voltage switching. 652 */ 653 static const struct of_device_id scfg_device_ids[] = { 654 { .compatible = "fsl,t1040-scfg", }, 655 { .compatible = "fsl,ls1012a-scfg", }, 656 { .compatible = "fsl,ls1046a-scfg", }, 657 {} 658 }; 659 660 /* SDHC IO VSEL control register definition */ 661 #define SCFG_SDHCIOVSELCR 0x408 662 #define SDHCIOVSELCR_TGLEN 0x80000000 663 #define SDHCIOVSELCR_VSELVAL 0x60000000 664 #define SDHCIOVSELCR_SDHC_VS 0x00000001 665 666 static int esdhc_signal_voltage_switch(struct mmc_host *mmc, 667 struct mmc_ios *ios) 668 { 669 struct sdhci_host *host = mmc_priv(mmc); 670 struct device_node *scfg_node; 671 void __iomem *scfg_base = NULL; 672 u32 sdhciovselcr; 673 u32 val; 674 675 /* 676 * Signal Voltage Switching is only applicable for Host Controllers 677 * v3.00 and above. 678 */ 679 if (host->version < SDHCI_SPEC_300) 680 return 0; 681 682 val = sdhci_readl(host, ESDHC_PROCTL); 683 684 switch (ios->signal_voltage) { 685 case MMC_SIGNAL_VOLTAGE_330: 686 val &= ~ESDHC_VOLT_SEL; 687 sdhci_writel(host, val, ESDHC_PROCTL); 688 return 0; 689 case MMC_SIGNAL_VOLTAGE_180: 690 scfg_node = of_find_matching_node(NULL, scfg_device_ids); 691 if (scfg_node) 692 scfg_base = of_iomap(scfg_node, 0); 693 if (scfg_base) { 694 sdhciovselcr = SDHCIOVSELCR_TGLEN | 695 SDHCIOVSELCR_VSELVAL; 696 iowrite32be(sdhciovselcr, 697 scfg_base + SCFG_SDHCIOVSELCR); 698 699 val |= ESDHC_VOLT_SEL; 700 sdhci_writel(host, val, ESDHC_PROCTL); 701 mdelay(5); 702 703 sdhciovselcr = SDHCIOVSELCR_TGLEN | 704 SDHCIOVSELCR_SDHC_VS; 705 iowrite32be(sdhciovselcr, 706 scfg_base + SCFG_SDHCIOVSELCR); 707 iounmap(scfg_base); 708 } else { 709 val |= ESDHC_VOLT_SEL; 710 sdhci_writel(host, val, ESDHC_PROCTL); 711 } 712 return 0; 713 default: 714 return 0; 715 } 716 } 717 718 static struct soc_device_attribute soc_fixup_tuning[] = { 719 { .family = "QorIQ T1040", .revision = "1.0", }, 720 { .family = "QorIQ T2080", .revision = "1.0", }, 721 { .family = "QorIQ T1023", .revision = "1.0", }, 722 { .family = "QorIQ LS1021A", .revision = "1.0", }, 723 { .family = "QorIQ LS1080A", .revision = "1.0", }, 724 { .family = "QorIQ LS2080A", .revision = "1.0", }, 725 { .family = "QorIQ LS1012A", .revision = "1.0", }, 726 { .family = "QorIQ LS1043A", .revision = "1.*", }, 727 { .family = "QorIQ LS1046A", .revision = "1.0", }, 728 { }, 729 }; 730 731 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 732 { 733 struct sdhci_host *host = mmc_priv(mmc); 734 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 735 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 736 u32 val; 737 738 /* Use tuning block for tuning procedure */ 739 esdhc_clock_enable(host, false); 740 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 741 val |= ESDHC_FLUSH_ASYNC_FIFO; 742 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 743 744 val = sdhci_readl(host, ESDHC_TBCTL); 745 val |= ESDHC_TB_EN; 746 sdhci_writel(host, val, ESDHC_TBCTL); 747 esdhc_clock_enable(host, true); 748 749 sdhci_execute_tuning(mmc, opcode); 750 if (host->tuning_err == -EAGAIN && esdhc->quirk_fixup_tuning) { 751 752 /* program TBPTR[TB_WNDW_END_PTR] = 3*DIV_RATIO and 753 * program TBPTR[TB_WNDW_START_PTR] = 5*DIV_RATIO 754 */ 755 val = sdhci_readl(host, ESDHC_TBPTR); 756 val = (val & ~((0x7f << 8) | 0x7f)) | 757 (3 * esdhc->div_ratio) | ((5 * esdhc->div_ratio) << 8); 758 sdhci_writel(host, val, ESDHC_TBPTR); 759 760 /* program the software tuning mode by setting 761 * TBCTL[TB_MODE]=2'h3 762 */ 763 val = sdhci_readl(host, ESDHC_TBCTL); 764 val |= 0x3; 765 sdhci_writel(host, val, ESDHC_TBCTL); 766 sdhci_execute_tuning(mmc, opcode); 767 } 768 return 0; 769 } 770 771 #ifdef CONFIG_PM_SLEEP 772 static u32 esdhc_proctl; 773 static int esdhc_of_suspend(struct device *dev) 774 { 775 struct sdhci_host *host = dev_get_drvdata(dev); 776 777 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL); 778 779 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 780 mmc_retune_needed(host->mmc); 781 782 return sdhci_suspend_host(host); 783 } 784 785 static int esdhc_of_resume(struct device *dev) 786 { 787 struct sdhci_host *host = dev_get_drvdata(dev); 788 int ret = sdhci_resume_host(host); 789 790 if (ret == 0) { 791 /* Isn't this already done by sdhci_resume_host() ? --rmk */ 792 esdhc_of_enable_dma(host); 793 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); 794 } 795 return ret; 796 } 797 #endif 798 799 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops, 800 esdhc_of_suspend, 801 esdhc_of_resume); 802 803 static const struct sdhci_ops sdhci_esdhc_be_ops = { 804 .read_l = esdhc_be_readl, 805 .read_w = esdhc_be_readw, 806 .read_b = esdhc_be_readb, 807 .write_l = esdhc_be_writel, 808 .write_w = esdhc_be_writew, 809 .write_b = esdhc_be_writeb, 810 .set_clock = esdhc_of_set_clock, 811 .enable_dma = esdhc_of_enable_dma, 812 .get_max_clock = esdhc_of_get_max_clock, 813 .get_min_clock = esdhc_of_get_min_clock, 814 .adma_workaround = esdhc_of_adma_workaround, 815 .set_bus_width = esdhc_pltfm_set_bus_width, 816 .reset = esdhc_reset, 817 .set_uhs_signaling = sdhci_set_uhs_signaling, 818 }; 819 820 static const struct sdhci_ops sdhci_esdhc_le_ops = { 821 .read_l = esdhc_le_readl, 822 .read_w = esdhc_le_readw, 823 .read_b = esdhc_le_readb, 824 .write_l = esdhc_le_writel, 825 .write_w = esdhc_le_writew, 826 .write_b = esdhc_le_writeb, 827 .set_clock = esdhc_of_set_clock, 828 .enable_dma = esdhc_of_enable_dma, 829 .get_max_clock = esdhc_of_get_max_clock, 830 .get_min_clock = esdhc_of_get_min_clock, 831 .adma_workaround = esdhc_of_adma_workaround, 832 .set_bus_width = esdhc_pltfm_set_bus_width, 833 .reset = esdhc_reset, 834 .set_uhs_signaling = sdhci_set_uhs_signaling, 835 }; 836 837 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = { 838 .quirks = ESDHC_DEFAULT_QUIRKS | 839 #ifdef CONFIG_PPC 840 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 841 #endif 842 SDHCI_QUIRK_NO_CARD_NO_RESET | 843 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 844 .ops = &sdhci_esdhc_be_ops, 845 }; 846 847 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = { 848 .quirks = ESDHC_DEFAULT_QUIRKS | 849 SDHCI_QUIRK_NO_CARD_NO_RESET | 850 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 851 .ops = &sdhci_esdhc_le_ops, 852 }; 853 854 static struct soc_device_attribute soc_incorrect_hostver[] = { 855 { .family = "QorIQ T4240", .revision = "1.0", }, 856 { .family = "QorIQ T4240", .revision = "2.0", }, 857 { }, 858 }; 859 860 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host) 861 { 862 const struct of_device_id *match; 863 struct sdhci_pltfm_host *pltfm_host; 864 struct sdhci_esdhc *esdhc; 865 struct device_node *np; 866 struct clk *clk; 867 u32 val; 868 u16 host_ver; 869 870 pltfm_host = sdhci_priv(host); 871 esdhc = sdhci_pltfm_priv(pltfm_host); 872 873 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); 874 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >> 875 SDHCI_VENDOR_VER_SHIFT; 876 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK; 877 if (soc_device_match(soc_incorrect_hostver)) 878 esdhc->quirk_incorrect_hostver = true; 879 else 880 esdhc->quirk_incorrect_hostver = false; 881 882 match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node); 883 if (match) 884 esdhc->clk_fixup = match->data; 885 np = pdev->dev.of_node; 886 clk = of_clk_get(np, 0); 887 if (!IS_ERR(clk)) { 888 /* 889 * esdhc->peripheral_clock would be assigned with a value 890 * which is eSDHC base clock when use periperal clock. 891 * For ls1046a, the clock value got by common clk API is 892 * peripheral clock while the eSDHC base clock is 1/2 893 * peripheral clock. 894 */ 895 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc")) 896 esdhc->peripheral_clock = clk_get_rate(clk) / 2; 897 else 898 esdhc->peripheral_clock = clk_get_rate(clk); 899 900 clk_put(clk); 901 } 902 903 if (esdhc->peripheral_clock) { 904 esdhc_clock_enable(host, false); 905 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 906 val |= ESDHC_PERIPHERAL_CLK_SEL; 907 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 908 esdhc_clock_enable(host, true); 909 } 910 } 911 912 static int sdhci_esdhc_probe(struct platform_device *pdev) 913 { 914 struct sdhci_host *host; 915 struct device_node *np; 916 struct sdhci_pltfm_host *pltfm_host; 917 struct sdhci_esdhc *esdhc; 918 int ret; 919 920 np = pdev->dev.of_node; 921 922 if (of_property_read_bool(np, "little-endian")) 923 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata, 924 sizeof(struct sdhci_esdhc)); 925 else 926 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata, 927 sizeof(struct sdhci_esdhc)); 928 929 if (IS_ERR(host)) 930 return PTR_ERR(host); 931 932 host->mmc_host_ops.start_signal_voltage_switch = 933 esdhc_signal_voltage_switch; 934 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning; 935 host->tuning_delay = 1; 936 937 esdhc_init(pdev, host); 938 939 sdhci_get_of_property(pdev); 940 941 pltfm_host = sdhci_priv(host); 942 esdhc = sdhci_pltfm_priv(pltfm_host); 943 if (soc_device_match(soc_fixup_tuning)) 944 esdhc->quirk_fixup_tuning = true; 945 else 946 esdhc->quirk_fixup_tuning = false; 947 948 if (esdhc->vendor_ver == VENDOR_V_22) 949 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; 950 951 if (esdhc->vendor_ver > VENDOR_V_22) 952 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 953 954 if (of_device_is_compatible(np, "fsl,p5040-esdhc") || 955 of_device_is_compatible(np, "fsl,p5020-esdhc") || 956 of_device_is_compatible(np, "fsl,p4080-esdhc") || 957 of_device_is_compatible(np, "fsl,p1020-esdhc") || 958 of_device_is_compatible(np, "fsl,t1040-esdhc")) 959 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 960 961 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc")) 962 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 963 964 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { 965 /* 966 * Freescale messed up with P2020 as it has a non-standard 967 * host control register 968 */ 969 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL; 970 } 971 972 /* call to generic mmc_of_parse to support additional capabilities */ 973 ret = mmc_of_parse(host->mmc); 974 if (ret) 975 goto err; 976 977 mmc_of_parse_voltage(np, &host->ocr_mask); 978 979 ret = sdhci_add_host(host); 980 if (ret) 981 goto err; 982 983 return 0; 984 err: 985 sdhci_pltfm_free(pdev); 986 return ret; 987 } 988 989 static struct platform_driver sdhci_esdhc_driver = { 990 .driver = { 991 .name = "sdhci-esdhc", 992 .of_match_table = sdhci_esdhc_of_match, 993 .pm = &esdhc_of_dev_pm_ops, 994 }, 995 .probe = sdhci_esdhc_probe, 996 .remove = sdhci_pltfm_unregister, 997 }; 998 999 module_platform_driver(sdhci_esdhc_driver); 1000 1001 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC"); 1002 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, " 1003 "Anton Vorontsov <avorontsov@ru.mvista.com>"); 1004 MODULE_LICENSE("GPL v2"); 1005