1 /* 2 * Freescale eSDHC controller driver. 3 * 4 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. 5 * Copyright (c) 2009 MontaVista Software, Inc. 6 * 7 * Authors: Xiaobo Xie <X.Xie@freescale.com> 8 * Anton Vorontsov <avorontsov@ru.mvista.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or (at 13 * your option) any later version. 14 */ 15 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/delay.h> 21 #include <linux/module.h> 22 #include <linux/sys_soc.h> 23 #include <linux/clk.h> 24 #include <linux/ktime.h> 25 #include <linux/mmc/host.h> 26 #include "sdhci-pltfm.h" 27 #include "sdhci-esdhc.h" 28 29 #define VENDOR_V_22 0x12 30 #define VENDOR_V_23 0x13 31 32 struct sdhci_esdhc { 33 u8 vendor_ver; 34 u8 spec_ver; 35 bool quirk_incorrect_hostver; 36 unsigned int peripheral_clock; 37 }; 38 39 /** 40 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register 41 * to make it compatible with SD spec. 42 * 43 * @host: pointer to sdhci_host 44 * @spec_reg: SD spec register address 45 * @value: 32bit eSDHC register value on spec_reg address 46 * 47 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 48 * registers are 32 bits. There are differences in register size, register 49 * address, register function, bit position and function between eSDHC spec 50 * and SD spec. 51 * 52 * Return a fixed up register value 53 */ 54 static u32 esdhc_readl_fixup(struct sdhci_host *host, 55 int spec_reg, u32 value) 56 { 57 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 58 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 59 u32 ret; 60 61 /* 62 * The bit of ADMA flag in eSDHC is not compatible with standard 63 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is 64 * supported by eSDHC. 65 * And for many FSL eSDHC controller, the reset value of field 66 * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA, 67 * only these vendor version is greater than 2.2/0x12 support ADMA. 68 */ 69 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) { 70 if (esdhc->vendor_ver > VENDOR_V_22) { 71 ret = value | SDHCI_CAN_DO_ADMA2; 72 return ret; 73 } 74 } 75 /* 76 * The DAT[3:0] line signal levels and the CMD line signal level are 77 * not compatible with standard SDHC register. The line signal levels 78 * DAT[7:0] are at bits 31:24 and the command line signal level is at 79 * bit 23. All other bits are the same as in the standard SDHC 80 * register. 81 */ 82 if (spec_reg == SDHCI_PRESENT_STATE) { 83 ret = value & 0x000fffff; 84 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK; 85 ret |= (value << 1) & SDHCI_CMD_LVL; 86 return ret; 87 } 88 89 /* 90 * DTS properties of mmc host are used to enable each speed mode 91 * according to soc and board capability. So clean up 92 * SDR50/SDR104/DDR50 support bits here. 93 */ 94 if (spec_reg == SDHCI_CAPABILITIES_1) { 95 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 96 SDHCI_SUPPORT_DDR50); 97 return ret; 98 } 99 100 ret = value; 101 return ret; 102 } 103 104 static u16 esdhc_readw_fixup(struct sdhci_host *host, 105 int spec_reg, u32 value) 106 { 107 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 108 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 109 u16 ret; 110 int shift = (spec_reg & 0x2) * 8; 111 112 if (spec_reg == SDHCI_HOST_VERSION) 113 ret = value & 0xffff; 114 else 115 ret = (value >> shift) & 0xffff; 116 /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect 117 * vendor version and spec version information. 118 */ 119 if ((spec_reg == SDHCI_HOST_VERSION) && 120 (esdhc->quirk_incorrect_hostver)) 121 ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200; 122 return ret; 123 } 124 125 static u8 esdhc_readb_fixup(struct sdhci_host *host, 126 int spec_reg, u32 value) 127 { 128 u8 ret; 129 u8 dma_bits; 130 int shift = (spec_reg & 0x3) * 8; 131 132 ret = (value >> shift) & 0xff; 133 134 /* 135 * "DMA select" locates at offset 0x28 in SD specification, but on 136 * P5020 or P3041, it locates at 0x29. 137 */ 138 if (spec_reg == SDHCI_HOST_CONTROL) { 139 /* DMA select is 22,23 bits in Protocol Control Register */ 140 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK; 141 /* fixup the result */ 142 ret &= ~SDHCI_CTRL_DMA_MASK; 143 ret |= dma_bits; 144 } 145 return ret; 146 } 147 148 /** 149 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be 150 * written into eSDHC register. 151 * 152 * @host: pointer to sdhci_host 153 * @spec_reg: SD spec register address 154 * @value: 8/16/32bit SD spec register value that would be written 155 * @old_value: 32bit eSDHC register value on spec_reg address 156 * 157 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 158 * registers are 32 bits. There are differences in register size, register 159 * address, register function, bit position and function between eSDHC spec 160 * and SD spec. 161 * 162 * Return a fixed up register value 163 */ 164 static u32 esdhc_writel_fixup(struct sdhci_host *host, 165 int spec_reg, u32 value, u32 old_value) 166 { 167 u32 ret; 168 169 /* 170 * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE] 171 * when SYSCTL[RSTD] is set for some special operations. 172 * No any impact on other operation. 173 */ 174 if (spec_reg == SDHCI_INT_ENABLE) 175 ret = value | SDHCI_INT_BLK_GAP; 176 else 177 ret = value; 178 179 return ret; 180 } 181 182 static u32 esdhc_writew_fixup(struct sdhci_host *host, 183 int spec_reg, u16 value, u32 old_value) 184 { 185 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 186 int shift = (spec_reg & 0x2) * 8; 187 u32 ret; 188 189 switch (spec_reg) { 190 case SDHCI_TRANSFER_MODE: 191 /* 192 * Postpone this write, we must do it together with a 193 * command write that is down below. Return old value. 194 */ 195 pltfm_host->xfer_mode_shadow = value; 196 return old_value; 197 case SDHCI_COMMAND: 198 ret = (value << 16) | pltfm_host->xfer_mode_shadow; 199 return ret; 200 } 201 202 ret = old_value & (~(0xffff << shift)); 203 ret |= (value << shift); 204 205 if (spec_reg == SDHCI_BLOCK_SIZE) { 206 /* 207 * Two last DMA bits are reserved, and first one is used for 208 * non-standard blksz of 4096 bytes that we don't support 209 * yet. So clear the DMA boundary bits. 210 */ 211 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0)); 212 } 213 return ret; 214 } 215 216 static u32 esdhc_writeb_fixup(struct sdhci_host *host, 217 int spec_reg, u8 value, u32 old_value) 218 { 219 u32 ret; 220 u32 dma_bits; 221 u8 tmp; 222 int shift = (spec_reg & 0x3) * 8; 223 224 /* 225 * eSDHC doesn't have a standard power control register, so we do 226 * nothing here to avoid incorrect operation. 227 */ 228 if (spec_reg == SDHCI_POWER_CONTROL) 229 return old_value; 230 /* 231 * "DMA select" location is offset 0x28 in SD specification, but on 232 * P5020 or P3041, it's located at 0x29. 233 */ 234 if (spec_reg == SDHCI_HOST_CONTROL) { 235 /* 236 * If host control register is not standard, exit 237 * this function 238 */ 239 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL) 240 return old_value; 241 242 /* DMA select is 22,23 bits in Protocol Control Register */ 243 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5; 244 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits; 245 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) | 246 (old_value & SDHCI_CTRL_DMA_MASK); 247 ret = (ret & (~0xff)) | tmp; 248 249 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */ 250 ret &= ~ESDHC_HOST_CONTROL_RES; 251 return ret; 252 } 253 254 ret = (old_value & (~(0xff << shift))) | (value << shift); 255 return ret; 256 } 257 258 static u32 esdhc_be_readl(struct sdhci_host *host, int reg) 259 { 260 u32 ret; 261 u32 value; 262 263 if (reg == SDHCI_CAPABILITIES_1) 264 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1); 265 else 266 value = ioread32be(host->ioaddr + reg); 267 268 ret = esdhc_readl_fixup(host, reg, value); 269 270 return ret; 271 } 272 273 static u32 esdhc_le_readl(struct sdhci_host *host, int reg) 274 { 275 u32 ret; 276 u32 value; 277 278 if (reg == SDHCI_CAPABILITIES_1) 279 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1); 280 else 281 value = ioread32(host->ioaddr + reg); 282 283 ret = esdhc_readl_fixup(host, reg, value); 284 285 return ret; 286 } 287 288 static u16 esdhc_be_readw(struct sdhci_host *host, int reg) 289 { 290 u16 ret; 291 u32 value; 292 int base = reg & ~0x3; 293 294 value = ioread32be(host->ioaddr + base); 295 ret = esdhc_readw_fixup(host, reg, value); 296 return ret; 297 } 298 299 static u16 esdhc_le_readw(struct sdhci_host *host, int reg) 300 { 301 u16 ret; 302 u32 value; 303 int base = reg & ~0x3; 304 305 value = ioread32(host->ioaddr + base); 306 ret = esdhc_readw_fixup(host, reg, value); 307 return ret; 308 } 309 310 static u8 esdhc_be_readb(struct sdhci_host *host, int reg) 311 { 312 u8 ret; 313 u32 value; 314 int base = reg & ~0x3; 315 316 value = ioread32be(host->ioaddr + base); 317 ret = esdhc_readb_fixup(host, reg, value); 318 return ret; 319 } 320 321 static u8 esdhc_le_readb(struct sdhci_host *host, int reg) 322 { 323 u8 ret; 324 u32 value; 325 int base = reg & ~0x3; 326 327 value = ioread32(host->ioaddr + base); 328 ret = esdhc_readb_fixup(host, reg, value); 329 return ret; 330 } 331 332 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) 333 { 334 u32 value; 335 336 value = esdhc_writel_fixup(host, reg, val, 0); 337 iowrite32be(value, host->ioaddr + reg); 338 } 339 340 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) 341 { 342 u32 value; 343 344 value = esdhc_writel_fixup(host, reg, val, 0); 345 iowrite32(value, host->ioaddr + reg); 346 } 347 348 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) 349 { 350 int base = reg & ~0x3; 351 u32 value; 352 u32 ret; 353 354 value = ioread32be(host->ioaddr + base); 355 ret = esdhc_writew_fixup(host, reg, val, value); 356 if (reg != SDHCI_TRANSFER_MODE) 357 iowrite32be(ret, host->ioaddr + base); 358 } 359 360 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) 361 { 362 int base = reg & ~0x3; 363 u32 value; 364 u32 ret; 365 366 value = ioread32(host->ioaddr + base); 367 ret = esdhc_writew_fixup(host, reg, val, value); 368 if (reg != SDHCI_TRANSFER_MODE) 369 iowrite32(ret, host->ioaddr + base); 370 } 371 372 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) 373 { 374 int base = reg & ~0x3; 375 u32 value; 376 u32 ret; 377 378 value = ioread32be(host->ioaddr + base); 379 ret = esdhc_writeb_fixup(host, reg, val, value); 380 iowrite32be(ret, host->ioaddr + base); 381 } 382 383 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) 384 { 385 int base = reg & ~0x3; 386 u32 value; 387 u32 ret; 388 389 value = ioread32(host->ioaddr + base); 390 ret = esdhc_writeb_fixup(host, reg, val, value); 391 iowrite32(ret, host->ioaddr + base); 392 } 393 394 /* 395 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA 396 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC]) 397 * and Block Gap Event(IRQSTAT[BGE]) are also set. 398 * For Continue, apply soft reset for data(SYSCTL[RSTD]); 399 * and re-issue the entire read transaction from beginning. 400 */ 401 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask) 402 { 403 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 404 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 405 bool applicable; 406 dma_addr_t dmastart; 407 dma_addr_t dmanow; 408 409 applicable = (intmask & SDHCI_INT_DATA_END) && 410 (intmask & SDHCI_INT_BLK_GAP) && 411 (esdhc->vendor_ver == VENDOR_V_23); 412 if (!applicable) 413 return; 414 415 host->data->error = 0; 416 dmastart = sg_dma_address(host->data->sg); 417 dmanow = dmastart + host->data->bytes_xfered; 418 /* 419 * Force update to the next DMA block boundary. 420 */ 421 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 422 SDHCI_DEFAULT_BOUNDARY_SIZE; 423 host->data->bytes_xfered = dmanow - dmastart; 424 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 425 } 426 427 static int esdhc_of_enable_dma(struct sdhci_host *host) 428 { 429 u32 value; 430 431 value = sdhci_readl(host, ESDHC_DMA_SYSCTL); 432 value |= ESDHC_DMA_SNOOP; 433 sdhci_writel(host, value, ESDHC_DMA_SYSCTL); 434 return 0; 435 } 436 437 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) 438 { 439 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 440 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 441 442 if (esdhc->peripheral_clock) 443 return esdhc->peripheral_clock; 444 else 445 return pltfm_host->clock; 446 } 447 448 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) 449 { 450 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 451 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 452 unsigned int clock; 453 454 if (esdhc->peripheral_clock) 455 clock = esdhc->peripheral_clock; 456 else 457 clock = pltfm_host->clock; 458 return clock / 256 / 16; 459 } 460 461 static void esdhc_clock_enable(struct sdhci_host *host, bool enable) 462 { 463 u32 val; 464 ktime_t timeout; 465 466 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 467 468 if (enable) 469 val |= ESDHC_CLOCK_SDCLKEN; 470 else 471 val &= ~ESDHC_CLOCK_SDCLKEN; 472 473 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL); 474 475 /* Wait max 20 ms */ 476 timeout = ktime_add_ms(ktime_get(), 20); 477 val = ESDHC_CLOCK_STABLE; 478 while (!(sdhci_readl(host, ESDHC_PRSSTAT) & val)) { 479 if (ktime_after(ktime_get(), timeout)) { 480 pr_err("%s: Internal clock never stabilised.\n", 481 mmc_hostname(host->mmc)); 482 break; 483 } 484 udelay(10); 485 } 486 } 487 488 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) 489 { 490 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 491 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 492 int pre_div = 1; 493 int div = 1; 494 ktime_t timeout; 495 u32 temp; 496 497 host->mmc->actual_clock = 0; 498 499 if (clock == 0) { 500 esdhc_clock_enable(host, false); 501 return; 502 } 503 504 /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */ 505 if (esdhc->vendor_ver < VENDOR_V_23) 506 pre_div = 2; 507 508 /* 509 * Limit SD clock to 167MHz for ls1046a according to its datasheet 510 */ 511 if (clock > 167000000 && 512 of_find_compatible_node(NULL, NULL, "fsl,ls1046a-esdhc")) 513 clock = 167000000; 514 515 /* 516 * Limit SD clock to 125MHz for ls1012a according to its datasheet 517 */ 518 if (clock > 125000000 && 519 of_find_compatible_node(NULL, NULL, "fsl,ls1012a-esdhc")) 520 clock = 125000000; 521 522 /* Workaround to reduce the clock frequency for p1010 esdhc */ 523 if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) { 524 if (clock > 20000000) 525 clock -= 5000000; 526 if (clock > 40000000) 527 clock -= 5000000; 528 } 529 530 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 531 temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | 532 ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK); 533 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 534 535 while (host->max_clk / pre_div / 16 > clock && pre_div < 256) 536 pre_div *= 2; 537 538 while (host->max_clk / pre_div / div > clock && div < 16) 539 div++; 540 541 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 542 clock, host->max_clk / pre_div / div); 543 host->mmc->actual_clock = host->max_clk / pre_div / div; 544 pre_div >>= 1; 545 div--; 546 547 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 548 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 549 | (div << ESDHC_DIVIDER_SHIFT) 550 | (pre_div << ESDHC_PREDIV_SHIFT)); 551 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 552 553 /* Wait max 20 ms */ 554 timeout = ktime_add_ms(ktime_get(), 20); 555 while (!(sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)) { 556 if (ktime_after(ktime_get(), timeout)) { 557 pr_err("%s: Internal clock never stabilised.\n", 558 mmc_hostname(host->mmc)); 559 return; 560 } 561 udelay(10); 562 } 563 564 temp |= ESDHC_CLOCK_SDCLKEN; 565 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 566 } 567 568 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 569 { 570 u32 ctrl; 571 572 ctrl = sdhci_readl(host, ESDHC_PROCTL); 573 ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK); 574 switch (width) { 575 case MMC_BUS_WIDTH_8: 576 ctrl |= ESDHC_CTRL_8BITBUS; 577 break; 578 579 case MMC_BUS_WIDTH_4: 580 ctrl |= ESDHC_CTRL_4BITBUS; 581 break; 582 583 default: 584 break; 585 } 586 587 sdhci_writel(host, ctrl, ESDHC_PROCTL); 588 } 589 590 static void esdhc_reset(struct sdhci_host *host, u8 mask) 591 { 592 sdhci_reset(host, mask); 593 594 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 595 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 596 } 597 598 /* The SCFG, Supplemental Configuration Unit, provides SoC specific 599 * configuration and status registers for the device. There is a 600 * SDHC IO VSEL control register on SCFG for some platforms. It's 601 * used to support SDHC IO voltage switching. 602 */ 603 static const struct of_device_id scfg_device_ids[] = { 604 { .compatible = "fsl,t1040-scfg", }, 605 { .compatible = "fsl,ls1012a-scfg", }, 606 { .compatible = "fsl,ls1046a-scfg", }, 607 {} 608 }; 609 610 /* SDHC IO VSEL control register definition */ 611 #define SCFG_SDHCIOVSELCR 0x408 612 #define SDHCIOVSELCR_TGLEN 0x80000000 613 #define SDHCIOVSELCR_VSELVAL 0x60000000 614 #define SDHCIOVSELCR_SDHC_VS 0x00000001 615 616 static int esdhc_signal_voltage_switch(struct mmc_host *mmc, 617 struct mmc_ios *ios) 618 { 619 struct sdhci_host *host = mmc_priv(mmc); 620 struct device_node *scfg_node; 621 void __iomem *scfg_base = NULL; 622 u32 sdhciovselcr; 623 u32 val; 624 625 /* 626 * Signal Voltage Switching is only applicable for Host Controllers 627 * v3.00 and above. 628 */ 629 if (host->version < SDHCI_SPEC_300) 630 return 0; 631 632 val = sdhci_readl(host, ESDHC_PROCTL); 633 634 switch (ios->signal_voltage) { 635 case MMC_SIGNAL_VOLTAGE_330: 636 val &= ~ESDHC_VOLT_SEL; 637 sdhci_writel(host, val, ESDHC_PROCTL); 638 return 0; 639 case MMC_SIGNAL_VOLTAGE_180: 640 scfg_node = of_find_matching_node(NULL, scfg_device_ids); 641 if (scfg_node) 642 scfg_base = of_iomap(scfg_node, 0); 643 if (scfg_base) { 644 sdhciovselcr = SDHCIOVSELCR_TGLEN | 645 SDHCIOVSELCR_VSELVAL; 646 iowrite32be(sdhciovselcr, 647 scfg_base + SCFG_SDHCIOVSELCR); 648 649 val |= ESDHC_VOLT_SEL; 650 sdhci_writel(host, val, ESDHC_PROCTL); 651 mdelay(5); 652 653 sdhciovselcr = SDHCIOVSELCR_TGLEN | 654 SDHCIOVSELCR_SDHC_VS; 655 iowrite32be(sdhciovselcr, 656 scfg_base + SCFG_SDHCIOVSELCR); 657 iounmap(scfg_base); 658 } else { 659 val |= ESDHC_VOLT_SEL; 660 sdhci_writel(host, val, ESDHC_PROCTL); 661 } 662 return 0; 663 default: 664 return 0; 665 } 666 } 667 668 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 669 { 670 struct sdhci_host *host = mmc_priv(mmc); 671 u32 val; 672 673 /* Use tuning block for tuning procedure */ 674 esdhc_clock_enable(host, false); 675 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 676 val |= ESDHC_FLUSH_ASYNC_FIFO; 677 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 678 679 val = sdhci_readl(host, ESDHC_TBCTL); 680 val |= ESDHC_TB_EN; 681 sdhci_writel(host, val, ESDHC_TBCTL); 682 esdhc_clock_enable(host, true); 683 684 return sdhci_execute_tuning(mmc, opcode); 685 } 686 687 #ifdef CONFIG_PM_SLEEP 688 static u32 esdhc_proctl; 689 static int esdhc_of_suspend(struct device *dev) 690 { 691 struct sdhci_host *host = dev_get_drvdata(dev); 692 693 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL); 694 695 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 696 mmc_retune_needed(host->mmc); 697 698 return sdhci_suspend_host(host); 699 } 700 701 static int esdhc_of_resume(struct device *dev) 702 { 703 struct sdhci_host *host = dev_get_drvdata(dev); 704 int ret = sdhci_resume_host(host); 705 706 if (ret == 0) { 707 /* Isn't this already done by sdhci_resume_host() ? --rmk */ 708 esdhc_of_enable_dma(host); 709 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); 710 } 711 return ret; 712 } 713 #endif 714 715 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops, 716 esdhc_of_suspend, 717 esdhc_of_resume); 718 719 static const struct sdhci_ops sdhci_esdhc_be_ops = { 720 .read_l = esdhc_be_readl, 721 .read_w = esdhc_be_readw, 722 .read_b = esdhc_be_readb, 723 .write_l = esdhc_be_writel, 724 .write_w = esdhc_be_writew, 725 .write_b = esdhc_be_writeb, 726 .set_clock = esdhc_of_set_clock, 727 .enable_dma = esdhc_of_enable_dma, 728 .get_max_clock = esdhc_of_get_max_clock, 729 .get_min_clock = esdhc_of_get_min_clock, 730 .adma_workaround = esdhc_of_adma_workaround, 731 .set_bus_width = esdhc_pltfm_set_bus_width, 732 .reset = esdhc_reset, 733 .set_uhs_signaling = sdhci_set_uhs_signaling, 734 }; 735 736 static const struct sdhci_ops sdhci_esdhc_le_ops = { 737 .read_l = esdhc_le_readl, 738 .read_w = esdhc_le_readw, 739 .read_b = esdhc_le_readb, 740 .write_l = esdhc_le_writel, 741 .write_w = esdhc_le_writew, 742 .write_b = esdhc_le_writeb, 743 .set_clock = esdhc_of_set_clock, 744 .enable_dma = esdhc_of_enable_dma, 745 .get_max_clock = esdhc_of_get_max_clock, 746 .get_min_clock = esdhc_of_get_min_clock, 747 .adma_workaround = esdhc_of_adma_workaround, 748 .set_bus_width = esdhc_pltfm_set_bus_width, 749 .reset = esdhc_reset, 750 .set_uhs_signaling = sdhci_set_uhs_signaling, 751 }; 752 753 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = { 754 .quirks = ESDHC_DEFAULT_QUIRKS | 755 #ifdef CONFIG_PPC 756 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 757 #endif 758 SDHCI_QUIRK_NO_CARD_NO_RESET | 759 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 760 .ops = &sdhci_esdhc_be_ops, 761 }; 762 763 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = { 764 .quirks = ESDHC_DEFAULT_QUIRKS | 765 SDHCI_QUIRK_NO_CARD_NO_RESET | 766 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 767 .ops = &sdhci_esdhc_le_ops, 768 }; 769 770 static struct soc_device_attribute soc_incorrect_hostver[] = { 771 { .family = "QorIQ T4240", .revision = "1.0", }, 772 { .family = "QorIQ T4240", .revision = "2.0", }, 773 { }, 774 }; 775 776 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host) 777 { 778 struct sdhci_pltfm_host *pltfm_host; 779 struct sdhci_esdhc *esdhc; 780 struct device_node *np; 781 struct clk *clk; 782 u32 val; 783 u16 host_ver; 784 785 pltfm_host = sdhci_priv(host); 786 esdhc = sdhci_pltfm_priv(pltfm_host); 787 788 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); 789 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >> 790 SDHCI_VENDOR_VER_SHIFT; 791 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK; 792 if (soc_device_match(soc_incorrect_hostver)) 793 esdhc->quirk_incorrect_hostver = true; 794 else 795 esdhc->quirk_incorrect_hostver = false; 796 797 np = pdev->dev.of_node; 798 clk = of_clk_get(np, 0); 799 if (!IS_ERR(clk)) { 800 /* 801 * esdhc->peripheral_clock would be assigned with a value 802 * which is eSDHC base clock when use periperal clock. 803 * For ls1046a, the clock value got by common clk API is 804 * peripheral clock while the eSDHC base clock is 1/2 805 * peripheral clock. 806 */ 807 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc")) 808 esdhc->peripheral_clock = clk_get_rate(clk) / 2; 809 else 810 esdhc->peripheral_clock = clk_get_rate(clk); 811 812 clk_put(clk); 813 } 814 815 if (esdhc->peripheral_clock) { 816 esdhc_clock_enable(host, false); 817 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 818 val |= ESDHC_PERIPHERAL_CLK_SEL; 819 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 820 esdhc_clock_enable(host, true); 821 } 822 } 823 824 static int sdhci_esdhc_probe(struct platform_device *pdev) 825 { 826 struct sdhci_host *host; 827 struct device_node *np; 828 struct sdhci_pltfm_host *pltfm_host; 829 struct sdhci_esdhc *esdhc; 830 int ret; 831 832 np = pdev->dev.of_node; 833 834 if (of_property_read_bool(np, "little-endian")) 835 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata, 836 sizeof(struct sdhci_esdhc)); 837 else 838 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata, 839 sizeof(struct sdhci_esdhc)); 840 841 if (IS_ERR(host)) 842 return PTR_ERR(host); 843 844 host->mmc_host_ops.start_signal_voltage_switch = 845 esdhc_signal_voltage_switch; 846 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning; 847 host->tuning_delay = 1; 848 849 esdhc_init(pdev, host); 850 851 sdhci_get_of_property(pdev); 852 853 pltfm_host = sdhci_priv(host); 854 esdhc = sdhci_pltfm_priv(pltfm_host); 855 if (esdhc->vendor_ver == VENDOR_V_22) 856 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; 857 858 if (esdhc->vendor_ver > VENDOR_V_22) 859 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 860 861 if (of_device_is_compatible(np, "fsl,p5040-esdhc") || 862 of_device_is_compatible(np, "fsl,p5020-esdhc") || 863 of_device_is_compatible(np, "fsl,p4080-esdhc") || 864 of_device_is_compatible(np, "fsl,p1020-esdhc") || 865 of_device_is_compatible(np, "fsl,t1040-esdhc")) 866 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 867 868 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc")) 869 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 870 871 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { 872 /* 873 * Freescale messed up with P2020 as it has a non-standard 874 * host control register 875 */ 876 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL; 877 } 878 879 /* call to generic mmc_of_parse to support additional capabilities */ 880 ret = mmc_of_parse(host->mmc); 881 if (ret) 882 goto err; 883 884 mmc_of_parse_voltage(np, &host->ocr_mask); 885 886 ret = sdhci_add_host(host); 887 if (ret) 888 goto err; 889 890 return 0; 891 err: 892 sdhci_pltfm_free(pdev); 893 return ret; 894 } 895 896 static const struct of_device_id sdhci_esdhc_of_match[] = { 897 { .compatible = "fsl,mpc8379-esdhc" }, 898 { .compatible = "fsl,mpc8536-esdhc" }, 899 { .compatible = "fsl,esdhc" }, 900 { } 901 }; 902 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); 903 904 static struct platform_driver sdhci_esdhc_driver = { 905 .driver = { 906 .name = "sdhci-esdhc", 907 .of_match_table = sdhci_esdhc_of_match, 908 .pm = &esdhc_of_dev_pm_ops, 909 }, 910 .probe = sdhci_esdhc_probe, 911 .remove = sdhci_pltfm_unregister, 912 }; 913 914 module_platform_driver(sdhci_esdhc_driver); 915 916 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC"); 917 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, " 918 "Anton Vorontsov <avorontsov@ru.mvista.com>"); 919 MODULE_LICENSE("GPL v2"); 920