1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Freescale eSDHC controller driver. 4 * 5 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. 6 * Copyright (c) 2009 MontaVista Software, Inc. 7 * 8 * Authors: Xiaobo Xie <X.Xie@freescale.com> 9 * Anton Vorontsov <avorontsov@ru.mvista.com> 10 */ 11 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/delay.h> 17 #include <linux/module.h> 18 #include <linux/sys_soc.h> 19 #include <linux/clk.h> 20 #include <linux/ktime.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include "sdhci-pltfm.h" 25 #include "sdhci-esdhc.h" 26 27 #define VENDOR_V_22 0x12 28 #define VENDOR_V_23 0x13 29 30 #define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1) 31 32 struct esdhc_clk_fixup { 33 const unsigned int sd_dflt_max_clk; 34 const unsigned int max_clk[MMC_TIMING_NUM]; 35 }; 36 37 static const struct esdhc_clk_fixup ls1021a_esdhc_clk = { 38 .sd_dflt_max_clk = 25000000, 39 .max_clk[MMC_TIMING_MMC_HS] = 46500000, 40 .max_clk[MMC_TIMING_SD_HS] = 46500000, 41 }; 42 43 static const struct esdhc_clk_fixup ls1046a_esdhc_clk = { 44 .sd_dflt_max_clk = 25000000, 45 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000, 46 .max_clk[MMC_TIMING_MMC_HS200] = 167000000, 47 }; 48 49 static const struct esdhc_clk_fixup ls1012a_esdhc_clk = { 50 .sd_dflt_max_clk = 25000000, 51 .max_clk[MMC_TIMING_UHS_SDR104] = 125000000, 52 .max_clk[MMC_TIMING_MMC_HS200] = 125000000, 53 }; 54 55 static const struct esdhc_clk_fixup p1010_esdhc_clk = { 56 .sd_dflt_max_clk = 20000000, 57 .max_clk[MMC_TIMING_LEGACY] = 20000000, 58 .max_clk[MMC_TIMING_MMC_HS] = 42000000, 59 .max_clk[MMC_TIMING_SD_HS] = 40000000, 60 }; 61 62 static const struct of_device_id sdhci_esdhc_of_match[] = { 63 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk}, 64 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk}, 65 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk}, 66 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk}, 67 { .compatible = "fsl,mpc8379-esdhc" }, 68 { .compatible = "fsl,mpc8536-esdhc" }, 69 { .compatible = "fsl,esdhc" }, 70 { } 71 }; 72 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); 73 74 struct sdhci_esdhc { 75 u8 vendor_ver; 76 u8 spec_ver; 77 bool quirk_incorrect_hostver; 78 bool quirk_limited_clk_division; 79 bool quirk_unreliable_pulse_detection; 80 bool quirk_tuning_erratum_type1; 81 bool quirk_tuning_erratum_type2; 82 bool quirk_ignore_data_inhibit; 83 bool quirk_delay_before_data_reset; 84 bool in_sw_tuning; 85 unsigned int peripheral_clock; 86 const struct esdhc_clk_fixup *clk_fixup; 87 u32 div_ratio; 88 }; 89 90 /** 91 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register 92 * to make it compatible with SD spec. 93 * 94 * @host: pointer to sdhci_host 95 * @spec_reg: SD spec register address 96 * @value: 32bit eSDHC register value on spec_reg address 97 * 98 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 99 * registers are 32 bits. There are differences in register size, register 100 * address, register function, bit position and function between eSDHC spec 101 * and SD spec. 102 * 103 * Return a fixed up register value 104 */ 105 static u32 esdhc_readl_fixup(struct sdhci_host *host, 106 int spec_reg, u32 value) 107 { 108 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 109 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 110 u32 ret; 111 112 /* 113 * The bit of ADMA flag in eSDHC is not compatible with standard 114 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is 115 * supported by eSDHC. 116 * And for many FSL eSDHC controller, the reset value of field 117 * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA, 118 * only these vendor version is greater than 2.2/0x12 support ADMA. 119 */ 120 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) { 121 if (esdhc->vendor_ver > VENDOR_V_22) { 122 ret = value | SDHCI_CAN_DO_ADMA2; 123 return ret; 124 } 125 } 126 /* 127 * The DAT[3:0] line signal levels and the CMD line signal level are 128 * not compatible with standard SDHC register. The line signal levels 129 * DAT[7:0] are at bits 31:24 and the command line signal level is at 130 * bit 23. All other bits are the same as in the standard SDHC 131 * register. 132 */ 133 if (spec_reg == SDHCI_PRESENT_STATE) { 134 ret = value & 0x000fffff; 135 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK; 136 ret |= (value << 1) & SDHCI_CMD_LVL; 137 return ret; 138 } 139 140 /* 141 * DTS properties of mmc host are used to enable each speed mode 142 * according to soc and board capability. So clean up 143 * SDR50/SDR104/DDR50 support bits here. 144 */ 145 if (spec_reg == SDHCI_CAPABILITIES_1) { 146 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 147 SDHCI_SUPPORT_DDR50); 148 return ret; 149 } 150 151 /* 152 * Some controllers have unreliable Data Line Active 153 * bit for commands with busy signal. This affects 154 * Command Inhibit (data) bit. Just ignore it since 155 * MMC core driver has already polled card status 156 * with CMD13 after any command with busy siganl. 157 */ 158 if ((spec_reg == SDHCI_PRESENT_STATE) && 159 (esdhc->quirk_ignore_data_inhibit == true)) { 160 ret = value & ~SDHCI_DATA_INHIBIT; 161 return ret; 162 } 163 164 ret = value; 165 return ret; 166 } 167 168 static u16 esdhc_readw_fixup(struct sdhci_host *host, 169 int spec_reg, u32 value) 170 { 171 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 172 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 173 u16 ret; 174 int shift = (spec_reg & 0x2) * 8; 175 176 if (spec_reg == SDHCI_HOST_VERSION) 177 ret = value & 0xffff; 178 else 179 ret = (value >> shift) & 0xffff; 180 /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect 181 * vendor version and spec version information. 182 */ 183 if ((spec_reg == SDHCI_HOST_VERSION) && 184 (esdhc->quirk_incorrect_hostver)) 185 ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200; 186 return ret; 187 } 188 189 static u8 esdhc_readb_fixup(struct sdhci_host *host, 190 int spec_reg, u32 value) 191 { 192 u8 ret; 193 u8 dma_bits; 194 int shift = (spec_reg & 0x3) * 8; 195 196 ret = (value >> shift) & 0xff; 197 198 /* 199 * "DMA select" locates at offset 0x28 in SD specification, but on 200 * P5020 or P3041, it locates at 0x29. 201 */ 202 if (spec_reg == SDHCI_HOST_CONTROL) { 203 /* DMA select is 22,23 bits in Protocol Control Register */ 204 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK; 205 /* fixup the result */ 206 ret &= ~SDHCI_CTRL_DMA_MASK; 207 ret |= dma_bits; 208 } 209 return ret; 210 } 211 212 /** 213 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be 214 * written into eSDHC register. 215 * 216 * @host: pointer to sdhci_host 217 * @spec_reg: SD spec register address 218 * @value: 8/16/32bit SD spec register value that would be written 219 * @old_value: 32bit eSDHC register value on spec_reg address 220 * 221 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 222 * registers are 32 bits. There are differences in register size, register 223 * address, register function, bit position and function between eSDHC spec 224 * and SD spec. 225 * 226 * Return a fixed up register value 227 */ 228 static u32 esdhc_writel_fixup(struct sdhci_host *host, 229 int spec_reg, u32 value, u32 old_value) 230 { 231 u32 ret; 232 233 /* 234 * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE] 235 * when SYSCTL[RSTD] is set for some special operations. 236 * No any impact on other operation. 237 */ 238 if (spec_reg == SDHCI_INT_ENABLE) 239 ret = value | SDHCI_INT_BLK_GAP; 240 else 241 ret = value; 242 243 return ret; 244 } 245 246 static u32 esdhc_writew_fixup(struct sdhci_host *host, 247 int spec_reg, u16 value, u32 old_value) 248 { 249 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 250 int shift = (spec_reg & 0x2) * 8; 251 u32 ret; 252 253 switch (spec_reg) { 254 case SDHCI_TRANSFER_MODE: 255 /* 256 * Postpone this write, we must do it together with a 257 * command write that is down below. Return old value. 258 */ 259 pltfm_host->xfer_mode_shadow = value; 260 return old_value; 261 case SDHCI_COMMAND: 262 ret = (value << 16) | pltfm_host->xfer_mode_shadow; 263 return ret; 264 } 265 266 ret = old_value & (~(0xffff << shift)); 267 ret |= (value << shift); 268 269 if (spec_reg == SDHCI_BLOCK_SIZE) { 270 /* 271 * Two last DMA bits are reserved, and first one is used for 272 * non-standard blksz of 4096 bytes that we don't support 273 * yet. So clear the DMA boundary bits. 274 */ 275 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0)); 276 } 277 return ret; 278 } 279 280 static u32 esdhc_writeb_fixup(struct sdhci_host *host, 281 int spec_reg, u8 value, u32 old_value) 282 { 283 u32 ret; 284 u32 dma_bits; 285 u8 tmp; 286 int shift = (spec_reg & 0x3) * 8; 287 288 /* 289 * eSDHC doesn't have a standard power control register, so we do 290 * nothing here to avoid incorrect operation. 291 */ 292 if (spec_reg == SDHCI_POWER_CONTROL) 293 return old_value; 294 /* 295 * "DMA select" location is offset 0x28 in SD specification, but on 296 * P5020 or P3041, it's located at 0x29. 297 */ 298 if (spec_reg == SDHCI_HOST_CONTROL) { 299 /* 300 * If host control register is not standard, exit 301 * this function 302 */ 303 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL) 304 return old_value; 305 306 /* DMA select is 22,23 bits in Protocol Control Register */ 307 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5; 308 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits; 309 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) | 310 (old_value & SDHCI_CTRL_DMA_MASK); 311 ret = (ret & (~0xff)) | tmp; 312 313 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */ 314 ret &= ~ESDHC_HOST_CONTROL_RES; 315 return ret; 316 } 317 318 ret = (old_value & (~(0xff << shift))) | (value << shift); 319 return ret; 320 } 321 322 static u32 esdhc_be_readl(struct sdhci_host *host, int reg) 323 { 324 u32 ret; 325 u32 value; 326 327 if (reg == SDHCI_CAPABILITIES_1) 328 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1); 329 else 330 value = ioread32be(host->ioaddr + reg); 331 332 ret = esdhc_readl_fixup(host, reg, value); 333 334 return ret; 335 } 336 337 static u32 esdhc_le_readl(struct sdhci_host *host, int reg) 338 { 339 u32 ret; 340 u32 value; 341 342 if (reg == SDHCI_CAPABILITIES_1) 343 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1); 344 else 345 value = ioread32(host->ioaddr + reg); 346 347 ret = esdhc_readl_fixup(host, reg, value); 348 349 return ret; 350 } 351 352 static u16 esdhc_be_readw(struct sdhci_host *host, int reg) 353 { 354 u16 ret; 355 u32 value; 356 int base = reg & ~0x3; 357 358 value = ioread32be(host->ioaddr + base); 359 ret = esdhc_readw_fixup(host, reg, value); 360 return ret; 361 } 362 363 static u16 esdhc_le_readw(struct sdhci_host *host, int reg) 364 { 365 u16 ret; 366 u32 value; 367 int base = reg & ~0x3; 368 369 value = ioread32(host->ioaddr + base); 370 ret = esdhc_readw_fixup(host, reg, value); 371 return ret; 372 } 373 374 static u8 esdhc_be_readb(struct sdhci_host *host, int reg) 375 { 376 u8 ret; 377 u32 value; 378 int base = reg & ~0x3; 379 380 value = ioread32be(host->ioaddr + base); 381 ret = esdhc_readb_fixup(host, reg, value); 382 return ret; 383 } 384 385 static u8 esdhc_le_readb(struct sdhci_host *host, int reg) 386 { 387 u8 ret; 388 u32 value; 389 int base = reg & ~0x3; 390 391 value = ioread32(host->ioaddr + base); 392 ret = esdhc_readb_fixup(host, reg, value); 393 return ret; 394 } 395 396 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) 397 { 398 u32 value; 399 400 value = esdhc_writel_fixup(host, reg, val, 0); 401 iowrite32be(value, host->ioaddr + reg); 402 } 403 404 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) 405 { 406 u32 value; 407 408 value = esdhc_writel_fixup(host, reg, val, 0); 409 iowrite32(value, host->ioaddr + reg); 410 } 411 412 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) 413 { 414 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 415 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 416 int base = reg & ~0x3; 417 u32 value; 418 u32 ret; 419 420 value = ioread32be(host->ioaddr + base); 421 ret = esdhc_writew_fixup(host, reg, val, value); 422 if (reg != SDHCI_TRANSFER_MODE) 423 iowrite32be(ret, host->ioaddr + base); 424 425 /* Starting SW tuning requires ESDHC_SMPCLKSEL to be set 426 * 1us later after ESDHC_EXTN is set. 427 */ 428 if (base == ESDHC_SYSTEM_CONTROL_2) { 429 if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) && 430 esdhc->in_sw_tuning) { 431 udelay(1); 432 ret |= ESDHC_SMPCLKSEL; 433 iowrite32be(ret, host->ioaddr + base); 434 } 435 } 436 } 437 438 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) 439 { 440 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 441 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 442 int base = reg & ~0x3; 443 u32 value; 444 u32 ret; 445 446 value = ioread32(host->ioaddr + base); 447 ret = esdhc_writew_fixup(host, reg, val, value); 448 if (reg != SDHCI_TRANSFER_MODE) 449 iowrite32(ret, host->ioaddr + base); 450 451 /* Starting SW tuning requires ESDHC_SMPCLKSEL to be set 452 * 1us later after ESDHC_EXTN is set. 453 */ 454 if (base == ESDHC_SYSTEM_CONTROL_2) { 455 if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) && 456 esdhc->in_sw_tuning) { 457 udelay(1); 458 ret |= ESDHC_SMPCLKSEL; 459 iowrite32(ret, host->ioaddr + base); 460 } 461 } 462 } 463 464 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) 465 { 466 int base = reg & ~0x3; 467 u32 value; 468 u32 ret; 469 470 value = ioread32be(host->ioaddr + base); 471 ret = esdhc_writeb_fixup(host, reg, val, value); 472 iowrite32be(ret, host->ioaddr + base); 473 } 474 475 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) 476 { 477 int base = reg & ~0x3; 478 u32 value; 479 u32 ret; 480 481 value = ioread32(host->ioaddr + base); 482 ret = esdhc_writeb_fixup(host, reg, val, value); 483 iowrite32(ret, host->ioaddr + base); 484 } 485 486 /* 487 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA 488 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC]) 489 * and Block Gap Event(IRQSTAT[BGE]) are also set. 490 * For Continue, apply soft reset for data(SYSCTL[RSTD]); 491 * and re-issue the entire read transaction from beginning. 492 */ 493 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask) 494 { 495 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 496 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 497 bool applicable; 498 dma_addr_t dmastart; 499 dma_addr_t dmanow; 500 501 applicable = (intmask & SDHCI_INT_DATA_END) && 502 (intmask & SDHCI_INT_BLK_GAP) && 503 (esdhc->vendor_ver == VENDOR_V_23); 504 if (!applicable) 505 return; 506 507 host->data->error = 0; 508 dmastart = sg_dma_address(host->data->sg); 509 dmanow = dmastart + host->data->bytes_xfered; 510 /* 511 * Force update to the next DMA block boundary. 512 */ 513 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 514 SDHCI_DEFAULT_BOUNDARY_SIZE; 515 host->data->bytes_xfered = dmanow - dmastart; 516 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 517 } 518 519 static int esdhc_of_enable_dma(struct sdhci_host *host) 520 { 521 u32 value; 522 struct device *dev = mmc_dev(host->mmc); 523 524 if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") || 525 of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) 526 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); 527 528 value = sdhci_readl(host, ESDHC_DMA_SYSCTL); 529 530 if (of_dma_is_coherent(dev->of_node)) 531 value |= ESDHC_DMA_SNOOP; 532 else 533 value &= ~ESDHC_DMA_SNOOP; 534 535 sdhci_writel(host, value, ESDHC_DMA_SYSCTL); 536 return 0; 537 } 538 539 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) 540 { 541 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 542 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 543 544 if (esdhc->peripheral_clock) 545 return esdhc->peripheral_clock; 546 else 547 return pltfm_host->clock; 548 } 549 550 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) 551 { 552 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 553 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 554 unsigned int clock; 555 556 if (esdhc->peripheral_clock) 557 clock = esdhc->peripheral_clock; 558 else 559 clock = pltfm_host->clock; 560 return clock / 256 / 16; 561 } 562 563 static void esdhc_clock_enable(struct sdhci_host *host, bool enable) 564 { 565 u32 val; 566 ktime_t timeout; 567 568 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 569 570 if (enable) 571 val |= ESDHC_CLOCK_SDCLKEN; 572 else 573 val &= ~ESDHC_CLOCK_SDCLKEN; 574 575 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL); 576 577 /* Wait max 20 ms */ 578 timeout = ktime_add_ms(ktime_get(), 20); 579 val = ESDHC_CLOCK_STABLE; 580 while (1) { 581 bool timedout = ktime_after(ktime_get(), timeout); 582 583 if (sdhci_readl(host, ESDHC_PRSSTAT) & val) 584 break; 585 if (timedout) { 586 pr_err("%s: Internal clock never stabilised.\n", 587 mmc_hostname(host->mmc)); 588 break; 589 } 590 udelay(10); 591 } 592 } 593 594 static void esdhc_flush_async_fifo(struct sdhci_host *host) 595 { 596 ktime_t timeout; 597 u32 val; 598 599 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 600 val |= ESDHC_FLUSH_ASYNC_FIFO; 601 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 602 603 /* Wait max 20 ms */ 604 timeout = ktime_add_ms(ktime_get(), 20); 605 while (1) { 606 bool timedout = ktime_after(ktime_get(), timeout); 607 608 if (!(sdhci_readl(host, ESDHC_DMA_SYSCTL) & 609 ESDHC_FLUSH_ASYNC_FIFO)) 610 break; 611 if (timedout) { 612 pr_err("%s: flushing asynchronous FIFO timeout.\n", 613 mmc_hostname(host->mmc)); 614 break; 615 } 616 usleep_range(10, 20); 617 } 618 } 619 620 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) 621 { 622 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 623 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 624 int pre_div = 1; 625 int div = 1; 626 int division; 627 ktime_t timeout; 628 long fixup = 0; 629 u32 temp; 630 631 host->mmc->actual_clock = 0; 632 633 if (clock == 0) { 634 esdhc_clock_enable(host, false); 635 return; 636 } 637 638 /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */ 639 if (esdhc->vendor_ver < VENDOR_V_23) 640 pre_div = 2; 641 642 if (host->mmc->card && mmc_card_sd(host->mmc->card) && 643 esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY) 644 fixup = esdhc->clk_fixup->sd_dflt_max_clk; 645 else if (esdhc->clk_fixup) 646 fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing]; 647 648 if (fixup && clock > fixup) 649 clock = fixup; 650 651 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 652 temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | 653 ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK); 654 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 655 656 while (host->max_clk / pre_div / 16 > clock && pre_div < 256) 657 pre_div *= 2; 658 659 while (host->max_clk / pre_div / div > clock && div < 16) 660 div++; 661 662 if (esdhc->quirk_limited_clk_division && 663 clock == MMC_HS200_MAX_DTR && 664 (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 || 665 host->flags & SDHCI_HS400_TUNING)) { 666 division = pre_div * div; 667 if (division <= 4) { 668 pre_div = 4; 669 div = 1; 670 } else if (division <= 8) { 671 pre_div = 4; 672 div = 2; 673 } else if (division <= 12) { 674 pre_div = 4; 675 div = 3; 676 } else { 677 pr_warn("%s: using unsupported clock division.\n", 678 mmc_hostname(host->mmc)); 679 } 680 } 681 682 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 683 clock, host->max_clk / pre_div / div); 684 host->mmc->actual_clock = host->max_clk / pre_div / div; 685 esdhc->div_ratio = pre_div * div; 686 pre_div >>= 1; 687 div--; 688 689 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 690 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 691 | (div << ESDHC_DIVIDER_SHIFT) 692 | (pre_div << ESDHC_PREDIV_SHIFT)); 693 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 694 695 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && 696 clock == MMC_HS200_MAX_DTR) { 697 temp = sdhci_readl(host, ESDHC_TBCTL); 698 sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL); 699 temp = sdhci_readl(host, ESDHC_SDCLKCTL); 700 sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL); 701 esdhc_clock_enable(host, true); 702 703 temp = sdhci_readl(host, ESDHC_DLLCFG0); 704 temp |= ESDHC_DLL_ENABLE; 705 if (host->mmc->actual_clock == MMC_HS200_MAX_DTR) 706 temp |= ESDHC_DLL_FREQ_SEL; 707 sdhci_writel(host, temp, ESDHC_DLLCFG0); 708 temp = sdhci_readl(host, ESDHC_TBCTL); 709 sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL); 710 711 esdhc_clock_enable(host, false); 712 esdhc_flush_async_fifo(host); 713 } 714 715 /* Wait max 20 ms */ 716 timeout = ktime_add_ms(ktime_get(), 20); 717 while (1) { 718 bool timedout = ktime_after(ktime_get(), timeout); 719 720 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE) 721 break; 722 if (timedout) { 723 pr_err("%s: Internal clock never stabilised.\n", 724 mmc_hostname(host->mmc)); 725 return; 726 } 727 udelay(10); 728 } 729 730 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 731 temp |= ESDHC_CLOCK_SDCLKEN; 732 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 733 } 734 735 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 736 { 737 u32 ctrl; 738 739 ctrl = sdhci_readl(host, ESDHC_PROCTL); 740 ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK); 741 switch (width) { 742 case MMC_BUS_WIDTH_8: 743 ctrl |= ESDHC_CTRL_8BITBUS; 744 break; 745 746 case MMC_BUS_WIDTH_4: 747 ctrl |= ESDHC_CTRL_4BITBUS; 748 break; 749 750 default: 751 break; 752 } 753 754 sdhci_writel(host, ctrl, ESDHC_PROCTL); 755 } 756 757 static void esdhc_reset(struct sdhci_host *host, u8 mask) 758 { 759 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 760 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 761 u32 val, bus_width = 0; 762 763 /* 764 * Add delay to make sure all the DMA transfers are finished 765 * for quirk. 766 */ 767 if (esdhc->quirk_delay_before_data_reset && 768 (mask & SDHCI_RESET_DATA) && 769 (host->flags & SDHCI_REQ_USE_DMA)) 770 mdelay(5); 771 772 /* 773 * Save bus-width for eSDHC whose vendor version is 2.2 774 * or lower for data reset. 775 */ 776 if ((mask & SDHCI_RESET_DATA) && 777 (esdhc->vendor_ver <= VENDOR_V_22)) { 778 val = sdhci_readl(host, ESDHC_PROCTL); 779 bus_width = val & ESDHC_CTRL_BUSWIDTH_MASK; 780 } 781 782 sdhci_reset(host, mask); 783 784 /* 785 * Restore bus-width setting and interrupt registers for eSDHC 786 * whose vendor version is 2.2 or lower for data reset. 787 */ 788 if ((mask & SDHCI_RESET_DATA) && 789 (esdhc->vendor_ver <= VENDOR_V_22)) { 790 val = sdhci_readl(host, ESDHC_PROCTL); 791 val &= ~ESDHC_CTRL_BUSWIDTH_MASK; 792 val |= bus_width; 793 sdhci_writel(host, val, ESDHC_PROCTL); 794 795 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 796 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 797 } 798 799 /* 800 * Some bits have to be cleaned manually for eSDHC whose spec 801 * version is higher than 3.0 for all reset. 802 */ 803 if ((mask & SDHCI_RESET_ALL) && 804 (esdhc->spec_ver >= SDHCI_SPEC_300)) { 805 val = sdhci_readl(host, ESDHC_TBCTL); 806 val &= ~ESDHC_TB_EN; 807 sdhci_writel(host, val, ESDHC_TBCTL); 808 809 /* 810 * Initialize eSDHC_DLLCFG1[DLL_PD_PULSE_STRETCH_SEL] to 811 * 0 for quirk. 812 */ 813 if (esdhc->quirk_unreliable_pulse_detection) { 814 val = sdhci_readl(host, ESDHC_DLLCFG1); 815 val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL; 816 sdhci_writel(host, val, ESDHC_DLLCFG1); 817 } 818 } 819 } 820 821 /* The SCFG, Supplemental Configuration Unit, provides SoC specific 822 * configuration and status registers for the device. There is a 823 * SDHC IO VSEL control register on SCFG for some platforms. It's 824 * used to support SDHC IO voltage switching. 825 */ 826 static const struct of_device_id scfg_device_ids[] = { 827 { .compatible = "fsl,t1040-scfg", }, 828 { .compatible = "fsl,ls1012a-scfg", }, 829 { .compatible = "fsl,ls1046a-scfg", }, 830 {} 831 }; 832 833 /* SDHC IO VSEL control register definition */ 834 #define SCFG_SDHCIOVSELCR 0x408 835 #define SDHCIOVSELCR_TGLEN 0x80000000 836 #define SDHCIOVSELCR_VSELVAL 0x60000000 837 #define SDHCIOVSELCR_SDHC_VS 0x00000001 838 839 static int esdhc_signal_voltage_switch(struct mmc_host *mmc, 840 struct mmc_ios *ios) 841 { 842 struct sdhci_host *host = mmc_priv(mmc); 843 struct device_node *scfg_node; 844 void __iomem *scfg_base = NULL; 845 u32 sdhciovselcr; 846 u32 val; 847 848 /* 849 * Signal Voltage Switching is only applicable for Host Controllers 850 * v3.00 and above. 851 */ 852 if (host->version < SDHCI_SPEC_300) 853 return 0; 854 855 val = sdhci_readl(host, ESDHC_PROCTL); 856 857 switch (ios->signal_voltage) { 858 case MMC_SIGNAL_VOLTAGE_330: 859 val &= ~ESDHC_VOLT_SEL; 860 sdhci_writel(host, val, ESDHC_PROCTL); 861 return 0; 862 case MMC_SIGNAL_VOLTAGE_180: 863 scfg_node = of_find_matching_node(NULL, scfg_device_ids); 864 if (scfg_node) 865 scfg_base = of_iomap(scfg_node, 0); 866 if (scfg_base) { 867 sdhciovselcr = SDHCIOVSELCR_TGLEN | 868 SDHCIOVSELCR_VSELVAL; 869 iowrite32be(sdhciovselcr, 870 scfg_base + SCFG_SDHCIOVSELCR); 871 872 val |= ESDHC_VOLT_SEL; 873 sdhci_writel(host, val, ESDHC_PROCTL); 874 mdelay(5); 875 876 sdhciovselcr = SDHCIOVSELCR_TGLEN | 877 SDHCIOVSELCR_SDHC_VS; 878 iowrite32be(sdhciovselcr, 879 scfg_base + SCFG_SDHCIOVSELCR); 880 iounmap(scfg_base); 881 } else { 882 val |= ESDHC_VOLT_SEL; 883 sdhci_writel(host, val, ESDHC_PROCTL); 884 } 885 return 0; 886 default: 887 return 0; 888 } 889 } 890 891 static struct soc_device_attribute soc_tuning_erratum_type1[] = { 892 { .family = "QorIQ T1023", }, 893 { .family = "QorIQ T1040", }, 894 { .family = "QorIQ T2080", }, 895 { .family = "QorIQ LS1021A", }, 896 { }, 897 }; 898 899 static struct soc_device_attribute soc_tuning_erratum_type2[] = { 900 { .family = "QorIQ LS1012A", }, 901 { .family = "QorIQ LS1043A", }, 902 { .family = "QorIQ LS1046A", }, 903 { .family = "QorIQ LS1080A", }, 904 { .family = "QorIQ LS2080A", }, 905 { .family = "QorIQ LA1575A", }, 906 { }, 907 }; 908 909 static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable) 910 { 911 u32 val; 912 913 esdhc_clock_enable(host, false); 914 esdhc_flush_async_fifo(host); 915 916 val = sdhci_readl(host, ESDHC_TBCTL); 917 if (enable) 918 val |= ESDHC_TB_EN; 919 else 920 val &= ~ESDHC_TB_EN; 921 sdhci_writel(host, val, ESDHC_TBCTL); 922 923 esdhc_clock_enable(host, true); 924 } 925 926 static void esdhc_tuning_window_ptr(struct sdhci_host *host, u8 *window_start, 927 u8 *window_end) 928 { 929 u32 val; 930 931 /* Write TBCTL[11:8]=4'h8 */ 932 val = sdhci_readl(host, ESDHC_TBCTL); 933 val &= ~(0xf << 8); 934 val |= 8 << 8; 935 sdhci_writel(host, val, ESDHC_TBCTL); 936 937 mdelay(1); 938 939 /* Read TBCTL[31:0] register and rewrite again */ 940 val = sdhci_readl(host, ESDHC_TBCTL); 941 sdhci_writel(host, val, ESDHC_TBCTL); 942 943 mdelay(1); 944 945 /* Read the TBSTAT[31:0] register twice */ 946 val = sdhci_readl(host, ESDHC_TBSTAT); 947 val = sdhci_readl(host, ESDHC_TBSTAT); 948 949 *window_end = val & 0xff; 950 *window_start = (val >> 8) & 0xff; 951 } 952 953 static void esdhc_prepare_sw_tuning(struct sdhci_host *host, u8 *window_start, 954 u8 *window_end) 955 { 956 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 957 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 958 u8 start_ptr, end_ptr; 959 960 if (esdhc->quirk_tuning_erratum_type1) { 961 *window_start = 5 * esdhc->div_ratio; 962 *window_end = 3 * esdhc->div_ratio; 963 return; 964 } 965 966 esdhc_tuning_window_ptr(host, &start_ptr, &end_ptr); 967 968 /* Reset data lines by setting ESDHCCTL[RSTD] */ 969 sdhci_reset(host, SDHCI_RESET_DATA); 970 /* Write 32'hFFFF_FFFF to IRQSTAT register */ 971 sdhci_writel(host, 0xFFFFFFFF, SDHCI_INT_STATUS); 972 973 /* If TBSTAT[15:8]-TBSTAT[7:0] > (4 * div_ratio) + 2 974 * or TBSTAT[7:0]-TBSTAT[15:8] > (4 * div_ratio) + 2, 975 * then program TBPTR[TB_WNDW_END_PTR] = 4 * div_ratio 976 * and program TBPTR[TB_WNDW_START_PTR] = 8 * div_ratio. 977 */ 978 979 if (abs(start_ptr - end_ptr) > (4 * esdhc->div_ratio + 2)) { 980 *window_start = 8 * esdhc->div_ratio; 981 *window_end = 4 * esdhc->div_ratio; 982 } else { 983 *window_start = 5 * esdhc->div_ratio; 984 *window_end = 3 * esdhc->div_ratio; 985 } 986 } 987 988 static int esdhc_execute_sw_tuning(struct mmc_host *mmc, u32 opcode, 989 u8 window_start, u8 window_end) 990 { 991 struct sdhci_host *host = mmc_priv(mmc); 992 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 993 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 994 u32 val; 995 int ret; 996 997 /* Program TBPTR[TB_WNDW_END_PTR] and TBPTR[TB_WNDW_START_PTR] */ 998 val = ((u32)window_start << ESDHC_WNDW_STRT_PTR_SHIFT) & 999 ESDHC_WNDW_STRT_PTR_MASK; 1000 val |= window_end & ESDHC_WNDW_END_PTR_MASK; 1001 sdhci_writel(host, val, ESDHC_TBPTR); 1002 1003 /* Program the software tuning mode by setting TBCTL[TB_MODE]=2'h3 */ 1004 val = sdhci_readl(host, ESDHC_TBCTL); 1005 val &= ~ESDHC_TB_MODE_MASK; 1006 val |= ESDHC_TB_MODE_SW; 1007 sdhci_writel(host, val, ESDHC_TBCTL); 1008 1009 esdhc->in_sw_tuning = true; 1010 ret = sdhci_execute_tuning(mmc, opcode); 1011 esdhc->in_sw_tuning = false; 1012 return ret; 1013 } 1014 1015 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1016 { 1017 struct sdhci_host *host = mmc_priv(mmc); 1018 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1019 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 1020 u8 window_start, window_end; 1021 int ret, retries = 1; 1022 bool hs400_tuning; 1023 unsigned int clk; 1024 u32 val; 1025 1026 /* For tuning mode, the sd clock divisor value 1027 * must be larger than 3 according to reference manual. 1028 */ 1029 clk = esdhc->peripheral_clock / 3; 1030 if (host->clock > clk) 1031 esdhc_of_set_clock(host, clk); 1032 1033 esdhc_tuning_block_enable(host, true); 1034 1035 hs400_tuning = host->flags & SDHCI_HS400_TUNING; 1036 1037 do { 1038 if (esdhc->quirk_limited_clk_division && 1039 hs400_tuning) 1040 esdhc_of_set_clock(host, host->clock); 1041 1042 /* Do HW tuning */ 1043 val = sdhci_readl(host, ESDHC_TBCTL); 1044 val &= ~ESDHC_TB_MODE_MASK; 1045 val |= ESDHC_TB_MODE_3; 1046 sdhci_writel(host, val, ESDHC_TBCTL); 1047 1048 ret = sdhci_execute_tuning(mmc, opcode); 1049 if (ret) 1050 break; 1051 1052 /* For type2 affected platforms of the tuning erratum, 1053 * tuning may succeed although eSDHC might not have 1054 * tuned properly. Need to check tuning window. 1055 */ 1056 if (esdhc->quirk_tuning_erratum_type2 && 1057 !host->tuning_err) { 1058 esdhc_tuning_window_ptr(host, &window_start, 1059 &window_end); 1060 if (abs(window_start - window_end) > 1061 (4 * esdhc->div_ratio + 2)) 1062 host->tuning_err = -EAGAIN; 1063 } 1064 1065 /* If HW tuning fails and triggers erratum, 1066 * try workaround. 1067 */ 1068 ret = host->tuning_err; 1069 if (ret == -EAGAIN && 1070 (esdhc->quirk_tuning_erratum_type1 || 1071 esdhc->quirk_tuning_erratum_type2)) { 1072 /* Recover HS400 tuning flag */ 1073 if (hs400_tuning) 1074 host->flags |= SDHCI_HS400_TUNING; 1075 pr_info("%s: Hold on to use fixed sampling clock. Try SW tuning!\n", 1076 mmc_hostname(mmc)); 1077 /* Do SW tuning */ 1078 esdhc_prepare_sw_tuning(host, &window_start, 1079 &window_end); 1080 ret = esdhc_execute_sw_tuning(mmc, opcode, 1081 window_start, 1082 window_end); 1083 if (ret) 1084 break; 1085 1086 /* Retry both HW/SW tuning with reduced clock. */ 1087 ret = host->tuning_err; 1088 if (ret == -EAGAIN && retries) { 1089 /* Recover HS400 tuning flag */ 1090 if (hs400_tuning) 1091 host->flags |= SDHCI_HS400_TUNING; 1092 1093 clk = host->max_clk / (esdhc->div_ratio + 1); 1094 esdhc_of_set_clock(host, clk); 1095 pr_info("%s: Hold on to use fixed sampling clock. Try tuning with reduced clock!\n", 1096 mmc_hostname(mmc)); 1097 } else { 1098 break; 1099 } 1100 } else { 1101 break; 1102 } 1103 } while (retries--); 1104 1105 if (ret) { 1106 esdhc_tuning_block_enable(host, false); 1107 } else if (hs400_tuning) { 1108 val = sdhci_readl(host, ESDHC_SDTIMNGCTL); 1109 val |= ESDHC_FLW_CTL_BG; 1110 sdhci_writel(host, val, ESDHC_SDTIMNGCTL); 1111 } 1112 1113 return ret; 1114 } 1115 1116 static void esdhc_set_uhs_signaling(struct sdhci_host *host, 1117 unsigned int timing) 1118 { 1119 if (timing == MMC_TIMING_MMC_HS400) 1120 esdhc_tuning_block_enable(host, true); 1121 else 1122 sdhci_set_uhs_signaling(host, timing); 1123 } 1124 1125 static u32 esdhc_irq(struct sdhci_host *host, u32 intmask) 1126 { 1127 u32 command; 1128 1129 if (of_find_compatible_node(NULL, NULL, 1130 "fsl,p2020-esdhc")) { 1131 command = SDHCI_GET_CMD(sdhci_readw(host, 1132 SDHCI_COMMAND)); 1133 if (command == MMC_WRITE_MULTIPLE_BLOCK && 1134 sdhci_readw(host, SDHCI_BLOCK_COUNT) && 1135 intmask & SDHCI_INT_DATA_END) { 1136 intmask &= ~SDHCI_INT_DATA_END; 1137 sdhci_writel(host, SDHCI_INT_DATA_END, 1138 SDHCI_INT_STATUS); 1139 } 1140 } 1141 return intmask; 1142 } 1143 1144 #ifdef CONFIG_PM_SLEEP 1145 static u32 esdhc_proctl; 1146 static int esdhc_of_suspend(struct device *dev) 1147 { 1148 struct sdhci_host *host = dev_get_drvdata(dev); 1149 1150 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL); 1151 1152 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1153 mmc_retune_needed(host->mmc); 1154 1155 return sdhci_suspend_host(host); 1156 } 1157 1158 static int esdhc_of_resume(struct device *dev) 1159 { 1160 struct sdhci_host *host = dev_get_drvdata(dev); 1161 int ret = sdhci_resume_host(host); 1162 1163 if (ret == 0) { 1164 /* Isn't this already done by sdhci_resume_host() ? --rmk */ 1165 esdhc_of_enable_dma(host); 1166 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); 1167 } 1168 return ret; 1169 } 1170 #endif 1171 1172 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops, 1173 esdhc_of_suspend, 1174 esdhc_of_resume); 1175 1176 static const struct sdhci_ops sdhci_esdhc_be_ops = { 1177 .read_l = esdhc_be_readl, 1178 .read_w = esdhc_be_readw, 1179 .read_b = esdhc_be_readb, 1180 .write_l = esdhc_be_writel, 1181 .write_w = esdhc_be_writew, 1182 .write_b = esdhc_be_writeb, 1183 .set_clock = esdhc_of_set_clock, 1184 .enable_dma = esdhc_of_enable_dma, 1185 .get_max_clock = esdhc_of_get_max_clock, 1186 .get_min_clock = esdhc_of_get_min_clock, 1187 .adma_workaround = esdhc_of_adma_workaround, 1188 .set_bus_width = esdhc_pltfm_set_bus_width, 1189 .reset = esdhc_reset, 1190 .set_uhs_signaling = esdhc_set_uhs_signaling, 1191 .irq = esdhc_irq, 1192 }; 1193 1194 static const struct sdhci_ops sdhci_esdhc_le_ops = { 1195 .read_l = esdhc_le_readl, 1196 .read_w = esdhc_le_readw, 1197 .read_b = esdhc_le_readb, 1198 .write_l = esdhc_le_writel, 1199 .write_w = esdhc_le_writew, 1200 .write_b = esdhc_le_writeb, 1201 .set_clock = esdhc_of_set_clock, 1202 .enable_dma = esdhc_of_enable_dma, 1203 .get_max_clock = esdhc_of_get_max_clock, 1204 .get_min_clock = esdhc_of_get_min_clock, 1205 .adma_workaround = esdhc_of_adma_workaround, 1206 .set_bus_width = esdhc_pltfm_set_bus_width, 1207 .reset = esdhc_reset, 1208 .set_uhs_signaling = esdhc_set_uhs_signaling, 1209 .irq = esdhc_irq, 1210 }; 1211 1212 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = { 1213 .quirks = ESDHC_DEFAULT_QUIRKS | 1214 #ifdef CONFIG_PPC 1215 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 1216 #endif 1217 SDHCI_QUIRK_NO_CARD_NO_RESET | 1218 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1219 .ops = &sdhci_esdhc_be_ops, 1220 }; 1221 1222 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = { 1223 .quirks = ESDHC_DEFAULT_QUIRKS | 1224 SDHCI_QUIRK_NO_CARD_NO_RESET | 1225 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1226 .ops = &sdhci_esdhc_le_ops, 1227 }; 1228 1229 static struct soc_device_attribute soc_incorrect_hostver[] = { 1230 { .family = "QorIQ T4240", .revision = "1.0", }, 1231 { .family = "QorIQ T4240", .revision = "2.0", }, 1232 { }, 1233 }; 1234 1235 static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = { 1236 { .family = "QorIQ LX2160A", .revision = "1.0", }, 1237 { .family = "QorIQ LX2160A", .revision = "2.0", }, 1238 { .family = "QorIQ LS1028A", .revision = "1.0", }, 1239 { }, 1240 }; 1241 1242 static struct soc_device_attribute soc_unreliable_pulse_detection[] = { 1243 { .family = "QorIQ LX2160A", .revision = "1.0", }, 1244 { }, 1245 }; 1246 1247 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host) 1248 { 1249 const struct of_device_id *match; 1250 struct sdhci_pltfm_host *pltfm_host; 1251 struct sdhci_esdhc *esdhc; 1252 struct device_node *np; 1253 struct clk *clk; 1254 u32 val; 1255 u16 host_ver; 1256 1257 pltfm_host = sdhci_priv(host); 1258 esdhc = sdhci_pltfm_priv(pltfm_host); 1259 1260 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); 1261 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >> 1262 SDHCI_VENDOR_VER_SHIFT; 1263 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK; 1264 if (soc_device_match(soc_incorrect_hostver)) 1265 esdhc->quirk_incorrect_hostver = true; 1266 else 1267 esdhc->quirk_incorrect_hostver = false; 1268 1269 if (soc_device_match(soc_fixup_sdhc_clkdivs)) 1270 esdhc->quirk_limited_clk_division = true; 1271 else 1272 esdhc->quirk_limited_clk_division = false; 1273 1274 if (soc_device_match(soc_unreliable_pulse_detection)) 1275 esdhc->quirk_unreliable_pulse_detection = true; 1276 else 1277 esdhc->quirk_unreliable_pulse_detection = false; 1278 1279 match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node); 1280 if (match) 1281 esdhc->clk_fixup = match->data; 1282 np = pdev->dev.of_node; 1283 1284 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) 1285 esdhc->quirk_delay_before_data_reset = true; 1286 1287 clk = of_clk_get(np, 0); 1288 if (!IS_ERR(clk)) { 1289 /* 1290 * esdhc->peripheral_clock would be assigned with a value 1291 * which is eSDHC base clock when use periperal clock. 1292 * For some platforms, the clock value got by common clk 1293 * API is peripheral clock while the eSDHC base clock is 1294 * 1/2 peripheral clock. 1295 */ 1296 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc") || 1297 of_device_is_compatible(np, "fsl,ls1028a-esdhc") || 1298 of_device_is_compatible(np, "fsl,ls1088a-esdhc")) 1299 esdhc->peripheral_clock = clk_get_rate(clk) / 2; 1300 else 1301 esdhc->peripheral_clock = clk_get_rate(clk); 1302 1303 clk_put(clk); 1304 } 1305 1306 if (esdhc->peripheral_clock) { 1307 esdhc_clock_enable(host, false); 1308 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 1309 val |= ESDHC_PERIPHERAL_CLK_SEL; 1310 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 1311 esdhc_clock_enable(host, true); 1312 } 1313 } 1314 1315 static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc) 1316 { 1317 esdhc_tuning_block_enable(mmc_priv(mmc), false); 1318 return 0; 1319 } 1320 1321 static int sdhci_esdhc_probe(struct platform_device *pdev) 1322 { 1323 struct sdhci_host *host; 1324 struct device_node *np; 1325 struct sdhci_pltfm_host *pltfm_host; 1326 struct sdhci_esdhc *esdhc; 1327 int ret; 1328 1329 np = pdev->dev.of_node; 1330 1331 if (of_property_read_bool(np, "little-endian")) 1332 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata, 1333 sizeof(struct sdhci_esdhc)); 1334 else 1335 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata, 1336 sizeof(struct sdhci_esdhc)); 1337 1338 if (IS_ERR(host)) 1339 return PTR_ERR(host); 1340 1341 host->mmc_host_ops.start_signal_voltage_switch = 1342 esdhc_signal_voltage_switch; 1343 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning; 1344 host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr; 1345 host->tuning_delay = 1; 1346 1347 esdhc_init(pdev, host); 1348 1349 sdhci_get_of_property(pdev); 1350 1351 pltfm_host = sdhci_priv(host); 1352 esdhc = sdhci_pltfm_priv(pltfm_host); 1353 if (soc_device_match(soc_tuning_erratum_type1)) 1354 esdhc->quirk_tuning_erratum_type1 = true; 1355 else 1356 esdhc->quirk_tuning_erratum_type1 = false; 1357 1358 if (soc_device_match(soc_tuning_erratum_type2)) 1359 esdhc->quirk_tuning_erratum_type2 = true; 1360 else 1361 esdhc->quirk_tuning_erratum_type2 = false; 1362 1363 if (esdhc->vendor_ver == VENDOR_V_22) 1364 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; 1365 1366 if (esdhc->vendor_ver > VENDOR_V_22) 1367 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1368 1369 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) { 1370 host->quirks |= SDHCI_QUIRK_RESET_AFTER_REQUEST; 1371 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1372 } 1373 1374 if (of_device_is_compatible(np, "fsl,p5040-esdhc") || 1375 of_device_is_compatible(np, "fsl,p5020-esdhc") || 1376 of_device_is_compatible(np, "fsl,p4080-esdhc") || 1377 of_device_is_compatible(np, "fsl,p1020-esdhc") || 1378 of_device_is_compatible(np, "fsl,t1040-esdhc")) 1379 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1380 1381 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc")) 1382 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1383 1384 esdhc->quirk_ignore_data_inhibit = false; 1385 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { 1386 /* 1387 * Freescale messed up with P2020 as it has a non-standard 1388 * host control register 1389 */ 1390 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL; 1391 esdhc->quirk_ignore_data_inhibit = true; 1392 } 1393 1394 /* call to generic mmc_of_parse to support additional capabilities */ 1395 ret = mmc_of_parse(host->mmc); 1396 if (ret) 1397 goto err; 1398 1399 mmc_of_parse_voltage(np, &host->ocr_mask); 1400 1401 ret = sdhci_add_host(host); 1402 if (ret) 1403 goto err; 1404 1405 return 0; 1406 err: 1407 sdhci_pltfm_free(pdev); 1408 return ret; 1409 } 1410 1411 static struct platform_driver sdhci_esdhc_driver = { 1412 .driver = { 1413 .name = "sdhci-esdhc", 1414 .of_match_table = sdhci_esdhc_of_match, 1415 .pm = &esdhc_of_dev_pm_ops, 1416 }, 1417 .probe = sdhci_esdhc_probe, 1418 .remove = sdhci_pltfm_unregister, 1419 }; 1420 1421 module_platform_driver(sdhci_esdhc_driver); 1422 1423 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC"); 1424 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, " 1425 "Anton Vorontsov <avorontsov@ru.mvista.com>"); 1426 MODULE_LICENSE("GPL v2"); 1427