1 /* 2 * Freescale eSDHC controller driver. 3 * 4 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. 5 * Copyright (c) 2009 MontaVista Software, Inc. 6 * 7 * Authors: Xiaobo Xie <X.Xie@freescale.com> 8 * Anton Vorontsov <avorontsov@ru.mvista.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or (at 13 * your option) any later version. 14 */ 15 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/delay.h> 21 #include <linux/module.h> 22 #include <linux/sys_soc.h> 23 #include <linux/clk.h> 24 #include <linux/ktime.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/mmc/host.h> 27 #include <linux/mmc/mmc.h> 28 #include "sdhci-pltfm.h" 29 #include "sdhci-esdhc.h" 30 31 #define VENDOR_V_22 0x12 32 #define VENDOR_V_23 0x13 33 34 #define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1) 35 36 struct esdhc_clk_fixup { 37 const unsigned int sd_dflt_max_clk; 38 const unsigned int max_clk[MMC_TIMING_NUM]; 39 }; 40 41 static const struct esdhc_clk_fixup ls1021a_esdhc_clk = { 42 .sd_dflt_max_clk = 25000000, 43 .max_clk[MMC_TIMING_MMC_HS] = 46500000, 44 .max_clk[MMC_TIMING_SD_HS] = 46500000, 45 }; 46 47 static const struct esdhc_clk_fixup ls1046a_esdhc_clk = { 48 .sd_dflt_max_clk = 25000000, 49 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000, 50 .max_clk[MMC_TIMING_MMC_HS200] = 167000000, 51 }; 52 53 static const struct esdhc_clk_fixup ls1012a_esdhc_clk = { 54 .sd_dflt_max_clk = 25000000, 55 .max_clk[MMC_TIMING_UHS_SDR104] = 125000000, 56 .max_clk[MMC_TIMING_MMC_HS200] = 125000000, 57 }; 58 59 static const struct esdhc_clk_fixup p1010_esdhc_clk = { 60 .sd_dflt_max_clk = 20000000, 61 .max_clk[MMC_TIMING_LEGACY] = 20000000, 62 .max_clk[MMC_TIMING_MMC_HS] = 42000000, 63 .max_clk[MMC_TIMING_SD_HS] = 40000000, 64 }; 65 66 static const struct of_device_id sdhci_esdhc_of_match[] = { 67 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk}, 68 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk}, 69 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk}, 70 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk}, 71 { .compatible = "fsl,mpc8379-esdhc" }, 72 { .compatible = "fsl,mpc8536-esdhc" }, 73 { .compatible = "fsl,esdhc" }, 74 { } 75 }; 76 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); 77 78 struct sdhci_esdhc { 79 u8 vendor_ver; 80 u8 spec_ver; 81 bool quirk_incorrect_hostver; 82 bool quirk_limited_clk_division; 83 bool quirk_unreliable_pulse_detection; 84 bool quirk_fixup_tuning; 85 bool quirk_ignore_data_inhibit; 86 unsigned int peripheral_clock; 87 const struct esdhc_clk_fixup *clk_fixup; 88 u32 div_ratio; 89 }; 90 91 /** 92 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register 93 * to make it compatible with SD spec. 94 * 95 * @host: pointer to sdhci_host 96 * @spec_reg: SD spec register address 97 * @value: 32bit eSDHC register value on spec_reg address 98 * 99 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 100 * registers are 32 bits. There are differences in register size, register 101 * address, register function, bit position and function between eSDHC spec 102 * and SD spec. 103 * 104 * Return a fixed up register value 105 */ 106 static u32 esdhc_readl_fixup(struct sdhci_host *host, 107 int spec_reg, u32 value) 108 { 109 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 110 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 111 u32 ret; 112 113 /* 114 * The bit of ADMA flag in eSDHC is not compatible with standard 115 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is 116 * supported by eSDHC. 117 * And for many FSL eSDHC controller, the reset value of field 118 * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA, 119 * only these vendor version is greater than 2.2/0x12 support ADMA. 120 */ 121 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) { 122 if (esdhc->vendor_ver > VENDOR_V_22) { 123 ret = value | SDHCI_CAN_DO_ADMA2; 124 return ret; 125 } 126 } 127 /* 128 * The DAT[3:0] line signal levels and the CMD line signal level are 129 * not compatible with standard SDHC register. The line signal levels 130 * DAT[7:0] are at bits 31:24 and the command line signal level is at 131 * bit 23. All other bits are the same as in the standard SDHC 132 * register. 133 */ 134 if (spec_reg == SDHCI_PRESENT_STATE) { 135 ret = value & 0x000fffff; 136 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK; 137 ret |= (value << 1) & SDHCI_CMD_LVL; 138 return ret; 139 } 140 141 /* 142 * DTS properties of mmc host are used to enable each speed mode 143 * according to soc and board capability. So clean up 144 * SDR50/SDR104/DDR50 support bits here. 145 */ 146 if (spec_reg == SDHCI_CAPABILITIES_1) { 147 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 148 SDHCI_SUPPORT_DDR50); 149 return ret; 150 } 151 152 /* 153 * Some controllers have unreliable Data Line Active 154 * bit for commands with busy signal. This affects 155 * Command Inhibit (data) bit. Just ignore it since 156 * MMC core driver has already polled card status 157 * with CMD13 after any command with busy siganl. 158 */ 159 if ((spec_reg == SDHCI_PRESENT_STATE) && 160 (esdhc->quirk_ignore_data_inhibit == true)) { 161 ret = value & ~SDHCI_DATA_INHIBIT; 162 return ret; 163 } 164 165 ret = value; 166 return ret; 167 } 168 169 static u16 esdhc_readw_fixup(struct sdhci_host *host, 170 int spec_reg, u32 value) 171 { 172 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 173 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 174 u16 ret; 175 int shift = (spec_reg & 0x2) * 8; 176 177 if (spec_reg == SDHCI_HOST_VERSION) 178 ret = value & 0xffff; 179 else 180 ret = (value >> shift) & 0xffff; 181 /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect 182 * vendor version and spec version information. 183 */ 184 if ((spec_reg == SDHCI_HOST_VERSION) && 185 (esdhc->quirk_incorrect_hostver)) 186 ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200; 187 return ret; 188 } 189 190 static u8 esdhc_readb_fixup(struct sdhci_host *host, 191 int spec_reg, u32 value) 192 { 193 u8 ret; 194 u8 dma_bits; 195 int shift = (spec_reg & 0x3) * 8; 196 197 ret = (value >> shift) & 0xff; 198 199 /* 200 * "DMA select" locates at offset 0x28 in SD specification, but on 201 * P5020 or P3041, it locates at 0x29. 202 */ 203 if (spec_reg == SDHCI_HOST_CONTROL) { 204 /* DMA select is 22,23 bits in Protocol Control Register */ 205 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK; 206 /* fixup the result */ 207 ret &= ~SDHCI_CTRL_DMA_MASK; 208 ret |= dma_bits; 209 } 210 return ret; 211 } 212 213 /** 214 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be 215 * written into eSDHC register. 216 * 217 * @host: pointer to sdhci_host 218 * @spec_reg: SD spec register address 219 * @value: 8/16/32bit SD spec register value that would be written 220 * @old_value: 32bit eSDHC register value on spec_reg address 221 * 222 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 223 * registers are 32 bits. There are differences in register size, register 224 * address, register function, bit position and function between eSDHC spec 225 * and SD spec. 226 * 227 * Return a fixed up register value 228 */ 229 static u32 esdhc_writel_fixup(struct sdhci_host *host, 230 int spec_reg, u32 value, u32 old_value) 231 { 232 u32 ret; 233 234 /* 235 * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE] 236 * when SYSCTL[RSTD] is set for some special operations. 237 * No any impact on other operation. 238 */ 239 if (spec_reg == SDHCI_INT_ENABLE) 240 ret = value | SDHCI_INT_BLK_GAP; 241 else 242 ret = value; 243 244 return ret; 245 } 246 247 static u32 esdhc_writew_fixup(struct sdhci_host *host, 248 int spec_reg, u16 value, u32 old_value) 249 { 250 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 251 int shift = (spec_reg & 0x2) * 8; 252 u32 ret; 253 254 switch (spec_reg) { 255 case SDHCI_TRANSFER_MODE: 256 /* 257 * Postpone this write, we must do it together with a 258 * command write that is down below. Return old value. 259 */ 260 pltfm_host->xfer_mode_shadow = value; 261 return old_value; 262 case SDHCI_COMMAND: 263 ret = (value << 16) | pltfm_host->xfer_mode_shadow; 264 return ret; 265 } 266 267 ret = old_value & (~(0xffff << shift)); 268 ret |= (value << shift); 269 270 if (spec_reg == SDHCI_BLOCK_SIZE) { 271 /* 272 * Two last DMA bits are reserved, and first one is used for 273 * non-standard blksz of 4096 bytes that we don't support 274 * yet. So clear the DMA boundary bits. 275 */ 276 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0)); 277 } 278 return ret; 279 } 280 281 static u32 esdhc_writeb_fixup(struct sdhci_host *host, 282 int spec_reg, u8 value, u32 old_value) 283 { 284 u32 ret; 285 u32 dma_bits; 286 u8 tmp; 287 int shift = (spec_reg & 0x3) * 8; 288 289 /* 290 * eSDHC doesn't have a standard power control register, so we do 291 * nothing here to avoid incorrect operation. 292 */ 293 if (spec_reg == SDHCI_POWER_CONTROL) 294 return old_value; 295 /* 296 * "DMA select" location is offset 0x28 in SD specification, but on 297 * P5020 or P3041, it's located at 0x29. 298 */ 299 if (spec_reg == SDHCI_HOST_CONTROL) { 300 /* 301 * If host control register is not standard, exit 302 * this function 303 */ 304 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL) 305 return old_value; 306 307 /* DMA select is 22,23 bits in Protocol Control Register */ 308 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5; 309 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits; 310 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) | 311 (old_value & SDHCI_CTRL_DMA_MASK); 312 ret = (ret & (~0xff)) | tmp; 313 314 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */ 315 ret &= ~ESDHC_HOST_CONTROL_RES; 316 return ret; 317 } 318 319 ret = (old_value & (~(0xff << shift))) | (value << shift); 320 return ret; 321 } 322 323 static u32 esdhc_be_readl(struct sdhci_host *host, int reg) 324 { 325 u32 ret; 326 u32 value; 327 328 if (reg == SDHCI_CAPABILITIES_1) 329 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1); 330 else 331 value = ioread32be(host->ioaddr + reg); 332 333 ret = esdhc_readl_fixup(host, reg, value); 334 335 return ret; 336 } 337 338 static u32 esdhc_le_readl(struct sdhci_host *host, int reg) 339 { 340 u32 ret; 341 u32 value; 342 343 if (reg == SDHCI_CAPABILITIES_1) 344 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1); 345 else 346 value = ioread32(host->ioaddr + reg); 347 348 ret = esdhc_readl_fixup(host, reg, value); 349 350 return ret; 351 } 352 353 static u16 esdhc_be_readw(struct sdhci_host *host, int reg) 354 { 355 u16 ret; 356 u32 value; 357 int base = reg & ~0x3; 358 359 value = ioread32be(host->ioaddr + base); 360 ret = esdhc_readw_fixup(host, reg, value); 361 return ret; 362 } 363 364 static u16 esdhc_le_readw(struct sdhci_host *host, int reg) 365 { 366 u16 ret; 367 u32 value; 368 int base = reg & ~0x3; 369 370 value = ioread32(host->ioaddr + base); 371 ret = esdhc_readw_fixup(host, reg, value); 372 return ret; 373 } 374 375 static u8 esdhc_be_readb(struct sdhci_host *host, int reg) 376 { 377 u8 ret; 378 u32 value; 379 int base = reg & ~0x3; 380 381 value = ioread32be(host->ioaddr + base); 382 ret = esdhc_readb_fixup(host, reg, value); 383 return ret; 384 } 385 386 static u8 esdhc_le_readb(struct sdhci_host *host, int reg) 387 { 388 u8 ret; 389 u32 value; 390 int base = reg & ~0x3; 391 392 value = ioread32(host->ioaddr + base); 393 ret = esdhc_readb_fixup(host, reg, value); 394 return ret; 395 } 396 397 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) 398 { 399 u32 value; 400 401 value = esdhc_writel_fixup(host, reg, val, 0); 402 iowrite32be(value, host->ioaddr + reg); 403 } 404 405 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) 406 { 407 u32 value; 408 409 value = esdhc_writel_fixup(host, reg, val, 0); 410 iowrite32(value, host->ioaddr + reg); 411 } 412 413 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) 414 { 415 int base = reg & ~0x3; 416 u32 value; 417 u32 ret; 418 419 value = ioread32be(host->ioaddr + base); 420 ret = esdhc_writew_fixup(host, reg, val, value); 421 if (reg != SDHCI_TRANSFER_MODE) 422 iowrite32be(ret, host->ioaddr + base); 423 } 424 425 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) 426 { 427 int base = reg & ~0x3; 428 u32 value; 429 u32 ret; 430 431 value = ioread32(host->ioaddr + base); 432 ret = esdhc_writew_fixup(host, reg, val, value); 433 if (reg != SDHCI_TRANSFER_MODE) 434 iowrite32(ret, host->ioaddr + base); 435 } 436 437 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) 438 { 439 int base = reg & ~0x3; 440 u32 value; 441 u32 ret; 442 443 value = ioread32be(host->ioaddr + base); 444 ret = esdhc_writeb_fixup(host, reg, val, value); 445 iowrite32be(ret, host->ioaddr + base); 446 } 447 448 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) 449 { 450 int base = reg & ~0x3; 451 u32 value; 452 u32 ret; 453 454 value = ioread32(host->ioaddr + base); 455 ret = esdhc_writeb_fixup(host, reg, val, value); 456 iowrite32(ret, host->ioaddr + base); 457 } 458 459 /* 460 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA 461 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC]) 462 * and Block Gap Event(IRQSTAT[BGE]) are also set. 463 * For Continue, apply soft reset for data(SYSCTL[RSTD]); 464 * and re-issue the entire read transaction from beginning. 465 */ 466 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask) 467 { 468 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 469 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 470 bool applicable; 471 dma_addr_t dmastart; 472 dma_addr_t dmanow; 473 474 applicable = (intmask & SDHCI_INT_DATA_END) && 475 (intmask & SDHCI_INT_BLK_GAP) && 476 (esdhc->vendor_ver == VENDOR_V_23); 477 if (!applicable) 478 return; 479 480 host->data->error = 0; 481 dmastart = sg_dma_address(host->data->sg); 482 dmanow = dmastart + host->data->bytes_xfered; 483 /* 484 * Force update to the next DMA block boundary. 485 */ 486 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 487 SDHCI_DEFAULT_BOUNDARY_SIZE; 488 host->data->bytes_xfered = dmanow - dmastart; 489 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 490 } 491 492 static int esdhc_of_enable_dma(struct sdhci_host *host) 493 { 494 u32 value; 495 struct device *dev = mmc_dev(host->mmc); 496 497 if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") || 498 of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) 499 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); 500 501 value = sdhci_readl(host, ESDHC_DMA_SYSCTL); 502 value |= ESDHC_DMA_SNOOP; 503 sdhci_writel(host, value, ESDHC_DMA_SYSCTL); 504 return 0; 505 } 506 507 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) 508 { 509 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 510 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 511 512 if (esdhc->peripheral_clock) 513 return esdhc->peripheral_clock; 514 else 515 return pltfm_host->clock; 516 } 517 518 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) 519 { 520 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 521 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 522 unsigned int clock; 523 524 if (esdhc->peripheral_clock) 525 clock = esdhc->peripheral_clock; 526 else 527 clock = pltfm_host->clock; 528 return clock / 256 / 16; 529 } 530 531 static void esdhc_clock_enable(struct sdhci_host *host, bool enable) 532 { 533 u32 val; 534 ktime_t timeout; 535 536 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 537 538 if (enable) 539 val |= ESDHC_CLOCK_SDCLKEN; 540 else 541 val &= ~ESDHC_CLOCK_SDCLKEN; 542 543 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL); 544 545 /* Wait max 20 ms */ 546 timeout = ktime_add_ms(ktime_get(), 20); 547 val = ESDHC_CLOCK_STABLE; 548 while (1) { 549 bool timedout = ktime_after(ktime_get(), timeout); 550 551 if (sdhci_readl(host, ESDHC_PRSSTAT) & val) 552 break; 553 if (timedout) { 554 pr_err("%s: Internal clock never stabilised.\n", 555 mmc_hostname(host->mmc)); 556 break; 557 } 558 udelay(10); 559 } 560 } 561 562 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) 563 { 564 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 565 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 566 int pre_div = 1; 567 int div = 1; 568 int division; 569 ktime_t timeout; 570 long fixup = 0; 571 u32 temp; 572 573 host->mmc->actual_clock = 0; 574 575 if (clock == 0) { 576 esdhc_clock_enable(host, false); 577 return; 578 } 579 580 /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */ 581 if (esdhc->vendor_ver < VENDOR_V_23) 582 pre_div = 2; 583 584 if (host->mmc->card && mmc_card_sd(host->mmc->card) && 585 esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY) 586 fixup = esdhc->clk_fixup->sd_dflt_max_clk; 587 else if (esdhc->clk_fixup) 588 fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing]; 589 590 if (fixup && clock > fixup) 591 clock = fixup; 592 593 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 594 temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | 595 ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK); 596 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 597 598 while (host->max_clk / pre_div / 16 > clock && pre_div < 256) 599 pre_div *= 2; 600 601 while (host->max_clk / pre_div / div > clock && div < 16) 602 div++; 603 604 if (esdhc->quirk_limited_clk_division && 605 clock == MMC_HS200_MAX_DTR && 606 (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 || 607 host->flags & SDHCI_HS400_TUNING)) { 608 division = pre_div * div; 609 if (division <= 4) { 610 pre_div = 4; 611 div = 1; 612 } else if (division <= 8) { 613 pre_div = 4; 614 div = 2; 615 } else if (division <= 12) { 616 pre_div = 4; 617 div = 3; 618 } else { 619 pr_warn("%s: using unsupported clock division.\n", 620 mmc_hostname(host->mmc)); 621 } 622 } 623 624 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 625 clock, host->max_clk / pre_div / div); 626 host->mmc->actual_clock = host->max_clk / pre_div / div; 627 esdhc->div_ratio = pre_div * div; 628 pre_div >>= 1; 629 div--; 630 631 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 632 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 633 | (div << ESDHC_DIVIDER_SHIFT) 634 | (pre_div << ESDHC_PREDIV_SHIFT)); 635 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 636 637 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && 638 clock == MMC_HS200_MAX_DTR) { 639 temp = sdhci_readl(host, ESDHC_TBCTL); 640 sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL); 641 temp = sdhci_readl(host, ESDHC_SDCLKCTL); 642 sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL); 643 esdhc_clock_enable(host, true); 644 645 temp = sdhci_readl(host, ESDHC_DLLCFG0); 646 temp |= ESDHC_DLL_ENABLE; 647 if (host->mmc->actual_clock == MMC_HS200_MAX_DTR) 648 temp |= ESDHC_DLL_FREQ_SEL; 649 sdhci_writel(host, temp, ESDHC_DLLCFG0); 650 temp = sdhci_readl(host, ESDHC_TBCTL); 651 sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL); 652 653 esdhc_clock_enable(host, false); 654 temp = sdhci_readl(host, ESDHC_DMA_SYSCTL); 655 temp |= ESDHC_FLUSH_ASYNC_FIFO; 656 sdhci_writel(host, temp, ESDHC_DMA_SYSCTL); 657 } 658 659 /* Wait max 20 ms */ 660 timeout = ktime_add_ms(ktime_get(), 20); 661 while (1) { 662 bool timedout = ktime_after(ktime_get(), timeout); 663 664 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE) 665 break; 666 if (timedout) { 667 pr_err("%s: Internal clock never stabilised.\n", 668 mmc_hostname(host->mmc)); 669 return; 670 } 671 udelay(10); 672 } 673 674 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 675 temp |= ESDHC_CLOCK_SDCLKEN; 676 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 677 } 678 679 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 680 { 681 u32 ctrl; 682 683 ctrl = sdhci_readl(host, ESDHC_PROCTL); 684 ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK); 685 switch (width) { 686 case MMC_BUS_WIDTH_8: 687 ctrl |= ESDHC_CTRL_8BITBUS; 688 break; 689 690 case MMC_BUS_WIDTH_4: 691 ctrl |= ESDHC_CTRL_4BITBUS; 692 break; 693 694 default: 695 break; 696 } 697 698 sdhci_writel(host, ctrl, ESDHC_PROCTL); 699 } 700 701 static void esdhc_reset(struct sdhci_host *host, u8 mask) 702 { 703 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 704 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 705 u32 val; 706 707 sdhci_reset(host, mask); 708 709 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 710 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 711 712 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) 713 mdelay(5); 714 715 if (mask & SDHCI_RESET_ALL) { 716 val = sdhci_readl(host, ESDHC_TBCTL); 717 val &= ~ESDHC_TB_EN; 718 sdhci_writel(host, val, ESDHC_TBCTL); 719 720 if (esdhc->quirk_unreliable_pulse_detection) { 721 val = sdhci_readl(host, ESDHC_DLLCFG1); 722 val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL; 723 sdhci_writel(host, val, ESDHC_DLLCFG1); 724 } 725 } 726 } 727 728 /* The SCFG, Supplemental Configuration Unit, provides SoC specific 729 * configuration and status registers for the device. There is a 730 * SDHC IO VSEL control register on SCFG for some platforms. It's 731 * used to support SDHC IO voltage switching. 732 */ 733 static const struct of_device_id scfg_device_ids[] = { 734 { .compatible = "fsl,t1040-scfg", }, 735 { .compatible = "fsl,ls1012a-scfg", }, 736 { .compatible = "fsl,ls1046a-scfg", }, 737 {} 738 }; 739 740 /* SDHC IO VSEL control register definition */ 741 #define SCFG_SDHCIOVSELCR 0x408 742 #define SDHCIOVSELCR_TGLEN 0x80000000 743 #define SDHCIOVSELCR_VSELVAL 0x60000000 744 #define SDHCIOVSELCR_SDHC_VS 0x00000001 745 746 static int esdhc_signal_voltage_switch(struct mmc_host *mmc, 747 struct mmc_ios *ios) 748 { 749 struct sdhci_host *host = mmc_priv(mmc); 750 struct device_node *scfg_node; 751 void __iomem *scfg_base = NULL; 752 u32 sdhciovselcr; 753 u32 val; 754 755 /* 756 * Signal Voltage Switching is only applicable for Host Controllers 757 * v3.00 and above. 758 */ 759 if (host->version < SDHCI_SPEC_300) 760 return 0; 761 762 val = sdhci_readl(host, ESDHC_PROCTL); 763 764 switch (ios->signal_voltage) { 765 case MMC_SIGNAL_VOLTAGE_330: 766 val &= ~ESDHC_VOLT_SEL; 767 sdhci_writel(host, val, ESDHC_PROCTL); 768 return 0; 769 case MMC_SIGNAL_VOLTAGE_180: 770 scfg_node = of_find_matching_node(NULL, scfg_device_ids); 771 if (scfg_node) 772 scfg_base = of_iomap(scfg_node, 0); 773 if (scfg_base) { 774 sdhciovselcr = SDHCIOVSELCR_TGLEN | 775 SDHCIOVSELCR_VSELVAL; 776 iowrite32be(sdhciovselcr, 777 scfg_base + SCFG_SDHCIOVSELCR); 778 779 val |= ESDHC_VOLT_SEL; 780 sdhci_writel(host, val, ESDHC_PROCTL); 781 mdelay(5); 782 783 sdhciovselcr = SDHCIOVSELCR_TGLEN | 784 SDHCIOVSELCR_SDHC_VS; 785 iowrite32be(sdhciovselcr, 786 scfg_base + SCFG_SDHCIOVSELCR); 787 iounmap(scfg_base); 788 } else { 789 val |= ESDHC_VOLT_SEL; 790 sdhci_writel(host, val, ESDHC_PROCTL); 791 } 792 return 0; 793 default: 794 return 0; 795 } 796 } 797 798 static struct soc_device_attribute soc_fixup_tuning[] = { 799 { .family = "QorIQ T1040", .revision = "1.0", }, 800 { .family = "QorIQ T2080", .revision = "1.0", }, 801 { .family = "QorIQ T1023", .revision = "1.0", }, 802 { .family = "QorIQ LS1021A", .revision = "1.0", }, 803 { .family = "QorIQ LS1080A", .revision = "1.0", }, 804 { .family = "QorIQ LS2080A", .revision = "1.0", }, 805 { .family = "QorIQ LS1012A", .revision = "1.0", }, 806 { .family = "QorIQ LS1043A", .revision = "1.*", }, 807 { .family = "QorIQ LS1046A", .revision = "1.0", }, 808 { }, 809 }; 810 811 static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable) 812 { 813 u32 val; 814 815 esdhc_clock_enable(host, false); 816 817 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 818 val |= ESDHC_FLUSH_ASYNC_FIFO; 819 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 820 821 val = sdhci_readl(host, ESDHC_TBCTL); 822 if (enable) 823 val |= ESDHC_TB_EN; 824 else 825 val &= ~ESDHC_TB_EN; 826 sdhci_writel(host, val, ESDHC_TBCTL); 827 828 esdhc_clock_enable(host, true); 829 } 830 831 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 832 { 833 struct sdhci_host *host = mmc_priv(mmc); 834 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 835 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 836 bool hs400_tuning; 837 u32 val; 838 int ret; 839 840 if (esdhc->quirk_limited_clk_division && 841 host->flags & SDHCI_HS400_TUNING) 842 esdhc_of_set_clock(host, host->clock); 843 844 esdhc_tuning_block_enable(host, true); 845 846 hs400_tuning = host->flags & SDHCI_HS400_TUNING; 847 ret = sdhci_execute_tuning(mmc, opcode); 848 849 if (hs400_tuning) { 850 val = sdhci_readl(host, ESDHC_SDTIMNGCTL); 851 val |= ESDHC_FLW_CTL_BG; 852 sdhci_writel(host, val, ESDHC_SDTIMNGCTL); 853 } 854 855 if (host->tuning_err == -EAGAIN && esdhc->quirk_fixup_tuning) { 856 857 /* program TBPTR[TB_WNDW_END_PTR] = 3*DIV_RATIO and 858 * program TBPTR[TB_WNDW_START_PTR] = 5*DIV_RATIO 859 */ 860 val = sdhci_readl(host, ESDHC_TBPTR); 861 val = (val & ~((0x7f << 8) | 0x7f)) | 862 (3 * esdhc->div_ratio) | ((5 * esdhc->div_ratio) << 8); 863 sdhci_writel(host, val, ESDHC_TBPTR); 864 865 /* program the software tuning mode by setting 866 * TBCTL[TB_MODE]=2'h3 867 */ 868 val = sdhci_readl(host, ESDHC_TBCTL); 869 val |= 0x3; 870 sdhci_writel(host, val, ESDHC_TBCTL); 871 sdhci_execute_tuning(mmc, opcode); 872 } 873 return ret; 874 } 875 876 static void esdhc_set_uhs_signaling(struct sdhci_host *host, 877 unsigned int timing) 878 { 879 if (timing == MMC_TIMING_MMC_HS400) 880 esdhc_tuning_block_enable(host, true); 881 else 882 sdhci_set_uhs_signaling(host, timing); 883 } 884 885 static u32 esdhc_irq(struct sdhci_host *host, u32 intmask) 886 { 887 u32 command; 888 889 if (of_find_compatible_node(NULL, NULL, 890 "fsl,p2020-esdhc")) { 891 command = SDHCI_GET_CMD(sdhci_readw(host, 892 SDHCI_COMMAND)); 893 if (command == MMC_WRITE_MULTIPLE_BLOCK && 894 sdhci_readw(host, SDHCI_BLOCK_COUNT) && 895 intmask & SDHCI_INT_DATA_END) { 896 intmask &= ~SDHCI_INT_DATA_END; 897 sdhci_writel(host, SDHCI_INT_DATA_END, 898 SDHCI_INT_STATUS); 899 } 900 } 901 return intmask; 902 } 903 904 #ifdef CONFIG_PM_SLEEP 905 static u32 esdhc_proctl; 906 static int esdhc_of_suspend(struct device *dev) 907 { 908 struct sdhci_host *host = dev_get_drvdata(dev); 909 910 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL); 911 912 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 913 mmc_retune_needed(host->mmc); 914 915 return sdhci_suspend_host(host); 916 } 917 918 static int esdhc_of_resume(struct device *dev) 919 { 920 struct sdhci_host *host = dev_get_drvdata(dev); 921 int ret = sdhci_resume_host(host); 922 923 if (ret == 0) { 924 /* Isn't this already done by sdhci_resume_host() ? --rmk */ 925 esdhc_of_enable_dma(host); 926 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); 927 } 928 return ret; 929 } 930 #endif 931 932 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops, 933 esdhc_of_suspend, 934 esdhc_of_resume); 935 936 static const struct sdhci_ops sdhci_esdhc_be_ops = { 937 .read_l = esdhc_be_readl, 938 .read_w = esdhc_be_readw, 939 .read_b = esdhc_be_readb, 940 .write_l = esdhc_be_writel, 941 .write_w = esdhc_be_writew, 942 .write_b = esdhc_be_writeb, 943 .set_clock = esdhc_of_set_clock, 944 .enable_dma = esdhc_of_enable_dma, 945 .get_max_clock = esdhc_of_get_max_clock, 946 .get_min_clock = esdhc_of_get_min_clock, 947 .adma_workaround = esdhc_of_adma_workaround, 948 .set_bus_width = esdhc_pltfm_set_bus_width, 949 .reset = esdhc_reset, 950 .set_uhs_signaling = esdhc_set_uhs_signaling, 951 .irq = esdhc_irq, 952 }; 953 954 static const struct sdhci_ops sdhci_esdhc_le_ops = { 955 .read_l = esdhc_le_readl, 956 .read_w = esdhc_le_readw, 957 .read_b = esdhc_le_readb, 958 .write_l = esdhc_le_writel, 959 .write_w = esdhc_le_writew, 960 .write_b = esdhc_le_writeb, 961 .set_clock = esdhc_of_set_clock, 962 .enable_dma = esdhc_of_enable_dma, 963 .get_max_clock = esdhc_of_get_max_clock, 964 .get_min_clock = esdhc_of_get_min_clock, 965 .adma_workaround = esdhc_of_adma_workaround, 966 .set_bus_width = esdhc_pltfm_set_bus_width, 967 .reset = esdhc_reset, 968 .set_uhs_signaling = esdhc_set_uhs_signaling, 969 .irq = esdhc_irq, 970 }; 971 972 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = { 973 .quirks = ESDHC_DEFAULT_QUIRKS | 974 #ifdef CONFIG_PPC 975 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 976 #endif 977 SDHCI_QUIRK_NO_CARD_NO_RESET | 978 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 979 .ops = &sdhci_esdhc_be_ops, 980 }; 981 982 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = { 983 .quirks = ESDHC_DEFAULT_QUIRKS | 984 SDHCI_QUIRK_NO_CARD_NO_RESET | 985 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 986 .ops = &sdhci_esdhc_le_ops, 987 }; 988 989 static struct soc_device_attribute soc_incorrect_hostver[] = { 990 { .family = "QorIQ T4240", .revision = "1.0", }, 991 { .family = "QorIQ T4240", .revision = "2.0", }, 992 { }, 993 }; 994 995 static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = { 996 { .family = "QorIQ LX2160A", .revision = "1.0", }, 997 { .family = "QorIQ LX2160A", .revision = "2.0", }, 998 { }, 999 }; 1000 1001 static struct soc_device_attribute soc_unreliable_pulse_detection[] = { 1002 { .family = "QorIQ LX2160A", .revision = "1.0", }, 1003 { }, 1004 }; 1005 1006 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host) 1007 { 1008 const struct of_device_id *match; 1009 struct sdhci_pltfm_host *pltfm_host; 1010 struct sdhci_esdhc *esdhc; 1011 struct device_node *np; 1012 struct clk *clk; 1013 u32 val; 1014 u16 host_ver; 1015 1016 pltfm_host = sdhci_priv(host); 1017 esdhc = sdhci_pltfm_priv(pltfm_host); 1018 1019 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); 1020 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >> 1021 SDHCI_VENDOR_VER_SHIFT; 1022 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK; 1023 if (soc_device_match(soc_incorrect_hostver)) 1024 esdhc->quirk_incorrect_hostver = true; 1025 else 1026 esdhc->quirk_incorrect_hostver = false; 1027 1028 if (soc_device_match(soc_fixup_sdhc_clkdivs)) 1029 esdhc->quirk_limited_clk_division = true; 1030 else 1031 esdhc->quirk_limited_clk_division = false; 1032 1033 if (soc_device_match(soc_unreliable_pulse_detection)) 1034 esdhc->quirk_unreliable_pulse_detection = true; 1035 else 1036 esdhc->quirk_unreliable_pulse_detection = false; 1037 1038 match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node); 1039 if (match) 1040 esdhc->clk_fixup = match->data; 1041 np = pdev->dev.of_node; 1042 clk = of_clk_get(np, 0); 1043 if (!IS_ERR(clk)) { 1044 /* 1045 * esdhc->peripheral_clock would be assigned with a value 1046 * which is eSDHC base clock when use periperal clock. 1047 * For ls1046a, the clock value got by common clk API is 1048 * peripheral clock while the eSDHC base clock is 1/2 1049 * peripheral clock. 1050 */ 1051 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc")) 1052 esdhc->peripheral_clock = clk_get_rate(clk) / 2; 1053 else 1054 esdhc->peripheral_clock = clk_get_rate(clk); 1055 1056 clk_put(clk); 1057 } 1058 1059 if (esdhc->peripheral_clock) { 1060 esdhc_clock_enable(host, false); 1061 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 1062 val |= ESDHC_PERIPHERAL_CLK_SEL; 1063 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 1064 esdhc_clock_enable(host, true); 1065 } 1066 } 1067 1068 static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc) 1069 { 1070 esdhc_tuning_block_enable(mmc_priv(mmc), false); 1071 return 0; 1072 } 1073 1074 static int sdhci_esdhc_probe(struct platform_device *pdev) 1075 { 1076 struct sdhci_host *host; 1077 struct device_node *np; 1078 struct sdhci_pltfm_host *pltfm_host; 1079 struct sdhci_esdhc *esdhc; 1080 int ret; 1081 1082 np = pdev->dev.of_node; 1083 1084 if (of_property_read_bool(np, "little-endian")) 1085 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata, 1086 sizeof(struct sdhci_esdhc)); 1087 else 1088 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata, 1089 sizeof(struct sdhci_esdhc)); 1090 1091 if (IS_ERR(host)) 1092 return PTR_ERR(host); 1093 1094 host->mmc_host_ops.start_signal_voltage_switch = 1095 esdhc_signal_voltage_switch; 1096 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning; 1097 host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr; 1098 host->tuning_delay = 1; 1099 1100 esdhc_init(pdev, host); 1101 1102 sdhci_get_of_property(pdev); 1103 1104 pltfm_host = sdhci_priv(host); 1105 esdhc = sdhci_pltfm_priv(pltfm_host); 1106 if (soc_device_match(soc_fixup_tuning)) 1107 esdhc->quirk_fixup_tuning = true; 1108 else 1109 esdhc->quirk_fixup_tuning = false; 1110 1111 if (esdhc->vendor_ver == VENDOR_V_22) 1112 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; 1113 1114 if (esdhc->vendor_ver > VENDOR_V_22) 1115 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1116 1117 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) { 1118 host->quirks2 |= SDHCI_QUIRK_RESET_AFTER_REQUEST; 1119 host->quirks2 |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1120 } 1121 1122 if (of_device_is_compatible(np, "fsl,p5040-esdhc") || 1123 of_device_is_compatible(np, "fsl,p5020-esdhc") || 1124 of_device_is_compatible(np, "fsl,p4080-esdhc") || 1125 of_device_is_compatible(np, "fsl,p1020-esdhc") || 1126 of_device_is_compatible(np, "fsl,t1040-esdhc")) 1127 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1128 1129 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc")) 1130 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1131 1132 esdhc->quirk_ignore_data_inhibit = false; 1133 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { 1134 /* 1135 * Freescale messed up with P2020 as it has a non-standard 1136 * host control register 1137 */ 1138 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL; 1139 esdhc->quirk_ignore_data_inhibit = true; 1140 } 1141 1142 /* call to generic mmc_of_parse to support additional capabilities */ 1143 ret = mmc_of_parse(host->mmc); 1144 if (ret) 1145 goto err; 1146 1147 mmc_of_parse_voltage(np, &host->ocr_mask); 1148 1149 ret = sdhci_add_host(host); 1150 if (ret) 1151 goto err; 1152 1153 return 0; 1154 err: 1155 sdhci_pltfm_free(pdev); 1156 return ret; 1157 } 1158 1159 static struct platform_driver sdhci_esdhc_driver = { 1160 .driver = { 1161 .name = "sdhci-esdhc", 1162 .of_match_table = sdhci_esdhc_of_match, 1163 .pm = &esdhc_of_dev_pm_ops, 1164 }, 1165 .probe = sdhci_esdhc_probe, 1166 .remove = sdhci_pltfm_unregister, 1167 }; 1168 1169 module_platform_driver(sdhci_esdhc_driver); 1170 1171 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC"); 1172 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, " 1173 "Anton Vorontsov <avorontsov@ru.mvista.com>"); 1174 MODULE_LICENSE("GPL v2"); 1175