17657c3a7SAlbert Herranz /* 27657c3a7SAlbert Herranz * Freescale eSDHC controller driver. 37657c3a7SAlbert Herranz * 4f060bc9cSJerry Huang * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. 57657c3a7SAlbert Herranz * Copyright (c) 2009 MontaVista Software, Inc. 67657c3a7SAlbert Herranz * 77657c3a7SAlbert Herranz * Authors: Xiaobo Xie <X.Xie@freescale.com> 87657c3a7SAlbert Herranz * Anton Vorontsov <avorontsov@ru.mvista.com> 97657c3a7SAlbert Herranz * 107657c3a7SAlbert Herranz * This program is free software; you can redistribute it and/or modify 117657c3a7SAlbert Herranz * it under the terms of the GNU General Public License as published by 127657c3a7SAlbert Herranz * the Free Software Foundation; either version 2 of the License, or (at 137657c3a7SAlbert Herranz * your option) any later version. 147657c3a7SAlbert Herranz */ 157657c3a7SAlbert Herranz 1666b50a00SOded Gabbay #include <linux/err.h> 177657c3a7SAlbert Herranz #include <linux/io.h> 18f060bc9cSJerry Huang #include <linux/of.h> 19ea35645aSyangbo lu #include <linux/of_address.h> 207657c3a7SAlbert Herranz #include <linux/delay.h> 2188b47679SPaul Gortmaker #include <linux/module.h> 22151ede40Syangbo lu #include <linux/sys_soc.h> 2319c3a0efSyangbo lu #include <linux/clk.h> 2419c3a0efSyangbo lu #include <linux/ktime.h> 255552d7adSLaurentiu Tudor #include <linux/dma-mapping.h> 267657c3a7SAlbert Herranz #include <linux/mmc/host.h> 27b214fe59SYinbo Zhu #include <linux/mmc/mmc.h> 2838576af1SShawn Guo #include "sdhci-pltfm.h" 2980872e21SWolfram Sang #include "sdhci-esdhc.h" 307657c3a7SAlbert Herranz 31137ccd46SJerry Huang #define VENDOR_V_22 0x12 32a4071fbbSHaijun Zhang #define VENDOR_V_23 0x13 33f4932cfdSyangbo lu 3467fdfbdfSyinbo.zhu #define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1) 3567fdfbdfSyinbo.zhu 3667fdfbdfSyinbo.zhu struct esdhc_clk_fixup { 3767fdfbdfSyinbo.zhu const unsigned int sd_dflt_max_clk; 3867fdfbdfSyinbo.zhu const unsigned int max_clk[MMC_TIMING_NUM]; 3967fdfbdfSyinbo.zhu }; 4067fdfbdfSyinbo.zhu 4167fdfbdfSyinbo.zhu static const struct esdhc_clk_fixup ls1021a_esdhc_clk = { 4267fdfbdfSyinbo.zhu .sd_dflt_max_clk = 25000000, 4367fdfbdfSyinbo.zhu .max_clk[MMC_TIMING_MMC_HS] = 46500000, 4467fdfbdfSyinbo.zhu .max_clk[MMC_TIMING_SD_HS] = 46500000, 4567fdfbdfSyinbo.zhu }; 4667fdfbdfSyinbo.zhu 4767fdfbdfSyinbo.zhu static const struct esdhc_clk_fixup ls1046a_esdhc_clk = { 4867fdfbdfSyinbo.zhu .sd_dflt_max_clk = 25000000, 4967fdfbdfSyinbo.zhu .max_clk[MMC_TIMING_UHS_SDR104] = 167000000, 5067fdfbdfSyinbo.zhu .max_clk[MMC_TIMING_MMC_HS200] = 167000000, 5167fdfbdfSyinbo.zhu }; 5267fdfbdfSyinbo.zhu 5367fdfbdfSyinbo.zhu static const struct esdhc_clk_fixup ls1012a_esdhc_clk = { 5467fdfbdfSyinbo.zhu .sd_dflt_max_clk = 25000000, 5567fdfbdfSyinbo.zhu .max_clk[MMC_TIMING_UHS_SDR104] = 125000000, 5667fdfbdfSyinbo.zhu .max_clk[MMC_TIMING_MMC_HS200] = 125000000, 5767fdfbdfSyinbo.zhu }; 5867fdfbdfSyinbo.zhu 5967fdfbdfSyinbo.zhu static const struct esdhc_clk_fixup p1010_esdhc_clk = { 6067fdfbdfSyinbo.zhu .sd_dflt_max_clk = 20000000, 6167fdfbdfSyinbo.zhu .max_clk[MMC_TIMING_LEGACY] = 20000000, 6267fdfbdfSyinbo.zhu .max_clk[MMC_TIMING_MMC_HS] = 42000000, 6367fdfbdfSyinbo.zhu .max_clk[MMC_TIMING_SD_HS] = 40000000, 6467fdfbdfSyinbo.zhu }; 6567fdfbdfSyinbo.zhu 6667fdfbdfSyinbo.zhu static const struct of_device_id sdhci_esdhc_of_match[] = { 6767fdfbdfSyinbo.zhu { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk}, 6867fdfbdfSyinbo.zhu { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk}, 6967fdfbdfSyinbo.zhu { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk}, 7067fdfbdfSyinbo.zhu { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk}, 7167fdfbdfSyinbo.zhu { .compatible = "fsl,mpc8379-esdhc" }, 7267fdfbdfSyinbo.zhu { .compatible = "fsl,mpc8536-esdhc" }, 7367fdfbdfSyinbo.zhu { .compatible = "fsl,esdhc" }, 7467fdfbdfSyinbo.zhu { } 7567fdfbdfSyinbo.zhu }; 7667fdfbdfSyinbo.zhu MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); 7767fdfbdfSyinbo.zhu 78f4932cfdSyangbo lu struct sdhci_esdhc { 79f4932cfdSyangbo lu u8 vendor_ver; 80f4932cfdSyangbo lu u8 spec_ver; 81151ede40Syangbo lu bool quirk_incorrect_hostver; 826079e63cSYangbo Lu bool quirk_limited_clk_division; 8348e304ccSYangbo Lu bool quirk_unreliable_pulse_detection; 84b1f378abSYinbo Zhu bool quirk_fixup_tuning; 8519c3a0efSyangbo lu unsigned int peripheral_clock; 8667fdfbdfSyinbo.zhu const struct esdhc_clk_fixup *clk_fixup; 87b1f378abSYinbo Zhu u32 div_ratio; 88f4932cfdSyangbo lu }; 89f4932cfdSyangbo lu 90f4932cfdSyangbo lu /** 91f4932cfdSyangbo lu * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register 92f4932cfdSyangbo lu * to make it compatible with SD spec. 93f4932cfdSyangbo lu * 94f4932cfdSyangbo lu * @host: pointer to sdhci_host 95f4932cfdSyangbo lu * @spec_reg: SD spec register address 96f4932cfdSyangbo lu * @value: 32bit eSDHC register value on spec_reg address 97f4932cfdSyangbo lu * 98f4932cfdSyangbo lu * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 99f4932cfdSyangbo lu * registers are 32 bits. There are differences in register size, register 100f4932cfdSyangbo lu * address, register function, bit position and function between eSDHC spec 101f4932cfdSyangbo lu * and SD spec. 102f4932cfdSyangbo lu * 103f4932cfdSyangbo lu * Return a fixed up register value 104f4932cfdSyangbo lu */ 105f4932cfdSyangbo lu static u32 esdhc_readl_fixup(struct sdhci_host *host, 106f4932cfdSyangbo lu int spec_reg, u32 value) 107137ccd46SJerry Huang { 108f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1098605e7aeSJisheng Zhang struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 110137ccd46SJerry Huang u32 ret; 111137ccd46SJerry Huang 112137ccd46SJerry Huang /* 113137ccd46SJerry Huang * The bit of ADMA flag in eSDHC is not compatible with standard 114137ccd46SJerry Huang * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is 115137ccd46SJerry Huang * supported by eSDHC. 116137ccd46SJerry Huang * And for many FSL eSDHC controller, the reset value of field 117f4932cfdSyangbo lu * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA, 118137ccd46SJerry Huang * only these vendor version is greater than 2.2/0x12 support ADMA. 119137ccd46SJerry Huang */ 120f4932cfdSyangbo lu if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) { 121f4932cfdSyangbo lu if (esdhc->vendor_ver > VENDOR_V_22) { 122f4932cfdSyangbo lu ret = value | SDHCI_CAN_DO_ADMA2; 123f4932cfdSyangbo lu return ret; 124137ccd46SJerry Huang } 125f4932cfdSyangbo lu } 126b0921d5cSMichael Walle /* 127b0921d5cSMichael Walle * The DAT[3:0] line signal levels and the CMD line signal level are 128b0921d5cSMichael Walle * not compatible with standard SDHC register. The line signal levels 129b0921d5cSMichael Walle * DAT[7:0] are at bits 31:24 and the command line signal level is at 130b0921d5cSMichael Walle * bit 23. All other bits are the same as in the standard SDHC 131b0921d5cSMichael Walle * register. 132b0921d5cSMichael Walle */ 133b0921d5cSMichael Walle if (spec_reg == SDHCI_PRESENT_STATE) { 134b0921d5cSMichael Walle ret = value & 0x000fffff; 135b0921d5cSMichael Walle ret |= (value >> 4) & SDHCI_DATA_LVL_MASK; 136b0921d5cSMichael Walle ret |= (value << 1) & SDHCI_CMD_LVL; 137b0921d5cSMichael Walle return ret; 138b0921d5cSMichael Walle } 139b0921d5cSMichael Walle 1402f3110ccSyangbo lu /* 1412f3110ccSyangbo lu * DTS properties of mmc host are used to enable each speed mode 1422f3110ccSyangbo lu * according to soc and board capability. So clean up 1432f3110ccSyangbo lu * SDR50/SDR104/DDR50 support bits here. 1442f3110ccSyangbo lu */ 1452f3110ccSyangbo lu if (spec_reg == SDHCI_CAPABILITIES_1) { 1462f3110ccSyangbo lu ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 1472f3110ccSyangbo lu SDHCI_SUPPORT_DDR50); 1482f3110ccSyangbo lu return ret; 1492f3110ccSyangbo lu } 1502f3110ccSyangbo lu 151f4932cfdSyangbo lu ret = value; 152137ccd46SJerry Huang return ret; 153137ccd46SJerry Huang } 154137ccd46SJerry Huang 155f4932cfdSyangbo lu static u16 esdhc_readw_fixup(struct sdhci_host *host, 156f4932cfdSyangbo lu int spec_reg, u32 value) 1577657c3a7SAlbert Herranz { 158151ede40Syangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 159151ede40Syangbo lu struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 1607657c3a7SAlbert Herranz u16 ret; 161f4932cfdSyangbo lu int shift = (spec_reg & 0x2) * 8; 1627657c3a7SAlbert Herranz 163f4932cfdSyangbo lu if (spec_reg == SDHCI_HOST_VERSION) 164f4932cfdSyangbo lu ret = value & 0xffff; 1657657c3a7SAlbert Herranz else 166f4932cfdSyangbo lu ret = (value >> shift) & 0xffff; 167151ede40Syangbo lu /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect 168151ede40Syangbo lu * vendor version and spec version information. 169151ede40Syangbo lu */ 170151ede40Syangbo lu if ((spec_reg == SDHCI_HOST_VERSION) && 171151ede40Syangbo lu (esdhc->quirk_incorrect_hostver)) 172151ede40Syangbo lu ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200; 173e51cbc9eSXu lei return ret; 174e51cbc9eSXu lei } 175e51cbc9eSXu lei 176f4932cfdSyangbo lu static u8 esdhc_readb_fixup(struct sdhci_host *host, 177f4932cfdSyangbo lu int spec_reg, u32 value) 178e51cbc9eSXu lei { 179f4932cfdSyangbo lu u8 ret; 180f4932cfdSyangbo lu u8 dma_bits; 181f4932cfdSyangbo lu int shift = (spec_reg & 0x3) * 8; 182f4932cfdSyangbo lu 183f4932cfdSyangbo lu ret = (value >> shift) & 0xff; 184ba8c4dc9SRoy Zang 185ba8c4dc9SRoy Zang /* 186ba8c4dc9SRoy Zang * "DMA select" locates at offset 0x28 in SD specification, but on 187ba8c4dc9SRoy Zang * P5020 or P3041, it locates at 0x29. 188ba8c4dc9SRoy Zang */ 189f4932cfdSyangbo lu if (spec_reg == SDHCI_HOST_CONTROL) { 190ba8c4dc9SRoy Zang /* DMA select is 22,23 bits in Protocol Control Register */ 191f4932cfdSyangbo lu dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK; 192ba8c4dc9SRoy Zang /* fixup the result */ 193ba8c4dc9SRoy Zang ret &= ~SDHCI_CTRL_DMA_MASK; 194ba8c4dc9SRoy Zang ret |= dma_bits; 195ba8c4dc9SRoy Zang } 196f4932cfdSyangbo lu return ret; 197f4932cfdSyangbo lu } 198f4932cfdSyangbo lu 199f4932cfdSyangbo lu /** 200f4932cfdSyangbo lu * esdhc_write*_fixup - Fixup the SD spec register value so that it could be 201f4932cfdSyangbo lu * written into eSDHC register. 202f4932cfdSyangbo lu * 203f4932cfdSyangbo lu * @host: pointer to sdhci_host 204f4932cfdSyangbo lu * @spec_reg: SD spec register address 205f4932cfdSyangbo lu * @value: 8/16/32bit SD spec register value that would be written 206f4932cfdSyangbo lu * @old_value: 32bit eSDHC register value on spec_reg address 207f4932cfdSyangbo lu * 208f4932cfdSyangbo lu * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 209f4932cfdSyangbo lu * registers are 32 bits. There are differences in register size, register 210f4932cfdSyangbo lu * address, register function, bit position and function between eSDHC spec 211f4932cfdSyangbo lu * and SD spec. 212f4932cfdSyangbo lu * 213f4932cfdSyangbo lu * Return a fixed up register value 214f4932cfdSyangbo lu */ 215f4932cfdSyangbo lu static u32 esdhc_writel_fixup(struct sdhci_host *host, 216f4932cfdSyangbo lu int spec_reg, u32 value, u32 old_value) 217f4932cfdSyangbo lu { 218f4932cfdSyangbo lu u32 ret; 219f4932cfdSyangbo lu 220f4932cfdSyangbo lu /* 221f4932cfdSyangbo lu * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE] 222f4932cfdSyangbo lu * when SYSCTL[RSTD] is set for some special operations. 223f4932cfdSyangbo lu * No any impact on other operation. 224f4932cfdSyangbo lu */ 225f4932cfdSyangbo lu if (spec_reg == SDHCI_INT_ENABLE) 226f4932cfdSyangbo lu ret = value | SDHCI_INT_BLK_GAP; 227f4932cfdSyangbo lu else 228f4932cfdSyangbo lu ret = value; 229ba8c4dc9SRoy Zang 2307657c3a7SAlbert Herranz return ret; 2317657c3a7SAlbert Herranz } 2327657c3a7SAlbert Herranz 233f4932cfdSyangbo lu static u32 esdhc_writew_fixup(struct sdhci_host *host, 234f4932cfdSyangbo lu int spec_reg, u16 value, u32 old_value) 235a4071fbbSHaijun Zhang { 236f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 237f4932cfdSyangbo lu int shift = (spec_reg & 0x2) * 8; 238f4932cfdSyangbo lu u32 ret; 239f4932cfdSyangbo lu 240f4932cfdSyangbo lu switch (spec_reg) { 241f4932cfdSyangbo lu case SDHCI_TRANSFER_MODE: 242a4071fbbSHaijun Zhang /* 243f4932cfdSyangbo lu * Postpone this write, we must do it together with a 244f4932cfdSyangbo lu * command write that is down below. Return old value. 245a4071fbbSHaijun Zhang */ 246f4932cfdSyangbo lu pltfm_host->xfer_mode_shadow = value; 247f4932cfdSyangbo lu return old_value; 248f4932cfdSyangbo lu case SDHCI_COMMAND: 249f4932cfdSyangbo lu ret = (value << 16) | pltfm_host->xfer_mode_shadow; 250f4932cfdSyangbo lu return ret; 251a4071fbbSHaijun Zhang } 252a4071fbbSHaijun Zhang 253f4932cfdSyangbo lu ret = old_value & (~(0xffff << shift)); 254f4932cfdSyangbo lu ret |= (value << shift); 255f4932cfdSyangbo lu 256f4932cfdSyangbo lu if (spec_reg == SDHCI_BLOCK_SIZE) { 2577657c3a7SAlbert Herranz /* 2587657c3a7SAlbert Herranz * Two last DMA bits are reserved, and first one is used for 2597657c3a7SAlbert Herranz * non-standard blksz of 4096 bytes that we don't support 2607657c3a7SAlbert Herranz * yet. So clear the DMA boundary bits. 2617657c3a7SAlbert Herranz */ 262f4932cfdSyangbo lu ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0)); 2637657c3a7SAlbert Herranz } 264f4932cfdSyangbo lu return ret; 2657657c3a7SAlbert Herranz } 2667657c3a7SAlbert Herranz 267f4932cfdSyangbo lu static u32 esdhc_writeb_fixup(struct sdhci_host *host, 268f4932cfdSyangbo lu int spec_reg, u8 value, u32 old_value) 2697657c3a7SAlbert Herranz { 270f4932cfdSyangbo lu u32 ret; 271f4932cfdSyangbo lu u32 dma_bits; 272f4932cfdSyangbo lu u8 tmp; 273f4932cfdSyangbo lu int shift = (spec_reg & 0x3) * 8; 274f4932cfdSyangbo lu 275ba8c4dc9SRoy Zang /* 2769e4703dfSyangbo lu * eSDHC doesn't have a standard power control register, so we do 2779e4703dfSyangbo lu * nothing here to avoid incorrect operation. 2789e4703dfSyangbo lu */ 2799e4703dfSyangbo lu if (spec_reg == SDHCI_POWER_CONTROL) 2809e4703dfSyangbo lu return old_value; 2819e4703dfSyangbo lu /* 282ba8c4dc9SRoy Zang * "DMA select" location is offset 0x28 in SD specification, but on 283ba8c4dc9SRoy Zang * P5020 or P3041, it's located at 0x29. 284ba8c4dc9SRoy Zang */ 285f4932cfdSyangbo lu if (spec_reg == SDHCI_HOST_CONTROL) { 286dcaff04dSOded Gabbay /* 287dcaff04dSOded Gabbay * If host control register is not standard, exit 288dcaff04dSOded Gabbay * this function 289dcaff04dSOded Gabbay */ 290dcaff04dSOded Gabbay if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL) 291f4932cfdSyangbo lu return old_value; 292dcaff04dSOded Gabbay 293ba8c4dc9SRoy Zang /* DMA select is 22,23 bits in Protocol Control Register */ 294f4932cfdSyangbo lu dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5; 295f4932cfdSyangbo lu ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits; 296f4932cfdSyangbo lu tmp = (value & (~SDHCI_CTRL_DMA_MASK)) | 297f4932cfdSyangbo lu (old_value & SDHCI_CTRL_DMA_MASK); 298f4932cfdSyangbo lu ret = (ret & (~0xff)) | tmp; 299f4932cfdSyangbo lu 300f4932cfdSyangbo lu /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */ 301f4932cfdSyangbo lu ret &= ~ESDHC_HOST_CONTROL_RES; 302f4932cfdSyangbo lu return ret; 303ba8c4dc9SRoy Zang } 304ba8c4dc9SRoy Zang 305f4932cfdSyangbo lu ret = (old_value & (~(0xff << shift))) | (value << shift); 306f4932cfdSyangbo lu return ret; 307f4932cfdSyangbo lu } 308f4932cfdSyangbo lu 309f4932cfdSyangbo lu static u32 esdhc_be_readl(struct sdhci_host *host, int reg) 310f4932cfdSyangbo lu { 311f4932cfdSyangbo lu u32 ret; 312f4932cfdSyangbo lu u32 value; 313f4932cfdSyangbo lu 3142f3110ccSyangbo lu if (reg == SDHCI_CAPABILITIES_1) 3152f3110ccSyangbo lu value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1); 3162f3110ccSyangbo lu else 317f4932cfdSyangbo lu value = ioread32be(host->ioaddr + reg); 3182f3110ccSyangbo lu 319f4932cfdSyangbo lu ret = esdhc_readl_fixup(host, reg, value); 320f4932cfdSyangbo lu 321f4932cfdSyangbo lu return ret; 322f4932cfdSyangbo lu } 323f4932cfdSyangbo lu 324f4932cfdSyangbo lu static u32 esdhc_le_readl(struct sdhci_host *host, int reg) 325f4932cfdSyangbo lu { 326f4932cfdSyangbo lu u32 ret; 327f4932cfdSyangbo lu u32 value; 328f4932cfdSyangbo lu 3292f3110ccSyangbo lu if (reg == SDHCI_CAPABILITIES_1) 3302f3110ccSyangbo lu value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1); 3312f3110ccSyangbo lu else 332f4932cfdSyangbo lu value = ioread32(host->ioaddr + reg); 3332f3110ccSyangbo lu 334f4932cfdSyangbo lu ret = esdhc_readl_fixup(host, reg, value); 335f4932cfdSyangbo lu 336f4932cfdSyangbo lu return ret; 337f4932cfdSyangbo lu } 338f4932cfdSyangbo lu 339f4932cfdSyangbo lu static u16 esdhc_be_readw(struct sdhci_host *host, int reg) 340f4932cfdSyangbo lu { 341f4932cfdSyangbo lu u16 ret; 342f4932cfdSyangbo lu u32 value; 343f4932cfdSyangbo lu int base = reg & ~0x3; 344f4932cfdSyangbo lu 345f4932cfdSyangbo lu value = ioread32be(host->ioaddr + base); 346f4932cfdSyangbo lu ret = esdhc_readw_fixup(host, reg, value); 347f4932cfdSyangbo lu return ret; 348f4932cfdSyangbo lu } 349f4932cfdSyangbo lu 350f4932cfdSyangbo lu static u16 esdhc_le_readw(struct sdhci_host *host, int reg) 351f4932cfdSyangbo lu { 352f4932cfdSyangbo lu u16 ret; 353f4932cfdSyangbo lu u32 value; 354f4932cfdSyangbo lu int base = reg & ~0x3; 355f4932cfdSyangbo lu 356f4932cfdSyangbo lu value = ioread32(host->ioaddr + base); 357f4932cfdSyangbo lu ret = esdhc_readw_fixup(host, reg, value); 358f4932cfdSyangbo lu return ret; 359f4932cfdSyangbo lu } 360f4932cfdSyangbo lu 361f4932cfdSyangbo lu static u8 esdhc_be_readb(struct sdhci_host *host, int reg) 362f4932cfdSyangbo lu { 363f4932cfdSyangbo lu u8 ret; 364f4932cfdSyangbo lu u32 value; 365f4932cfdSyangbo lu int base = reg & ~0x3; 366f4932cfdSyangbo lu 367f4932cfdSyangbo lu value = ioread32be(host->ioaddr + base); 368f4932cfdSyangbo lu ret = esdhc_readb_fixup(host, reg, value); 369f4932cfdSyangbo lu return ret; 370f4932cfdSyangbo lu } 371f4932cfdSyangbo lu 372f4932cfdSyangbo lu static u8 esdhc_le_readb(struct sdhci_host *host, int reg) 373f4932cfdSyangbo lu { 374f4932cfdSyangbo lu u8 ret; 375f4932cfdSyangbo lu u32 value; 376f4932cfdSyangbo lu int base = reg & ~0x3; 377f4932cfdSyangbo lu 378f4932cfdSyangbo lu value = ioread32(host->ioaddr + base); 379f4932cfdSyangbo lu ret = esdhc_readb_fixup(host, reg, value); 380f4932cfdSyangbo lu return ret; 381f4932cfdSyangbo lu } 382f4932cfdSyangbo lu 383f4932cfdSyangbo lu static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) 384f4932cfdSyangbo lu { 385f4932cfdSyangbo lu u32 value; 386f4932cfdSyangbo lu 387f4932cfdSyangbo lu value = esdhc_writel_fixup(host, reg, val, 0); 388f4932cfdSyangbo lu iowrite32be(value, host->ioaddr + reg); 389f4932cfdSyangbo lu } 390f4932cfdSyangbo lu 391f4932cfdSyangbo lu static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) 392f4932cfdSyangbo lu { 393f4932cfdSyangbo lu u32 value; 394f4932cfdSyangbo lu 395f4932cfdSyangbo lu value = esdhc_writel_fixup(host, reg, val, 0); 396f4932cfdSyangbo lu iowrite32(value, host->ioaddr + reg); 397f4932cfdSyangbo lu } 398f4932cfdSyangbo lu 399f4932cfdSyangbo lu static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) 400f4932cfdSyangbo lu { 401f4932cfdSyangbo lu int base = reg & ~0x3; 402f4932cfdSyangbo lu u32 value; 403f4932cfdSyangbo lu u32 ret; 404f4932cfdSyangbo lu 405f4932cfdSyangbo lu value = ioread32be(host->ioaddr + base); 406f4932cfdSyangbo lu ret = esdhc_writew_fixup(host, reg, val, value); 407f4932cfdSyangbo lu if (reg != SDHCI_TRANSFER_MODE) 408f4932cfdSyangbo lu iowrite32be(ret, host->ioaddr + base); 409f4932cfdSyangbo lu } 410f4932cfdSyangbo lu 411f4932cfdSyangbo lu static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) 412f4932cfdSyangbo lu { 413f4932cfdSyangbo lu int base = reg & ~0x3; 414f4932cfdSyangbo lu u32 value; 415f4932cfdSyangbo lu u32 ret; 416f4932cfdSyangbo lu 417f4932cfdSyangbo lu value = ioread32(host->ioaddr + base); 418f4932cfdSyangbo lu ret = esdhc_writew_fixup(host, reg, val, value); 419f4932cfdSyangbo lu if (reg != SDHCI_TRANSFER_MODE) 420f4932cfdSyangbo lu iowrite32(ret, host->ioaddr + base); 421f4932cfdSyangbo lu } 422f4932cfdSyangbo lu 423f4932cfdSyangbo lu static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) 424f4932cfdSyangbo lu { 425f4932cfdSyangbo lu int base = reg & ~0x3; 426f4932cfdSyangbo lu u32 value; 427f4932cfdSyangbo lu u32 ret; 428f4932cfdSyangbo lu 429f4932cfdSyangbo lu value = ioread32be(host->ioaddr + base); 430f4932cfdSyangbo lu ret = esdhc_writeb_fixup(host, reg, val, value); 431f4932cfdSyangbo lu iowrite32be(ret, host->ioaddr + base); 432f4932cfdSyangbo lu } 433f4932cfdSyangbo lu 434f4932cfdSyangbo lu static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) 435f4932cfdSyangbo lu { 436f4932cfdSyangbo lu int base = reg & ~0x3; 437f4932cfdSyangbo lu u32 value; 438f4932cfdSyangbo lu u32 ret; 439f4932cfdSyangbo lu 440f4932cfdSyangbo lu value = ioread32(host->ioaddr + base); 441f4932cfdSyangbo lu ret = esdhc_writeb_fixup(host, reg, val, value); 442f4932cfdSyangbo lu iowrite32(ret, host->ioaddr + base); 4437657c3a7SAlbert Herranz } 4447657c3a7SAlbert Herranz 445a4071fbbSHaijun Zhang /* 446a4071fbbSHaijun Zhang * For Abort or Suspend after Stop at Block Gap, ignore the ADMA 447a4071fbbSHaijun Zhang * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC]) 448a4071fbbSHaijun Zhang * and Block Gap Event(IRQSTAT[BGE]) are also set. 449a4071fbbSHaijun Zhang * For Continue, apply soft reset for data(SYSCTL[RSTD]); 450a4071fbbSHaijun Zhang * and re-issue the entire read transaction from beginning. 451a4071fbbSHaijun Zhang */ 452f4932cfdSyangbo lu static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask) 453a4071fbbSHaijun Zhang { 454f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 4558605e7aeSJisheng Zhang struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 456a4071fbbSHaijun Zhang bool applicable; 457a4071fbbSHaijun Zhang dma_addr_t dmastart; 458a4071fbbSHaijun Zhang dma_addr_t dmanow; 459a4071fbbSHaijun Zhang 460a4071fbbSHaijun Zhang applicable = (intmask & SDHCI_INT_DATA_END) && 461a4071fbbSHaijun Zhang (intmask & SDHCI_INT_BLK_GAP) && 462f4932cfdSyangbo lu (esdhc->vendor_ver == VENDOR_V_23); 463a4071fbbSHaijun Zhang if (!applicable) 464a4071fbbSHaijun Zhang return; 465a4071fbbSHaijun Zhang 466a4071fbbSHaijun Zhang host->data->error = 0; 467a4071fbbSHaijun Zhang dmastart = sg_dma_address(host->data->sg); 468a4071fbbSHaijun Zhang dmanow = dmastart + host->data->bytes_xfered; 469a4071fbbSHaijun Zhang /* 470a4071fbbSHaijun Zhang * Force update to the next DMA block boundary. 471a4071fbbSHaijun Zhang */ 472a4071fbbSHaijun Zhang dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 473a4071fbbSHaijun Zhang SDHCI_DEFAULT_BOUNDARY_SIZE; 474a4071fbbSHaijun Zhang host->data->bytes_xfered = dmanow - dmastart; 475a4071fbbSHaijun Zhang sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 476a4071fbbSHaijun Zhang } 477a4071fbbSHaijun Zhang 47880872e21SWolfram Sang static int esdhc_of_enable_dma(struct sdhci_host *host) 4797657c3a7SAlbert Herranz { 480f4932cfdSyangbo lu u32 value; 4815552d7adSLaurentiu Tudor struct device *dev = mmc_dev(host->mmc); 4825552d7adSLaurentiu Tudor 4835552d7adSLaurentiu Tudor if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") || 4845552d7adSLaurentiu Tudor of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) 4855552d7adSLaurentiu Tudor dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); 486f4932cfdSyangbo lu 487f4932cfdSyangbo lu value = sdhci_readl(host, ESDHC_DMA_SYSCTL); 488f4932cfdSyangbo lu value |= ESDHC_DMA_SNOOP; 489f4932cfdSyangbo lu sdhci_writel(host, value, ESDHC_DMA_SYSCTL); 4907657c3a7SAlbert Herranz return 0; 4917657c3a7SAlbert Herranz } 4927657c3a7SAlbert Herranz 49380872e21SWolfram Sang static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) 4947657c3a7SAlbert Herranz { 495e307148fSShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 49619c3a0efSyangbo lu struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 4977657c3a7SAlbert Herranz 49819c3a0efSyangbo lu if (esdhc->peripheral_clock) 49919c3a0efSyangbo lu return esdhc->peripheral_clock; 50019c3a0efSyangbo lu else 501e307148fSShawn Guo return pltfm_host->clock; 5027657c3a7SAlbert Herranz } 5037657c3a7SAlbert Herranz 50480872e21SWolfram Sang static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) 5057657c3a7SAlbert Herranz { 506e307148fSShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 50719c3a0efSyangbo lu struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 50819c3a0efSyangbo lu unsigned int clock; 5097657c3a7SAlbert Herranz 51019c3a0efSyangbo lu if (esdhc->peripheral_clock) 51119c3a0efSyangbo lu clock = esdhc->peripheral_clock; 51219c3a0efSyangbo lu else 51319c3a0efSyangbo lu clock = pltfm_host->clock; 51419c3a0efSyangbo lu return clock / 256 / 16; 5157657c3a7SAlbert Herranz } 5167657c3a7SAlbert Herranz 517dd3f6983Syangbo lu static void esdhc_clock_enable(struct sdhci_host *host, bool enable) 518dd3f6983Syangbo lu { 519dd3f6983Syangbo lu u32 val; 520dd3f6983Syangbo lu ktime_t timeout; 521dd3f6983Syangbo lu 522dd3f6983Syangbo lu val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 523dd3f6983Syangbo lu 524dd3f6983Syangbo lu if (enable) 525dd3f6983Syangbo lu val |= ESDHC_CLOCK_SDCLKEN; 526dd3f6983Syangbo lu else 527dd3f6983Syangbo lu val &= ~ESDHC_CLOCK_SDCLKEN; 528dd3f6983Syangbo lu 529dd3f6983Syangbo lu sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL); 530dd3f6983Syangbo lu 531dd3f6983Syangbo lu /* Wait max 20 ms */ 532dd3f6983Syangbo lu timeout = ktime_add_ms(ktime_get(), 20); 533dd3f6983Syangbo lu val = ESDHC_CLOCK_STABLE; 534ea6d0273SAdrian Hunter while (1) { 535ea6d0273SAdrian Hunter bool timedout = ktime_after(ktime_get(), timeout); 536ea6d0273SAdrian Hunter 537ea6d0273SAdrian Hunter if (sdhci_readl(host, ESDHC_PRSSTAT) & val) 538ea6d0273SAdrian Hunter break; 539ea6d0273SAdrian Hunter if (timedout) { 540dd3f6983Syangbo lu pr_err("%s: Internal clock never stabilised.\n", 541dd3f6983Syangbo lu mmc_hostname(host->mmc)); 542dd3f6983Syangbo lu break; 543dd3f6983Syangbo lu } 544dd3f6983Syangbo lu udelay(10); 545dd3f6983Syangbo lu } 546dd3f6983Syangbo lu } 547dd3f6983Syangbo lu 548f060bc9cSJerry Huang static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) 549f060bc9cSJerry Huang { 550f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 5518605e7aeSJisheng Zhang struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 552bd455029SJoakim Tjernlund int pre_div = 1; 553d31fc00aSDong Aisheng int div = 1; 5546079e63cSYangbo Lu int division; 555e145ac45Syangbo lu ktime_t timeout; 55667fdfbdfSyinbo.zhu long fixup = 0; 557d31fc00aSDong Aisheng u32 temp; 558d31fc00aSDong Aisheng 5591650d0c7SRussell King host->mmc->actual_clock = 0; 5601650d0c7SRussell King 561dd3f6983Syangbo lu if (clock == 0) { 562dd3f6983Syangbo lu esdhc_clock_enable(host, false); 563373073efSRussell King return; 564dd3f6983Syangbo lu } 565d31fc00aSDong Aisheng 56677bd2f6fSYangbo Lu /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */ 567f4932cfdSyangbo lu if (esdhc->vendor_ver < VENDOR_V_23) 56877bd2f6fSYangbo Lu pre_div = 2; 56977bd2f6fSYangbo Lu 57067fdfbdfSyinbo.zhu if (host->mmc->card && mmc_card_sd(host->mmc->card) && 57167fdfbdfSyinbo.zhu esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY) 57267fdfbdfSyinbo.zhu fixup = esdhc->clk_fixup->sd_dflt_max_clk; 57367fdfbdfSyinbo.zhu else if (esdhc->clk_fixup) 57467fdfbdfSyinbo.zhu fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing]; 575a627f025Syangbo lu 57667fdfbdfSyinbo.zhu if (fixup && clock > fixup) 57767fdfbdfSyinbo.zhu clock = fixup; 578f060bc9cSJerry Huang 579d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 580e87d2db2Syangbo lu temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | 581e87d2db2Syangbo lu ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK); 582d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 583d31fc00aSDong Aisheng 584d31fc00aSDong Aisheng while (host->max_clk / pre_div / 16 > clock && pre_div < 256) 585d31fc00aSDong Aisheng pre_div *= 2; 586d31fc00aSDong Aisheng 587d31fc00aSDong Aisheng while (host->max_clk / pre_div / div > clock && div < 16) 588d31fc00aSDong Aisheng div++; 589d31fc00aSDong Aisheng 5906079e63cSYangbo Lu if (esdhc->quirk_limited_clk_division && 5916079e63cSYangbo Lu clock == MMC_HS200_MAX_DTR && 5926079e63cSYangbo Lu (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 || 5936079e63cSYangbo Lu host->flags & SDHCI_HS400_TUNING)) { 5946079e63cSYangbo Lu division = pre_div * div; 5956079e63cSYangbo Lu if (division <= 4) { 5966079e63cSYangbo Lu pre_div = 4; 5976079e63cSYangbo Lu div = 1; 5986079e63cSYangbo Lu } else if (division <= 8) { 5996079e63cSYangbo Lu pre_div = 4; 6006079e63cSYangbo Lu div = 2; 6016079e63cSYangbo Lu } else if (division <= 12) { 6026079e63cSYangbo Lu pre_div = 4; 6036079e63cSYangbo Lu div = 3; 6046079e63cSYangbo Lu } else { 605b11c36d5SColin Ian King pr_warn("%s: using unsupported clock division.\n", 6066079e63cSYangbo Lu mmc_hostname(host->mmc)); 6076079e63cSYangbo Lu } 6086079e63cSYangbo Lu } 6096079e63cSYangbo Lu 610d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 611e76b8559SDong Aisheng clock, host->max_clk / pre_div / div); 612bd455029SJoakim Tjernlund host->mmc->actual_clock = host->max_clk / pre_div / div; 613b1f378abSYinbo Zhu esdhc->div_ratio = pre_div * div; 614d31fc00aSDong Aisheng pre_div >>= 1; 615d31fc00aSDong Aisheng div--; 616d31fc00aSDong Aisheng 617d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 618d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 619d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 620d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 621d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 622e87d2db2Syangbo lu 62354e08d9aSYangbo Lu if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && 62454e08d9aSYangbo Lu clock == MMC_HS200_MAX_DTR) { 62554e08d9aSYangbo Lu temp = sdhci_readl(host, ESDHC_TBCTL); 62654e08d9aSYangbo Lu sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL); 62754e08d9aSYangbo Lu temp = sdhci_readl(host, ESDHC_SDCLKCTL); 62854e08d9aSYangbo Lu sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL); 62954e08d9aSYangbo Lu esdhc_clock_enable(host, true); 63054e08d9aSYangbo Lu 63154e08d9aSYangbo Lu temp = sdhci_readl(host, ESDHC_DLLCFG0); 63258d0bf84SYangbo Lu temp |= ESDHC_DLL_ENABLE; 63358d0bf84SYangbo Lu if (host->mmc->actual_clock == MMC_HS200_MAX_DTR) 63458d0bf84SYangbo Lu temp |= ESDHC_DLL_FREQ_SEL; 63554e08d9aSYangbo Lu sdhci_writel(host, temp, ESDHC_DLLCFG0); 63654e08d9aSYangbo Lu temp = sdhci_readl(host, ESDHC_TBCTL); 63754e08d9aSYangbo Lu sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL); 63854e08d9aSYangbo Lu 63954e08d9aSYangbo Lu esdhc_clock_enable(host, false); 64054e08d9aSYangbo Lu temp = sdhci_readl(host, ESDHC_DMA_SYSCTL); 64154e08d9aSYangbo Lu temp |= ESDHC_FLUSH_ASYNC_FIFO; 64254e08d9aSYangbo Lu sdhci_writel(host, temp, ESDHC_DMA_SYSCTL); 64354e08d9aSYangbo Lu } 64454e08d9aSYangbo Lu 645e87d2db2Syangbo lu /* Wait max 20 ms */ 646e145ac45Syangbo lu timeout = ktime_add_ms(ktime_get(), 20); 647ea6d0273SAdrian Hunter while (1) { 648ea6d0273SAdrian Hunter bool timedout = ktime_after(ktime_get(), timeout); 649ea6d0273SAdrian Hunter 650ea6d0273SAdrian Hunter if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE) 651ea6d0273SAdrian Hunter break; 652ea6d0273SAdrian Hunter if (timedout) { 653e87d2db2Syangbo lu pr_err("%s: Internal clock never stabilised.\n", 654e87d2db2Syangbo lu mmc_hostname(host->mmc)); 655e87d2db2Syangbo lu return; 656e87d2db2Syangbo lu } 657e145ac45Syangbo lu udelay(10); 658f060bc9cSJerry Huang } 659f060bc9cSJerry Huang 66054e08d9aSYangbo Lu temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 661e87d2db2Syangbo lu temp |= ESDHC_CLOCK_SDCLKEN; 662e87d2db2Syangbo lu sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 663e87d2db2Syangbo lu } 664e87d2db2Syangbo lu 6652317f56cSRussell King static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 66666b50a00SOded Gabbay { 66766b50a00SOded Gabbay u32 ctrl; 66866b50a00SOded Gabbay 669f4932cfdSyangbo lu ctrl = sdhci_readl(host, ESDHC_PROCTL); 670f4932cfdSyangbo lu ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK); 67166b50a00SOded Gabbay switch (width) { 67266b50a00SOded Gabbay case MMC_BUS_WIDTH_8: 673f4932cfdSyangbo lu ctrl |= ESDHC_CTRL_8BITBUS; 67466b50a00SOded Gabbay break; 67566b50a00SOded Gabbay 67666b50a00SOded Gabbay case MMC_BUS_WIDTH_4: 677f4932cfdSyangbo lu ctrl |= ESDHC_CTRL_4BITBUS; 67866b50a00SOded Gabbay break; 67966b50a00SOded Gabbay 68066b50a00SOded Gabbay default: 68166b50a00SOded Gabbay break; 68266b50a00SOded Gabbay } 68366b50a00SOded Gabbay 684f4932cfdSyangbo lu sdhci_writel(host, ctrl, ESDHC_PROCTL); 68566b50a00SOded Gabbay } 68666b50a00SOded Gabbay 687304f0a98SAlessio Igor Bogani static void esdhc_reset(struct sdhci_host *host, u8 mask) 688304f0a98SAlessio Igor Bogani { 68948e304ccSYangbo Lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 69048e304ccSYangbo Lu struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 691f2bc6000Syinbo.zhu u32 val; 692f2bc6000Syinbo.zhu 693304f0a98SAlessio Igor Bogani sdhci_reset(host, mask); 694304f0a98SAlessio Igor Bogani 695304f0a98SAlessio Igor Bogani sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 696304f0a98SAlessio Igor Bogani sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 697f2bc6000Syinbo.zhu 6985dd19552SYinbo Zhu if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) 6995dd19552SYinbo Zhu mdelay(5); 7005dd19552SYinbo Zhu 701f2bc6000Syinbo.zhu if (mask & SDHCI_RESET_ALL) { 702f2bc6000Syinbo.zhu val = sdhci_readl(host, ESDHC_TBCTL); 703f2bc6000Syinbo.zhu val &= ~ESDHC_TB_EN; 704f2bc6000Syinbo.zhu sdhci_writel(host, val, ESDHC_TBCTL); 70548e304ccSYangbo Lu 70648e304ccSYangbo Lu if (esdhc->quirk_unreliable_pulse_detection) { 70748e304ccSYangbo Lu val = sdhci_readl(host, ESDHC_DLLCFG1); 70848e304ccSYangbo Lu val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL; 70948e304ccSYangbo Lu sdhci_writel(host, val, ESDHC_DLLCFG1); 71048e304ccSYangbo Lu } 711f2bc6000Syinbo.zhu } 712304f0a98SAlessio Igor Bogani } 713304f0a98SAlessio Igor Bogani 714ea35645aSyangbo lu /* The SCFG, Supplemental Configuration Unit, provides SoC specific 715ea35645aSyangbo lu * configuration and status registers for the device. There is a 716ea35645aSyangbo lu * SDHC IO VSEL control register on SCFG for some platforms. It's 717ea35645aSyangbo lu * used to support SDHC IO voltage switching. 718ea35645aSyangbo lu */ 719ea35645aSyangbo lu static const struct of_device_id scfg_device_ids[] = { 720ea35645aSyangbo lu { .compatible = "fsl,t1040-scfg", }, 721ea35645aSyangbo lu { .compatible = "fsl,ls1012a-scfg", }, 722ea35645aSyangbo lu { .compatible = "fsl,ls1046a-scfg", }, 723ea35645aSyangbo lu {} 724ea35645aSyangbo lu }; 725ea35645aSyangbo lu 726ea35645aSyangbo lu /* SDHC IO VSEL control register definition */ 727ea35645aSyangbo lu #define SCFG_SDHCIOVSELCR 0x408 728ea35645aSyangbo lu #define SDHCIOVSELCR_TGLEN 0x80000000 729ea35645aSyangbo lu #define SDHCIOVSELCR_VSELVAL 0x60000000 730ea35645aSyangbo lu #define SDHCIOVSELCR_SDHC_VS 0x00000001 731ea35645aSyangbo lu 732ea35645aSyangbo lu static int esdhc_signal_voltage_switch(struct mmc_host *mmc, 733ea35645aSyangbo lu struct mmc_ios *ios) 734ea35645aSyangbo lu { 735ea35645aSyangbo lu struct sdhci_host *host = mmc_priv(mmc); 736ea35645aSyangbo lu struct device_node *scfg_node; 737ea35645aSyangbo lu void __iomem *scfg_base = NULL; 738ea35645aSyangbo lu u32 sdhciovselcr; 739ea35645aSyangbo lu u32 val; 740ea35645aSyangbo lu 741ea35645aSyangbo lu /* 742ea35645aSyangbo lu * Signal Voltage Switching is only applicable for Host Controllers 743ea35645aSyangbo lu * v3.00 and above. 744ea35645aSyangbo lu */ 745ea35645aSyangbo lu if (host->version < SDHCI_SPEC_300) 746ea35645aSyangbo lu return 0; 747ea35645aSyangbo lu 748ea35645aSyangbo lu val = sdhci_readl(host, ESDHC_PROCTL); 749ea35645aSyangbo lu 750ea35645aSyangbo lu switch (ios->signal_voltage) { 751ea35645aSyangbo lu case MMC_SIGNAL_VOLTAGE_330: 752ea35645aSyangbo lu val &= ~ESDHC_VOLT_SEL; 753ea35645aSyangbo lu sdhci_writel(host, val, ESDHC_PROCTL); 754ea35645aSyangbo lu return 0; 755ea35645aSyangbo lu case MMC_SIGNAL_VOLTAGE_180: 756ea35645aSyangbo lu scfg_node = of_find_matching_node(NULL, scfg_device_ids); 757ea35645aSyangbo lu if (scfg_node) 758ea35645aSyangbo lu scfg_base = of_iomap(scfg_node, 0); 759ea35645aSyangbo lu if (scfg_base) { 760ea35645aSyangbo lu sdhciovselcr = SDHCIOVSELCR_TGLEN | 761ea35645aSyangbo lu SDHCIOVSELCR_VSELVAL; 762ea35645aSyangbo lu iowrite32be(sdhciovselcr, 763ea35645aSyangbo lu scfg_base + SCFG_SDHCIOVSELCR); 764ea35645aSyangbo lu 765ea35645aSyangbo lu val |= ESDHC_VOLT_SEL; 766ea35645aSyangbo lu sdhci_writel(host, val, ESDHC_PROCTL); 767ea35645aSyangbo lu mdelay(5); 768ea35645aSyangbo lu 769ea35645aSyangbo lu sdhciovselcr = SDHCIOVSELCR_TGLEN | 770ea35645aSyangbo lu SDHCIOVSELCR_SDHC_VS; 771ea35645aSyangbo lu iowrite32be(sdhciovselcr, 772ea35645aSyangbo lu scfg_base + SCFG_SDHCIOVSELCR); 773ea35645aSyangbo lu iounmap(scfg_base); 774ea35645aSyangbo lu } else { 775ea35645aSyangbo lu val |= ESDHC_VOLT_SEL; 776ea35645aSyangbo lu sdhci_writel(host, val, ESDHC_PROCTL); 777ea35645aSyangbo lu } 778ea35645aSyangbo lu return 0; 779ea35645aSyangbo lu default: 780ea35645aSyangbo lu return 0; 781ea35645aSyangbo lu } 782ea35645aSyangbo lu } 783ea35645aSyangbo lu 784b1f378abSYinbo Zhu static struct soc_device_attribute soc_fixup_tuning[] = { 785b1f378abSYinbo Zhu { .family = "QorIQ T1040", .revision = "1.0", }, 786b1f378abSYinbo Zhu { .family = "QorIQ T2080", .revision = "1.0", }, 787b1f378abSYinbo Zhu { .family = "QorIQ T1023", .revision = "1.0", }, 788b1f378abSYinbo Zhu { .family = "QorIQ LS1021A", .revision = "1.0", }, 789b1f378abSYinbo Zhu { .family = "QorIQ LS1080A", .revision = "1.0", }, 790b1f378abSYinbo Zhu { .family = "QorIQ LS2080A", .revision = "1.0", }, 791b1f378abSYinbo Zhu { .family = "QorIQ LS1012A", .revision = "1.0", }, 792b1f378abSYinbo Zhu { .family = "QorIQ LS1043A", .revision = "1.*", }, 793b1f378abSYinbo Zhu { .family = "QorIQ LS1046A", .revision = "1.0", }, 794b1f378abSYinbo Zhu { }, 795b1f378abSYinbo Zhu }; 796b1f378abSYinbo Zhu 79754e08d9aSYangbo Lu static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable) 798ba49cbd0Syangbo lu { 799ba49cbd0Syangbo lu u32 val; 800ba49cbd0Syangbo lu 801ba49cbd0Syangbo lu esdhc_clock_enable(host, false); 80254e08d9aSYangbo Lu 803ba49cbd0Syangbo lu val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 804ba49cbd0Syangbo lu val |= ESDHC_FLUSH_ASYNC_FIFO; 805ba49cbd0Syangbo lu sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 806ba49cbd0Syangbo lu 807ba49cbd0Syangbo lu val = sdhci_readl(host, ESDHC_TBCTL); 80854e08d9aSYangbo Lu if (enable) 809ba49cbd0Syangbo lu val |= ESDHC_TB_EN; 81054e08d9aSYangbo Lu else 81154e08d9aSYangbo Lu val &= ~ESDHC_TB_EN; 812ba49cbd0Syangbo lu sdhci_writel(host, val, ESDHC_TBCTL); 813ba49cbd0Syangbo lu 81454e08d9aSYangbo Lu esdhc_clock_enable(host, true); 81554e08d9aSYangbo Lu } 81654e08d9aSYangbo Lu 81754e08d9aSYangbo Lu static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 81854e08d9aSYangbo Lu { 81954e08d9aSYangbo Lu struct sdhci_host *host = mmc_priv(mmc); 82054e08d9aSYangbo Lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 82154e08d9aSYangbo Lu struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 82254e08d9aSYangbo Lu bool hs400_tuning; 82354e08d9aSYangbo Lu u32 val; 82454e08d9aSYangbo Lu int ret; 82554e08d9aSYangbo Lu 8266079e63cSYangbo Lu if (esdhc->quirk_limited_clk_division && 8276079e63cSYangbo Lu host->flags & SDHCI_HS400_TUNING) 8286079e63cSYangbo Lu esdhc_of_set_clock(host, host->clock); 8296079e63cSYangbo Lu 83054e08d9aSYangbo Lu esdhc_tuning_block_enable(host, true); 83154e08d9aSYangbo Lu 83254e08d9aSYangbo Lu hs400_tuning = host->flags & SDHCI_HS400_TUNING; 83354e08d9aSYangbo Lu ret = sdhci_execute_tuning(mmc, opcode); 83454e08d9aSYangbo Lu 83554e08d9aSYangbo Lu if (hs400_tuning) { 83654e08d9aSYangbo Lu val = sdhci_readl(host, ESDHC_SDTIMNGCTL); 83754e08d9aSYangbo Lu val |= ESDHC_FLW_CTL_BG; 83854e08d9aSYangbo Lu sdhci_writel(host, val, ESDHC_SDTIMNGCTL); 83954e08d9aSYangbo Lu } 84054e08d9aSYangbo Lu 841b1f378abSYinbo Zhu if (host->tuning_err == -EAGAIN && esdhc->quirk_fixup_tuning) { 842b1f378abSYinbo Zhu 843b1f378abSYinbo Zhu /* program TBPTR[TB_WNDW_END_PTR] = 3*DIV_RATIO and 844b1f378abSYinbo Zhu * program TBPTR[TB_WNDW_START_PTR] = 5*DIV_RATIO 845b1f378abSYinbo Zhu */ 846b1f378abSYinbo Zhu val = sdhci_readl(host, ESDHC_TBPTR); 847b1f378abSYinbo Zhu val = (val & ~((0x7f << 8) | 0x7f)) | 848b1f378abSYinbo Zhu (3 * esdhc->div_ratio) | ((5 * esdhc->div_ratio) << 8); 849b1f378abSYinbo Zhu sdhci_writel(host, val, ESDHC_TBPTR); 850b1f378abSYinbo Zhu 851b1f378abSYinbo Zhu /* program the software tuning mode by setting 852b1f378abSYinbo Zhu * TBCTL[TB_MODE]=2'h3 853b1f378abSYinbo Zhu */ 854b1f378abSYinbo Zhu val = sdhci_readl(host, ESDHC_TBCTL); 855b1f378abSYinbo Zhu val |= 0x3; 856b1f378abSYinbo Zhu sdhci_writel(host, val, ESDHC_TBCTL); 857b1f378abSYinbo Zhu sdhci_execute_tuning(mmc, opcode); 858b1f378abSYinbo Zhu } 85954e08d9aSYangbo Lu return ret; 86054e08d9aSYangbo Lu } 86154e08d9aSYangbo Lu 86254e08d9aSYangbo Lu static void esdhc_set_uhs_signaling(struct sdhci_host *host, 86354e08d9aSYangbo Lu unsigned int timing) 86454e08d9aSYangbo Lu { 86554e08d9aSYangbo Lu if (timing == MMC_TIMING_MMC_HS400) 86654e08d9aSYangbo Lu esdhc_tuning_block_enable(host, true); 86754e08d9aSYangbo Lu else 86854e08d9aSYangbo Lu sdhci_set_uhs_signaling(host, timing); 869ba49cbd0Syangbo lu } 870ba49cbd0Syangbo lu 871b214fe59SYinbo Zhu static u32 esdhc_irq(struct sdhci_host *host, u32 intmask) 872b214fe59SYinbo Zhu { 873b214fe59SYinbo Zhu u32 command; 874b214fe59SYinbo Zhu 875b214fe59SYinbo Zhu if (of_find_compatible_node(NULL, NULL, 876b214fe59SYinbo Zhu "fsl,p2020-esdhc")) { 877b214fe59SYinbo Zhu command = SDHCI_GET_CMD(sdhci_readw(host, 878b214fe59SYinbo Zhu SDHCI_COMMAND)); 879b214fe59SYinbo Zhu if (command == MMC_WRITE_MULTIPLE_BLOCK && 880b214fe59SYinbo Zhu sdhci_readw(host, SDHCI_BLOCK_COUNT) && 881b214fe59SYinbo Zhu intmask & SDHCI_INT_DATA_END) { 882b214fe59SYinbo Zhu intmask &= ~SDHCI_INT_DATA_END; 883b214fe59SYinbo Zhu sdhci_writel(host, SDHCI_INT_DATA_END, 884b214fe59SYinbo Zhu SDHCI_INT_STATUS); 885b214fe59SYinbo Zhu } 886b214fe59SYinbo Zhu } 887b214fe59SYinbo Zhu return intmask; 888b214fe59SYinbo Zhu } 889b214fe59SYinbo Zhu 8909e48b336SUlf Hansson #ifdef CONFIG_PM_SLEEP 891723f7924SRussell King static u32 esdhc_proctl; 892723f7924SRussell King static int esdhc_of_suspend(struct device *dev) 893723f7924SRussell King { 894723f7924SRussell King struct sdhci_host *host = dev_get_drvdata(dev); 895723f7924SRussell King 896f4932cfdSyangbo lu esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL); 897723f7924SRussell King 898d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 899d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 900d38dcad4SAdrian Hunter 901723f7924SRussell King return sdhci_suspend_host(host); 902723f7924SRussell King } 903723f7924SRussell King 90406732b84SUlf Hansson static int esdhc_of_resume(struct device *dev) 905723f7924SRussell King { 906723f7924SRussell King struct sdhci_host *host = dev_get_drvdata(dev); 907723f7924SRussell King int ret = sdhci_resume_host(host); 908723f7924SRussell King 909723f7924SRussell King if (ret == 0) { 910723f7924SRussell King /* Isn't this already done by sdhci_resume_host() ? --rmk */ 911723f7924SRussell King esdhc_of_enable_dma(host); 912f4932cfdSyangbo lu sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); 913723f7924SRussell King } 914723f7924SRussell King return ret; 915723f7924SRussell King } 916723f7924SRussell King #endif 917723f7924SRussell King 9189e48b336SUlf Hansson static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops, 9199e48b336SUlf Hansson esdhc_of_suspend, 9209e48b336SUlf Hansson esdhc_of_resume); 9219e48b336SUlf Hansson 922f4932cfdSyangbo lu static const struct sdhci_ops sdhci_esdhc_be_ops = { 923f4932cfdSyangbo lu .read_l = esdhc_be_readl, 924f4932cfdSyangbo lu .read_w = esdhc_be_readw, 925f4932cfdSyangbo lu .read_b = esdhc_be_readb, 926f4932cfdSyangbo lu .write_l = esdhc_be_writel, 927f4932cfdSyangbo lu .write_w = esdhc_be_writew, 928f4932cfdSyangbo lu .write_b = esdhc_be_writeb, 929f4932cfdSyangbo lu .set_clock = esdhc_of_set_clock, 930f4932cfdSyangbo lu .enable_dma = esdhc_of_enable_dma, 931f4932cfdSyangbo lu .get_max_clock = esdhc_of_get_max_clock, 932f4932cfdSyangbo lu .get_min_clock = esdhc_of_get_min_clock, 933f4932cfdSyangbo lu .adma_workaround = esdhc_of_adma_workaround, 934f4932cfdSyangbo lu .set_bus_width = esdhc_pltfm_set_bus_width, 935f4932cfdSyangbo lu .reset = esdhc_reset, 93654e08d9aSYangbo Lu .set_uhs_signaling = esdhc_set_uhs_signaling, 937b214fe59SYinbo Zhu .irq = esdhc_irq, 938f4932cfdSyangbo lu }; 939f4932cfdSyangbo lu 940f4932cfdSyangbo lu static const struct sdhci_ops sdhci_esdhc_le_ops = { 941f4932cfdSyangbo lu .read_l = esdhc_le_readl, 942f4932cfdSyangbo lu .read_w = esdhc_le_readw, 943f4932cfdSyangbo lu .read_b = esdhc_le_readb, 944f4932cfdSyangbo lu .write_l = esdhc_le_writel, 945f4932cfdSyangbo lu .write_w = esdhc_le_writew, 946f4932cfdSyangbo lu .write_b = esdhc_le_writeb, 947f4932cfdSyangbo lu .set_clock = esdhc_of_set_clock, 948f4932cfdSyangbo lu .enable_dma = esdhc_of_enable_dma, 949f4932cfdSyangbo lu .get_max_clock = esdhc_of_get_max_clock, 950f4932cfdSyangbo lu .get_min_clock = esdhc_of_get_min_clock, 951f4932cfdSyangbo lu .adma_workaround = esdhc_of_adma_workaround, 952f4932cfdSyangbo lu .set_bus_width = esdhc_pltfm_set_bus_width, 953f4932cfdSyangbo lu .reset = esdhc_reset, 95454e08d9aSYangbo Lu .set_uhs_signaling = esdhc_set_uhs_signaling, 955b214fe59SYinbo Zhu .irq = esdhc_irq, 956f4932cfdSyangbo lu }; 957f4932cfdSyangbo lu 958f4932cfdSyangbo lu static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = { 959e9acc77dSyangbo lu .quirks = ESDHC_DEFAULT_QUIRKS | 960e9acc77dSyangbo lu #ifdef CONFIG_PPC 961e9acc77dSyangbo lu SDHCI_QUIRK_BROKEN_CARD_DETECTION | 962e9acc77dSyangbo lu #endif 963e9acc77dSyangbo lu SDHCI_QUIRK_NO_CARD_NO_RESET | 964e9acc77dSyangbo lu SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 965f4932cfdSyangbo lu .ops = &sdhci_esdhc_be_ops, 9667657c3a7SAlbert Herranz }; 96738576af1SShawn Guo 968f4932cfdSyangbo lu static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = { 969e9acc77dSyangbo lu .quirks = ESDHC_DEFAULT_QUIRKS | 970e9acc77dSyangbo lu SDHCI_QUIRK_NO_CARD_NO_RESET | 971e9acc77dSyangbo lu SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 972f4932cfdSyangbo lu .ops = &sdhci_esdhc_le_ops, 973f4932cfdSyangbo lu }; 974f4932cfdSyangbo lu 975151ede40Syangbo lu static struct soc_device_attribute soc_incorrect_hostver[] = { 976151ede40Syangbo lu { .family = "QorIQ T4240", .revision = "1.0", }, 977151ede40Syangbo lu { .family = "QorIQ T4240", .revision = "2.0", }, 978151ede40Syangbo lu { }, 979151ede40Syangbo lu }; 980151ede40Syangbo lu 9816079e63cSYangbo Lu static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = { 9826079e63cSYangbo Lu { .family = "QorIQ LX2160A", .revision = "1.0", }, 9838e9a6919SYinbo Zhu { .family = "QorIQ LX2160A", .revision = "2.0", }, 9846079e63cSYangbo Lu { }, 9856079e63cSYangbo Lu }; 9866079e63cSYangbo Lu 98748e304ccSYangbo Lu static struct soc_device_attribute soc_unreliable_pulse_detection[] = { 98848e304ccSYangbo Lu { .family = "QorIQ LX2160A", .revision = "1.0", }, 98948e304ccSYangbo Lu { }, 99048e304ccSYangbo Lu }; 99148e304ccSYangbo Lu 992f4932cfdSyangbo lu static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host) 993f4932cfdSyangbo lu { 99467fdfbdfSyinbo.zhu const struct of_device_id *match; 995f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host; 996f4932cfdSyangbo lu struct sdhci_esdhc *esdhc; 99719c3a0efSyangbo lu struct device_node *np; 99819c3a0efSyangbo lu struct clk *clk; 99919c3a0efSyangbo lu u32 val; 1000f4932cfdSyangbo lu u16 host_ver; 1001f4932cfdSyangbo lu 1002f4932cfdSyangbo lu pltfm_host = sdhci_priv(host); 10038605e7aeSJisheng Zhang esdhc = sdhci_pltfm_priv(pltfm_host); 1004f4932cfdSyangbo lu 1005f4932cfdSyangbo lu host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); 1006f4932cfdSyangbo lu esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >> 1007f4932cfdSyangbo lu SDHCI_VENDOR_VER_SHIFT; 1008f4932cfdSyangbo lu esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK; 1009151ede40Syangbo lu if (soc_device_match(soc_incorrect_hostver)) 1010151ede40Syangbo lu esdhc->quirk_incorrect_hostver = true; 1011151ede40Syangbo lu else 1012151ede40Syangbo lu esdhc->quirk_incorrect_hostver = false; 101319c3a0efSyangbo lu 10146079e63cSYangbo Lu if (soc_device_match(soc_fixup_sdhc_clkdivs)) 10156079e63cSYangbo Lu esdhc->quirk_limited_clk_division = true; 10166079e63cSYangbo Lu else 10176079e63cSYangbo Lu esdhc->quirk_limited_clk_division = false; 10186079e63cSYangbo Lu 101948e304ccSYangbo Lu if (soc_device_match(soc_unreliable_pulse_detection)) 102048e304ccSYangbo Lu esdhc->quirk_unreliable_pulse_detection = true; 102148e304ccSYangbo Lu else 102248e304ccSYangbo Lu esdhc->quirk_unreliable_pulse_detection = false; 102348e304ccSYangbo Lu 102467fdfbdfSyinbo.zhu match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node); 102567fdfbdfSyinbo.zhu if (match) 102667fdfbdfSyinbo.zhu esdhc->clk_fixup = match->data; 102719c3a0efSyangbo lu np = pdev->dev.of_node; 102819c3a0efSyangbo lu clk = of_clk_get(np, 0); 102919c3a0efSyangbo lu if (!IS_ERR(clk)) { 103019c3a0efSyangbo lu /* 103119c3a0efSyangbo lu * esdhc->peripheral_clock would be assigned with a value 103219c3a0efSyangbo lu * which is eSDHC base clock when use periperal clock. 103319c3a0efSyangbo lu * For ls1046a, the clock value got by common clk API is 103419c3a0efSyangbo lu * peripheral clock while the eSDHC base clock is 1/2 103519c3a0efSyangbo lu * peripheral clock. 103619c3a0efSyangbo lu */ 103719c3a0efSyangbo lu if (of_device_is_compatible(np, "fsl,ls1046a-esdhc")) 103819c3a0efSyangbo lu esdhc->peripheral_clock = clk_get_rate(clk) / 2; 103919c3a0efSyangbo lu else 104019c3a0efSyangbo lu esdhc->peripheral_clock = clk_get_rate(clk); 104119c3a0efSyangbo lu 104219c3a0efSyangbo lu clk_put(clk); 104319c3a0efSyangbo lu } 104419c3a0efSyangbo lu 104519c3a0efSyangbo lu if (esdhc->peripheral_clock) { 104619c3a0efSyangbo lu esdhc_clock_enable(host, false); 104719c3a0efSyangbo lu val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 104819c3a0efSyangbo lu val |= ESDHC_PERIPHERAL_CLK_SEL; 104919c3a0efSyangbo lu sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 105019c3a0efSyangbo lu esdhc_clock_enable(host, true); 105119c3a0efSyangbo lu } 1052f4932cfdSyangbo lu } 1053f4932cfdSyangbo lu 105454e08d9aSYangbo Lu static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc) 105554e08d9aSYangbo Lu { 105654e08d9aSYangbo Lu esdhc_tuning_block_enable(mmc_priv(mmc), false); 105754e08d9aSYangbo Lu return 0; 105854e08d9aSYangbo Lu } 105954e08d9aSYangbo Lu 1060c3be1efdSBill Pemberton static int sdhci_esdhc_probe(struct platform_device *pdev) 106138576af1SShawn Guo { 106266b50a00SOded Gabbay struct sdhci_host *host; 1063dcaff04dSOded Gabbay struct device_node *np; 10641ef5e49eSyangbo lu struct sdhci_pltfm_host *pltfm_host; 10651ef5e49eSyangbo lu struct sdhci_esdhc *esdhc; 106666b50a00SOded Gabbay int ret; 106766b50a00SOded Gabbay 1068f4932cfdSyangbo lu np = pdev->dev.of_node; 1069f4932cfdSyangbo lu 1070150d4240SJulia Lawall if (of_property_read_bool(np, "little-endian")) 10718605e7aeSJisheng Zhang host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata, 10728605e7aeSJisheng Zhang sizeof(struct sdhci_esdhc)); 1073f4932cfdSyangbo lu else 10748605e7aeSJisheng Zhang host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata, 10758605e7aeSJisheng Zhang sizeof(struct sdhci_esdhc)); 1076f4932cfdSyangbo lu 107766b50a00SOded Gabbay if (IS_ERR(host)) 107866b50a00SOded Gabbay return PTR_ERR(host); 107966b50a00SOded Gabbay 1080ea35645aSyangbo lu host->mmc_host_ops.start_signal_voltage_switch = 1081ea35645aSyangbo lu esdhc_signal_voltage_switch; 1082ba49cbd0Syangbo lu host->mmc_host_ops.execute_tuning = esdhc_execute_tuning; 108354e08d9aSYangbo Lu host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr; 10846b236f37Syangbo lu host->tuning_delay = 1; 1085ea35645aSyangbo lu 1086f4932cfdSyangbo lu esdhc_init(pdev, host); 1087f4932cfdSyangbo lu 108866b50a00SOded Gabbay sdhci_get_of_property(pdev); 108966b50a00SOded Gabbay 10901ef5e49eSyangbo lu pltfm_host = sdhci_priv(host); 10918605e7aeSJisheng Zhang esdhc = sdhci_pltfm_priv(pltfm_host); 1092b1f378abSYinbo Zhu if (soc_device_match(soc_fixup_tuning)) 1093b1f378abSYinbo Zhu esdhc->quirk_fixup_tuning = true; 1094b1f378abSYinbo Zhu else 1095b1f378abSYinbo Zhu esdhc->quirk_fixup_tuning = false; 1096b1f378abSYinbo Zhu 10971ef5e49eSyangbo lu if (esdhc->vendor_ver == VENDOR_V_22) 10981ef5e49eSyangbo lu host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; 10991ef5e49eSyangbo lu 11001ef5e49eSyangbo lu if (esdhc->vendor_ver > VENDOR_V_22) 11011ef5e49eSyangbo lu host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 11021ef5e49eSyangbo lu 110305cb6b2aSYinbo Zhu if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) { 1104a46e4271SYinbo Zhu host->quirks2 |= SDHCI_QUIRK_RESET_AFTER_REQUEST; 110505cb6b2aSYinbo Zhu host->quirks2 |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 110605cb6b2aSYinbo Zhu } 1107a46e4271SYinbo Zhu 110874fd5e30SYangbo Lu if (of_device_is_compatible(np, "fsl,p5040-esdhc") || 110974fd5e30SYangbo Lu of_device_is_compatible(np, "fsl,p5020-esdhc") || 111074fd5e30SYangbo Lu of_device_is_compatible(np, "fsl,p4080-esdhc") || 111174fd5e30SYangbo Lu of_device_is_compatible(np, "fsl,p1020-esdhc") || 1112e9acc77dSyangbo lu of_device_is_compatible(np, "fsl,t1040-esdhc")) 111374fd5e30SYangbo Lu host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 111474fd5e30SYangbo Lu 1115a22950c8Syangbo lu if (of_device_is_compatible(np, "fsl,ls1021a-esdhc")) 1116a22950c8Syangbo lu host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1117a22950c8Syangbo lu 1118dcaff04dSOded Gabbay if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { 1119dcaff04dSOded Gabbay /* 1120dcaff04dSOded Gabbay * Freescale messed up with P2020 as it has a non-standard 1121dcaff04dSOded Gabbay * host control register 1122dcaff04dSOded Gabbay */ 1123dcaff04dSOded Gabbay host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL; 1124dcaff04dSOded Gabbay } 1125dcaff04dSOded Gabbay 112666b50a00SOded Gabbay /* call to generic mmc_of_parse to support additional capabilities */ 1127f0991408SUlf Hansson ret = mmc_of_parse(host->mmc); 1128f0991408SUlf Hansson if (ret) 1129f0991408SUlf Hansson goto err; 1130f0991408SUlf Hansson 1131490104acSHaijun Zhang mmc_of_parse_voltage(np, &host->ocr_mask); 113266b50a00SOded Gabbay 113366b50a00SOded Gabbay ret = sdhci_add_host(host); 113466b50a00SOded Gabbay if (ret) 1135f0991408SUlf Hansson goto err; 113666b50a00SOded Gabbay 1137f0991408SUlf Hansson return 0; 1138f0991408SUlf Hansson err: 1139f0991408SUlf Hansson sdhci_pltfm_free(pdev); 114066b50a00SOded Gabbay return ret; 114138576af1SShawn Guo } 114238576af1SShawn Guo 114338576af1SShawn Guo static struct platform_driver sdhci_esdhc_driver = { 114438576af1SShawn Guo .driver = { 114538576af1SShawn Guo .name = "sdhci-esdhc", 114638576af1SShawn Guo .of_match_table = sdhci_esdhc_of_match, 11479e48b336SUlf Hansson .pm = &esdhc_of_dev_pm_ops, 114838576af1SShawn Guo }, 114938576af1SShawn Guo .probe = sdhci_esdhc_probe, 1150caebcae9SKevin Hao .remove = sdhci_pltfm_unregister, 115138576af1SShawn Guo }; 115238576af1SShawn Guo 1153d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_driver); 115438576af1SShawn Guo 115538576af1SShawn Guo MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC"); 115638576af1SShawn Guo MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, " 115738576af1SShawn Guo "Anton Vorontsov <avorontsov@ru.mvista.com>"); 115838576af1SShawn Guo MODULE_LICENSE("GPL v2"); 1159