17657c3a7SAlbert Herranz /* 27657c3a7SAlbert Herranz * Freescale eSDHC controller driver. 37657c3a7SAlbert Herranz * 4f060bc9cSJerry Huang * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. 57657c3a7SAlbert Herranz * Copyright (c) 2009 MontaVista Software, Inc. 67657c3a7SAlbert Herranz * 77657c3a7SAlbert Herranz * Authors: Xiaobo Xie <X.Xie@freescale.com> 87657c3a7SAlbert Herranz * Anton Vorontsov <avorontsov@ru.mvista.com> 97657c3a7SAlbert Herranz * 107657c3a7SAlbert Herranz * This program is free software; you can redistribute it and/or modify 117657c3a7SAlbert Herranz * it under the terms of the GNU General Public License as published by 127657c3a7SAlbert Herranz * the Free Software Foundation; either version 2 of the License, or (at 137657c3a7SAlbert Herranz * your option) any later version. 147657c3a7SAlbert Herranz */ 157657c3a7SAlbert Herranz 1666b50a00SOded Gabbay #include <linux/err.h> 177657c3a7SAlbert Herranz #include <linux/io.h> 18f060bc9cSJerry Huang #include <linux/of.h> 19ea35645aSyangbo lu #include <linux/of_address.h> 207657c3a7SAlbert Herranz #include <linux/delay.h> 2188b47679SPaul Gortmaker #include <linux/module.h> 22151ede40Syangbo lu #include <linux/sys_soc.h> 2319c3a0efSyangbo lu #include <linux/clk.h> 2419c3a0efSyangbo lu #include <linux/ktime.h> 255552d7adSLaurentiu Tudor #include <linux/dma-mapping.h> 267657c3a7SAlbert Herranz #include <linux/mmc/host.h> 2738576af1SShawn Guo #include "sdhci-pltfm.h" 2880872e21SWolfram Sang #include "sdhci-esdhc.h" 297657c3a7SAlbert Herranz 30137ccd46SJerry Huang #define VENDOR_V_22 0x12 31a4071fbbSHaijun Zhang #define VENDOR_V_23 0x13 32f4932cfdSyangbo lu 3367fdfbdfSyinbo.zhu #define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1) 3467fdfbdfSyinbo.zhu 3567fdfbdfSyinbo.zhu struct esdhc_clk_fixup { 3667fdfbdfSyinbo.zhu const unsigned int sd_dflt_max_clk; 3767fdfbdfSyinbo.zhu const unsigned int max_clk[MMC_TIMING_NUM]; 3867fdfbdfSyinbo.zhu }; 3967fdfbdfSyinbo.zhu 4067fdfbdfSyinbo.zhu static const struct esdhc_clk_fixup ls1021a_esdhc_clk = { 4167fdfbdfSyinbo.zhu .sd_dflt_max_clk = 25000000, 4267fdfbdfSyinbo.zhu .max_clk[MMC_TIMING_MMC_HS] = 46500000, 4367fdfbdfSyinbo.zhu .max_clk[MMC_TIMING_SD_HS] = 46500000, 4467fdfbdfSyinbo.zhu }; 4567fdfbdfSyinbo.zhu 4667fdfbdfSyinbo.zhu static const struct esdhc_clk_fixup ls1046a_esdhc_clk = { 4767fdfbdfSyinbo.zhu .sd_dflt_max_clk = 25000000, 4867fdfbdfSyinbo.zhu .max_clk[MMC_TIMING_UHS_SDR104] = 167000000, 4967fdfbdfSyinbo.zhu .max_clk[MMC_TIMING_MMC_HS200] = 167000000, 5067fdfbdfSyinbo.zhu }; 5167fdfbdfSyinbo.zhu 5267fdfbdfSyinbo.zhu static const struct esdhc_clk_fixup ls1012a_esdhc_clk = { 5367fdfbdfSyinbo.zhu .sd_dflt_max_clk = 25000000, 5467fdfbdfSyinbo.zhu .max_clk[MMC_TIMING_UHS_SDR104] = 125000000, 5567fdfbdfSyinbo.zhu .max_clk[MMC_TIMING_MMC_HS200] = 125000000, 5667fdfbdfSyinbo.zhu }; 5767fdfbdfSyinbo.zhu 5867fdfbdfSyinbo.zhu static const struct esdhc_clk_fixup p1010_esdhc_clk = { 5967fdfbdfSyinbo.zhu .sd_dflt_max_clk = 20000000, 6067fdfbdfSyinbo.zhu .max_clk[MMC_TIMING_LEGACY] = 20000000, 6167fdfbdfSyinbo.zhu .max_clk[MMC_TIMING_MMC_HS] = 42000000, 6267fdfbdfSyinbo.zhu .max_clk[MMC_TIMING_SD_HS] = 40000000, 6367fdfbdfSyinbo.zhu }; 6467fdfbdfSyinbo.zhu 6567fdfbdfSyinbo.zhu static const struct of_device_id sdhci_esdhc_of_match[] = { 6667fdfbdfSyinbo.zhu { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk}, 6767fdfbdfSyinbo.zhu { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk}, 6867fdfbdfSyinbo.zhu { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk}, 6967fdfbdfSyinbo.zhu { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk}, 7067fdfbdfSyinbo.zhu { .compatible = "fsl,mpc8379-esdhc" }, 7167fdfbdfSyinbo.zhu { .compatible = "fsl,mpc8536-esdhc" }, 7267fdfbdfSyinbo.zhu { .compatible = "fsl,esdhc" }, 7367fdfbdfSyinbo.zhu { } 7467fdfbdfSyinbo.zhu }; 7567fdfbdfSyinbo.zhu MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); 7667fdfbdfSyinbo.zhu 77f4932cfdSyangbo lu struct sdhci_esdhc { 78f4932cfdSyangbo lu u8 vendor_ver; 79f4932cfdSyangbo lu u8 spec_ver; 80151ede40Syangbo lu bool quirk_incorrect_hostver; 8119c3a0efSyangbo lu unsigned int peripheral_clock; 8267fdfbdfSyinbo.zhu const struct esdhc_clk_fixup *clk_fixup; 83f4932cfdSyangbo lu }; 84f4932cfdSyangbo lu 85f4932cfdSyangbo lu /** 86f4932cfdSyangbo lu * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register 87f4932cfdSyangbo lu * to make it compatible with SD spec. 88f4932cfdSyangbo lu * 89f4932cfdSyangbo lu * @host: pointer to sdhci_host 90f4932cfdSyangbo lu * @spec_reg: SD spec register address 91f4932cfdSyangbo lu * @value: 32bit eSDHC register value on spec_reg address 92f4932cfdSyangbo lu * 93f4932cfdSyangbo lu * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 94f4932cfdSyangbo lu * registers are 32 bits. There are differences in register size, register 95f4932cfdSyangbo lu * address, register function, bit position and function between eSDHC spec 96f4932cfdSyangbo lu * and SD spec. 97f4932cfdSyangbo lu * 98f4932cfdSyangbo lu * Return a fixed up register value 99f4932cfdSyangbo lu */ 100f4932cfdSyangbo lu static u32 esdhc_readl_fixup(struct sdhci_host *host, 101f4932cfdSyangbo lu int spec_reg, u32 value) 102137ccd46SJerry Huang { 103f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1048605e7aeSJisheng Zhang struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 105137ccd46SJerry Huang u32 ret; 106137ccd46SJerry Huang 107137ccd46SJerry Huang /* 108137ccd46SJerry Huang * The bit of ADMA flag in eSDHC is not compatible with standard 109137ccd46SJerry Huang * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is 110137ccd46SJerry Huang * supported by eSDHC. 111137ccd46SJerry Huang * And for many FSL eSDHC controller, the reset value of field 112f4932cfdSyangbo lu * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA, 113137ccd46SJerry Huang * only these vendor version is greater than 2.2/0x12 support ADMA. 114137ccd46SJerry Huang */ 115f4932cfdSyangbo lu if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) { 116f4932cfdSyangbo lu if (esdhc->vendor_ver > VENDOR_V_22) { 117f4932cfdSyangbo lu ret = value | SDHCI_CAN_DO_ADMA2; 118f4932cfdSyangbo lu return ret; 119137ccd46SJerry Huang } 120f4932cfdSyangbo lu } 121b0921d5cSMichael Walle /* 122b0921d5cSMichael Walle * The DAT[3:0] line signal levels and the CMD line signal level are 123b0921d5cSMichael Walle * not compatible with standard SDHC register. The line signal levels 124b0921d5cSMichael Walle * DAT[7:0] are at bits 31:24 and the command line signal level is at 125b0921d5cSMichael Walle * bit 23. All other bits are the same as in the standard SDHC 126b0921d5cSMichael Walle * register. 127b0921d5cSMichael Walle */ 128b0921d5cSMichael Walle if (spec_reg == SDHCI_PRESENT_STATE) { 129b0921d5cSMichael Walle ret = value & 0x000fffff; 130b0921d5cSMichael Walle ret |= (value >> 4) & SDHCI_DATA_LVL_MASK; 131b0921d5cSMichael Walle ret |= (value << 1) & SDHCI_CMD_LVL; 132b0921d5cSMichael Walle return ret; 133b0921d5cSMichael Walle } 134b0921d5cSMichael Walle 1352f3110ccSyangbo lu /* 1362f3110ccSyangbo lu * DTS properties of mmc host are used to enable each speed mode 1372f3110ccSyangbo lu * according to soc and board capability. So clean up 1382f3110ccSyangbo lu * SDR50/SDR104/DDR50 support bits here. 1392f3110ccSyangbo lu */ 1402f3110ccSyangbo lu if (spec_reg == SDHCI_CAPABILITIES_1) { 1412f3110ccSyangbo lu ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 1422f3110ccSyangbo lu SDHCI_SUPPORT_DDR50); 1432f3110ccSyangbo lu return ret; 1442f3110ccSyangbo lu } 1452f3110ccSyangbo lu 146f4932cfdSyangbo lu ret = value; 147137ccd46SJerry Huang return ret; 148137ccd46SJerry Huang } 149137ccd46SJerry Huang 150f4932cfdSyangbo lu static u16 esdhc_readw_fixup(struct sdhci_host *host, 151f4932cfdSyangbo lu int spec_reg, u32 value) 1527657c3a7SAlbert Herranz { 153151ede40Syangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 154151ede40Syangbo lu struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 1557657c3a7SAlbert Herranz u16 ret; 156f4932cfdSyangbo lu int shift = (spec_reg & 0x2) * 8; 1577657c3a7SAlbert Herranz 158f4932cfdSyangbo lu if (spec_reg == SDHCI_HOST_VERSION) 159f4932cfdSyangbo lu ret = value & 0xffff; 1607657c3a7SAlbert Herranz else 161f4932cfdSyangbo lu ret = (value >> shift) & 0xffff; 162151ede40Syangbo lu /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect 163151ede40Syangbo lu * vendor version and spec version information. 164151ede40Syangbo lu */ 165151ede40Syangbo lu if ((spec_reg == SDHCI_HOST_VERSION) && 166151ede40Syangbo lu (esdhc->quirk_incorrect_hostver)) 167151ede40Syangbo lu ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200; 168e51cbc9eSXu lei return ret; 169e51cbc9eSXu lei } 170e51cbc9eSXu lei 171f4932cfdSyangbo lu static u8 esdhc_readb_fixup(struct sdhci_host *host, 172f4932cfdSyangbo lu int spec_reg, u32 value) 173e51cbc9eSXu lei { 174f4932cfdSyangbo lu u8 ret; 175f4932cfdSyangbo lu u8 dma_bits; 176f4932cfdSyangbo lu int shift = (spec_reg & 0x3) * 8; 177f4932cfdSyangbo lu 178f4932cfdSyangbo lu ret = (value >> shift) & 0xff; 179ba8c4dc9SRoy Zang 180ba8c4dc9SRoy Zang /* 181ba8c4dc9SRoy Zang * "DMA select" locates at offset 0x28 in SD specification, but on 182ba8c4dc9SRoy Zang * P5020 or P3041, it locates at 0x29. 183ba8c4dc9SRoy Zang */ 184f4932cfdSyangbo lu if (spec_reg == SDHCI_HOST_CONTROL) { 185ba8c4dc9SRoy Zang /* DMA select is 22,23 bits in Protocol Control Register */ 186f4932cfdSyangbo lu dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK; 187ba8c4dc9SRoy Zang /* fixup the result */ 188ba8c4dc9SRoy Zang ret &= ~SDHCI_CTRL_DMA_MASK; 189ba8c4dc9SRoy Zang ret |= dma_bits; 190ba8c4dc9SRoy Zang } 191f4932cfdSyangbo lu return ret; 192f4932cfdSyangbo lu } 193f4932cfdSyangbo lu 194f4932cfdSyangbo lu /** 195f4932cfdSyangbo lu * esdhc_write*_fixup - Fixup the SD spec register value so that it could be 196f4932cfdSyangbo lu * written into eSDHC register. 197f4932cfdSyangbo lu * 198f4932cfdSyangbo lu * @host: pointer to sdhci_host 199f4932cfdSyangbo lu * @spec_reg: SD spec register address 200f4932cfdSyangbo lu * @value: 8/16/32bit SD spec register value that would be written 201f4932cfdSyangbo lu * @old_value: 32bit eSDHC register value on spec_reg address 202f4932cfdSyangbo lu * 203f4932cfdSyangbo lu * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 204f4932cfdSyangbo lu * registers are 32 bits. There are differences in register size, register 205f4932cfdSyangbo lu * address, register function, bit position and function between eSDHC spec 206f4932cfdSyangbo lu * and SD spec. 207f4932cfdSyangbo lu * 208f4932cfdSyangbo lu * Return a fixed up register value 209f4932cfdSyangbo lu */ 210f4932cfdSyangbo lu static u32 esdhc_writel_fixup(struct sdhci_host *host, 211f4932cfdSyangbo lu int spec_reg, u32 value, u32 old_value) 212f4932cfdSyangbo lu { 213f4932cfdSyangbo lu u32 ret; 214f4932cfdSyangbo lu 215f4932cfdSyangbo lu /* 216f4932cfdSyangbo lu * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE] 217f4932cfdSyangbo lu * when SYSCTL[RSTD] is set for some special operations. 218f4932cfdSyangbo lu * No any impact on other operation. 219f4932cfdSyangbo lu */ 220f4932cfdSyangbo lu if (spec_reg == SDHCI_INT_ENABLE) 221f4932cfdSyangbo lu ret = value | SDHCI_INT_BLK_GAP; 222f4932cfdSyangbo lu else 223f4932cfdSyangbo lu ret = value; 224ba8c4dc9SRoy Zang 2257657c3a7SAlbert Herranz return ret; 2267657c3a7SAlbert Herranz } 2277657c3a7SAlbert Herranz 228f4932cfdSyangbo lu static u32 esdhc_writew_fixup(struct sdhci_host *host, 229f4932cfdSyangbo lu int spec_reg, u16 value, u32 old_value) 230a4071fbbSHaijun Zhang { 231f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 232f4932cfdSyangbo lu int shift = (spec_reg & 0x2) * 8; 233f4932cfdSyangbo lu u32 ret; 234f4932cfdSyangbo lu 235f4932cfdSyangbo lu switch (spec_reg) { 236f4932cfdSyangbo lu case SDHCI_TRANSFER_MODE: 237a4071fbbSHaijun Zhang /* 238f4932cfdSyangbo lu * Postpone this write, we must do it together with a 239f4932cfdSyangbo lu * command write that is down below. Return old value. 240a4071fbbSHaijun Zhang */ 241f4932cfdSyangbo lu pltfm_host->xfer_mode_shadow = value; 242f4932cfdSyangbo lu return old_value; 243f4932cfdSyangbo lu case SDHCI_COMMAND: 244f4932cfdSyangbo lu ret = (value << 16) | pltfm_host->xfer_mode_shadow; 245f4932cfdSyangbo lu return ret; 246a4071fbbSHaijun Zhang } 247a4071fbbSHaijun Zhang 248f4932cfdSyangbo lu ret = old_value & (~(0xffff << shift)); 249f4932cfdSyangbo lu ret |= (value << shift); 250f4932cfdSyangbo lu 251f4932cfdSyangbo lu if (spec_reg == SDHCI_BLOCK_SIZE) { 2527657c3a7SAlbert Herranz /* 2537657c3a7SAlbert Herranz * Two last DMA bits are reserved, and first one is used for 2547657c3a7SAlbert Herranz * non-standard blksz of 4096 bytes that we don't support 2557657c3a7SAlbert Herranz * yet. So clear the DMA boundary bits. 2567657c3a7SAlbert Herranz */ 257f4932cfdSyangbo lu ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0)); 2587657c3a7SAlbert Herranz } 259f4932cfdSyangbo lu return ret; 2607657c3a7SAlbert Herranz } 2617657c3a7SAlbert Herranz 262f4932cfdSyangbo lu static u32 esdhc_writeb_fixup(struct sdhci_host *host, 263f4932cfdSyangbo lu int spec_reg, u8 value, u32 old_value) 2647657c3a7SAlbert Herranz { 265f4932cfdSyangbo lu u32 ret; 266f4932cfdSyangbo lu u32 dma_bits; 267f4932cfdSyangbo lu u8 tmp; 268f4932cfdSyangbo lu int shift = (spec_reg & 0x3) * 8; 269f4932cfdSyangbo lu 270ba8c4dc9SRoy Zang /* 2719e4703dfSyangbo lu * eSDHC doesn't have a standard power control register, so we do 2729e4703dfSyangbo lu * nothing here to avoid incorrect operation. 2739e4703dfSyangbo lu */ 2749e4703dfSyangbo lu if (spec_reg == SDHCI_POWER_CONTROL) 2759e4703dfSyangbo lu return old_value; 2769e4703dfSyangbo lu /* 277ba8c4dc9SRoy Zang * "DMA select" location is offset 0x28 in SD specification, but on 278ba8c4dc9SRoy Zang * P5020 or P3041, it's located at 0x29. 279ba8c4dc9SRoy Zang */ 280f4932cfdSyangbo lu if (spec_reg == SDHCI_HOST_CONTROL) { 281dcaff04dSOded Gabbay /* 282dcaff04dSOded Gabbay * If host control register is not standard, exit 283dcaff04dSOded Gabbay * this function 284dcaff04dSOded Gabbay */ 285dcaff04dSOded Gabbay if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL) 286f4932cfdSyangbo lu return old_value; 287dcaff04dSOded Gabbay 288ba8c4dc9SRoy Zang /* DMA select is 22,23 bits in Protocol Control Register */ 289f4932cfdSyangbo lu dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5; 290f4932cfdSyangbo lu ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits; 291f4932cfdSyangbo lu tmp = (value & (~SDHCI_CTRL_DMA_MASK)) | 292f4932cfdSyangbo lu (old_value & SDHCI_CTRL_DMA_MASK); 293f4932cfdSyangbo lu ret = (ret & (~0xff)) | tmp; 294f4932cfdSyangbo lu 295f4932cfdSyangbo lu /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */ 296f4932cfdSyangbo lu ret &= ~ESDHC_HOST_CONTROL_RES; 297f4932cfdSyangbo lu return ret; 298ba8c4dc9SRoy Zang } 299ba8c4dc9SRoy Zang 300f4932cfdSyangbo lu ret = (old_value & (~(0xff << shift))) | (value << shift); 301f4932cfdSyangbo lu return ret; 302f4932cfdSyangbo lu } 303f4932cfdSyangbo lu 304f4932cfdSyangbo lu static u32 esdhc_be_readl(struct sdhci_host *host, int reg) 305f4932cfdSyangbo lu { 306f4932cfdSyangbo lu u32 ret; 307f4932cfdSyangbo lu u32 value; 308f4932cfdSyangbo lu 3092f3110ccSyangbo lu if (reg == SDHCI_CAPABILITIES_1) 3102f3110ccSyangbo lu value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1); 3112f3110ccSyangbo lu else 312f4932cfdSyangbo lu value = ioread32be(host->ioaddr + reg); 3132f3110ccSyangbo lu 314f4932cfdSyangbo lu ret = esdhc_readl_fixup(host, reg, value); 315f4932cfdSyangbo lu 316f4932cfdSyangbo lu return ret; 317f4932cfdSyangbo lu } 318f4932cfdSyangbo lu 319f4932cfdSyangbo lu static u32 esdhc_le_readl(struct sdhci_host *host, int reg) 320f4932cfdSyangbo lu { 321f4932cfdSyangbo lu u32 ret; 322f4932cfdSyangbo lu u32 value; 323f4932cfdSyangbo lu 3242f3110ccSyangbo lu if (reg == SDHCI_CAPABILITIES_1) 3252f3110ccSyangbo lu value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1); 3262f3110ccSyangbo lu else 327f4932cfdSyangbo lu value = ioread32(host->ioaddr + reg); 3282f3110ccSyangbo lu 329f4932cfdSyangbo lu ret = esdhc_readl_fixup(host, reg, value); 330f4932cfdSyangbo lu 331f4932cfdSyangbo lu return ret; 332f4932cfdSyangbo lu } 333f4932cfdSyangbo lu 334f4932cfdSyangbo lu static u16 esdhc_be_readw(struct sdhci_host *host, int reg) 335f4932cfdSyangbo lu { 336f4932cfdSyangbo lu u16 ret; 337f4932cfdSyangbo lu u32 value; 338f4932cfdSyangbo lu int base = reg & ~0x3; 339f4932cfdSyangbo lu 340f4932cfdSyangbo lu value = ioread32be(host->ioaddr + base); 341f4932cfdSyangbo lu ret = esdhc_readw_fixup(host, reg, value); 342f4932cfdSyangbo lu return ret; 343f4932cfdSyangbo lu } 344f4932cfdSyangbo lu 345f4932cfdSyangbo lu static u16 esdhc_le_readw(struct sdhci_host *host, int reg) 346f4932cfdSyangbo lu { 347f4932cfdSyangbo lu u16 ret; 348f4932cfdSyangbo lu u32 value; 349f4932cfdSyangbo lu int base = reg & ~0x3; 350f4932cfdSyangbo lu 351f4932cfdSyangbo lu value = ioread32(host->ioaddr + base); 352f4932cfdSyangbo lu ret = esdhc_readw_fixup(host, reg, value); 353f4932cfdSyangbo lu return ret; 354f4932cfdSyangbo lu } 355f4932cfdSyangbo lu 356f4932cfdSyangbo lu static u8 esdhc_be_readb(struct sdhci_host *host, int reg) 357f4932cfdSyangbo lu { 358f4932cfdSyangbo lu u8 ret; 359f4932cfdSyangbo lu u32 value; 360f4932cfdSyangbo lu int base = reg & ~0x3; 361f4932cfdSyangbo lu 362f4932cfdSyangbo lu value = ioread32be(host->ioaddr + base); 363f4932cfdSyangbo lu ret = esdhc_readb_fixup(host, reg, value); 364f4932cfdSyangbo lu return ret; 365f4932cfdSyangbo lu } 366f4932cfdSyangbo lu 367f4932cfdSyangbo lu static u8 esdhc_le_readb(struct sdhci_host *host, int reg) 368f4932cfdSyangbo lu { 369f4932cfdSyangbo lu u8 ret; 370f4932cfdSyangbo lu u32 value; 371f4932cfdSyangbo lu int base = reg & ~0x3; 372f4932cfdSyangbo lu 373f4932cfdSyangbo lu value = ioread32(host->ioaddr + base); 374f4932cfdSyangbo lu ret = esdhc_readb_fixup(host, reg, value); 375f4932cfdSyangbo lu return ret; 376f4932cfdSyangbo lu } 377f4932cfdSyangbo lu 378f4932cfdSyangbo lu static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) 379f4932cfdSyangbo lu { 380f4932cfdSyangbo lu u32 value; 381f4932cfdSyangbo lu 382f4932cfdSyangbo lu value = esdhc_writel_fixup(host, reg, val, 0); 383f4932cfdSyangbo lu iowrite32be(value, host->ioaddr + reg); 384f4932cfdSyangbo lu } 385f4932cfdSyangbo lu 386f4932cfdSyangbo lu static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) 387f4932cfdSyangbo lu { 388f4932cfdSyangbo lu u32 value; 389f4932cfdSyangbo lu 390f4932cfdSyangbo lu value = esdhc_writel_fixup(host, reg, val, 0); 391f4932cfdSyangbo lu iowrite32(value, host->ioaddr + reg); 392f4932cfdSyangbo lu } 393f4932cfdSyangbo lu 394f4932cfdSyangbo lu static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) 395f4932cfdSyangbo lu { 396f4932cfdSyangbo lu int base = reg & ~0x3; 397f4932cfdSyangbo lu u32 value; 398f4932cfdSyangbo lu u32 ret; 399f4932cfdSyangbo lu 400f4932cfdSyangbo lu value = ioread32be(host->ioaddr + base); 401f4932cfdSyangbo lu ret = esdhc_writew_fixup(host, reg, val, value); 402f4932cfdSyangbo lu if (reg != SDHCI_TRANSFER_MODE) 403f4932cfdSyangbo lu iowrite32be(ret, host->ioaddr + base); 404f4932cfdSyangbo lu } 405f4932cfdSyangbo lu 406f4932cfdSyangbo lu static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) 407f4932cfdSyangbo lu { 408f4932cfdSyangbo lu int base = reg & ~0x3; 409f4932cfdSyangbo lu u32 value; 410f4932cfdSyangbo lu u32 ret; 411f4932cfdSyangbo lu 412f4932cfdSyangbo lu value = ioread32(host->ioaddr + base); 413f4932cfdSyangbo lu ret = esdhc_writew_fixup(host, reg, val, value); 414f4932cfdSyangbo lu if (reg != SDHCI_TRANSFER_MODE) 415f4932cfdSyangbo lu iowrite32(ret, host->ioaddr + base); 416f4932cfdSyangbo lu } 417f4932cfdSyangbo lu 418f4932cfdSyangbo lu static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) 419f4932cfdSyangbo lu { 420f4932cfdSyangbo lu int base = reg & ~0x3; 421f4932cfdSyangbo lu u32 value; 422f4932cfdSyangbo lu u32 ret; 423f4932cfdSyangbo lu 424f4932cfdSyangbo lu value = ioread32be(host->ioaddr + base); 425f4932cfdSyangbo lu ret = esdhc_writeb_fixup(host, reg, val, value); 426f4932cfdSyangbo lu iowrite32be(ret, host->ioaddr + base); 427f4932cfdSyangbo lu } 428f4932cfdSyangbo lu 429f4932cfdSyangbo lu static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) 430f4932cfdSyangbo lu { 431f4932cfdSyangbo lu int base = reg & ~0x3; 432f4932cfdSyangbo lu u32 value; 433f4932cfdSyangbo lu u32 ret; 434f4932cfdSyangbo lu 435f4932cfdSyangbo lu value = ioread32(host->ioaddr + base); 436f4932cfdSyangbo lu ret = esdhc_writeb_fixup(host, reg, val, value); 437f4932cfdSyangbo lu iowrite32(ret, host->ioaddr + base); 4387657c3a7SAlbert Herranz } 4397657c3a7SAlbert Herranz 440a4071fbbSHaijun Zhang /* 441a4071fbbSHaijun Zhang * For Abort or Suspend after Stop at Block Gap, ignore the ADMA 442a4071fbbSHaijun Zhang * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC]) 443a4071fbbSHaijun Zhang * and Block Gap Event(IRQSTAT[BGE]) are also set. 444a4071fbbSHaijun Zhang * For Continue, apply soft reset for data(SYSCTL[RSTD]); 445a4071fbbSHaijun Zhang * and re-issue the entire read transaction from beginning. 446a4071fbbSHaijun Zhang */ 447f4932cfdSyangbo lu static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask) 448a4071fbbSHaijun Zhang { 449f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 4508605e7aeSJisheng Zhang struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 451a4071fbbSHaijun Zhang bool applicable; 452a4071fbbSHaijun Zhang dma_addr_t dmastart; 453a4071fbbSHaijun Zhang dma_addr_t dmanow; 454a4071fbbSHaijun Zhang 455a4071fbbSHaijun Zhang applicable = (intmask & SDHCI_INT_DATA_END) && 456a4071fbbSHaijun Zhang (intmask & SDHCI_INT_BLK_GAP) && 457f4932cfdSyangbo lu (esdhc->vendor_ver == VENDOR_V_23); 458a4071fbbSHaijun Zhang if (!applicable) 459a4071fbbSHaijun Zhang return; 460a4071fbbSHaijun Zhang 461a4071fbbSHaijun Zhang host->data->error = 0; 462a4071fbbSHaijun Zhang dmastart = sg_dma_address(host->data->sg); 463a4071fbbSHaijun Zhang dmanow = dmastart + host->data->bytes_xfered; 464a4071fbbSHaijun Zhang /* 465a4071fbbSHaijun Zhang * Force update to the next DMA block boundary. 466a4071fbbSHaijun Zhang */ 467a4071fbbSHaijun Zhang dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 468a4071fbbSHaijun Zhang SDHCI_DEFAULT_BOUNDARY_SIZE; 469a4071fbbSHaijun Zhang host->data->bytes_xfered = dmanow - dmastart; 470a4071fbbSHaijun Zhang sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 471a4071fbbSHaijun Zhang } 472a4071fbbSHaijun Zhang 47380872e21SWolfram Sang static int esdhc_of_enable_dma(struct sdhci_host *host) 4747657c3a7SAlbert Herranz { 475f4932cfdSyangbo lu u32 value; 4765552d7adSLaurentiu Tudor struct device *dev = mmc_dev(host->mmc); 4775552d7adSLaurentiu Tudor 4785552d7adSLaurentiu Tudor if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") || 4795552d7adSLaurentiu Tudor of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) 4805552d7adSLaurentiu Tudor dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); 481f4932cfdSyangbo lu 482f4932cfdSyangbo lu value = sdhci_readl(host, ESDHC_DMA_SYSCTL); 483f4932cfdSyangbo lu value |= ESDHC_DMA_SNOOP; 484f4932cfdSyangbo lu sdhci_writel(host, value, ESDHC_DMA_SYSCTL); 4857657c3a7SAlbert Herranz return 0; 4867657c3a7SAlbert Herranz } 4877657c3a7SAlbert Herranz 48880872e21SWolfram Sang static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) 4897657c3a7SAlbert Herranz { 490e307148fSShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 49119c3a0efSyangbo lu struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 4927657c3a7SAlbert Herranz 49319c3a0efSyangbo lu if (esdhc->peripheral_clock) 49419c3a0efSyangbo lu return esdhc->peripheral_clock; 49519c3a0efSyangbo lu else 496e307148fSShawn Guo return pltfm_host->clock; 4977657c3a7SAlbert Herranz } 4987657c3a7SAlbert Herranz 49980872e21SWolfram Sang static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) 5007657c3a7SAlbert Herranz { 501e307148fSShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 50219c3a0efSyangbo lu struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 50319c3a0efSyangbo lu unsigned int clock; 5047657c3a7SAlbert Herranz 50519c3a0efSyangbo lu if (esdhc->peripheral_clock) 50619c3a0efSyangbo lu clock = esdhc->peripheral_clock; 50719c3a0efSyangbo lu else 50819c3a0efSyangbo lu clock = pltfm_host->clock; 50919c3a0efSyangbo lu return clock / 256 / 16; 5107657c3a7SAlbert Herranz } 5117657c3a7SAlbert Herranz 512dd3f6983Syangbo lu static void esdhc_clock_enable(struct sdhci_host *host, bool enable) 513dd3f6983Syangbo lu { 514dd3f6983Syangbo lu u32 val; 515dd3f6983Syangbo lu ktime_t timeout; 516dd3f6983Syangbo lu 517dd3f6983Syangbo lu val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 518dd3f6983Syangbo lu 519dd3f6983Syangbo lu if (enable) 520dd3f6983Syangbo lu val |= ESDHC_CLOCK_SDCLKEN; 521dd3f6983Syangbo lu else 522dd3f6983Syangbo lu val &= ~ESDHC_CLOCK_SDCLKEN; 523dd3f6983Syangbo lu 524dd3f6983Syangbo lu sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL); 525dd3f6983Syangbo lu 526dd3f6983Syangbo lu /* Wait max 20 ms */ 527dd3f6983Syangbo lu timeout = ktime_add_ms(ktime_get(), 20); 528dd3f6983Syangbo lu val = ESDHC_CLOCK_STABLE; 529dd3f6983Syangbo lu while (!(sdhci_readl(host, ESDHC_PRSSTAT) & val)) { 530dd3f6983Syangbo lu if (ktime_after(ktime_get(), timeout)) { 531dd3f6983Syangbo lu pr_err("%s: Internal clock never stabilised.\n", 532dd3f6983Syangbo lu mmc_hostname(host->mmc)); 533dd3f6983Syangbo lu break; 534dd3f6983Syangbo lu } 535dd3f6983Syangbo lu udelay(10); 536dd3f6983Syangbo lu } 537dd3f6983Syangbo lu } 538dd3f6983Syangbo lu 539f060bc9cSJerry Huang static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) 540f060bc9cSJerry Huang { 541f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 5428605e7aeSJisheng Zhang struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 543bd455029SJoakim Tjernlund int pre_div = 1; 544d31fc00aSDong Aisheng int div = 1; 545e145ac45Syangbo lu ktime_t timeout; 54667fdfbdfSyinbo.zhu long fixup = 0; 547d31fc00aSDong Aisheng u32 temp; 548d31fc00aSDong Aisheng 5491650d0c7SRussell King host->mmc->actual_clock = 0; 5501650d0c7SRussell King 551dd3f6983Syangbo lu if (clock == 0) { 552dd3f6983Syangbo lu esdhc_clock_enable(host, false); 553373073efSRussell King return; 554dd3f6983Syangbo lu } 555d31fc00aSDong Aisheng 55677bd2f6fSYangbo Lu /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */ 557f4932cfdSyangbo lu if (esdhc->vendor_ver < VENDOR_V_23) 55877bd2f6fSYangbo Lu pre_div = 2; 55977bd2f6fSYangbo Lu 56067fdfbdfSyinbo.zhu if (host->mmc->card && mmc_card_sd(host->mmc->card) && 56167fdfbdfSyinbo.zhu esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY) 56267fdfbdfSyinbo.zhu fixup = esdhc->clk_fixup->sd_dflt_max_clk; 56367fdfbdfSyinbo.zhu else if (esdhc->clk_fixup) 56467fdfbdfSyinbo.zhu fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing]; 565a627f025Syangbo lu 56667fdfbdfSyinbo.zhu if (fixup && clock > fixup) 56767fdfbdfSyinbo.zhu clock = fixup; 568f060bc9cSJerry Huang 569d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 570e87d2db2Syangbo lu temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | 571e87d2db2Syangbo lu ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK); 572d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 573d31fc00aSDong Aisheng 574d31fc00aSDong Aisheng while (host->max_clk / pre_div / 16 > clock && pre_div < 256) 575d31fc00aSDong Aisheng pre_div *= 2; 576d31fc00aSDong Aisheng 577d31fc00aSDong Aisheng while (host->max_clk / pre_div / div > clock && div < 16) 578d31fc00aSDong Aisheng div++; 579d31fc00aSDong Aisheng 580d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 581e76b8559SDong Aisheng clock, host->max_clk / pre_div / div); 582bd455029SJoakim Tjernlund host->mmc->actual_clock = host->max_clk / pre_div / div; 583d31fc00aSDong Aisheng pre_div >>= 1; 584d31fc00aSDong Aisheng div--; 585d31fc00aSDong Aisheng 586d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 587d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 588d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 589d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 590d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 591e87d2db2Syangbo lu 592e87d2db2Syangbo lu /* Wait max 20 ms */ 593e145ac45Syangbo lu timeout = ktime_add_ms(ktime_get(), 20); 594e87d2db2Syangbo lu while (!(sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)) { 595e145ac45Syangbo lu if (ktime_after(ktime_get(), timeout)) { 596e87d2db2Syangbo lu pr_err("%s: Internal clock never stabilised.\n", 597e87d2db2Syangbo lu mmc_hostname(host->mmc)); 598e87d2db2Syangbo lu return; 599e87d2db2Syangbo lu } 600e145ac45Syangbo lu udelay(10); 601f060bc9cSJerry Huang } 602f060bc9cSJerry Huang 603e87d2db2Syangbo lu temp |= ESDHC_CLOCK_SDCLKEN; 604e87d2db2Syangbo lu sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 605e87d2db2Syangbo lu } 606e87d2db2Syangbo lu 6072317f56cSRussell King static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 60866b50a00SOded Gabbay { 60966b50a00SOded Gabbay u32 ctrl; 61066b50a00SOded Gabbay 611f4932cfdSyangbo lu ctrl = sdhci_readl(host, ESDHC_PROCTL); 612f4932cfdSyangbo lu ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK); 61366b50a00SOded Gabbay switch (width) { 61466b50a00SOded Gabbay case MMC_BUS_WIDTH_8: 615f4932cfdSyangbo lu ctrl |= ESDHC_CTRL_8BITBUS; 61666b50a00SOded Gabbay break; 61766b50a00SOded Gabbay 61866b50a00SOded Gabbay case MMC_BUS_WIDTH_4: 619f4932cfdSyangbo lu ctrl |= ESDHC_CTRL_4BITBUS; 62066b50a00SOded Gabbay break; 62166b50a00SOded Gabbay 62266b50a00SOded Gabbay default: 62366b50a00SOded Gabbay break; 62466b50a00SOded Gabbay } 62566b50a00SOded Gabbay 626f4932cfdSyangbo lu sdhci_writel(host, ctrl, ESDHC_PROCTL); 62766b50a00SOded Gabbay } 62866b50a00SOded Gabbay 629304f0a98SAlessio Igor Bogani static void esdhc_reset(struct sdhci_host *host, u8 mask) 630304f0a98SAlessio Igor Bogani { 631f2bc6000Syinbo.zhu u32 val; 632f2bc6000Syinbo.zhu 633304f0a98SAlessio Igor Bogani sdhci_reset(host, mask); 634304f0a98SAlessio Igor Bogani 635304f0a98SAlessio Igor Bogani sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 636304f0a98SAlessio Igor Bogani sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 637f2bc6000Syinbo.zhu 638f2bc6000Syinbo.zhu if (mask & SDHCI_RESET_ALL) { 639f2bc6000Syinbo.zhu val = sdhci_readl(host, ESDHC_TBCTL); 640f2bc6000Syinbo.zhu val &= ~ESDHC_TB_EN; 641f2bc6000Syinbo.zhu sdhci_writel(host, val, ESDHC_TBCTL); 642f2bc6000Syinbo.zhu } 643304f0a98SAlessio Igor Bogani } 644304f0a98SAlessio Igor Bogani 645ea35645aSyangbo lu /* The SCFG, Supplemental Configuration Unit, provides SoC specific 646ea35645aSyangbo lu * configuration and status registers for the device. There is a 647ea35645aSyangbo lu * SDHC IO VSEL control register on SCFG for some platforms. It's 648ea35645aSyangbo lu * used to support SDHC IO voltage switching. 649ea35645aSyangbo lu */ 650ea35645aSyangbo lu static const struct of_device_id scfg_device_ids[] = { 651ea35645aSyangbo lu { .compatible = "fsl,t1040-scfg", }, 652ea35645aSyangbo lu { .compatible = "fsl,ls1012a-scfg", }, 653ea35645aSyangbo lu { .compatible = "fsl,ls1046a-scfg", }, 654ea35645aSyangbo lu {} 655ea35645aSyangbo lu }; 656ea35645aSyangbo lu 657ea35645aSyangbo lu /* SDHC IO VSEL control register definition */ 658ea35645aSyangbo lu #define SCFG_SDHCIOVSELCR 0x408 659ea35645aSyangbo lu #define SDHCIOVSELCR_TGLEN 0x80000000 660ea35645aSyangbo lu #define SDHCIOVSELCR_VSELVAL 0x60000000 661ea35645aSyangbo lu #define SDHCIOVSELCR_SDHC_VS 0x00000001 662ea35645aSyangbo lu 663ea35645aSyangbo lu static int esdhc_signal_voltage_switch(struct mmc_host *mmc, 664ea35645aSyangbo lu struct mmc_ios *ios) 665ea35645aSyangbo lu { 666ea35645aSyangbo lu struct sdhci_host *host = mmc_priv(mmc); 667ea35645aSyangbo lu struct device_node *scfg_node; 668ea35645aSyangbo lu void __iomem *scfg_base = NULL; 669ea35645aSyangbo lu u32 sdhciovselcr; 670ea35645aSyangbo lu u32 val; 671ea35645aSyangbo lu 672ea35645aSyangbo lu /* 673ea35645aSyangbo lu * Signal Voltage Switching is only applicable for Host Controllers 674ea35645aSyangbo lu * v3.00 and above. 675ea35645aSyangbo lu */ 676ea35645aSyangbo lu if (host->version < SDHCI_SPEC_300) 677ea35645aSyangbo lu return 0; 678ea35645aSyangbo lu 679ea35645aSyangbo lu val = sdhci_readl(host, ESDHC_PROCTL); 680ea35645aSyangbo lu 681ea35645aSyangbo lu switch (ios->signal_voltage) { 682ea35645aSyangbo lu case MMC_SIGNAL_VOLTAGE_330: 683ea35645aSyangbo lu val &= ~ESDHC_VOLT_SEL; 684ea35645aSyangbo lu sdhci_writel(host, val, ESDHC_PROCTL); 685ea35645aSyangbo lu return 0; 686ea35645aSyangbo lu case MMC_SIGNAL_VOLTAGE_180: 687ea35645aSyangbo lu scfg_node = of_find_matching_node(NULL, scfg_device_ids); 688ea35645aSyangbo lu if (scfg_node) 689ea35645aSyangbo lu scfg_base = of_iomap(scfg_node, 0); 690ea35645aSyangbo lu if (scfg_base) { 691ea35645aSyangbo lu sdhciovselcr = SDHCIOVSELCR_TGLEN | 692ea35645aSyangbo lu SDHCIOVSELCR_VSELVAL; 693ea35645aSyangbo lu iowrite32be(sdhciovselcr, 694ea35645aSyangbo lu scfg_base + SCFG_SDHCIOVSELCR); 695ea35645aSyangbo lu 696ea35645aSyangbo lu val |= ESDHC_VOLT_SEL; 697ea35645aSyangbo lu sdhci_writel(host, val, ESDHC_PROCTL); 698ea35645aSyangbo lu mdelay(5); 699ea35645aSyangbo lu 700ea35645aSyangbo lu sdhciovselcr = SDHCIOVSELCR_TGLEN | 701ea35645aSyangbo lu SDHCIOVSELCR_SDHC_VS; 702ea35645aSyangbo lu iowrite32be(sdhciovselcr, 703ea35645aSyangbo lu scfg_base + SCFG_SDHCIOVSELCR); 704ea35645aSyangbo lu iounmap(scfg_base); 705ea35645aSyangbo lu } else { 706ea35645aSyangbo lu val |= ESDHC_VOLT_SEL; 707ea35645aSyangbo lu sdhci_writel(host, val, ESDHC_PROCTL); 708ea35645aSyangbo lu } 709ea35645aSyangbo lu return 0; 710ea35645aSyangbo lu default: 711ea35645aSyangbo lu return 0; 712ea35645aSyangbo lu } 713ea35645aSyangbo lu } 714ea35645aSyangbo lu 715ba49cbd0Syangbo lu static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 716ba49cbd0Syangbo lu { 717ba49cbd0Syangbo lu struct sdhci_host *host = mmc_priv(mmc); 718ba49cbd0Syangbo lu u32 val; 719ba49cbd0Syangbo lu 720ba49cbd0Syangbo lu /* Use tuning block for tuning procedure */ 721ba49cbd0Syangbo lu esdhc_clock_enable(host, false); 722ba49cbd0Syangbo lu val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 723ba49cbd0Syangbo lu val |= ESDHC_FLUSH_ASYNC_FIFO; 724ba49cbd0Syangbo lu sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 725ba49cbd0Syangbo lu 726ba49cbd0Syangbo lu val = sdhci_readl(host, ESDHC_TBCTL); 727ba49cbd0Syangbo lu val |= ESDHC_TB_EN; 728ba49cbd0Syangbo lu sdhci_writel(host, val, ESDHC_TBCTL); 729ba49cbd0Syangbo lu esdhc_clock_enable(host, true); 730ba49cbd0Syangbo lu 731ba49cbd0Syangbo lu return sdhci_execute_tuning(mmc, opcode); 732ba49cbd0Syangbo lu } 733ba49cbd0Syangbo lu 7349e48b336SUlf Hansson #ifdef CONFIG_PM_SLEEP 735723f7924SRussell King static u32 esdhc_proctl; 736723f7924SRussell King static int esdhc_of_suspend(struct device *dev) 737723f7924SRussell King { 738723f7924SRussell King struct sdhci_host *host = dev_get_drvdata(dev); 739723f7924SRussell King 740f4932cfdSyangbo lu esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL); 741723f7924SRussell King 742d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 743d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 744d38dcad4SAdrian Hunter 745723f7924SRussell King return sdhci_suspend_host(host); 746723f7924SRussell King } 747723f7924SRussell King 74806732b84SUlf Hansson static int esdhc_of_resume(struct device *dev) 749723f7924SRussell King { 750723f7924SRussell King struct sdhci_host *host = dev_get_drvdata(dev); 751723f7924SRussell King int ret = sdhci_resume_host(host); 752723f7924SRussell King 753723f7924SRussell King if (ret == 0) { 754723f7924SRussell King /* Isn't this already done by sdhci_resume_host() ? --rmk */ 755723f7924SRussell King esdhc_of_enable_dma(host); 756f4932cfdSyangbo lu sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); 757723f7924SRussell King } 758723f7924SRussell King return ret; 759723f7924SRussell King } 760723f7924SRussell King #endif 761723f7924SRussell King 7629e48b336SUlf Hansson static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops, 7639e48b336SUlf Hansson esdhc_of_suspend, 7649e48b336SUlf Hansson esdhc_of_resume); 7659e48b336SUlf Hansson 766f4932cfdSyangbo lu static const struct sdhci_ops sdhci_esdhc_be_ops = { 767f4932cfdSyangbo lu .read_l = esdhc_be_readl, 768f4932cfdSyangbo lu .read_w = esdhc_be_readw, 769f4932cfdSyangbo lu .read_b = esdhc_be_readb, 770f4932cfdSyangbo lu .write_l = esdhc_be_writel, 771f4932cfdSyangbo lu .write_w = esdhc_be_writew, 772f4932cfdSyangbo lu .write_b = esdhc_be_writeb, 773f4932cfdSyangbo lu .set_clock = esdhc_of_set_clock, 774f4932cfdSyangbo lu .enable_dma = esdhc_of_enable_dma, 775f4932cfdSyangbo lu .get_max_clock = esdhc_of_get_max_clock, 776f4932cfdSyangbo lu .get_min_clock = esdhc_of_get_min_clock, 777f4932cfdSyangbo lu .adma_workaround = esdhc_of_adma_workaround, 778f4932cfdSyangbo lu .set_bus_width = esdhc_pltfm_set_bus_width, 779f4932cfdSyangbo lu .reset = esdhc_reset, 780f4932cfdSyangbo lu .set_uhs_signaling = sdhci_set_uhs_signaling, 781f4932cfdSyangbo lu }; 782f4932cfdSyangbo lu 783f4932cfdSyangbo lu static const struct sdhci_ops sdhci_esdhc_le_ops = { 784f4932cfdSyangbo lu .read_l = esdhc_le_readl, 785f4932cfdSyangbo lu .read_w = esdhc_le_readw, 786f4932cfdSyangbo lu .read_b = esdhc_le_readb, 787f4932cfdSyangbo lu .write_l = esdhc_le_writel, 788f4932cfdSyangbo lu .write_w = esdhc_le_writew, 789f4932cfdSyangbo lu .write_b = esdhc_le_writeb, 790f4932cfdSyangbo lu .set_clock = esdhc_of_set_clock, 791f4932cfdSyangbo lu .enable_dma = esdhc_of_enable_dma, 792f4932cfdSyangbo lu .get_max_clock = esdhc_of_get_max_clock, 793f4932cfdSyangbo lu .get_min_clock = esdhc_of_get_min_clock, 794f4932cfdSyangbo lu .adma_workaround = esdhc_of_adma_workaround, 795f4932cfdSyangbo lu .set_bus_width = esdhc_pltfm_set_bus_width, 796f4932cfdSyangbo lu .reset = esdhc_reset, 797f4932cfdSyangbo lu .set_uhs_signaling = sdhci_set_uhs_signaling, 798f4932cfdSyangbo lu }; 799f4932cfdSyangbo lu 800f4932cfdSyangbo lu static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = { 801e9acc77dSyangbo lu .quirks = ESDHC_DEFAULT_QUIRKS | 802e9acc77dSyangbo lu #ifdef CONFIG_PPC 803e9acc77dSyangbo lu SDHCI_QUIRK_BROKEN_CARD_DETECTION | 804e9acc77dSyangbo lu #endif 805e9acc77dSyangbo lu SDHCI_QUIRK_NO_CARD_NO_RESET | 806e9acc77dSyangbo lu SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 807f4932cfdSyangbo lu .ops = &sdhci_esdhc_be_ops, 8087657c3a7SAlbert Herranz }; 80938576af1SShawn Guo 810f4932cfdSyangbo lu static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = { 811e9acc77dSyangbo lu .quirks = ESDHC_DEFAULT_QUIRKS | 812e9acc77dSyangbo lu SDHCI_QUIRK_NO_CARD_NO_RESET | 813e9acc77dSyangbo lu SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 814f4932cfdSyangbo lu .ops = &sdhci_esdhc_le_ops, 815f4932cfdSyangbo lu }; 816f4932cfdSyangbo lu 817151ede40Syangbo lu static struct soc_device_attribute soc_incorrect_hostver[] = { 818151ede40Syangbo lu { .family = "QorIQ T4240", .revision = "1.0", }, 819151ede40Syangbo lu { .family = "QorIQ T4240", .revision = "2.0", }, 820151ede40Syangbo lu { }, 821151ede40Syangbo lu }; 822151ede40Syangbo lu 823f4932cfdSyangbo lu static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host) 824f4932cfdSyangbo lu { 82567fdfbdfSyinbo.zhu const struct of_device_id *match; 826f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host; 827f4932cfdSyangbo lu struct sdhci_esdhc *esdhc; 82819c3a0efSyangbo lu struct device_node *np; 82919c3a0efSyangbo lu struct clk *clk; 83019c3a0efSyangbo lu u32 val; 831f4932cfdSyangbo lu u16 host_ver; 832f4932cfdSyangbo lu 833f4932cfdSyangbo lu pltfm_host = sdhci_priv(host); 8348605e7aeSJisheng Zhang esdhc = sdhci_pltfm_priv(pltfm_host); 835f4932cfdSyangbo lu 836f4932cfdSyangbo lu host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); 837f4932cfdSyangbo lu esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >> 838f4932cfdSyangbo lu SDHCI_VENDOR_VER_SHIFT; 839f4932cfdSyangbo lu esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK; 840151ede40Syangbo lu if (soc_device_match(soc_incorrect_hostver)) 841151ede40Syangbo lu esdhc->quirk_incorrect_hostver = true; 842151ede40Syangbo lu else 843151ede40Syangbo lu esdhc->quirk_incorrect_hostver = false; 84419c3a0efSyangbo lu 84567fdfbdfSyinbo.zhu match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node); 84667fdfbdfSyinbo.zhu if (match) 84767fdfbdfSyinbo.zhu esdhc->clk_fixup = match->data; 84819c3a0efSyangbo lu np = pdev->dev.of_node; 84919c3a0efSyangbo lu clk = of_clk_get(np, 0); 85019c3a0efSyangbo lu if (!IS_ERR(clk)) { 85119c3a0efSyangbo lu /* 85219c3a0efSyangbo lu * esdhc->peripheral_clock would be assigned with a value 85319c3a0efSyangbo lu * which is eSDHC base clock when use periperal clock. 85419c3a0efSyangbo lu * For ls1046a, the clock value got by common clk API is 85519c3a0efSyangbo lu * peripheral clock while the eSDHC base clock is 1/2 85619c3a0efSyangbo lu * peripheral clock. 85719c3a0efSyangbo lu */ 85819c3a0efSyangbo lu if (of_device_is_compatible(np, "fsl,ls1046a-esdhc")) 85919c3a0efSyangbo lu esdhc->peripheral_clock = clk_get_rate(clk) / 2; 86019c3a0efSyangbo lu else 86119c3a0efSyangbo lu esdhc->peripheral_clock = clk_get_rate(clk); 86219c3a0efSyangbo lu 86319c3a0efSyangbo lu clk_put(clk); 86419c3a0efSyangbo lu } 86519c3a0efSyangbo lu 86619c3a0efSyangbo lu if (esdhc->peripheral_clock) { 86719c3a0efSyangbo lu esdhc_clock_enable(host, false); 86819c3a0efSyangbo lu val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 86919c3a0efSyangbo lu val |= ESDHC_PERIPHERAL_CLK_SEL; 87019c3a0efSyangbo lu sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 87119c3a0efSyangbo lu esdhc_clock_enable(host, true); 87219c3a0efSyangbo lu } 873f4932cfdSyangbo lu } 874f4932cfdSyangbo lu 875c3be1efdSBill Pemberton static int sdhci_esdhc_probe(struct platform_device *pdev) 87638576af1SShawn Guo { 87766b50a00SOded Gabbay struct sdhci_host *host; 878dcaff04dSOded Gabbay struct device_node *np; 8791ef5e49eSyangbo lu struct sdhci_pltfm_host *pltfm_host; 8801ef5e49eSyangbo lu struct sdhci_esdhc *esdhc; 88166b50a00SOded Gabbay int ret; 88266b50a00SOded Gabbay 883f4932cfdSyangbo lu np = pdev->dev.of_node; 884f4932cfdSyangbo lu 885150d4240SJulia Lawall if (of_property_read_bool(np, "little-endian")) 8868605e7aeSJisheng Zhang host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata, 8878605e7aeSJisheng Zhang sizeof(struct sdhci_esdhc)); 888f4932cfdSyangbo lu else 8898605e7aeSJisheng Zhang host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata, 8908605e7aeSJisheng Zhang sizeof(struct sdhci_esdhc)); 891f4932cfdSyangbo lu 89266b50a00SOded Gabbay if (IS_ERR(host)) 89366b50a00SOded Gabbay return PTR_ERR(host); 89466b50a00SOded Gabbay 895ea35645aSyangbo lu host->mmc_host_ops.start_signal_voltage_switch = 896ea35645aSyangbo lu esdhc_signal_voltage_switch; 897ba49cbd0Syangbo lu host->mmc_host_ops.execute_tuning = esdhc_execute_tuning; 8986b236f37Syangbo lu host->tuning_delay = 1; 899ea35645aSyangbo lu 900f4932cfdSyangbo lu esdhc_init(pdev, host); 901f4932cfdSyangbo lu 90266b50a00SOded Gabbay sdhci_get_of_property(pdev); 90366b50a00SOded Gabbay 9041ef5e49eSyangbo lu pltfm_host = sdhci_priv(host); 9058605e7aeSJisheng Zhang esdhc = sdhci_pltfm_priv(pltfm_host); 9061ef5e49eSyangbo lu if (esdhc->vendor_ver == VENDOR_V_22) 9071ef5e49eSyangbo lu host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; 9081ef5e49eSyangbo lu 9091ef5e49eSyangbo lu if (esdhc->vendor_ver > VENDOR_V_22) 9101ef5e49eSyangbo lu host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 9111ef5e49eSyangbo lu 91274fd5e30SYangbo Lu if (of_device_is_compatible(np, "fsl,p5040-esdhc") || 91374fd5e30SYangbo Lu of_device_is_compatible(np, "fsl,p5020-esdhc") || 91474fd5e30SYangbo Lu of_device_is_compatible(np, "fsl,p4080-esdhc") || 91574fd5e30SYangbo Lu of_device_is_compatible(np, "fsl,p1020-esdhc") || 916e9acc77dSyangbo lu of_device_is_compatible(np, "fsl,t1040-esdhc")) 91774fd5e30SYangbo Lu host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 91874fd5e30SYangbo Lu 919a22950c8Syangbo lu if (of_device_is_compatible(np, "fsl,ls1021a-esdhc")) 920a22950c8Syangbo lu host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 921a22950c8Syangbo lu 922dcaff04dSOded Gabbay if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { 923dcaff04dSOded Gabbay /* 924dcaff04dSOded Gabbay * Freescale messed up with P2020 as it has a non-standard 925dcaff04dSOded Gabbay * host control register 926dcaff04dSOded Gabbay */ 927dcaff04dSOded Gabbay host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL; 928dcaff04dSOded Gabbay } 929dcaff04dSOded Gabbay 93066b50a00SOded Gabbay /* call to generic mmc_of_parse to support additional capabilities */ 931f0991408SUlf Hansson ret = mmc_of_parse(host->mmc); 932f0991408SUlf Hansson if (ret) 933f0991408SUlf Hansson goto err; 934f0991408SUlf Hansson 935490104acSHaijun Zhang mmc_of_parse_voltage(np, &host->ocr_mask); 93666b50a00SOded Gabbay 93766b50a00SOded Gabbay ret = sdhci_add_host(host); 93866b50a00SOded Gabbay if (ret) 939f0991408SUlf Hansson goto err; 94066b50a00SOded Gabbay 941f0991408SUlf Hansson return 0; 942f0991408SUlf Hansson err: 943f0991408SUlf Hansson sdhci_pltfm_free(pdev); 94466b50a00SOded Gabbay return ret; 94538576af1SShawn Guo } 94638576af1SShawn Guo 94738576af1SShawn Guo static struct platform_driver sdhci_esdhc_driver = { 94838576af1SShawn Guo .driver = { 94938576af1SShawn Guo .name = "sdhci-esdhc", 95038576af1SShawn Guo .of_match_table = sdhci_esdhc_of_match, 9519e48b336SUlf Hansson .pm = &esdhc_of_dev_pm_ops, 95238576af1SShawn Guo }, 95338576af1SShawn Guo .probe = sdhci_esdhc_probe, 954caebcae9SKevin Hao .remove = sdhci_pltfm_unregister, 95538576af1SShawn Guo }; 95638576af1SShawn Guo 957d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_driver); 95838576af1SShawn Guo 95938576af1SShawn Guo MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC"); 96038576af1SShawn Guo MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, " 96138576af1SShawn Guo "Anton Vorontsov <avorontsov@ru.mvista.com>"); 96238576af1SShawn Guo MODULE_LICENSE("GPL v2"); 963