1 /* 2 * Atmel SDMMC controller driver. 3 * 4 * Copyright (C) 2015 Atmel, 5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 6 * 7 * This software is licensed under the terms of the GNU General Public 8 * License version 2, as published by the Free Software Foundation, and 9 * may be copied, distributed, and modified under those terms. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/slot-gpio.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/pm.h> 28 #include <linux/pm_runtime.h> 29 30 #include "sdhci-pltfm.h" 31 32 #define SDMMC_MC1R 0x204 33 #define SDMMC_MC1R_DDR BIT(3) 34 #define SDMMC_CACR 0x230 35 #define SDMMC_CACR_CAPWREN BIT(0) 36 #define SDMMC_CACR_KEY (0x46 << 8) 37 38 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */ 39 40 struct sdhci_at91_priv { 41 struct clk *hclock; 42 struct clk *gck; 43 struct clk *mainck; 44 }; 45 46 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock) 47 { 48 u16 clk; 49 unsigned long timeout; 50 51 host->mmc->actual_clock = 0; 52 53 /* 54 * There is no requirement to disable the internal clock before 55 * changing the SD clock configuration. Moreover, disabling the 56 * internal clock, changing the configuration and re-enabling the 57 * internal clock causes some bugs. It can prevent to get the internal 58 * clock stable flag ready and an unexpected switch to the base clock 59 * when using presets. 60 */ 61 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 62 clk &= SDHCI_CLOCK_INT_EN; 63 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 64 65 if (clock == 0) 66 return; 67 68 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 69 70 clk |= SDHCI_CLOCK_INT_EN; 71 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 72 73 /* Wait max 20 ms */ 74 timeout = 20; 75 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 76 & SDHCI_CLOCK_INT_STABLE)) { 77 if (timeout == 0) { 78 pr_err("%s: Internal clock never stabilised.\n", 79 mmc_hostname(host->mmc)); 80 return; 81 } 82 timeout--; 83 mdelay(1); 84 } 85 86 clk |= SDHCI_CLOCK_CARD_EN; 87 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 88 } 89 90 /* 91 * In this specific implementation of the SDHCI controller, the power register 92 * needs to have a valid voltage set even when the power supply is managed by 93 * an external regulator. 94 */ 95 static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode, 96 unsigned short vdd) 97 { 98 if (!IS_ERR(host->mmc->supply.vmmc)) { 99 struct mmc_host *mmc = host->mmc; 100 101 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 102 } 103 sdhci_set_power_noreg(host, mode, vdd); 104 } 105 106 void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) 107 { 108 if (timing == MMC_TIMING_MMC_DDR52) 109 sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R); 110 sdhci_set_uhs_signaling(host, timing); 111 } 112 113 static const struct sdhci_ops sdhci_at91_sama5d2_ops = { 114 .set_clock = sdhci_at91_set_clock, 115 .set_bus_width = sdhci_set_bus_width, 116 .reset = sdhci_reset, 117 .set_uhs_signaling = sdhci_at91_set_uhs_signaling, 118 .set_power = sdhci_at91_set_power, 119 }; 120 121 static const struct sdhci_pltfm_data soc_data_sama5d2 = { 122 .ops = &sdhci_at91_sama5d2_ops, 123 }; 124 125 static const struct of_device_id sdhci_at91_dt_match[] = { 126 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, 127 {} 128 }; 129 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match); 130 131 #ifdef CONFIG_PM 132 static int sdhci_at91_runtime_suspend(struct device *dev) 133 { 134 struct sdhci_host *host = dev_get_drvdata(dev); 135 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 136 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 137 int ret; 138 139 ret = sdhci_runtime_suspend_host(host); 140 141 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 142 mmc_retune_needed(host->mmc); 143 144 clk_disable_unprepare(priv->gck); 145 clk_disable_unprepare(priv->hclock); 146 clk_disable_unprepare(priv->mainck); 147 148 return ret; 149 } 150 151 static int sdhci_at91_runtime_resume(struct device *dev) 152 { 153 struct sdhci_host *host = dev_get_drvdata(dev); 154 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 155 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 156 int ret; 157 158 ret = clk_prepare_enable(priv->mainck); 159 if (ret) { 160 dev_err(dev, "can't enable mainck\n"); 161 return ret; 162 } 163 164 ret = clk_prepare_enable(priv->hclock); 165 if (ret) { 166 dev_err(dev, "can't enable hclock\n"); 167 return ret; 168 } 169 170 ret = clk_prepare_enable(priv->gck); 171 if (ret) { 172 dev_err(dev, "can't enable gck\n"); 173 return ret; 174 } 175 176 return sdhci_runtime_resume_host(host); 177 } 178 #endif /* CONFIG_PM */ 179 180 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = { 181 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 182 pm_runtime_force_resume) 183 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend, 184 sdhci_at91_runtime_resume, 185 NULL) 186 }; 187 188 static int sdhci_at91_probe(struct platform_device *pdev) 189 { 190 const struct of_device_id *match; 191 const struct sdhci_pltfm_data *soc_data; 192 struct sdhci_host *host; 193 struct sdhci_pltfm_host *pltfm_host; 194 struct sdhci_at91_priv *priv; 195 unsigned int caps0, caps1; 196 unsigned int clk_base, clk_mul; 197 unsigned int gck_rate, real_gck_rate; 198 int ret; 199 unsigned int preset_div; 200 201 match = of_match_device(sdhci_at91_dt_match, &pdev->dev); 202 if (!match) 203 return -EINVAL; 204 soc_data = match->data; 205 206 host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv)); 207 if (IS_ERR(host)) 208 return PTR_ERR(host); 209 210 pltfm_host = sdhci_priv(host); 211 priv = sdhci_pltfm_priv(pltfm_host); 212 213 priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); 214 if (IS_ERR(priv->mainck)) { 215 dev_err(&pdev->dev, "failed to get baseclk\n"); 216 return PTR_ERR(priv->mainck); 217 } 218 219 priv->hclock = devm_clk_get(&pdev->dev, "hclock"); 220 if (IS_ERR(priv->hclock)) { 221 dev_err(&pdev->dev, "failed to get hclock\n"); 222 return PTR_ERR(priv->hclock); 223 } 224 225 priv->gck = devm_clk_get(&pdev->dev, "multclk"); 226 if (IS_ERR(priv->gck)) { 227 dev_err(&pdev->dev, "failed to get multclk\n"); 228 return PTR_ERR(priv->gck); 229 } 230 231 /* 232 * The mult clock is provided by as a generated clock by the PMC 233 * controller. In order to set the rate of gck, we have to get the 234 * base clock rate and the clock mult from capabilities. 235 */ 236 clk_prepare_enable(priv->hclock); 237 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); 238 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); 239 clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 240 clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; 241 gck_rate = clk_base * 1000000 * (clk_mul + 1); 242 ret = clk_set_rate(priv->gck, gck_rate); 243 if (ret < 0) { 244 dev_err(&pdev->dev, "failed to set gck"); 245 goto hclock_disable_unprepare; 246 } 247 /* 248 * We need to check if we have the requested rate for gck because in 249 * some cases this rate could be not supported. If it happens, the rate 250 * is the closest one gck can provide. We have to update the value 251 * of clk mul. 252 */ 253 real_gck_rate = clk_get_rate(priv->gck); 254 if (real_gck_rate != gck_rate) { 255 clk_mul = real_gck_rate / (clk_base * 1000000) - 1; 256 caps1 &= (~SDHCI_CLOCK_MUL_MASK); 257 caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK); 258 /* Set capabilities in r/w mode. */ 259 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR); 260 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1); 261 /* Set capabilities in ro mode. */ 262 writel(0, host->ioaddr + SDMMC_CACR); 263 dev_info(&pdev->dev, "update clk mul to %u as gck rate is %u Hz\n", 264 clk_mul, real_gck_rate); 265 } 266 267 /* 268 * We have to set preset values because it depends on the clk_mul 269 * value. Moreover, SDR104 is supported in a degraded mode since the 270 * maximum sd clock value is 120 MHz instead of 208 MHz. For that 271 * reason, we need to use presets to support SDR104. 272 */ 273 preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1; 274 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 275 host->ioaddr + SDHCI_PRESET_FOR_SDR12); 276 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1; 277 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 278 host->ioaddr + SDHCI_PRESET_FOR_SDR25); 279 preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1; 280 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 281 host->ioaddr + SDHCI_PRESET_FOR_SDR50); 282 preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1; 283 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 284 host->ioaddr + SDHCI_PRESET_FOR_SDR104); 285 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1; 286 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 287 host->ioaddr + SDHCI_PRESET_FOR_DDR50); 288 289 clk_prepare_enable(priv->mainck); 290 clk_prepare_enable(priv->gck); 291 292 ret = mmc_of_parse(host->mmc); 293 if (ret) 294 goto clocks_disable_unprepare; 295 296 sdhci_get_of_property(pdev); 297 298 pm_runtime_get_noresume(&pdev->dev); 299 pm_runtime_set_active(&pdev->dev); 300 pm_runtime_enable(&pdev->dev); 301 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 302 pm_runtime_use_autosuspend(&pdev->dev); 303 304 ret = sdhci_add_host(host); 305 if (ret) 306 goto pm_runtime_disable; 307 308 /* 309 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes 310 * the assumption that all the clocks of the controller are disabled. 311 * It means we can't get irq from it when it is runtime suspended. 312 * For that reason, it is not planned to wake-up on a card detect irq 313 * from the controller. 314 * If we want to use runtime PM and to be able to wake-up on card 315 * insertion, we have to use a GPIO for the card detection or we can 316 * use polling. Be aware that using polling will resume/suspend the 317 * controller between each attempt. 318 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries 319 * to enable polling via device tree with broken-cd property. 320 */ 321 if (mmc_card_is_removable(host->mmc) && 322 mmc_gpio_get_cd(host->mmc) < 0) { 323 host->mmc->caps |= MMC_CAP_NEEDS_POLL; 324 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 325 } 326 327 pm_runtime_put_autosuspend(&pdev->dev); 328 329 return 0; 330 331 pm_runtime_disable: 332 pm_runtime_disable(&pdev->dev); 333 pm_runtime_set_suspended(&pdev->dev); 334 pm_runtime_put_noidle(&pdev->dev); 335 clocks_disable_unprepare: 336 clk_disable_unprepare(priv->gck); 337 clk_disable_unprepare(priv->mainck); 338 hclock_disable_unprepare: 339 clk_disable_unprepare(priv->hclock); 340 sdhci_pltfm_free(pdev); 341 return ret; 342 } 343 344 static int sdhci_at91_remove(struct platform_device *pdev) 345 { 346 struct sdhci_host *host = platform_get_drvdata(pdev); 347 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 348 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 349 struct clk *gck = priv->gck; 350 struct clk *hclock = priv->hclock; 351 struct clk *mainck = priv->mainck; 352 353 pm_runtime_get_sync(&pdev->dev); 354 pm_runtime_disable(&pdev->dev); 355 pm_runtime_put_noidle(&pdev->dev); 356 357 sdhci_pltfm_unregister(pdev); 358 359 clk_disable_unprepare(gck); 360 clk_disable_unprepare(hclock); 361 clk_disable_unprepare(mainck); 362 363 return 0; 364 } 365 366 static struct platform_driver sdhci_at91_driver = { 367 .driver = { 368 .name = "sdhci-at91", 369 .of_match_table = sdhci_at91_dt_match, 370 .pm = &sdhci_at91_dev_pm_ops, 371 }, 372 .probe = sdhci_at91_probe, 373 .remove = sdhci_at91_remove, 374 }; 375 376 module_platform_driver(sdhci_at91_driver); 377 378 MODULE_DESCRIPTION("SDHCI driver for at91"); 379 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); 380 MODULE_LICENSE("GPL v2"); 381