1 /* 2 * Atmel SDMMC controller driver. 3 * 4 * Copyright (C) 2015 Atmel, 5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 6 * 7 * This software is licensed under the terms of the GNU General Public 8 * License version 2, as published by the Free Software Foundation, and 9 * may be copied, distributed, and modified under those terms. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/slot-gpio.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/pm.h> 28 #include <linux/pm_runtime.h> 29 30 #include "sdhci-pltfm.h" 31 32 #define SDMMC_MC1R 0x204 33 #define SDMMC_MC1R_DDR BIT(3) 34 #define SDMMC_MC1R_FCD BIT(7) 35 #define SDMMC_CACR 0x230 36 #define SDMMC_CACR_CAPWREN BIT(0) 37 #define SDMMC_CACR_KEY (0x46 << 8) 38 39 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */ 40 41 struct sdhci_at91_priv { 42 struct clk *hclock; 43 struct clk *gck; 44 struct clk *mainck; 45 }; 46 47 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host) 48 { 49 u8 mc1r; 50 51 mc1r = readb(host->ioaddr + SDMMC_MC1R); 52 mc1r |= SDMMC_MC1R_FCD; 53 writeb(mc1r, host->ioaddr + SDMMC_MC1R); 54 } 55 56 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock) 57 { 58 u16 clk; 59 unsigned long timeout; 60 61 host->mmc->actual_clock = 0; 62 63 /* 64 * There is no requirement to disable the internal clock before 65 * changing the SD clock configuration. Moreover, disabling the 66 * internal clock, changing the configuration and re-enabling the 67 * internal clock causes some bugs. It can prevent to get the internal 68 * clock stable flag ready and an unexpected switch to the base clock 69 * when using presets. 70 */ 71 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 72 clk &= SDHCI_CLOCK_INT_EN; 73 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 74 75 if (clock == 0) 76 return; 77 78 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 79 80 clk |= SDHCI_CLOCK_INT_EN; 81 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 82 83 /* Wait max 20 ms */ 84 timeout = 20; 85 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 86 & SDHCI_CLOCK_INT_STABLE)) { 87 if (timeout == 0) { 88 pr_err("%s: Internal clock never stabilised.\n", 89 mmc_hostname(host->mmc)); 90 return; 91 } 92 timeout--; 93 mdelay(1); 94 } 95 96 clk |= SDHCI_CLOCK_CARD_EN; 97 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 98 } 99 100 /* 101 * In this specific implementation of the SDHCI controller, the power register 102 * needs to have a valid voltage set even when the power supply is managed by 103 * an external regulator. 104 */ 105 static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode, 106 unsigned short vdd) 107 { 108 if (!IS_ERR(host->mmc->supply.vmmc)) { 109 struct mmc_host *mmc = host->mmc; 110 111 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 112 } 113 sdhci_set_power_noreg(host, mode, vdd); 114 } 115 116 void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) 117 { 118 if (timing == MMC_TIMING_MMC_DDR52) 119 sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R); 120 sdhci_set_uhs_signaling(host, timing); 121 } 122 123 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask) 124 { 125 sdhci_reset(host, mask); 126 127 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 128 sdhci_at91_set_force_card_detect(host); 129 } 130 131 static const struct sdhci_ops sdhci_at91_sama5d2_ops = { 132 .set_clock = sdhci_at91_set_clock, 133 .set_bus_width = sdhci_set_bus_width, 134 .reset = sdhci_at91_reset, 135 .set_uhs_signaling = sdhci_at91_set_uhs_signaling, 136 .set_power = sdhci_at91_set_power, 137 }; 138 139 static const struct sdhci_pltfm_data soc_data_sama5d2 = { 140 .ops = &sdhci_at91_sama5d2_ops, 141 }; 142 143 static const struct of_device_id sdhci_at91_dt_match[] = { 144 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, 145 {} 146 }; 147 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match); 148 149 static int sdhci_at91_set_clks_presets(struct device *dev) 150 { 151 struct sdhci_host *host = dev_get_drvdata(dev); 152 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 153 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 154 int ret; 155 unsigned int caps0, caps1; 156 unsigned int clk_base, clk_mul; 157 unsigned int gck_rate, real_gck_rate; 158 unsigned int preset_div; 159 160 /* 161 * The mult clock is provided by as a generated clock by the PMC 162 * controller. In order to set the rate of gck, we have to get the 163 * base clock rate and the clock mult from capabilities. 164 */ 165 clk_prepare_enable(priv->hclock); 166 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); 167 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); 168 clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 169 clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; 170 gck_rate = clk_base * 1000000 * (clk_mul + 1); 171 ret = clk_set_rate(priv->gck, gck_rate); 172 if (ret < 0) { 173 dev_err(dev, "failed to set gck"); 174 clk_disable_unprepare(priv->hclock); 175 return ret; 176 } 177 /* 178 * We need to check if we have the requested rate for gck because in 179 * some cases this rate could be not supported. If it happens, the rate 180 * is the closest one gck can provide. We have to update the value 181 * of clk mul. 182 */ 183 real_gck_rate = clk_get_rate(priv->gck); 184 if (real_gck_rate != gck_rate) { 185 clk_mul = real_gck_rate / (clk_base * 1000000) - 1; 186 caps1 &= (~SDHCI_CLOCK_MUL_MASK); 187 caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & 188 SDHCI_CLOCK_MUL_MASK); 189 /* Set capabilities in r/w mode. */ 190 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, 191 host->ioaddr + SDMMC_CACR); 192 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1); 193 /* Set capabilities in ro mode. */ 194 writel(0, host->ioaddr + SDMMC_CACR); 195 dev_info(dev, "update clk mul to %u as gck rate is %u Hz\n", 196 clk_mul, real_gck_rate); 197 } 198 199 /* 200 * We have to set preset values because it depends on the clk_mul 201 * value. Moreover, SDR104 is supported in a degraded mode since the 202 * maximum sd clock value is 120 MHz instead of 208 MHz. For that 203 * reason, we need to use presets to support SDR104. 204 */ 205 preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1; 206 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 207 host->ioaddr + SDHCI_PRESET_FOR_SDR12); 208 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1; 209 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 210 host->ioaddr + SDHCI_PRESET_FOR_SDR25); 211 preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1; 212 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 213 host->ioaddr + SDHCI_PRESET_FOR_SDR50); 214 preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1; 215 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 216 host->ioaddr + SDHCI_PRESET_FOR_SDR104); 217 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1; 218 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 219 host->ioaddr + SDHCI_PRESET_FOR_DDR50); 220 221 clk_prepare_enable(priv->mainck); 222 clk_prepare_enable(priv->gck); 223 224 return 0; 225 } 226 227 #ifdef CONFIG_PM 228 static int sdhci_at91_runtime_suspend(struct device *dev) 229 { 230 struct sdhci_host *host = dev_get_drvdata(dev); 231 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 232 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 233 int ret; 234 235 ret = sdhci_runtime_suspend_host(host); 236 237 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 238 mmc_retune_needed(host->mmc); 239 240 clk_disable_unprepare(priv->gck); 241 clk_disable_unprepare(priv->hclock); 242 clk_disable_unprepare(priv->mainck); 243 244 return ret; 245 } 246 247 static int sdhci_at91_runtime_resume(struct device *dev) 248 { 249 struct sdhci_host *host = dev_get_drvdata(dev); 250 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 251 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 252 int ret; 253 254 ret = clk_prepare_enable(priv->mainck); 255 if (ret) { 256 dev_err(dev, "can't enable mainck\n"); 257 return ret; 258 } 259 260 ret = clk_prepare_enable(priv->hclock); 261 if (ret) { 262 dev_err(dev, "can't enable hclock\n"); 263 return ret; 264 } 265 266 ret = clk_prepare_enable(priv->gck); 267 if (ret) { 268 dev_err(dev, "can't enable gck\n"); 269 return ret; 270 } 271 272 return sdhci_runtime_resume_host(host); 273 } 274 #endif /* CONFIG_PM */ 275 276 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = { 277 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 278 pm_runtime_force_resume) 279 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend, 280 sdhci_at91_runtime_resume, 281 NULL) 282 }; 283 284 static int sdhci_at91_probe(struct platform_device *pdev) 285 { 286 const struct of_device_id *match; 287 const struct sdhci_pltfm_data *soc_data; 288 struct sdhci_host *host; 289 struct sdhci_pltfm_host *pltfm_host; 290 struct sdhci_at91_priv *priv; 291 int ret; 292 293 match = of_match_device(sdhci_at91_dt_match, &pdev->dev); 294 if (!match) 295 return -EINVAL; 296 soc_data = match->data; 297 298 host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv)); 299 if (IS_ERR(host)) 300 return PTR_ERR(host); 301 302 pltfm_host = sdhci_priv(host); 303 priv = sdhci_pltfm_priv(pltfm_host); 304 305 priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); 306 if (IS_ERR(priv->mainck)) { 307 dev_err(&pdev->dev, "failed to get baseclk\n"); 308 return PTR_ERR(priv->mainck); 309 } 310 311 priv->hclock = devm_clk_get(&pdev->dev, "hclock"); 312 if (IS_ERR(priv->hclock)) { 313 dev_err(&pdev->dev, "failed to get hclock\n"); 314 return PTR_ERR(priv->hclock); 315 } 316 317 priv->gck = devm_clk_get(&pdev->dev, "multclk"); 318 if (IS_ERR(priv->gck)) { 319 dev_err(&pdev->dev, "failed to get multclk\n"); 320 return PTR_ERR(priv->gck); 321 } 322 323 ret = sdhci_at91_set_clks_presets(&pdev->dev); 324 if (ret) 325 goto sdhci_pltfm_free; 326 327 ret = mmc_of_parse(host->mmc); 328 if (ret) 329 goto clocks_disable_unprepare; 330 331 sdhci_get_of_property(pdev); 332 333 pm_runtime_get_noresume(&pdev->dev); 334 pm_runtime_set_active(&pdev->dev); 335 pm_runtime_enable(&pdev->dev); 336 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 337 pm_runtime_use_autosuspend(&pdev->dev); 338 339 ret = sdhci_add_host(host); 340 if (ret) 341 goto pm_runtime_disable; 342 343 /* 344 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes 345 * the assumption that all the clocks of the controller are disabled. 346 * It means we can't get irq from it when it is runtime suspended. 347 * For that reason, it is not planned to wake-up on a card detect irq 348 * from the controller. 349 * If we want to use runtime PM and to be able to wake-up on card 350 * insertion, we have to use a GPIO for the card detection or we can 351 * use polling. Be aware that using polling will resume/suspend the 352 * controller between each attempt. 353 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries 354 * to enable polling via device tree with broken-cd property. 355 */ 356 if (mmc_card_is_removable(host->mmc) && 357 mmc_gpio_get_cd(host->mmc) < 0) { 358 host->mmc->caps |= MMC_CAP_NEEDS_POLL; 359 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 360 } 361 362 /* 363 * If the device attached to the MMC bus is not removable, it is safer 364 * to set the Force Card Detect bit. People often don't connect the 365 * card detect signal and use this pin for another purpose. If the card 366 * detect pin is not muxed to SDHCI controller, a default value is 367 * used. This value can be different from a SoC revision to another 368 * one. Problems come when this default value is not card present. To 369 * avoid this case, if the device is non removable then the card 370 * detection procedure using the SDMCC_CD signal is bypassed. 371 * This bit is reset when a software reset for all command is performed 372 * so we need to implement our own reset function to set back this bit. 373 */ 374 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 375 sdhci_at91_set_force_card_detect(host); 376 377 pm_runtime_put_autosuspend(&pdev->dev); 378 379 return 0; 380 381 pm_runtime_disable: 382 pm_runtime_disable(&pdev->dev); 383 pm_runtime_set_suspended(&pdev->dev); 384 pm_runtime_put_noidle(&pdev->dev); 385 clocks_disable_unprepare: 386 clk_disable_unprepare(priv->gck); 387 clk_disable_unprepare(priv->mainck); 388 clk_disable_unprepare(priv->hclock); 389 sdhci_pltfm_free: 390 sdhci_pltfm_free(pdev); 391 return ret; 392 } 393 394 static int sdhci_at91_remove(struct platform_device *pdev) 395 { 396 struct sdhci_host *host = platform_get_drvdata(pdev); 397 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 398 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 399 struct clk *gck = priv->gck; 400 struct clk *hclock = priv->hclock; 401 struct clk *mainck = priv->mainck; 402 403 pm_runtime_get_sync(&pdev->dev); 404 pm_runtime_disable(&pdev->dev); 405 pm_runtime_put_noidle(&pdev->dev); 406 407 sdhci_pltfm_unregister(pdev); 408 409 clk_disable_unprepare(gck); 410 clk_disable_unprepare(hclock); 411 clk_disable_unprepare(mainck); 412 413 return 0; 414 } 415 416 static struct platform_driver sdhci_at91_driver = { 417 .driver = { 418 .name = "sdhci-at91", 419 .of_match_table = sdhci_at91_dt_match, 420 .pm = &sdhci_at91_dev_pm_ops, 421 }, 422 .probe = sdhci_at91_probe, 423 .remove = sdhci_at91_remove, 424 }; 425 426 module_platform_driver(sdhci_at91_driver); 427 428 MODULE_DESCRIPTION("SDHCI driver for at91"); 429 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); 430 MODULE_LICENSE("GPL v2"); 431