1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Atmel SDMMC controller driver. 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <linux/kernel.h> 16 #include <linux/mmc/host.h> 17 #include <linux/mmc/slot-gpio.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/pm.h> 22 #include <linux/pm_runtime.h> 23 24 #include "sdhci-pltfm.h" 25 26 #define SDMMC_MC1R 0x204 27 #define SDMMC_MC1R_DDR BIT(3) 28 #define SDMMC_MC1R_FCD BIT(7) 29 #define SDMMC_CACR 0x230 30 #define SDMMC_CACR_CAPWREN BIT(0) 31 #define SDMMC_CACR_KEY (0x46 << 8) 32 #define SDMMC_CALCR 0x240 33 #define SDMMC_CALCR_EN BIT(0) 34 #define SDMMC_CALCR_ALWYSON BIT(4) 35 36 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */ 37 38 struct sdhci_at91_soc_data { 39 const struct sdhci_pltfm_data *pdata; 40 bool baseclk_is_generated_internally; 41 unsigned int divider_for_baseclk; 42 }; 43 44 struct sdhci_at91_priv { 45 const struct sdhci_at91_soc_data *soc_data; 46 struct clk *hclock; 47 struct clk *gck; 48 struct clk *mainck; 49 bool restore_needed; 50 bool cal_always_on; 51 }; 52 53 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host) 54 { 55 u8 mc1r; 56 57 mc1r = readb(host->ioaddr + SDMMC_MC1R); 58 mc1r |= SDMMC_MC1R_FCD; 59 writeb(mc1r, host->ioaddr + SDMMC_MC1R); 60 } 61 62 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock) 63 { 64 u16 clk; 65 unsigned long timeout; 66 67 host->mmc->actual_clock = 0; 68 69 /* 70 * There is no requirement to disable the internal clock before 71 * changing the SD clock configuration. Moreover, disabling the 72 * internal clock, changing the configuration and re-enabling the 73 * internal clock causes some bugs. It can prevent to get the internal 74 * clock stable flag ready and an unexpected switch to the base clock 75 * when using presets. 76 */ 77 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 78 clk &= SDHCI_CLOCK_INT_EN; 79 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 80 81 if (clock == 0) 82 return; 83 84 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 85 86 clk |= SDHCI_CLOCK_INT_EN; 87 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 88 89 /* Wait max 20 ms */ 90 timeout = 20; 91 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 92 & SDHCI_CLOCK_INT_STABLE)) { 93 if (timeout == 0) { 94 pr_err("%s: Internal clock never stabilised.\n", 95 mmc_hostname(host->mmc)); 96 return; 97 } 98 timeout--; 99 mdelay(1); 100 } 101 102 clk |= SDHCI_CLOCK_CARD_EN; 103 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 104 } 105 106 static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, 107 unsigned int timing) 108 { 109 if (timing == MMC_TIMING_MMC_DDR52) 110 sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R); 111 sdhci_set_uhs_signaling(host, timing); 112 } 113 114 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask) 115 { 116 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 117 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 118 unsigned int tmp; 119 120 sdhci_reset(host, mask); 121 122 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) 123 || mmc_gpio_get_cd(host->mmc) >= 0) 124 sdhci_at91_set_force_card_detect(host); 125 126 if (priv->cal_always_on && (mask & SDHCI_RESET_ALL)) { 127 u32 calcr = sdhci_readl(host, SDMMC_CALCR); 128 129 sdhci_writel(host, calcr | SDMMC_CALCR_ALWYSON | SDMMC_CALCR_EN, 130 SDMMC_CALCR); 131 132 if (read_poll_timeout(sdhci_readl, tmp, !(tmp & SDMMC_CALCR_EN), 133 10, 20000, false, host, SDMMC_CALCR)) 134 dev_err(mmc_dev(host->mmc), "Failed to calibrate\n"); 135 } 136 } 137 138 static const struct sdhci_ops sdhci_at91_sama5d2_ops = { 139 .set_clock = sdhci_at91_set_clock, 140 .set_bus_width = sdhci_set_bus_width, 141 .reset = sdhci_at91_reset, 142 .set_uhs_signaling = sdhci_at91_set_uhs_signaling, 143 .set_power = sdhci_set_power_and_bus_voltage, 144 }; 145 146 static const struct sdhci_pltfm_data sdhci_sama5d2_pdata = { 147 .ops = &sdhci_at91_sama5d2_ops, 148 }; 149 150 static const struct sdhci_at91_soc_data soc_data_sama5d2 = { 151 .pdata = &sdhci_sama5d2_pdata, 152 .baseclk_is_generated_internally = false, 153 }; 154 155 static const struct sdhci_at91_soc_data soc_data_sam9x60 = { 156 .pdata = &sdhci_sama5d2_pdata, 157 .baseclk_is_generated_internally = true, 158 .divider_for_baseclk = 2, 159 }; 160 161 static const struct of_device_id sdhci_at91_dt_match[] = { 162 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, 163 { .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 }, 164 {} 165 }; 166 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match); 167 168 static int sdhci_at91_set_clks_presets(struct device *dev) 169 { 170 struct sdhci_host *host = dev_get_drvdata(dev); 171 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 172 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 173 unsigned int caps0, caps1; 174 unsigned int clk_base, clk_mul; 175 unsigned int gck_rate, clk_base_rate; 176 unsigned int preset_div; 177 178 clk_prepare_enable(priv->hclock); 179 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); 180 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); 181 182 gck_rate = clk_get_rate(priv->gck); 183 if (priv->soc_data->baseclk_is_generated_internally) 184 clk_base_rate = gck_rate / priv->soc_data->divider_for_baseclk; 185 else 186 clk_base_rate = clk_get_rate(priv->mainck); 187 188 clk_base = clk_base_rate / 1000000; 189 clk_mul = gck_rate / clk_base_rate - 1; 190 191 caps0 &= ~SDHCI_CLOCK_V3_BASE_MASK; 192 caps0 |= FIELD_PREP(SDHCI_CLOCK_V3_BASE_MASK, clk_base); 193 caps1 &= ~SDHCI_CLOCK_MUL_MASK; 194 caps1 |= FIELD_PREP(SDHCI_CLOCK_MUL_MASK, clk_mul); 195 /* Set capabilities in r/w mode. */ 196 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR); 197 writel(caps0, host->ioaddr + SDHCI_CAPABILITIES); 198 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1); 199 /* Set capabilities in ro mode. */ 200 writel(0, host->ioaddr + SDMMC_CACR); 201 202 dev_dbg(dev, "update clk mul to %u as gck rate is %u Hz and clk base is %u Hz\n", 203 clk_mul, gck_rate, clk_base_rate); 204 205 /* 206 * We have to set preset values because it depends on the clk_mul 207 * value. Moreover, SDR104 is supported in a degraded mode since the 208 * maximum sd clock value is 120 MHz instead of 208 MHz. For that 209 * reason, we need to use presets to support SDR104. 210 */ 211 preset_div = DIV_ROUND_UP(gck_rate, 24000000) - 1; 212 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 213 host->ioaddr + SDHCI_PRESET_FOR_SDR12); 214 preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; 215 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 216 host->ioaddr + SDHCI_PRESET_FOR_SDR25); 217 preset_div = DIV_ROUND_UP(gck_rate, 100000000) - 1; 218 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 219 host->ioaddr + SDHCI_PRESET_FOR_SDR50); 220 preset_div = DIV_ROUND_UP(gck_rate, 120000000) - 1; 221 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 222 host->ioaddr + SDHCI_PRESET_FOR_SDR104); 223 preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; 224 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 225 host->ioaddr + SDHCI_PRESET_FOR_DDR50); 226 227 clk_prepare_enable(priv->mainck); 228 clk_prepare_enable(priv->gck); 229 230 return 0; 231 } 232 233 #ifdef CONFIG_PM_SLEEP 234 static int sdhci_at91_suspend(struct device *dev) 235 { 236 struct sdhci_host *host = dev_get_drvdata(dev); 237 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 238 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 239 int ret; 240 241 ret = pm_runtime_force_suspend(dev); 242 243 priv->restore_needed = true; 244 245 return ret; 246 } 247 #endif /* CONFIG_PM_SLEEP */ 248 249 #ifdef CONFIG_PM 250 static int sdhci_at91_runtime_suspend(struct device *dev) 251 { 252 struct sdhci_host *host = dev_get_drvdata(dev); 253 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 254 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 255 int ret; 256 257 ret = sdhci_runtime_suspend_host(host); 258 259 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 260 mmc_retune_needed(host->mmc); 261 262 clk_disable_unprepare(priv->gck); 263 clk_disable_unprepare(priv->hclock); 264 clk_disable_unprepare(priv->mainck); 265 266 return ret; 267 } 268 269 static int sdhci_at91_runtime_resume(struct device *dev) 270 { 271 struct sdhci_host *host = dev_get_drvdata(dev); 272 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 273 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 274 int ret; 275 276 if (priv->restore_needed) { 277 ret = sdhci_at91_set_clks_presets(dev); 278 if (ret) 279 return ret; 280 281 priv->restore_needed = false; 282 goto out; 283 } 284 285 ret = clk_prepare_enable(priv->mainck); 286 if (ret) { 287 dev_err(dev, "can't enable mainck\n"); 288 return ret; 289 } 290 291 ret = clk_prepare_enable(priv->hclock); 292 if (ret) { 293 dev_err(dev, "can't enable hclock\n"); 294 return ret; 295 } 296 297 ret = clk_prepare_enable(priv->gck); 298 if (ret) { 299 dev_err(dev, "can't enable gck\n"); 300 return ret; 301 } 302 303 out: 304 return sdhci_runtime_resume_host(host, 0); 305 } 306 #endif /* CONFIG_PM */ 307 308 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = { 309 SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume) 310 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend, 311 sdhci_at91_runtime_resume, 312 NULL) 313 }; 314 315 static int sdhci_at91_probe(struct platform_device *pdev) 316 { 317 const struct of_device_id *match; 318 const struct sdhci_at91_soc_data *soc_data; 319 struct sdhci_host *host; 320 struct sdhci_pltfm_host *pltfm_host; 321 struct sdhci_at91_priv *priv; 322 int ret; 323 324 match = of_match_device(sdhci_at91_dt_match, &pdev->dev); 325 if (!match) 326 return -EINVAL; 327 soc_data = match->data; 328 329 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*priv)); 330 if (IS_ERR(host)) 331 return PTR_ERR(host); 332 333 pltfm_host = sdhci_priv(host); 334 priv = sdhci_pltfm_priv(pltfm_host); 335 priv->soc_data = soc_data; 336 337 priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); 338 if (IS_ERR(priv->mainck)) { 339 if (soc_data->baseclk_is_generated_internally) { 340 priv->mainck = NULL; 341 } else { 342 dev_err(&pdev->dev, "failed to get baseclk\n"); 343 ret = PTR_ERR(priv->mainck); 344 goto sdhci_pltfm_free; 345 } 346 } 347 348 priv->hclock = devm_clk_get(&pdev->dev, "hclock"); 349 if (IS_ERR(priv->hclock)) { 350 dev_err(&pdev->dev, "failed to get hclock\n"); 351 ret = PTR_ERR(priv->hclock); 352 goto sdhci_pltfm_free; 353 } 354 355 priv->gck = devm_clk_get(&pdev->dev, "multclk"); 356 if (IS_ERR(priv->gck)) { 357 dev_err(&pdev->dev, "failed to get multclk\n"); 358 ret = PTR_ERR(priv->gck); 359 goto sdhci_pltfm_free; 360 } 361 362 ret = sdhci_at91_set_clks_presets(&pdev->dev); 363 if (ret) 364 goto sdhci_pltfm_free; 365 366 priv->restore_needed = false; 367 368 /* 369 * if SDCAL pin is wrongly connected, we must enable 370 * the analog calibration cell permanently. 371 */ 372 priv->cal_always_on = 373 device_property_read_bool(&pdev->dev, 374 "microchip,sdcal-inverted"); 375 376 ret = mmc_of_parse(host->mmc); 377 if (ret) 378 goto clocks_disable_unprepare; 379 380 sdhci_get_of_property(pdev); 381 382 pm_runtime_get_noresume(&pdev->dev); 383 pm_runtime_set_active(&pdev->dev); 384 pm_runtime_enable(&pdev->dev); 385 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 386 pm_runtime_use_autosuspend(&pdev->dev); 387 388 /* HS200 is broken at this moment */ 389 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 390 391 ret = sdhci_add_host(host); 392 if (ret) 393 goto pm_runtime_disable; 394 395 /* 396 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes 397 * the assumption that all the clocks of the controller are disabled. 398 * It means we can't get irq from it when it is runtime suspended. 399 * For that reason, it is not planned to wake-up on a card detect irq 400 * from the controller. 401 * If we want to use runtime PM and to be able to wake-up on card 402 * insertion, we have to use a GPIO for the card detection or we can 403 * use polling. Be aware that using polling will resume/suspend the 404 * controller between each attempt. 405 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries 406 * to enable polling via device tree with broken-cd property. 407 */ 408 if (mmc_card_is_removable(host->mmc) && 409 mmc_gpio_get_cd(host->mmc) < 0) { 410 host->mmc->caps |= MMC_CAP_NEEDS_POLL; 411 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 412 } 413 414 /* 415 * If the device attached to the MMC bus is not removable, it is safer 416 * to set the Force Card Detect bit. People often don't connect the 417 * card detect signal and use this pin for another purpose. If the card 418 * detect pin is not muxed to SDHCI controller, a default value is 419 * used. This value can be different from a SoC revision to another 420 * one. Problems come when this default value is not card present. To 421 * avoid this case, if the device is non removable then the card 422 * detection procedure using the SDMCC_CD signal is bypassed. 423 * This bit is reset when a software reset for all command is performed 424 * so we need to implement our own reset function to set back this bit. 425 * 426 * WA: SAMA5D2 doesn't drive CMD if using CD GPIO line. 427 */ 428 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) 429 || mmc_gpio_get_cd(host->mmc) >= 0) 430 sdhci_at91_set_force_card_detect(host); 431 432 pm_runtime_put_autosuspend(&pdev->dev); 433 434 return 0; 435 436 pm_runtime_disable: 437 pm_runtime_disable(&pdev->dev); 438 pm_runtime_set_suspended(&pdev->dev); 439 pm_runtime_put_noidle(&pdev->dev); 440 clocks_disable_unprepare: 441 clk_disable_unprepare(priv->gck); 442 clk_disable_unprepare(priv->mainck); 443 clk_disable_unprepare(priv->hclock); 444 sdhci_pltfm_free: 445 sdhci_pltfm_free(pdev); 446 return ret; 447 } 448 449 static int sdhci_at91_remove(struct platform_device *pdev) 450 { 451 struct sdhci_host *host = platform_get_drvdata(pdev); 452 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 453 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 454 struct clk *gck = priv->gck; 455 struct clk *hclock = priv->hclock; 456 struct clk *mainck = priv->mainck; 457 458 pm_runtime_get_sync(&pdev->dev); 459 pm_runtime_disable(&pdev->dev); 460 pm_runtime_put_noidle(&pdev->dev); 461 462 sdhci_pltfm_unregister(pdev); 463 464 clk_disable_unprepare(gck); 465 clk_disable_unprepare(hclock); 466 clk_disable_unprepare(mainck); 467 468 return 0; 469 } 470 471 static struct platform_driver sdhci_at91_driver = { 472 .driver = { 473 .name = "sdhci-at91", 474 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 475 .of_match_table = sdhci_at91_dt_match, 476 .pm = &sdhci_at91_dev_pm_ops, 477 }, 478 .probe = sdhci_at91_probe, 479 .remove = sdhci_at91_remove, 480 }; 481 482 module_platform_driver(sdhci_at91_driver); 483 484 MODULE_DESCRIPTION("SDHCI driver for at91"); 485 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); 486 MODULE_LICENSE("GPL v2"); 487