1 /* 2 * Atmel SDMMC controller driver. 3 * 4 * Copyright (C) 2015 Atmel, 5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 6 * 7 * This software is licensed under the terms of the GNU General Public 8 * License version 2, as published by the Free Software Foundation, and 9 * may be copied, distributed, and modified under those terms. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/err.h> 19 #include <linux/io.h> 20 #include <linux/mmc/host.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/pm.h> 25 #include <linux/pm_runtime.h> 26 27 #include "sdhci-pltfm.h" 28 29 #define SDMMC_CACR 0x230 30 #define SDMMC_CACR_CAPWREN BIT(0) 31 #define SDMMC_CACR_KEY (0x46 << 8) 32 33 struct sdhci_at91_priv { 34 struct clk *hclock; 35 struct clk *gck; 36 struct clk *mainck; 37 }; 38 39 static const struct sdhci_ops sdhci_at91_sama5d2_ops = { 40 .set_clock = sdhci_set_clock, 41 .set_bus_width = sdhci_set_bus_width, 42 .reset = sdhci_reset, 43 .set_uhs_signaling = sdhci_set_uhs_signaling, 44 }; 45 46 static const struct sdhci_pltfm_data soc_data_sama5d2 = { 47 .ops = &sdhci_at91_sama5d2_ops, 48 .quirks2 = SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST, 49 }; 50 51 static const struct of_device_id sdhci_at91_dt_match[] = { 52 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, 53 {} 54 }; 55 56 #ifdef CONFIG_PM 57 static int sdhci_at91_runtime_suspend(struct device *dev) 58 { 59 struct sdhci_host *host = dev_get_drvdata(dev); 60 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 61 struct sdhci_at91_priv *priv = pltfm_host->priv; 62 int ret; 63 64 ret = sdhci_runtime_suspend_host(host); 65 66 clk_disable_unprepare(priv->gck); 67 clk_disable_unprepare(priv->hclock); 68 clk_disable_unprepare(priv->mainck); 69 70 return ret; 71 } 72 73 static int sdhci_at91_runtime_resume(struct device *dev) 74 { 75 struct sdhci_host *host = dev_get_drvdata(dev); 76 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 77 struct sdhci_at91_priv *priv = pltfm_host->priv; 78 int ret; 79 80 ret = clk_prepare_enable(priv->mainck); 81 if (ret) { 82 dev_err(dev, "can't enable mainck\n"); 83 return ret; 84 } 85 86 ret = clk_prepare_enable(priv->hclock); 87 if (ret) { 88 dev_err(dev, "can't enable hclock\n"); 89 return ret; 90 } 91 92 ret = clk_prepare_enable(priv->gck); 93 if (ret) { 94 dev_err(dev, "can't enable gck\n"); 95 return ret; 96 } 97 98 return sdhci_runtime_resume_host(host); 99 } 100 #endif /* CONFIG_PM */ 101 102 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = { 103 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 104 pm_runtime_force_resume) 105 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend, 106 sdhci_at91_runtime_resume, 107 NULL) 108 }; 109 110 static int sdhci_at91_probe(struct platform_device *pdev) 111 { 112 const struct of_device_id *match; 113 const struct sdhci_pltfm_data *soc_data; 114 struct sdhci_host *host; 115 struct sdhci_pltfm_host *pltfm_host; 116 struct sdhci_at91_priv *priv; 117 unsigned int caps0, caps1; 118 unsigned int clk_base, clk_mul; 119 unsigned int gck_rate, real_gck_rate; 120 int ret; 121 122 match = of_match_device(sdhci_at91_dt_match, &pdev->dev); 123 if (!match) 124 return -EINVAL; 125 soc_data = match->data; 126 127 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 128 if (!priv) { 129 dev_err(&pdev->dev, "unable to allocate private data\n"); 130 return -ENOMEM; 131 } 132 133 priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); 134 if (IS_ERR(priv->mainck)) { 135 dev_err(&pdev->dev, "failed to get baseclk\n"); 136 return PTR_ERR(priv->mainck); 137 } 138 139 priv->hclock = devm_clk_get(&pdev->dev, "hclock"); 140 if (IS_ERR(priv->hclock)) { 141 dev_err(&pdev->dev, "failed to get hclock\n"); 142 return PTR_ERR(priv->hclock); 143 } 144 145 priv->gck = devm_clk_get(&pdev->dev, "multclk"); 146 if (IS_ERR(priv->gck)) { 147 dev_err(&pdev->dev, "failed to get multclk\n"); 148 return PTR_ERR(priv->gck); 149 } 150 151 host = sdhci_pltfm_init(pdev, soc_data, 0); 152 if (IS_ERR(host)) 153 return PTR_ERR(host); 154 155 /* 156 * The mult clock is provided by as a generated clock by the PMC 157 * controller. In order to set the rate of gck, we have to get the 158 * base clock rate and the clock mult from capabilities. 159 */ 160 clk_prepare_enable(priv->hclock); 161 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); 162 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); 163 clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 164 clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; 165 gck_rate = clk_base * 1000000 * (clk_mul + 1); 166 ret = clk_set_rate(priv->gck, gck_rate); 167 if (ret < 0) { 168 dev_err(&pdev->dev, "failed to set gck"); 169 goto hclock_disable_unprepare; 170 } 171 /* 172 * We need to check if we have the requested rate for gck because in 173 * some cases this rate could be not supported. If it happens, the rate 174 * is the closest one gck can provide. We have to update the value 175 * of clk mul. 176 */ 177 real_gck_rate = clk_get_rate(priv->gck); 178 if (real_gck_rate != gck_rate) { 179 clk_mul = real_gck_rate / (clk_base * 1000000) - 1; 180 caps1 &= (~SDHCI_CLOCK_MUL_MASK); 181 caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK); 182 /* Set capabilities in r/w mode. */ 183 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR); 184 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1); 185 /* Set capabilities in ro mode. */ 186 writel(0, host->ioaddr + SDMMC_CACR); 187 dev_info(&pdev->dev, "update clk mul to %u as gck rate is %u Hz\n", 188 clk_mul, real_gck_rate); 189 } 190 191 clk_prepare_enable(priv->mainck); 192 clk_prepare_enable(priv->gck); 193 194 pltfm_host = sdhci_priv(host); 195 pltfm_host->priv = priv; 196 197 ret = mmc_of_parse(host->mmc); 198 if (ret) 199 goto clocks_disable_unprepare; 200 201 sdhci_get_of_property(pdev); 202 203 pm_runtime_get_noresume(&pdev->dev); 204 pm_runtime_set_active(&pdev->dev); 205 pm_runtime_enable(&pdev->dev); 206 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 207 pm_runtime_use_autosuspend(&pdev->dev); 208 209 ret = sdhci_add_host(host); 210 if (ret) 211 goto pm_runtime_disable; 212 213 pm_runtime_put_autosuspend(&pdev->dev); 214 215 return 0; 216 217 pm_runtime_disable: 218 pm_runtime_disable(&pdev->dev); 219 pm_runtime_set_suspended(&pdev->dev); 220 clocks_disable_unprepare: 221 clk_disable_unprepare(priv->gck); 222 clk_disable_unprepare(priv->mainck); 223 hclock_disable_unprepare: 224 clk_disable_unprepare(priv->hclock); 225 sdhci_pltfm_free(pdev); 226 return ret; 227 } 228 229 static int sdhci_at91_remove(struct platform_device *pdev) 230 { 231 struct sdhci_host *host = platform_get_drvdata(pdev); 232 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 233 struct sdhci_at91_priv *priv = pltfm_host->priv; 234 235 pm_runtime_get_sync(&pdev->dev); 236 pm_runtime_disable(&pdev->dev); 237 pm_runtime_put_noidle(&pdev->dev); 238 239 sdhci_pltfm_unregister(pdev); 240 241 clk_disable_unprepare(priv->gck); 242 clk_disable_unprepare(priv->hclock); 243 clk_disable_unprepare(priv->mainck); 244 245 return 0; 246 } 247 248 static struct platform_driver sdhci_at91_driver = { 249 .driver = { 250 .name = "sdhci-at91", 251 .of_match_table = sdhci_at91_dt_match, 252 .pm = &sdhci_at91_dev_pm_ops, 253 }, 254 .probe = sdhci_at91_probe, 255 .remove = sdhci_at91_remove, 256 }; 257 258 module_platform_driver(sdhci_at91_driver); 259 260 MODULE_DESCRIPTION("SDHCI driver for at91"); 261 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); 262 MODULE_LICENSE("GPL v2"); 263