1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Atmel SDMMC controller driver. 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/mmc/host.h> 15 #include <linux/mmc/slot-gpio.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_device.h> 19 #include <linux/pm.h> 20 #include <linux/pm_runtime.h> 21 22 #include "sdhci-pltfm.h" 23 24 #define SDMMC_MC1R 0x204 25 #define SDMMC_MC1R_DDR BIT(3) 26 #define SDMMC_MC1R_FCD BIT(7) 27 #define SDMMC_CACR 0x230 28 #define SDMMC_CACR_CAPWREN BIT(0) 29 #define SDMMC_CACR_KEY (0x46 << 8) 30 #define SDMMC_CALCR 0x240 31 #define SDMMC_CALCR_EN BIT(0) 32 #define SDMMC_CALCR_ALWYSON BIT(4) 33 34 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */ 35 36 struct sdhci_at91_soc_data { 37 const struct sdhci_pltfm_data *pdata; 38 bool baseclk_is_generated_internally; 39 unsigned int divider_for_baseclk; 40 }; 41 42 struct sdhci_at91_priv { 43 const struct sdhci_at91_soc_data *soc_data; 44 struct clk *hclock; 45 struct clk *gck; 46 struct clk *mainck; 47 bool restore_needed; 48 bool cal_always_on; 49 }; 50 51 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host) 52 { 53 u8 mc1r; 54 55 mc1r = readb(host->ioaddr + SDMMC_MC1R); 56 mc1r |= SDMMC_MC1R_FCD; 57 writeb(mc1r, host->ioaddr + SDMMC_MC1R); 58 } 59 60 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock) 61 { 62 u16 clk; 63 unsigned long timeout; 64 65 host->mmc->actual_clock = 0; 66 67 /* 68 * There is no requirement to disable the internal clock before 69 * changing the SD clock configuration. Moreover, disabling the 70 * internal clock, changing the configuration and re-enabling the 71 * internal clock causes some bugs. It can prevent to get the internal 72 * clock stable flag ready and an unexpected switch to the base clock 73 * when using presets. 74 */ 75 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 76 clk &= SDHCI_CLOCK_INT_EN; 77 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 78 79 if (clock == 0) 80 return; 81 82 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 83 84 clk |= SDHCI_CLOCK_INT_EN; 85 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 86 87 /* Wait max 20 ms */ 88 timeout = 20; 89 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 90 & SDHCI_CLOCK_INT_STABLE)) { 91 if (timeout == 0) { 92 pr_err("%s: Internal clock never stabilised.\n", 93 mmc_hostname(host->mmc)); 94 return; 95 } 96 timeout--; 97 mdelay(1); 98 } 99 100 clk |= SDHCI_CLOCK_CARD_EN; 101 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 102 } 103 104 static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, 105 unsigned int timing) 106 { 107 if (timing == MMC_TIMING_MMC_DDR52) 108 sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R); 109 sdhci_set_uhs_signaling(host, timing); 110 } 111 112 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask) 113 { 114 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 115 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 116 117 sdhci_reset(host, mask); 118 119 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) 120 || mmc_gpio_get_cd(host->mmc) >= 0) 121 sdhci_at91_set_force_card_detect(host); 122 123 if (priv->cal_always_on && (mask & SDHCI_RESET_ALL)) 124 sdhci_writel(host, SDMMC_CALCR_ALWYSON | SDMMC_CALCR_EN, 125 SDMMC_CALCR); 126 } 127 128 static const struct sdhci_ops sdhci_at91_sama5d2_ops = { 129 .set_clock = sdhci_at91_set_clock, 130 .set_bus_width = sdhci_set_bus_width, 131 .reset = sdhci_at91_reset, 132 .set_uhs_signaling = sdhci_at91_set_uhs_signaling, 133 .set_power = sdhci_set_power_and_bus_voltage, 134 }; 135 136 static const struct sdhci_pltfm_data sdhci_sama5d2_pdata = { 137 .ops = &sdhci_at91_sama5d2_ops, 138 }; 139 140 static const struct sdhci_at91_soc_data soc_data_sama5d2 = { 141 .pdata = &sdhci_sama5d2_pdata, 142 .baseclk_is_generated_internally = false, 143 }; 144 145 static const struct sdhci_at91_soc_data soc_data_sam9x60 = { 146 .pdata = &sdhci_sama5d2_pdata, 147 .baseclk_is_generated_internally = true, 148 .divider_for_baseclk = 2, 149 }; 150 151 static const struct of_device_id sdhci_at91_dt_match[] = { 152 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, 153 { .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 }, 154 {} 155 }; 156 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match); 157 158 static int sdhci_at91_set_clks_presets(struct device *dev) 159 { 160 struct sdhci_host *host = dev_get_drvdata(dev); 161 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 162 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 163 unsigned int caps0, caps1; 164 unsigned int clk_base, clk_mul; 165 unsigned int gck_rate, clk_base_rate; 166 unsigned int preset_div; 167 168 clk_prepare_enable(priv->hclock); 169 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); 170 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); 171 172 gck_rate = clk_get_rate(priv->gck); 173 if (priv->soc_data->baseclk_is_generated_internally) 174 clk_base_rate = gck_rate / priv->soc_data->divider_for_baseclk; 175 else 176 clk_base_rate = clk_get_rate(priv->mainck); 177 178 clk_base = clk_base_rate / 1000000; 179 clk_mul = gck_rate / clk_base_rate - 1; 180 181 caps0 &= ~SDHCI_CLOCK_V3_BASE_MASK; 182 caps0 |= (clk_base << SDHCI_CLOCK_BASE_SHIFT) & SDHCI_CLOCK_V3_BASE_MASK; 183 caps1 &= ~SDHCI_CLOCK_MUL_MASK; 184 caps1 |= (clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK; 185 /* Set capabilities in r/w mode. */ 186 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR); 187 writel(caps0, host->ioaddr + SDHCI_CAPABILITIES); 188 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1); 189 /* Set capabilities in ro mode. */ 190 writel(0, host->ioaddr + SDMMC_CACR); 191 192 dev_info(dev, "update clk mul to %u as gck rate is %u Hz and clk base is %u Hz\n", 193 clk_mul, gck_rate, clk_base_rate); 194 195 /* 196 * We have to set preset values because it depends on the clk_mul 197 * value. Moreover, SDR104 is supported in a degraded mode since the 198 * maximum sd clock value is 120 MHz instead of 208 MHz. For that 199 * reason, we need to use presets to support SDR104. 200 */ 201 preset_div = DIV_ROUND_UP(gck_rate, 24000000) - 1; 202 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 203 host->ioaddr + SDHCI_PRESET_FOR_SDR12); 204 preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; 205 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 206 host->ioaddr + SDHCI_PRESET_FOR_SDR25); 207 preset_div = DIV_ROUND_UP(gck_rate, 100000000) - 1; 208 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 209 host->ioaddr + SDHCI_PRESET_FOR_SDR50); 210 preset_div = DIV_ROUND_UP(gck_rate, 120000000) - 1; 211 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 212 host->ioaddr + SDHCI_PRESET_FOR_SDR104); 213 preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; 214 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 215 host->ioaddr + SDHCI_PRESET_FOR_DDR50); 216 217 clk_prepare_enable(priv->mainck); 218 clk_prepare_enable(priv->gck); 219 220 return 0; 221 } 222 223 #ifdef CONFIG_PM_SLEEP 224 static int sdhci_at91_suspend(struct device *dev) 225 { 226 struct sdhci_host *host = dev_get_drvdata(dev); 227 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 228 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 229 int ret; 230 231 ret = pm_runtime_force_suspend(dev); 232 233 priv->restore_needed = true; 234 235 return ret; 236 } 237 #endif /* CONFIG_PM_SLEEP */ 238 239 #ifdef CONFIG_PM 240 static int sdhci_at91_runtime_suspend(struct device *dev) 241 { 242 struct sdhci_host *host = dev_get_drvdata(dev); 243 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 244 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 245 int ret; 246 247 ret = sdhci_runtime_suspend_host(host); 248 249 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 250 mmc_retune_needed(host->mmc); 251 252 clk_disable_unprepare(priv->gck); 253 clk_disable_unprepare(priv->hclock); 254 clk_disable_unprepare(priv->mainck); 255 256 return ret; 257 } 258 259 static int sdhci_at91_runtime_resume(struct device *dev) 260 { 261 struct sdhci_host *host = dev_get_drvdata(dev); 262 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 263 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 264 int ret; 265 266 if (priv->restore_needed) { 267 ret = sdhci_at91_set_clks_presets(dev); 268 if (ret) 269 return ret; 270 271 priv->restore_needed = false; 272 goto out; 273 } 274 275 ret = clk_prepare_enable(priv->mainck); 276 if (ret) { 277 dev_err(dev, "can't enable mainck\n"); 278 return ret; 279 } 280 281 ret = clk_prepare_enable(priv->hclock); 282 if (ret) { 283 dev_err(dev, "can't enable hclock\n"); 284 return ret; 285 } 286 287 ret = clk_prepare_enable(priv->gck); 288 if (ret) { 289 dev_err(dev, "can't enable gck\n"); 290 return ret; 291 } 292 293 out: 294 return sdhci_runtime_resume_host(host, 0); 295 } 296 #endif /* CONFIG_PM */ 297 298 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = { 299 SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume) 300 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend, 301 sdhci_at91_runtime_resume, 302 NULL) 303 }; 304 305 static int sdhci_at91_probe(struct platform_device *pdev) 306 { 307 const struct of_device_id *match; 308 const struct sdhci_at91_soc_data *soc_data; 309 struct sdhci_host *host; 310 struct sdhci_pltfm_host *pltfm_host; 311 struct sdhci_at91_priv *priv; 312 int ret; 313 314 match = of_match_device(sdhci_at91_dt_match, &pdev->dev); 315 if (!match) 316 return -EINVAL; 317 soc_data = match->data; 318 319 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*priv)); 320 if (IS_ERR(host)) 321 return PTR_ERR(host); 322 323 pltfm_host = sdhci_priv(host); 324 priv = sdhci_pltfm_priv(pltfm_host); 325 priv->soc_data = soc_data; 326 327 priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); 328 if (IS_ERR(priv->mainck)) { 329 if (soc_data->baseclk_is_generated_internally) { 330 priv->mainck = NULL; 331 } else { 332 dev_err(&pdev->dev, "failed to get baseclk\n"); 333 ret = PTR_ERR(priv->mainck); 334 goto sdhci_pltfm_free; 335 } 336 } 337 338 priv->hclock = devm_clk_get(&pdev->dev, "hclock"); 339 if (IS_ERR(priv->hclock)) { 340 dev_err(&pdev->dev, "failed to get hclock\n"); 341 ret = PTR_ERR(priv->hclock); 342 goto sdhci_pltfm_free; 343 } 344 345 priv->gck = devm_clk_get(&pdev->dev, "multclk"); 346 if (IS_ERR(priv->gck)) { 347 dev_err(&pdev->dev, "failed to get multclk\n"); 348 ret = PTR_ERR(priv->gck); 349 goto sdhci_pltfm_free; 350 } 351 352 ret = sdhci_at91_set_clks_presets(&pdev->dev); 353 if (ret) 354 goto sdhci_pltfm_free; 355 356 priv->restore_needed = false; 357 358 /* 359 * if SDCAL pin is wrongly connected, we must enable 360 * the analog calibration cell permanently. 361 */ 362 priv->cal_always_on = 363 device_property_read_bool(&pdev->dev, 364 "microchip,sdcal-inverted"); 365 366 ret = mmc_of_parse(host->mmc); 367 if (ret) 368 goto clocks_disable_unprepare; 369 370 sdhci_get_of_property(pdev); 371 372 pm_runtime_get_noresume(&pdev->dev); 373 pm_runtime_set_active(&pdev->dev); 374 pm_runtime_enable(&pdev->dev); 375 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 376 pm_runtime_use_autosuspend(&pdev->dev); 377 378 /* HS200 is broken at this moment */ 379 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 380 381 ret = sdhci_add_host(host); 382 if (ret) 383 goto pm_runtime_disable; 384 385 /* 386 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes 387 * the assumption that all the clocks of the controller are disabled. 388 * It means we can't get irq from it when it is runtime suspended. 389 * For that reason, it is not planned to wake-up on a card detect irq 390 * from the controller. 391 * If we want to use runtime PM and to be able to wake-up on card 392 * insertion, we have to use a GPIO for the card detection or we can 393 * use polling. Be aware that using polling will resume/suspend the 394 * controller between each attempt. 395 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries 396 * to enable polling via device tree with broken-cd property. 397 */ 398 if (mmc_card_is_removable(host->mmc) && 399 mmc_gpio_get_cd(host->mmc) < 0) { 400 host->mmc->caps |= MMC_CAP_NEEDS_POLL; 401 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 402 } 403 404 /* 405 * If the device attached to the MMC bus is not removable, it is safer 406 * to set the Force Card Detect bit. People often don't connect the 407 * card detect signal and use this pin for another purpose. If the card 408 * detect pin is not muxed to SDHCI controller, a default value is 409 * used. This value can be different from a SoC revision to another 410 * one. Problems come when this default value is not card present. To 411 * avoid this case, if the device is non removable then the card 412 * detection procedure using the SDMCC_CD signal is bypassed. 413 * This bit is reset when a software reset for all command is performed 414 * so we need to implement our own reset function to set back this bit. 415 * 416 * WA: SAMA5D2 doesn't drive CMD if using CD GPIO line. 417 */ 418 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) 419 || mmc_gpio_get_cd(host->mmc) >= 0) 420 sdhci_at91_set_force_card_detect(host); 421 422 pm_runtime_put_autosuspend(&pdev->dev); 423 424 return 0; 425 426 pm_runtime_disable: 427 pm_runtime_disable(&pdev->dev); 428 pm_runtime_set_suspended(&pdev->dev); 429 pm_runtime_put_noidle(&pdev->dev); 430 clocks_disable_unprepare: 431 clk_disable_unprepare(priv->gck); 432 clk_disable_unprepare(priv->mainck); 433 clk_disable_unprepare(priv->hclock); 434 sdhci_pltfm_free: 435 sdhci_pltfm_free(pdev); 436 return ret; 437 } 438 439 static int sdhci_at91_remove(struct platform_device *pdev) 440 { 441 struct sdhci_host *host = platform_get_drvdata(pdev); 442 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 443 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 444 struct clk *gck = priv->gck; 445 struct clk *hclock = priv->hclock; 446 struct clk *mainck = priv->mainck; 447 448 pm_runtime_get_sync(&pdev->dev); 449 pm_runtime_disable(&pdev->dev); 450 pm_runtime_put_noidle(&pdev->dev); 451 452 sdhci_pltfm_unregister(pdev); 453 454 clk_disable_unprepare(gck); 455 clk_disable_unprepare(hclock); 456 clk_disable_unprepare(mainck); 457 458 return 0; 459 } 460 461 static struct platform_driver sdhci_at91_driver = { 462 .driver = { 463 .name = "sdhci-at91", 464 .of_match_table = sdhci_at91_dt_match, 465 .pm = &sdhci_at91_dev_pm_ops, 466 }, 467 .probe = sdhci_at91_probe, 468 .remove = sdhci_at91_remove, 469 }; 470 471 module_platform_driver(sdhci_at91_driver); 472 473 MODULE_DESCRIPTION("SDHCI driver for at91"); 474 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); 475 MODULE_LICENSE("GPL v2"); 476