1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Atmel SDMMC controller driver. 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/mmc/host.h> 15 #include <linux/mmc/slot-gpio.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_device.h> 19 #include <linux/pm.h> 20 #include <linux/pm_runtime.h> 21 22 #include "sdhci-pltfm.h" 23 24 #define SDMMC_MC1R 0x204 25 #define SDMMC_MC1R_DDR BIT(3) 26 #define SDMMC_MC1R_FCD BIT(7) 27 #define SDMMC_CACR 0x230 28 #define SDMMC_CACR_CAPWREN BIT(0) 29 #define SDMMC_CACR_KEY (0x46 << 8) 30 #define SDMMC_CALCR 0x240 31 #define SDMMC_CALCR_EN BIT(0) 32 #define SDMMC_CALCR_ALWYSON BIT(4) 33 34 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */ 35 36 struct sdhci_at91_soc_data { 37 const struct sdhci_pltfm_data *pdata; 38 bool baseclk_is_generated_internally; 39 unsigned int divider_for_baseclk; 40 }; 41 42 struct sdhci_at91_priv { 43 const struct sdhci_at91_soc_data *soc_data; 44 struct clk *hclock; 45 struct clk *gck; 46 struct clk *mainck; 47 bool restore_needed; 48 bool cal_always_on; 49 }; 50 51 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host) 52 { 53 u8 mc1r; 54 55 mc1r = readb(host->ioaddr + SDMMC_MC1R); 56 mc1r |= SDMMC_MC1R_FCD; 57 writeb(mc1r, host->ioaddr + SDMMC_MC1R); 58 } 59 60 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock) 61 { 62 u16 clk; 63 unsigned long timeout; 64 65 host->mmc->actual_clock = 0; 66 67 /* 68 * There is no requirement to disable the internal clock before 69 * changing the SD clock configuration. Moreover, disabling the 70 * internal clock, changing the configuration and re-enabling the 71 * internal clock causes some bugs. It can prevent to get the internal 72 * clock stable flag ready and an unexpected switch to the base clock 73 * when using presets. 74 */ 75 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 76 clk &= SDHCI_CLOCK_INT_EN; 77 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 78 79 if (clock == 0) 80 return; 81 82 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 83 84 clk |= SDHCI_CLOCK_INT_EN; 85 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 86 87 /* Wait max 20 ms */ 88 timeout = 20; 89 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 90 & SDHCI_CLOCK_INT_STABLE)) { 91 if (timeout == 0) { 92 pr_err("%s: Internal clock never stabilised.\n", 93 mmc_hostname(host->mmc)); 94 return; 95 } 96 timeout--; 97 mdelay(1); 98 } 99 100 clk |= SDHCI_CLOCK_CARD_EN; 101 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 102 } 103 104 /* 105 * In this specific implementation of the SDHCI controller, the power register 106 * needs to have a valid voltage set even when the power supply is managed by 107 * an external regulator. 108 */ 109 static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode, 110 unsigned short vdd) 111 { 112 if (!IS_ERR(host->mmc->supply.vmmc)) { 113 struct mmc_host *mmc = host->mmc; 114 115 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 116 } 117 sdhci_set_power_noreg(host, mode, vdd); 118 } 119 120 static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, 121 unsigned int timing) 122 { 123 if (timing == MMC_TIMING_MMC_DDR52) 124 sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R); 125 sdhci_set_uhs_signaling(host, timing); 126 } 127 128 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask) 129 { 130 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 131 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 132 133 sdhci_reset(host, mask); 134 135 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) 136 || mmc_gpio_get_cd(host->mmc) >= 0) 137 sdhci_at91_set_force_card_detect(host); 138 139 if (priv->cal_always_on && (mask & SDHCI_RESET_ALL)) 140 sdhci_writel(host, SDMMC_CALCR_ALWYSON | SDMMC_CALCR_EN, 141 SDMMC_CALCR); 142 } 143 144 static const struct sdhci_ops sdhci_at91_sama5d2_ops = { 145 .set_clock = sdhci_at91_set_clock, 146 .set_bus_width = sdhci_set_bus_width, 147 .reset = sdhci_at91_reset, 148 .set_uhs_signaling = sdhci_at91_set_uhs_signaling, 149 .set_power = sdhci_at91_set_power, 150 }; 151 152 static const struct sdhci_pltfm_data sdhci_sama5d2_pdata = { 153 .ops = &sdhci_at91_sama5d2_ops, 154 }; 155 156 static const struct sdhci_at91_soc_data soc_data_sama5d2 = { 157 .pdata = &sdhci_sama5d2_pdata, 158 .baseclk_is_generated_internally = false, 159 }; 160 161 static const struct sdhci_at91_soc_data soc_data_sam9x60 = { 162 .pdata = &sdhci_sama5d2_pdata, 163 .baseclk_is_generated_internally = true, 164 .divider_for_baseclk = 2, 165 }; 166 167 static const struct of_device_id sdhci_at91_dt_match[] = { 168 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, 169 { .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 }, 170 {} 171 }; 172 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match); 173 174 static int sdhci_at91_set_clks_presets(struct device *dev) 175 { 176 struct sdhci_host *host = dev_get_drvdata(dev); 177 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 178 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 179 unsigned int caps0, caps1; 180 unsigned int clk_base, clk_mul; 181 unsigned int gck_rate, clk_base_rate; 182 unsigned int preset_div; 183 184 clk_prepare_enable(priv->hclock); 185 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); 186 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); 187 188 gck_rate = clk_get_rate(priv->gck); 189 if (priv->soc_data->baseclk_is_generated_internally) 190 clk_base_rate = gck_rate / priv->soc_data->divider_for_baseclk; 191 else 192 clk_base_rate = clk_get_rate(priv->mainck); 193 194 clk_base = clk_base_rate / 1000000; 195 clk_mul = gck_rate / clk_base_rate - 1; 196 197 caps0 &= ~SDHCI_CLOCK_V3_BASE_MASK; 198 caps0 |= (clk_base << SDHCI_CLOCK_BASE_SHIFT) & SDHCI_CLOCK_V3_BASE_MASK; 199 caps1 &= ~SDHCI_CLOCK_MUL_MASK; 200 caps1 |= (clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK; 201 /* Set capabilities in r/w mode. */ 202 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR); 203 writel(caps0, host->ioaddr + SDHCI_CAPABILITIES); 204 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1); 205 /* Set capabilities in ro mode. */ 206 writel(0, host->ioaddr + SDMMC_CACR); 207 208 dev_info(dev, "update clk mul to %u as gck rate is %u Hz and clk base is %u Hz\n", 209 clk_mul, gck_rate, clk_base_rate); 210 211 /* 212 * We have to set preset values because it depends on the clk_mul 213 * value. Moreover, SDR104 is supported in a degraded mode since the 214 * maximum sd clock value is 120 MHz instead of 208 MHz. For that 215 * reason, we need to use presets to support SDR104. 216 */ 217 preset_div = DIV_ROUND_UP(gck_rate, 24000000) - 1; 218 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 219 host->ioaddr + SDHCI_PRESET_FOR_SDR12); 220 preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; 221 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 222 host->ioaddr + SDHCI_PRESET_FOR_SDR25); 223 preset_div = DIV_ROUND_UP(gck_rate, 100000000) - 1; 224 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 225 host->ioaddr + SDHCI_PRESET_FOR_SDR50); 226 preset_div = DIV_ROUND_UP(gck_rate, 120000000) - 1; 227 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 228 host->ioaddr + SDHCI_PRESET_FOR_SDR104); 229 preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; 230 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 231 host->ioaddr + SDHCI_PRESET_FOR_DDR50); 232 233 clk_prepare_enable(priv->mainck); 234 clk_prepare_enable(priv->gck); 235 236 return 0; 237 } 238 239 #ifdef CONFIG_PM_SLEEP 240 static int sdhci_at91_suspend(struct device *dev) 241 { 242 struct sdhci_host *host = dev_get_drvdata(dev); 243 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 244 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 245 int ret; 246 247 ret = pm_runtime_force_suspend(dev); 248 249 priv->restore_needed = true; 250 251 return ret; 252 } 253 #endif /* CONFIG_PM_SLEEP */ 254 255 #ifdef CONFIG_PM 256 static int sdhci_at91_runtime_suspend(struct device *dev) 257 { 258 struct sdhci_host *host = dev_get_drvdata(dev); 259 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 260 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 261 int ret; 262 263 ret = sdhci_runtime_suspend_host(host); 264 265 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 266 mmc_retune_needed(host->mmc); 267 268 clk_disable_unprepare(priv->gck); 269 clk_disable_unprepare(priv->hclock); 270 clk_disable_unprepare(priv->mainck); 271 272 return ret; 273 } 274 275 static int sdhci_at91_runtime_resume(struct device *dev) 276 { 277 struct sdhci_host *host = dev_get_drvdata(dev); 278 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 279 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 280 int ret; 281 282 if (priv->restore_needed) { 283 ret = sdhci_at91_set_clks_presets(dev); 284 if (ret) 285 return ret; 286 287 priv->restore_needed = false; 288 goto out; 289 } 290 291 ret = clk_prepare_enable(priv->mainck); 292 if (ret) { 293 dev_err(dev, "can't enable mainck\n"); 294 return ret; 295 } 296 297 ret = clk_prepare_enable(priv->hclock); 298 if (ret) { 299 dev_err(dev, "can't enable hclock\n"); 300 return ret; 301 } 302 303 ret = clk_prepare_enable(priv->gck); 304 if (ret) { 305 dev_err(dev, "can't enable gck\n"); 306 return ret; 307 } 308 309 out: 310 return sdhci_runtime_resume_host(host, 0); 311 } 312 #endif /* CONFIG_PM */ 313 314 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = { 315 SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume) 316 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend, 317 sdhci_at91_runtime_resume, 318 NULL) 319 }; 320 321 static int sdhci_at91_probe(struct platform_device *pdev) 322 { 323 const struct of_device_id *match; 324 const struct sdhci_at91_soc_data *soc_data; 325 struct sdhci_host *host; 326 struct sdhci_pltfm_host *pltfm_host; 327 struct sdhci_at91_priv *priv; 328 int ret; 329 330 match = of_match_device(sdhci_at91_dt_match, &pdev->dev); 331 if (!match) 332 return -EINVAL; 333 soc_data = match->data; 334 335 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*priv)); 336 if (IS_ERR(host)) 337 return PTR_ERR(host); 338 339 pltfm_host = sdhci_priv(host); 340 priv = sdhci_pltfm_priv(pltfm_host); 341 priv->soc_data = soc_data; 342 343 priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); 344 if (IS_ERR(priv->mainck)) { 345 if (soc_data->baseclk_is_generated_internally) { 346 priv->mainck = NULL; 347 } else { 348 dev_err(&pdev->dev, "failed to get baseclk\n"); 349 ret = PTR_ERR(priv->mainck); 350 goto sdhci_pltfm_free; 351 } 352 } 353 354 priv->hclock = devm_clk_get(&pdev->dev, "hclock"); 355 if (IS_ERR(priv->hclock)) { 356 dev_err(&pdev->dev, "failed to get hclock\n"); 357 ret = PTR_ERR(priv->hclock); 358 goto sdhci_pltfm_free; 359 } 360 361 priv->gck = devm_clk_get(&pdev->dev, "multclk"); 362 if (IS_ERR(priv->gck)) { 363 dev_err(&pdev->dev, "failed to get multclk\n"); 364 ret = PTR_ERR(priv->gck); 365 goto sdhci_pltfm_free; 366 } 367 368 ret = sdhci_at91_set_clks_presets(&pdev->dev); 369 if (ret) 370 goto sdhci_pltfm_free; 371 372 priv->restore_needed = false; 373 374 /* 375 * if SDCAL pin is wrongly connected, we must enable 376 * the analog calibration cell permanently. 377 */ 378 priv->cal_always_on = 379 device_property_read_bool(&pdev->dev, 380 "microchip,sdcal-inverted"); 381 382 ret = mmc_of_parse(host->mmc); 383 if (ret) 384 goto clocks_disable_unprepare; 385 386 sdhci_get_of_property(pdev); 387 388 pm_runtime_get_noresume(&pdev->dev); 389 pm_runtime_set_active(&pdev->dev); 390 pm_runtime_enable(&pdev->dev); 391 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 392 pm_runtime_use_autosuspend(&pdev->dev); 393 394 /* HS200 is broken at this moment */ 395 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 396 397 ret = sdhci_add_host(host); 398 if (ret) 399 goto pm_runtime_disable; 400 401 /* 402 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes 403 * the assumption that all the clocks of the controller are disabled. 404 * It means we can't get irq from it when it is runtime suspended. 405 * For that reason, it is not planned to wake-up on a card detect irq 406 * from the controller. 407 * If we want to use runtime PM and to be able to wake-up on card 408 * insertion, we have to use a GPIO for the card detection or we can 409 * use polling. Be aware that using polling will resume/suspend the 410 * controller between each attempt. 411 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries 412 * to enable polling via device tree with broken-cd property. 413 */ 414 if (mmc_card_is_removable(host->mmc) && 415 mmc_gpio_get_cd(host->mmc) < 0) { 416 host->mmc->caps |= MMC_CAP_NEEDS_POLL; 417 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 418 } 419 420 /* 421 * If the device attached to the MMC bus is not removable, it is safer 422 * to set the Force Card Detect bit. People often don't connect the 423 * card detect signal and use this pin for another purpose. If the card 424 * detect pin is not muxed to SDHCI controller, a default value is 425 * used. This value can be different from a SoC revision to another 426 * one. Problems come when this default value is not card present. To 427 * avoid this case, if the device is non removable then the card 428 * detection procedure using the SDMCC_CD signal is bypassed. 429 * This bit is reset when a software reset for all command is performed 430 * so we need to implement our own reset function to set back this bit. 431 * 432 * WA: SAMA5D2 doesn't drive CMD if using CD GPIO line. 433 */ 434 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) 435 || mmc_gpio_get_cd(host->mmc) >= 0) 436 sdhci_at91_set_force_card_detect(host); 437 438 pm_runtime_put_autosuspend(&pdev->dev); 439 440 return 0; 441 442 pm_runtime_disable: 443 pm_runtime_disable(&pdev->dev); 444 pm_runtime_set_suspended(&pdev->dev); 445 pm_runtime_put_noidle(&pdev->dev); 446 clocks_disable_unprepare: 447 clk_disable_unprepare(priv->gck); 448 clk_disable_unprepare(priv->mainck); 449 clk_disable_unprepare(priv->hclock); 450 sdhci_pltfm_free: 451 sdhci_pltfm_free(pdev); 452 return ret; 453 } 454 455 static int sdhci_at91_remove(struct platform_device *pdev) 456 { 457 struct sdhci_host *host = platform_get_drvdata(pdev); 458 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 459 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 460 struct clk *gck = priv->gck; 461 struct clk *hclock = priv->hclock; 462 struct clk *mainck = priv->mainck; 463 464 pm_runtime_get_sync(&pdev->dev); 465 pm_runtime_disable(&pdev->dev); 466 pm_runtime_put_noidle(&pdev->dev); 467 468 sdhci_pltfm_unregister(pdev); 469 470 clk_disable_unprepare(gck); 471 clk_disable_unprepare(hclock); 472 clk_disable_unprepare(mainck); 473 474 return 0; 475 } 476 477 static struct platform_driver sdhci_at91_driver = { 478 .driver = { 479 .name = "sdhci-at91", 480 .of_match_table = sdhci_at91_dt_match, 481 .pm = &sdhci_at91_dev_pm_ops, 482 }, 483 .probe = sdhci_at91_probe, 484 .remove = sdhci_at91_remove, 485 }; 486 487 module_platform_driver(sdhci_at91_driver); 488 489 MODULE_DESCRIPTION("SDHCI driver for at91"); 490 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); 491 MODULE_LICENSE("GPL v2"); 492