1 /* 2 * Atmel SDMMC controller driver. 3 * 4 * Copyright (C) 2015 Atmel, 5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 6 * 7 * This software is licensed under the terms of the GNU General Public 8 * License version 2, as published by the Free Software Foundation, and 9 * may be copied, distributed, and modified under those terms. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/slot-gpio.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/pm.h> 28 #include <linux/pm_runtime.h> 29 30 #include "sdhci-pltfm.h" 31 32 #define SDMMC_CACR 0x230 33 #define SDMMC_CACR_CAPWREN BIT(0) 34 #define SDMMC_CACR_KEY (0x46 << 8) 35 36 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */ 37 38 struct sdhci_at91_priv { 39 struct clk *hclock; 40 struct clk *gck; 41 struct clk *mainck; 42 }; 43 44 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock) 45 { 46 u16 clk; 47 unsigned long timeout; 48 49 host->mmc->actual_clock = 0; 50 51 /* 52 * There is no requirement to disable the internal clock before 53 * changing the SD clock configuration. Moreover, disabling the 54 * internal clock, changing the configuration and re-enabling the 55 * internal clock causes some bugs. It can prevent to get the internal 56 * clock stable flag ready and an unexpected switch to the base clock 57 * when using presets. 58 */ 59 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 60 clk &= SDHCI_CLOCK_INT_EN; 61 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 62 63 if (clock == 0) 64 return; 65 66 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 67 68 clk |= SDHCI_CLOCK_INT_EN; 69 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 70 71 /* Wait max 20 ms */ 72 timeout = 20; 73 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 74 & SDHCI_CLOCK_INT_STABLE)) { 75 if (timeout == 0) { 76 pr_err("%s: Internal clock never stabilised.\n", 77 mmc_hostname(host->mmc)); 78 return; 79 } 80 timeout--; 81 mdelay(1); 82 } 83 84 clk |= SDHCI_CLOCK_CARD_EN; 85 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 86 } 87 88 static const struct sdhci_ops sdhci_at91_sama5d2_ops = { 89 .set_clock = sdhci_at91_set_clock, 90 .set_bus_width = sdhci_set_bus_width, 91 .reset = sdhci_reset, 92 .set_uhs_signaling = sdhci_set_uhs_signaling, 93 }; 94 95 static const struct sdhci_pltfm_data soc_data_sama5d2 = { 96 .ops = &sdhci_at91_sama5d2_ops, 97 }; 98 99 static const struct of_device_id sdhci_at91_dt_match[] = { 100 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, 101 {} 102 }; 103 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match); 104 105 #ifdef CONFIG_PM 106 static int sdhci_at91_runtime_suspend(struct device *dev) 107 { 108 struct sdhci_host *host = dev_get_drvdata(dev); 109 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 110 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 111 int ret; 112 113 ret = sdhci_runtime_suspend_host(host); 114 115 clk_disable_unprepare(priv->gck); 116 clk_disable_unprepare(priv->hclock); 117 clk_disable_unprepare(priv->mainck); 118 119 return ret; 120 } 121 122 static int sdhci_at91_runtime_resume(struct device *dev) 123 { 124 struct sdhci_host *host = dev_get_drvdata(dev); 125 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 126 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 127 int ret; 128 129 ret = clk_prepare_enable(priv->mainck); 130 if (ret) { 131 dev_err(dev, "can't enable mainck\n"); 132 return ret; 133 } 134 135 ret = clk_prepare_enable(priv->hclock); 136 if (ret) { 137 dev_err(dev, "can't enable hclock\n"); 138 return ret; 139 } 140 141 ret = clk_prepare_enable(priv->gck); 142 if (ret) { 143 dev_err(dev, "can't enable gck\n"); 144 return ret; 145 } 146 147 return sdhci_runtime_resume_host(host); 148 } 149 #endif /* CONFIG_PM */ 150 151 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = { 152 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 153 pm_runtime_force_resume) 154 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend, 155 sdhci_at91_runtime_resume, 156 NULL) 157 }; 158 159 static int sdhci_at91_probe(struct platform_device *pdev) 160 { 161 const struct of_device_id *match; 162 const struct sdhci_pltfm_data *soc_data; 163 struct sdhci_host *host; 164 struct sdhci_pltfm_host *pltfm_host; 165 struct sdhci_at91_priv *priv; 166 unsigned int caps0, caps1; 167 unsigned int clk_base, clk_mul; 168 unsigned int gck_rate, real_gck_rate; 169 int ret; 170 unsigned int preset_div; 171 172 match = of_match_device(sdhci_at91_dt_match, &pdev->dev); 173 if (!match) 174 return -EINVAL; 175 soc_data = match->data; 176 177 host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv)); 178 if (IS_ERR(host)) 179 return PTR_ERR(host); 180 181 pltfm_host = sdhci_priv(host); 182 priv = sdhci_pltfm_priv(pltfm_host); 183 184 priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); 185 if (IS_ERR(priv->mainck)) { 186 dev_err(&pdev->dev, "failed to get baseclk\n"); 187 return PTR_ERR(priv->mainck); 188 } 189 190 priv->hclock = devm_clk_get(&pdev->dev, "hclock"); 191 if (IS_ERR(priv->hclock)) { 192 dev_err(&pdev->dev, "failed to get hclock\n"); 193 return PTR_ERR(priv->hclock); 194 } 195 196 priv->gck = devm_clk_get(&pdev->dev, "multclk"); 197 if (IS_ERR(priv->gck)) { 198 dev_err(&pdev->dev, "failed to get multclk\n"); 199 return PTR_ERR(priv->gck); 200 } 201 202 /* 203 * The mult clock is provided by as a generated clock by the PMC 204 * controller. In order to set the rate of gck, we have to get the 205 * base clock rate and the clock mult from capabilities. 206 */ 207 clk_prepare_enable(priv->hclock); 208 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); 209 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); 210 clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 211 clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; 212 gck_rate = clk_base * 1000000 * (clk_mul + 1); 213 ret = clk_set_rate(priv->gck, gck_rate); 214 if (ret < 0) { 215 dev_err(&pdev->dev, "failed to set gck"); 216 goto hclock_disable_unprepare; 217 } 218 /* 219 * We need to check if we have the requested rate for gck because in 220 * some cases this rate could be not supported. If it happens, the rate 221 * is the closest one gck can provide. We have to update the value 222 * of clk mul. 223 */ 224 real_gck_rate = clk_get_rate(priv->gck); 225 if (real_gck_rate != gck_rate) { 226 clk_mul = real_gck_rate / (clk_base * 1000000) - 1; 227 caps1 &= (~SDHCI_CLOCK_MUL_MASK); 228 caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK); 229 /* Set capabilities in r/w mode. */ 230 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR); 231 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1); 232 /* Set capabilities in ro mode. */ 233 writel(0, host->ioaddr + SDMMC_CACR); 234 dev_info(&pdev->dev, "update clk mul to %u as gck rate is %u Hz\n", 235 clk_mul, real_gck_rate); 236 } 237 238 /* 239 * We have to set preset values because it depends on the clk_mul 240 * value. Moreover, SDR104 is supported in a degraded mode since the 241 * maximum sd clock value is 120 MHz instead of 208 MHz. For that 242 * reason, we need to use presets to support SDR104. 243 */ 244 preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1; 245 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 246 host->ioaddr + SDHCI_PRESET_FOR_SDR12); 247 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1; 248 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 249 host->ioaddr + SDHCI_PRESET_FOR_SDR25); 250 preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1; 251 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 252 host->ioaddr + SDHCI_PRESET_FOR_SDR50); 253 preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1; 254 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 255 host->ioaddr + SDHCI_PRESET_FOR_SDR104); 256 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1; 257 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 258 host->ioaddr + SDHCI_PRESET_FOR_DDR50); 259 260 clk_prepare_enable(priv->mainck); 261 clk_prepare_enable(priv->gck); 262 263 ret = mmc_of_parse(host->mmc); 264 if (ret) 265 goto clocks_disable_unprepare; 266 267 sdhci_get_of_property(pdev); 268 269 pm_runtime_get_noresume(&pdev->dev); 270 pm_runtime_set_active(&pdev->dev); 271 pm_runtime_enable(&pdev->dev); 272 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 273 pm_runtime_use_autosuspend(&pdev->dev); 274 275 ret = sdhci_add_host(host); 276 if (ret) 277 goto pm_runtime_disable; 278 279 /* 280 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes 281 * the assumption that all the clocks of the controller are disabled. 282 * It means we can't get irq from it when it is runtime suspended. 283 * For that reason, it is not planned to wake-up on a card detect irq 284 * from the controller. 285 * If we want to use runtime PM and to be able to wake-up on card 286 * insertion, we have to use a GPIO for the card detection or we can 287 * use polling. Be aware that using polling will resume/suspend the 288 * controller between each attempt. 289 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries 290 * to enable polling via device tree with broken-cd property. 291 */ 292 if (mmc_card_is_removable(host->mmc) && 293 mmc_gpio_get_cd(host->mmc) < 0) { 294 host->mmc->caps |= MMC_CAP_NEEDS_POLL; 295 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 296 } 297 298 pm_runtime_put_autosuspend(&pdev->dev); 299 300 return 0; 301 302 pm_runtime_disable: 303 pm_runtime_disable(&pdev->dev); 304 pm_runtime_set_suspended(&pdev->dev); 305 pm_runtime_put_noidle(&pdev->dev); 306 clocks_disable_unprepare: 307 clk_disable_unprepare(priv->gck); 308 clk_disable_unprepare(priv->mainck); 309 hclock_disable_unprepare: 310 clk_disable_unprepare(priv->hclock); 311 sdhci_pltfm_free(pdev); 312 return ret; 313 } 314 315 static int sdhci_at91_remove(struct platform_device *pdev) 316 { 317 struct sdhci_host *host = platform_get_drvdata(pdev); 318 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 319 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 320 struct clk *gck = priv->gck; 321 struct clk *hclock = priv->hclock; 322 struct clk *mainck = priv->mainck; 323 324 pm_runtime_get_sync(&pdev->dev); 325 pm_runtime_disable(&pdev->dev); 326 pm_runtime_put_noidle(&pdev->dev); 327 328 sdhci_pltfm_unregister(pdev); 329 330 clk_disable_unprepare(gck); 331 clk_disable_unprepare(hclock); 332 clk_disable_unprepare(mainck); 333 334 return 0; 335 } 336 337 static struct platform_driver sdhci_at91_driver = { 338 .driver = { 339 .name = "sdhci-at91", 340 .of_match_table = sdhci_at91_dt_match, 341 .pm = &sdhci_at91_dev_pm_ops, 342 }, 343 .probe = sdhci_at91_probe, 344 .remove = sdhci_at91_remove, 345 }; 346 347 module_platform_driver(sdhci_at91_driver); 348 349 MODULE_DESCRIPTION("SDHCI driver for at91"); 350 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); 351 MODULE_LICENSE("GPL v2"); 352