1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Atmel SDMMC controller driver. 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <linux/kernel.h> 16 #include <linux/mmc/host.h> 17 #include <linux/mmc/slot-gpio.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/pm.h> 22 #include <linux/pm_runtime.h> 23 24 #include "sdhci-pltfm.h" 25 26 #define SDMMC_MC1R 0x204 27 #define SDMMC_MC1R_DDR BIT(3) 28 #define SDMMC_MC1R_FCD BIT(7) 29 #define SDMMC_CACR 0x230 30 #define SDMMC_CACR_CAPWREN BIT(0) 31 #define SDMMC_CACR_KEY (0x46 << 8) 32 #define SDMMC_CALCR 0x240 33 #define SDMMC_CALCR_EN BIT(0) 34 #define SDMMC_CALCR_ALWYSON BIT(4) 35 36 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */ 37 38 struct sdhci_at91_soc_data { 39 const struct sdhci_pltfm_data *pdata; 40 bool baseclk_is_generated_internally; 41 unsigned int divider_for_baseclk; 42 }; 43 44 struct sdhci_at91_priv { 45 const struct sdhci_at91_soc_data *soc_data; 46 struct clk *hclock; 47 struct clk *gck; 48 struct clk *mainck; 49 bool restore_needed; 50 bool cal_always_on; 51 }; 52 53 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host) 54 { 55 u8 mc1r; 56 57 mc1r = readb(host->ioaddr + SDMMC_MC1R); 58 mc1r |= SDMMC_MC1R_FCD; 59 writeb(mc1r, host->ioaddr + SDMMC_MC1R); 60 } 61 62 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock) 63 { 64 u16 clk; 65 66 host->mmc->actual_clock = 0; 67 68 /* 69 * There is no requirement to disable the internal clock before 70 * changing the SD clock configuration. Moreover, disabling the 71 * internal clock, changing the configuration and re-enabling the 72 * internal clock causes some bugs. It can prevent to get the internal 73 * clock stable flag ready and an unexpected switch to the base clock 74 * when using presets. 75 */ 76 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 77 clk &= SDHCI_CLOCK_INT_EN; 78 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 79 80 if (clock == 0) 81 return; 82 83 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 84 85 clk |= SDHCI_CLOCK_INT_EN; 86 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 87 88 /* Wait max 20 ms */ 89 if (read_poll_timeout(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE), 90 1000, 20000, false, host, SDHCI_CLOCK_CONTROL)) { 91 pr_err("%s: Internal clock never stabilised.\n", 92 mmc_hostname(host->mmc)); 93 return; 94 } 95 96 clk |= SDHCI_CLOCK_CARD_EN; 97 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 98 } 99 100 static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, 101 unsigned int timing) 102 { 103 if (timing == MMC_TIMING_MMC_DDR52) 104 sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R); 105 sdhci_set_uhs_signaling(host, timing); 106 } 107 108 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask) 109 { 110 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 111 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 112 unsigned int tmp; 113 114 sdhci_reset(host, mask); 115 116 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) 117 || mmc_gpio_get_cd(host->mmc) >= 0) 118 sdhci_at91_set_force_card_detect(host); 119 120 if (priv->cal_always_on && (mask & SDHCI_RESET_ALL)) { 121 u32 calcr = sdhci_readl(host, SDMMC_CALCR); 122 123 sdhci_writel(host, calcr | SDMMC_CALCR_ALWYSON | SDMMC_CALCR_EN, 124 SDMMC_CALCR); 125 126 if (read_poll_timeout(sdhci_readl, tmp, !(tmp & SDMMC_CALCR_EN), 127 10, 20000, false, host, SDMMC_CALCR)) 128 dev_err(mmc_dev(host->mmc), "Failed to calibrate\n"); 129 } 130 } 131 132 static const struct sdhci_ops sdhci_at91_sama5d2_ops = { 133 .set_clock = sdhci_at91_set_clock, 134 .set_bus_width = sdhci_set_bus_width, 135 .reset = sdhci_at91_reset, 136 .set_uhs_signaling = sdhci_at91_set_uhs_signaling, 137 .set_power = sdhci_set_power_and_bus_voltage, 138 }; 139 140 static const struct sdhci_pltfm_data sdhci_sama5d2_pdata = { 141 .ops = &sdhci_at91_sama5d2_ops, 142 }; 143 144 static const struct sdhci_at91_soc_data soc_data_sama5d2 = { 145 .pdata = &sdhci_sama5d2_pdata, 146 .baseclk_is_generated_internally = false, 147 }; 148 149 static const struct sdhci_at91_soc_data soc_data_sam9x60 = { 150 .pdata = &sdhci_sama5d2_pdata, 151 .baseclk_is_generated_internally = true, 152 .divider_for_baseclk = 2, 153 }; 154 155 static const struct of_device_id sdhci_at91_dt_match[] = { 156 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, 157 { .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 }, 158 {} 159 }; 160 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match); 161 162 static int sdhci_at91_set_clks_presets(struct device *dev) 163 { 164 struct sdhci_host *host = dev_get_drvdata(dev); 165 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 166 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 167 unsigned int caps0, caps1; 168 unsigned int clk_base, clk_mul; 169 unsigned int gck_rate, clk_base_rate; 170 unsigned int preset_div; 171 172 clk_prepare_enable(priv->hclock); 173 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); 174 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); 175 176 gck_rate = clk_get_rate(priv->gck); 177 if (priv->soc_data->baseclk_is_generated_internally) 178 clk_base_rate = gck_rate / priv->soc_data->divider_for_baseclk; 179 else 180 clk_base_rate = clk_get_rate(priv->mainck); 181 182 clk_base = clk_base_rate / 1000000; 183 clk_mul = gck_rate / clk_base_rate - 1; 184 185 caps0 &= ~SDHCI_CLOCK_V3_BASE_MASK; 186 caps0 |= FIELD_PREP(SDHCI_CLOCK_V3_BASE_MASK, clk_base); 187 caps1 &= ~SDHCI_CLOCK_MUL_MASK; 188 caps1 |= FIELD_PREP(SDHCI_CLOCK_MUL_MASK, clk_mul); 189 /* Set capabilities in r/w mode. */ 190 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR); 191 writel(caps0, host->ioaddr + SDHCI_CAPABILITIES); 192 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1); 193 /* Set capabilities in ro mode. */ 194 writel(0, host->ioaddr + SDMMC_CACR); 195 196 dev_dbg(dev, "update clk mul to %u as gck rate is %u Hz and clk base is %u Hz\n", 197 clk_mul, gck_rate, clk_base_rate); 198 199 /* 200 * We have to set preset values because it depends on the clk_mul 201 * value. Moreover, SDR104 is supported in a degraded mode since the 202 * maximum sd clock value is 120 MHz instead of 208 MHz. For that 203 * reason, we need to use presets to support SDR104. 204 */ 205 preset_div = DIV_ROUND_UP(gck_rate, 24000000) - 1; 206 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 207 host->ioaddr + SDHCI_PRESET_FOR_SDR12); 208 preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; 209 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 210 host->ioaddr + SDHCI_PRESET_FOR_SDR25); 211 preset_div = DIV_ROUND_UP(gck_rate, 100000000) - 1; 212 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 213 host->ioaddr + SDHCI_PRESET_FOR_SDR50); 214 preset_div = DIV_ROUND_UP(gck_rate, 120000000) - 1; 215 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 216 host->ioaddr + SDHCI_PRESET_FOR_SDR104); 217 preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; 218 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 219 host->ioaddr + SDHCI_PRESET_FOR_DDR50); 220 221 clk_prepare_enable(priv->mainck); 222 clk_prepare_enable(priv->gck); 223 224 return 0; 225 } 226 227 #ifdef CONFIG_PM_SLEEP 228 static int sdhci_at91_suspend(struct device *dev) 229 { 230 struct sdhci_host *host = dev_get_drvdata(dev); 231 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 232 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 233 int ret; 234 235 ret = pm_runtime_force_suspend(dev); 236 237 priv->restore_needed = true; 238 239 return ret; 240 } 241 #endif /* CONFIG_PM_SLEEP */ 242 243 #ifdef CONFIG_PM 244 static int sdhci_at91_runtime_suspend(struct device *dev) 245 { 246 struct sdhci_host *host = dev_get_drvdata(dev); 247 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 248 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 249 int ret; 250 251 ret = sdhci_runtime_suspend_host(host); 252 253 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 254 mmc_retune_needed(host->mmc); 255 256 clk_disable_unprepare(priv->gck); 257 clk_disable_unprepare(priv->hclock); 258 clk_disable_unprepare(priv->mainck); 259 260 return ret; 261 } 262 263 static int sdhci_at91_runtime_resume(struct device *dev) 264 { 265 struct sdhci_host *host = dev_get_drvdata(dev); 266 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 267 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 268 int ret; 269 270 if (priv->restore_needed) { 271 ret = sdhci_at91_set_clks_presets(dev); 272 if (ret) 273 return ret; 274 275 priv->restore_needed = false; 276 goto out; 277 } 278 279 ret = clk_prepare_enable(priv->mainck); 280 if (ret) { 281 dev_err(dev, "can't enable mainck\n"); 282 return ret; 283 } 284 285 ret = clk_prepare_enable(priv->hclock); 286 if (ret) { 287 dev_err(dev, "can't enable hclock\n"); 288 return ret; 289 } 290 291 ret = clk_prepare_enable(priv->gck); 292 if (ret) { 293 dev_err(dev, "can't enable gck\n"); 294 return ret; 295 } 296 297 out: 298 return sdhci_runtime_resume_host(host, 0); 299 } 300 #endif /* CONFIG_PM */ 301 302 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = { 303 SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume) 304 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend, 305 sdhci_at91_runtime_resume, 306 NULL) 307 }; 308 309 static int sdhci_at91_probe(struct platform_device *pdev) 310 { 311 const struct of_device_id *match; 312 const struct sdhci_at91_soc_data *soc_data; 313 struct sdhci_host *host; 314 struct sdhci_pltfm_host *pltfm_host; 315 struct sdhci_at91_priv *priv; 316 int ret; 317 318 match = of_match_device(sdhci_at91_dt_match, &pdev->dev); 319 if (!match) 320 return -EINVAL; 321 soc_data = match->data; 322 323 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*priv)); 324 if (IS_ERR(host)) 325 return PTR_ERR(host); 326 327 pltfm_host = sdhci_priv(host); 328 priv = sdhci_pltfm_priv(pltfm_host); 329 priv->soc_data = soc_data; 330 331 priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); 332 if (IS_ERR(priv->mainck)) { 333 if (soc_data->baseclk_is_generated_internally) { 334 priv->mainck = NULL; 335 } else { 336 dev_err(&pdev->dev, "failed to get baseclk\n"); 337 ret = PTR_ERR(priv->mainck); 338 goto sdhci_pltfm_free; 339 } 340 } 341 342 priv->hclock = devm_clk_get(&pdev->dev, "hclock"); 343 if (IS_ERR(priv->hclock)) { 344 dev_err(&pdev->dev, "failed to get hclock\n"); 345 ret = PTR_ERR(priv->hclock); 346 goto sdhci_pltfm_free; 347 } 348 349 priv->gck = devm_clk_get(&pdev->dev, "multclk"); 350 if (IS_ERR(priv->gck)) { 351 dev_err(&pdev->dev, "failed to get multclk\n"); 352 ret = PTR_ERR(priv->gck); 353 goto sdhci_pltfm_free; 354 } 355 356 ret = sdhci_at91_set_clks_presets(&pdev->dev); 357 if (ret) 358 goto sdhci_pltfm_free; 359 360 priv->restore_needed = false; 361 362 /* 363 * if SDCAL pin is wrongly connected, we must enable 364 * the analog calibration cell permanently. 365 */ 366 priv->cal_always_on = 367 device_property_read_bool(&pdev->dev, 368 "microchip,sdcal-inverted"); 369 370 ret = mmc_of_parse(host->mmc); 371 if (ret) 372 goto clocks_disable_unprepare; 373 374 sdhci_get_of_property(pdev); 375 376 pm_runtime_get_noresume(&pdev->dev); 377 pm_runtime_set_active(&pdev->dev); 378 pm_runtime_enable(&pdev->dev); 379 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 380 pm_runtime_use_autosuspend(&pdev->dev); 381 382 /* HS200 is broken at this moment */ 383 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 384 385 ret = sdhci_add_host(host); 386 if (ret) 387 goto pm_runtime_disable; 388 389 /* 390 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes 391 * the assumption that all the clocks of the controller are disabled. 392 * It means we can't get irq from it when it is runtime suspended. 393 * For that reason, it is not planned to wake-up on a card detect irq 394 * from the controller. 395 * If we want to use runtime PM and to be able to wake-up on card 396 * insertion, we have to use a GPIO for the card detection or we can 397 * use polling. Be aware that using polling will resume/suspend the 398 * controller between each attempt. 399 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries 400 * to enable polling via device tree with broken-cd property. 401 */ 402 if (mmc_card_is_removable(host->mmc) && 403 mmc_gpio_get_cd(host->mmc) < 0) { 404 host->mmc->caps |= MMC_CAP_NEEDS_POLL; 405 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 406 } 407 408 /* 409 * If the device attached to the MMC bus is not removable, it is safer 410 * to set the Force Card Detect bit. People often don't connect the 411 * card detect signal and use this pin for another purpose. If the card 412 * detect pin is not muxed to SDHCI controller, a default value is 413 * used. This value can be different from a SoC revision to another 414 * one. Problems come when this default value is not card present. To 415 * avoid this case, if the device is non removable then the card 416 * detection procedure using the SDMCC_CD signal is bypassed. 417 * This bit is reset when a software reset for all command is performed 418 * so we need to implement our own reset function to set back this bit. 419 * 420 * WA: SAMA5D2 doesn't drive CMD if using CD GPIO line. 421 */ 422 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) 423 || mmc_gpio_get_cd(host->mmc) >= 0) 424 sdhci_at91_set_force_card_detect(host); 425 426 pm_runtime_put_autosuspend(&pdev->dev); 427 428 return 0; 429 430 pm_runtime_disable: 431 pm_runtime_disable(&pdev->dev); 432 pm_runtime_set_suspended(&pdev->dev); 433 pm_runtime_put_noidle(&pdev->dev); 434 clocks_disable_unprepare: 435 clk_disable_unprepare(priv->gck); 436 clk_disable_unprepare(priv->mainck); 437 clk_disable_unprepare(priv->hclock); 438 sdhci_pltfm_free: 439 sdhci_pltfm_free(pdev); 440 return ret; 441 } 442 443 static int sdhci_at91_remove(struct platform_device *pdev) 444 { 445 struct sdhci_host *host = platform_get_drvdata(pdev); 446 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 447 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 448 struct clk *gck = priv->gck; 449 struct clk *hclock = priv->hclock; 450 struct clk *mainck = priv->mainck; 451 452 pm_runtime_get_sync(&pdev->dev); 453 pm_runtime_disable(&pdev->dev); 454 pm_runtime_put_noidle(&pdev->dev); 455 456 sdhci_pltfm_unregister(pdev); 457 458 clk_disable_unprepare(gck); 459 clk_disable_unprepare(hclock); 460 clk_disable_unprepare(mainck); 461 462 return 0; 463 } 464 465 static struct platform_driver sdhci_at91_driver = { 466 .driver = { 467 .name = "sdhci-at91", 468 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 469 .of_match_table = sdhci_at91_dt_match, 470 .pm = &sdhci_at91_dev_pm_ops, 471 }, 472 .probe = sdhci_at91_probe, 473 .remove = sdhci_at91_remove, 474 }; 475 476 module_platform_driver(sdhci_at91_driver); 477 478 MODULE_DESCRIPTION("SDHCI driver for at91"); 479 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); 480 MODULE_LICENSE("GPL v2"); 481