1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Atmel SDMMC controller driver. 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <linux/kernel.h> 16 #include <linux/mmc/host.h> 17 #include <linux/mmc/slot-gpio.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/pm.h> 22 #include <linux/pm_runtime.h> 23 24 #include "sdhci-pltfm.h" 25 26 #define SDMMC_MC1R 0x204 27 #define SDMMC_MC1R_DDR BIT(3) 28 #define SDMMC_MC1R_FCD BIT(7) 29 #define SDMMC_CACR 0x230 30 #define SDMMC_CACR_CAPWREN BIT(0) 31 #define SDMMC_CACR_KEY (0x46 << 8) 32 #define SDMMC_CALCR 0x240 33 #define SDMMC_CALCR_EN BIT(0) 34 #define SDMMC_CALCR_ALWYSON BIT(4) 35 36 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */ 37 38 struct sdhci_at91_soc_data { 39 const struct sdhci_pltfm_data *pdata; 40 bool baseclk_is_generated_internally; 41 unsigned int divider_for_baseclk; 42 }; 43 44 struct sdhci_at91_priv { 45 const struct sdhci_at91_soc_data *soc_data; 46 struct clk *hclock; 47 struct clk *gck; 48 struct clk *mainck; 49 bool restore_needed; 50 bool cal_always_on; 51 }; 52 53 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host) 54 { 55 u8 mc1r; 56 57 mc1r = readb(host->ioaddr + SDMMC_MC1R); 58 mc1r |= SDMMC_MC1R_FCD; 59 writeb(mc1r, host->ioaddr + SDMMC_MC1R); 60 } 61 62 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock) 63 { 64 u16 clk; 65 66 host->mmc->actual_clock = 0; 67 68 /* 69 * There is no requirement to disable the internal clock before 70 * changing the SD clock configuration. Moreover, disabling the 71 * internal clock, changing the configuration and re-enabling the 72 * internal clock causes some bugs. It can prevent to get the internal 73 * clock stable flag ready and an unexpected switch to the base clock 74 * when using presets. 75 */ 76 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 77 clk &= SDHCI_CLOCK_INT_EN; 78 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 79 80 if (clock == 0) 81 return; 82 83 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 84 85 clk |= SDHCI_CLOCK_INT_EN; 86 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 87 88 /* Wait max 20 ms */ 89 if (read_poll_timeout(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE), 90 1000, 20000, false, host, SDHCI_CLOCK_CONTROL)) { 91 pr_err("%s: Internal clock never stabilised.\n", 92 mmc_hostname(host->mmc)); 93 return; 94 } 95 96 clk |= SDHCI_CLOCK_CARD_EN; 97 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 98 } 99 100 static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, 101 unsigned int timing) 102 { 103 u8 mc1r; 104 105 if (timing == MMC_TIMING_MMC_DDR52) { 106 mc1r = sdhci_readb(host, SDMMC_MC1R); 107 mc1r |= SDMMC_MC1R_DDR; 108 sdhci_writeb(host, mc1r, SDMMC_MC1R); 109 } 110 sdhci_set_uhs_signaling(host, timing); 111 } 112 113 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask) 114 { 115 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 116 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 117 unsigned int tmp; 118 119 sdhci_reset(host, mask); 120 121 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) 122 || mmc_gpio_get_cd(host->mmc) >= 0) 123 sdhci_at91_set_force_card_detect(host); 124 125 if (priv->cal_always_on && (mask & SDHCI_RESET_ALL)) { 126 u32 calcr = sdhci_readl(host, SDMMC_CALCR); 127 128 sdhci_writel(host, calcr | SDMMC_CALCR_ALWYSON | SDMMC_CALCR_EN, 129 SDMMC_CALCR); 130 131 if (read_poll_timeout(sdhci_readl, tmp, !(tmp & SDMMC_CALCR_EN), 132 10, 20000, false, host, SDMMC_CALCR)) 133 dev_err(mmc_dev(host->mmc), "Failed to calibrate\n"); 134 } 135 } 136 137 static const struct sdhci_ops sdhci_at91_sama5d2_ops = { 138 .set_clock = sdhci_at91_set_clock, 139 .set_bus_width = sdhci_set_bus_width, 140 .reset = sdhci_at91_reset, 141 .set_uhs_signaling = sdhci_at91_set_uhs_signaling, 142 .set_power = sdhci_set_power_and_bus_voltage, 143 }; 144 145 static const struct sdhci_pltfm_data sdhci_sama5d2_pdata = { 146 .ops = &sdhci_at91_sama5d2_ops, 147 }; 148 149 static const struct sdhci_at91_soc_data soc_data_sama5d2 = { 150 .pdata = &sdhci_sama5d2_pdata, 151 .baseclk_is_generated_internally = false, 152 }; 153 154 static const struct sdhci_at91_soc_data soc_data_sam9x60 = { 155 .pdata = &sdhci_sama5d2_pdata, 156 .baseclk_is_generated_internally = true, 157 .divider_for_baseclk = 2, 158 }; 159 160 static const struct of_device_id sdhci_at91_dt_match[] = { 161 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, 162 { .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 }, 163 {} 164 }; 165 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match); 166 167 static int sdhci_at91_set_clks_presets(struct device *dev) 168 { 169 struct sdhci_host *host = dev_get_drvdata(dev); 170 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 171 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 172 unsigned int caps0, caps1; 173 unsigned int clk_base, clk_mul; 174 unsigned int gck_rate, clk_base_rate; 175 unsigned int preset_div; 176 177 clk_prepare_enable(priv->hclock); 178 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); 179 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); 180 181 gck_rate = clk_get_rate(priv->gck); 182 if (priv->soc_data->baseclk_is_generated_internally) 183 clk_base_rate = gck_rate / priv->soc_data->divider_for_baseclk; 184 else 185 clk_base_rate = clk_get_rate(priv->mainck); 186 187 clk_base = clk_base_rate / 1000000; 188 clk_mul = gck_rate / clk_base_rate - 1; 189 190 caps0 &= ~SDHCI_CLOCK_V3_BASE_MASK; 191 caps0 |= FIELD_PREP(SDHCI_CLOCK_V3_BASE_MASK, clk_base); 192 caps1 &= ~SDHCI_CLOCK_MUL_MASK; 193 caps1 |= FIELD_PREP(SDHCI_CLOCK_MUL_MASK, clk_mul); 194 /* Set capabilities in r/w mode. */ 195 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR); 196 writel(caps0, host->ioaddr + SDHCI_CAPABILITIES); 197 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1); 198 /* Set capabilities in ro mode. */ 199 writel(0, host->ioaddr + SDMMC_CACR); 200 201 dev_dbg(dev, "update clk mul to %u as gck rate is %u Hz and clk base is %u Hz\n", 202 clk_mul, gck_rate, clk_base_rate); 203 204 /* 205 * We have to set preset values because it depends on the clk_mul 206 * value. Moreover, SDR104 is supported in a degraded mode since the 207 * maximum sd clock value is 120 MHz instead of 208 MHz. For that 208 * reason, we need to use presets to support SDR104. 209 */ 210 preset_div = DIV_ROUND_UP(gck_rate, 24000000) - 1; 211 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 212 host->ioaddr + SDHCI_PRESET_FOR_SDR12); 213 preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; 214 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 215 host->ioaddr + SDHCI_PRESET_FOR_SDR25); 216 preset_div = DIV_ROUND_UP(gck_rate, 100000000) - 1; 217 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 218 host->ioaddr + SDHCI_PRESET_FOR_SDR50); 219 preset_div = DIV_ROUND_UP(gck_rate, 120000000) - 1; 220 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 221 host->ioaddr + SDHCI_PRESET_FOR_SDR104); 222 preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; 223 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 224 host->ioaddr + SDHCI_PRESET_FOR_DDR50); 225 226 clk_prepare_enable(priv->mainck); 227 clk_prepare_enable(priv->gck); 228 229 return 0; 230 } 231 232 #ifdef CONFIG_PM_SLEEP 233 static int sdhci_at91_suspend(struct device *dev) 234 { 235 struct sdhci_host *host = dev_get_drvdata(dev); 236 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 237 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 238 int ret; 239 240 ret = pm_runtime_force_suspend(dev); 241 242 priv->restore_needed = true; 243 244 return ret; 245 } 246 #endif /* CONFIG_PM_SLEEP */ 247 248 #ifdef CONFIG_PM 249 static int sdhci_at91_runtime_suspend(struct device *dev) 250 { 251 struct sdhci_host *host = dev_get_drvdata(dev); 252 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 253 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 254 int ret; 255 256 ret = sdhci_runtime_suspend_host(host); 257 258 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 259 mmc_retune_needed(host->mmc); 260 261 clk_disable_unprepare(priv->gck); 262 clk_disable_unprepare(priv->hclock); 263 clk_disable_unprepare(priv->mainck); 264 265 return ret; 266 } 267 268 static int sdhci_at91_runtime_resume(struct device *dev) 269 { 270 struct sdhci_host *host = dev_get_drvdata(dev); 271 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 272 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 273 int ret; 274 275 if (priv->restore_needed) { 276 ret = sdhci_at91_set_clks_presets(dev); 277 if (ret) 278 return ret; 279 280 priv->restore_needed = false; 281 goto out; 282 } 283 284 ret = clk_prepare_enable(priv->mainck); 285 if (ret) { 286 dev_err(dev, "can't enable mainck\n"); 287 return ret; 288 } 289 290 ret = clk_prepare_enable(priv->hclock); 291 if (ret) { 292 dev_err(dev, "can't enable hclock\n"); 293 return ret; 294 } 295 296 ret = clk_prepare_enable(priv->gck); 297 if (ret) { 298 dev_err(dev, "can't enable gck\n"); 299 return ret; 300 } 301 302 out: 303 return sdhci_runtime_resume_host(host, 0); 304 } 305 #endif /* CONFIG_PM */ 306 307 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = { 308 SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume) 309 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend, 310 sdhci_at91_runtime_resume, 311 NULL) 312 }; 313 314 static int sdhci_at91_probe(struct platform_device *pdev) 315 { 316 const struct sdhci_at91_soc_data *soc_data; 317 struct sdhci_host *host; 318 struct sdhci_pltfm_host *pltfm_host; 319 struct sdhci_at91_priv *priv; 320 int ret; 321 322 soc_data = of_device_get_match_data(&pdev->dev); 323 if (!soc_data) 324 return -EINVAL; 325 326 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*priv)); 327 if (IS_ERR(host)) 328 return PTR_ERR(host); 329 330 pltfm_host = sdhci_priv(host); 331 priv = sdhci_pltfm_priv(pltfm_host); 332 priv->soc_data = soc_data; 333 334 priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); 335 if (IS_ERR(priv->mainck)) { 336 if (soc_data->baseclk_is_generated_internally) { 337 priv->mainck = NULL; 338 } else { 339 dev_err(&pdev->dev, "failed to get baseclk\n"); 340 ret = PTR_ERR(priv->mainck); 341 goto sdhci_pltfm_free; 342 } 343 } 344 345 priv->hclock = devm_clk_get(&pdev->dev, "hclock"); 346 if (IS_ERR(priv->hclock)) { 347 dev_err(&pdev->dev, "failed to get hclock\n"); 348 ret = PTR_ERR(priv->hclock); 349 goto sdhci_pltfm_free; 350 } 351 352 priv->gck = devm_clk_get(&pdev->dev, "multclk"); 353 if (IS_ERR(priv->gck)) { 354 dev_err(&pdev->dev, "failed to get multclk\n"); 355 ret = PTR_ERR(priv->gck); 356 goto sdhci_pltfm_free; 357 } 358 359 ret = sdhci_at91_set_clks_presets(&pdev->dev); 360 if (ret) 361 goto sdhci_pltfm_free; 362 363 priv->restore_needed = false; 364 365 /* 366 * if SDCAL pin is wrongly connected, we must enable 367 * the analog calibration cell permanently. 368 */ 369 priv->cal_always_on = 370 device_property_read_bool(&pdev->dev, 371 "microchip,sdcal-inverted"); 372 373 ret = mmc_of_parse(host->mmc); 374 if (ret) 375 goto clocks_disable_unprepare; 376 377 sdhci_get_of_property(pdev); 378 379 pm_runtime_get_noresume(&pdev->dev); 380 pm_runtime_set_active(&pdev->dev); 381 pm_runtime_enable(&pdev->dev); 382 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 383 pm_runtime_use_autosuspend(&pdev->dev); 384 385 /* HS200 is broken at this moment */ 386 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 387 388 ret = sdhci_add_host(host); 389 if (ret) 390 goto pm_runtime_disable; 391 392 /* 393 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes 394 * the assumption that all the clocks of the controller are disabled. 395 * It means we can't get irq from it when it is runtime suspended. 396 * For that reason, it is not planned to wake-up on a card detect irq 397 * from the controller. 398 * If we want to use runtime PM and to be able to wake-up on card 399 * insertion, we have to use a GPIO for the card detection or we can 400 * use polling. Be aware that using polling will resume/suspend the 401 * controller between each attempt. 402 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries 403 * to enable polling via device tree with broken-cd property. 404 */ 405 if (mmc_card_is_removable(host->mmc) && 406 mmc_gpio_get_cd(host->mmc) < 0) { 407 host->mmc->caps |= MMC_CAP_NEEDS_POLL; 408 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 409 } 410 411 /* 412 * If the device attached to the MMC bus is not removable, it is safer 413 * to set the Force Card Detect bit. People often don't connect the 414 * card detect signal and use this pin for another purpose. If the card 415 * detect pin is not muxed to SDHCI controller, a default value is 416 * used. This value can be different from a SoC revision to another 417 * one. Problems come when this default value is not card present. To 418 * avoid this case, if the device is non removable then the card 419 * detection procedure using the SDMCC_CD signal is bypassed. 420 * This bit is reset when a software reset for all command is performed 421 * so we need to implement our own reset function to set back this bit. 422 * 423 * WA: SAMA5D2 doesn't drive CMD if using CD GPIO line. 424 */ 425 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) 426 || mmc_gpio_get_cd(host->mmc) >= 0) 427 sdhci_at91_set_force_card_detect(host); 428 429 pm_runtime_put_autosuspend(&pdev->dev); 430 431 return 0; 432 433 pm_runtime_disable: 434 pm_runtime_disable(&pdev->dev); 435 pm_runtime_set_suspended(&pdev->dev); 436 pm_runtime_put_noidle(&pdev->dev); 437 clocks_disable_unprepare: 438 clk_disable_unprepare(priv->gck); 439 clk_disable_unprepare(priv->mainck); 440 clk_disable_unprepare(priv->hclock); 441 sdhci_pltfm_free: 442 sdhci_pltfm_free(pdev); 443 return ret; 444 } 445 446 static int sdhci_at91_remove(struct platform_device *pdev) 447 { 448 struct sdhci_host *host = platform_get_drvdata(pdev); 449 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 450 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 451 struct clk *gck = priv->gck; 452 struct clk *hclock = priv->hclock; 453 struct clk *mainck = priv->mainck; 454 455 pm_runtime_get_sync(&pdev->dev); 456 pm_runtime_disable(&pdev->dev); 457 pm_runtime_put_noidle(&pdev->dev); 458 459 sdhci_pltfm_unregister(pdev); 460 461 clk_disable_unprepare(gck); 462 clk_disable_unprepare(hclock); 463 clk_disable_unprepare(mainck); 464 465 return 0; 466 } 467 468 static struct platform_driver sdhci_at91_driver = { 469 .driver = { 470 .name = "sdhci-at91", 471 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 472 .of_match_table = sdhci_at91_dt_match, 473 .pm = &sdhci_at91_dev_pm_ops, 474 }, 475 .probe = sdhci_at91_probe, 476 .remove = sdhci_at91_remove, 477 }; 478 479 module_platform_driver(sdhci_at91_driver); 480 481 MODULE_DESCRIPTION("SDHCI driver for at91"); 482 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); 483 MODULE_LICENSE("GPL v2"); 484