1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Atmel SDMMC controller driver. 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/mmc/host.h> 15 #include <linux/mmc/slot-gpio.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_device.h> 19 #include <linux/pm.h> 20 #include <linux/pm_runtime.h> 21 22 #include "sdhci-pltfm.h" 23 24 #define SDMMC_MC1R 0x204 25 #define SDMMC_MC1R_DDR BIT(3) 26 #define SDMMC_MC1R_FCD BIT(7) 27 #define SDMMC_CACR 0x230 28 #define SDMMC_CACR_CAPWREN BIT(0) 29 #define SDMMC_CACR_KEY (0x46 << 8) 30 #define SDMMC_CALCR 0x240 31 #define SDMMC_CALCR_EN BIT(0) 32 #define SDMMC_CALCR_ALWYSON BIT(4) 33 34 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */ 35 36 struct sdhci_at91_priv { 37 struct clk *hclock; 38 struct clk *gck; 39 struct clk *mainck; 40 bool restore_needed; 41 bool cal_always_on; 42 }; 43 44 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host) 45 { 46 u8 mc1r; 47 48 mc1r = readb(host->ioaddr + SDMMC_MC1R); 49 mc1r |= SDMMC_MC1R_FCD; 50 writeb(mc1r, host->ioaddr + SDMMC_MC1R); 51 } 52 53 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock) 54 { 55 u16 clk; 56 unsigned long timeout; 57 58 host->mmc->actual_clock = 0; 59 60 /* 61 * There is no requirement to disable the internal clock before 62 * changing the SD clock configuration. Moreover, disabling the 63 * internal clock, changing the configuration and re-enabling the 64 * internal clock causes some bugs. It can prevent to get the internal 65 * clock stable flag ready and an unexpected switch to the base clock 66 * when using presets. 67 */ 68 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 69 clk &= SDHCI_CLOCK_INT_EN; 70 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 71 72 if (clock == 0) 73 return; 74 75 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 76 77 clk |= SDHCI_CLOCK_INT_EN; 78 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 79 80 /* Wait max 20 ms */ 81 timeout = 20; 82 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 83 & SDHCI_CLOCK_INT_STABLE)) { 84 if (timeout == 0) { 85 pr_err("%s: Internal clock never stabilised.\n", 86 mmc_hostname(host->mmc)); 87 return; 88 } 89 timeout--; 90 mdelay(1); 91 } 92 93 clk |= SDHCI_CLOCK_CARD_EN; 94 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 95 } 96 97 /* 98 * In this specific implementation of the SDHCI controller, the power register 99 * needs to have a valid voltage set even when the power supply is managed by 100 * an external regulator. 101 */ 102 static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode, 103 unsigned short vdd) 104 { 105 if (!IS_ERR(host->mmc->supply.vmmc)) { 106 struct mmc_host *mmc = host->mmc; 107 108 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 109 } 110 sdhci_set_power_noreg(host, mode, vdd); 111 } 112 113 static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, 114 unsigned int timing) 115 { 116 if (timing == MMC_TIMING_MMC_DDR52) 117 sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R); 118 sdhci_set_uhs_signaling(host, timing); 119 } 120 121 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask) 122 { 123 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 124 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 125 126 sdhci_reset(host, mask); 127 128 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 129 sdhci_at91_set_force_card_detect(host); 130 131 if (priv->cal_always_on && (mask & SDHCI_RESET_ALL)) 132 sdhci_writel(host, SDMMC_CALCR_ALWYSON | SDMMC_CALCR_EN, 133 SDMMC_CALCR); 134 } 135 136 static const struct sdhci_ops sdhci_at91_sama5d2_ops = { 137 .set_clock = sdhci_at91_set_clock, 138 .set_bus_width = sdhci_set_bus_width, 139 .reset = sdhci_at91_reset, 140 .set_uhs_signaling = sdhci_at91_set_uhs_signaling, 141 .set_power = sdhci_at91_set_power, 142 }; 143 144 static const struct sdhci_pltfm_data soc_data_sama5d2 = { 145 .ops = &sdhci_at91_sama5d2_ops, 146 }; 147 148 static const struct of_device_id sdhci_at91_dt_match[] = { 149 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, 150 {} 151 }; 152 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match); 153 154 static int sdhci_at91_set_clks_presets(struct device *dev) 155 { 156 struct sdhci_host *host = dev_get_drvdata(dev); 157 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 158 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 159 int ret; 160 unsigned int caps0, caps1; 161 unsigned int clk_base, clk_mul; 162 unsigned int gck_rate, real_gck_rate; 163 unsigned int preset_div; 164 165 /* 166 * The mult clock is provided by as a generated clock by the PMC 167 * controller. In order to set the rate of gck, we have to get the 168 * base clock rate and the clock mult from capabilities. 169 */ 170 clk_prepare_enable(priv->hclock); 171 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); 172 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); 173 clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 174 clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; 175 gck_rate = clk_base * 1000000 * (clk_mul + 1); 176 ret = clk_set_rate(priv->gck, gck_rate); 177 if (ret < 0) { 178 dev_err(dev, "failed to set gck"); 179 clk_disable_unprepare(priv->hclock); 180 return ret; 181 } 182 /* 183 * We need to check if we have the requested rate for gck because in 184 * some cases this rate could be not supported. If it happens, the rate 185 * is the closest one gck can provide. We have to update the value 186 * of clk mul. 187 */ 188 real_gck_rate = clk_get_rate(priv->gck); 189 if (real_gck_rate != gck_rate) { 190 clk_mul = real_gck_rate / (clk_base * 1000000) - 1; 191 caps1 &= (~SDHCI_CLOCK_MUL_MASK); 192 caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & 193 SDHCI_CLOCK_MUL_MASK); 194 /* Set capabilities in r/w mode. */ 195 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, 196 host->ioaddr + SDMMC_CACR); 197 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1); 198 /* Set capabilities in ro mode. */ 199 writel(0, host->ioaddr + SDMMC_CACR); 200 dev_info(dev, "update clk mul to %u as gck rate is %u Hz\n", 201 clk_mul, real_gck_rate); 202 } 203 204 /* 205 * We have to set preset values because it depends on the clk_mul 206 * value. Moreover, SDR104 is supported in a degraded mode since the 207 * maximum sd clock value is 120 MHz instead of 208 MHz. For that 208 * reason, we need to use presets to support SDR104. 209 */ 210 preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1; 211 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 212 host->ioaddr + SDHCI_PRESET_FOR_SDR12); 213 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1; 214 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 215 host->ioaddr + SDHCI_PRESET_FOR_SDR25); 216 preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1; 217 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 218 host->ioaddr + SDHCI_PRESET_FOR_SDR50); 219 preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1; 220 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 221 host->ioaddr + SDHCI_PRESET_FOR_SDR104); 222 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1; 223 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 224 host->ioaddr + SDHCI_PRESET_FOR_DDR50); 225 226 clk_prepare_enable(priv->mainck); 227 clk_prepare_enable(priv->gck); 228 229 return 0; 230 } 231 232 #ifdef CONFIG_PM_SLEEP 233 static int sdhci_at91_suspend(struct device *dev) 234 { 235 struct sdhci_host *host = dev_get_drvdata(dev); 236 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 237 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 238 int ret; 239 240 ret = pm_runtime_force_suspend(dev); 241 242 priv->restore_needed = true; 243 244 return ret; 245 } 246 #endif /* CONFIG_PM_SLEEP */ 247 248 #ifdef CONFIG_PM 249 static int sdhci_at91_runtime_suspend(struct device *dev) 250 { 251 struct sdhci_host *host = dev_get_drvdata(dev); 252 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 253 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 254 int ret; 255 256 ret = sdhci_runtime_suspend_host(host); 257 258 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 259 mmc_retune_needed(host->mmc); 260 261 clk_disable_unprepare(priv->gck); 262 clk_disable_unprepare(priv->hclock); 263 clk_disable_unprepare(priv->mainck); 264 265 return ret; 266 } 267 268 static int sdhci_at91_runtime_resume(struct device *dev) 269 { 270 struct sdhci_host *host = dev_get_drvdata(dev); 271 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 272 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 273 int ret; 274 275 if (priv->restore_needed) { 276 ret = sdhci_at91_set_clks_presets(dev); 277 if (ret) 278 return ret; 279 280 priv->restore_needed = false; 281 goto out; 282 } 283 284 ret = clk_prepare_enable(priv->mainck); 285 if (ret) { 286 dev_err(dev, "can't enable mainck\n"); 287 return ret; 288 } 289 290 ret = clk_prepare_enable(priv->hclock); 291 if (ret) { 292 dev_err(dev, "can't enable hclock\n"); 293 return ret; 294 } 295 296 ret = clk_prepare_enable(priv->gck); 297 if (ret) { 298 dev_err(dev, "can't enable gck\n"); 299 return ret; 300 } 301 302 out: 303 return sdhci_runtime_resume_host(host, 0); 304 } 305 #endif /* CONFIG_PM */ 306 307 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = { 308 SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume) 309 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend, 310 sdhci_at91_runtime_resume, 311 NULL) 312 }; 313 314 static int sdhci_at91_probe(struct platform_device *pdev) 315 { 316 const struct of_device_id *match; 317 const struct sdhci_pltfm_data *soc_data; 318 struct sdhci_host *host; 319 struct sdhci_pltfm_host *pltfm_host; 320 struct sdhci_at91_priv *priv; 321 int ret; 322 323 match = of_match_device(sdhci_at91_dt_match, &pdev->dev); 324 if (!match) 325 return -EINVAL; 326 soc_data = match->data; 327 328 host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv)); 329 if (IS_ERR(host)) 330 return PTR_ERR(host); 331 332 pltfm_host = sdhci_priv(host); 333 priv = sdhci_pltfm_priv(pltfm_host); 334 335 priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); 336 if (IS_ERR(priv->mainck)) { 337 dev_err(&pdev->dev, "failed to get baseclk\n"); 338 return PTR_ERR(priv->mainck); 339 } 340 341 priv->hclock = devm_clk_get(&pdev->dev, "hclock"); 342 if (IS_ERR(priv->hclock)) { 343 dev_err(&pdev->dev, "failed to get hclock\n"); 344 return PTR_ERR(priv->hclock); 345 } 346 347 priv->gck = devm_clk_get(&pdev->dev, "multclk"); 348 if (IS_ERR(priv->gck)) { 349 dev_err(&pdev->dev, "failed to get multclk\n"); 350 return PTR_ERR(priv->gck); 351 } 352 353 ret = sdhci_at91_set_clks_presets(&pdev->dev); 354 if (ret) 355 goto sdhci_pltfm_free; 356 357 priv->restore_needed = false; 358 359 /* 360 * if SDCAL pin is wrongly connected, we must enable 361 * the analog calibration cell permanently. 362 */ 363 priv->cal_always_on = 364 device_property_read_bool(&pdev->dev, 365 "microchip,sdcal-inverted"); 366 367 ret = mmc_of_parse(host->mmc); 368 if (ret) 369 goto clocks_disable_unprepare; 370 371 sdhci_get_of_property(pdev); 372 373 pm_runtime_get_noresume(&pdev->dev); 374 pm_runtime_set_active(&pdev->dev); 375 pm_runtime_enable(&pdev->dev); 376 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 377 pm_runtime_use_autosuspend(&pdev->dev); 378 379 /* HS200 is broken at this moment */ 380 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 381 382 ret = sdhci_add_host(host); 383 if (ret) 384 goto pm_runtime_disable; 385 386 /* 387 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes 388 * the assumption that all the clocks of the controller are disabled. 389 * It means we can't get irq from it when it is runtime suspended. 390 * For that reason, it is not planned to wake-up on a card detect irq 391 * from the controller. 392 * If we want to use runtime PM and to be able to wake-up on card 393 * insertion, we have to use a GPIO for the card detection or we can 394 * use polling. Be aware that using polling will resume/suspend the 395 * controller between each attempt. 396 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries 397 * to enable polling via device tree with broken-cd property. 398 */ 399 if (mmc_card_is_removable(host->mmc) && 400 mmc_gpio_get_cd(host->mmc) < 0) { 401 host->mmc->caps |= MMC_CAP_NEEDS_POLL; 402 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 403 } 404 405 /* 406 * If the device attached to the MMC bus is not removable, it is safer 407 * to set the Force Card Detect bit. People often don't connect the 408 * card detect signal and use this pin for another purpose. If the card 409 * detect pin is not muxed to SDHCI controller, a default value is 410 * used. This value can be different from a SoC revision to another 411 * one. Problems come when this default value is not card present. To 412 * avoid this case, if the device is non removable then the card 413 * detection procedure using the SDMCC_CD signal is bypassed. 414 * This bit is reset when a software reset for all command is performed 415 * so we need to implement our own reset function to set back this bit. 416 */ 417 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 418 sdhci_at91_set_force_card_detect(host); 419 420 pm_runtime_put_autosuspend(&pdev->dev); 421 422 return 0; 423 424 pm_runtime_disable: 425 pm_runtime_disable(&pdev->dev); 426 pm_runtime_set_suspended(&pdev->dev); 427 pm_runtime_put_noidle(&pdev->dev); 428 clocks_disable_unprepare: 429 clk_disable_unprepare(priv->gck); 430 clk_disable_unprepare(priv->mainck); 431 clk_disable_unprepare(priv->hclock); 432 sdhci_pltfm_free: 433 sdhci_pltfm_free(pdev); 434 return ret; 435 } 436 437 static int sdhci_at91_remove(struct platform_device *pdev) 438 { 439 struct sdhci_host *host = platform_get_drvdata(pdev); 440 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 441 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 442 struct clk *gck = priv->gck; 443 struct clk *hclock = priv->hclock; 444 struct clk *mainck = priv->mainck; 445 446 pm_runtime_get_sync(&pdev->dev); 447 pm_runtime_disable(&pdev->dev); 448 pm_runtime_put_noidle(&pdev->dev); 449 450 sdhci_pltfm_unregister(pdev); 451 452 clk_disable_unprepare(gck); 453 clk_disable_unprepare(hclock); 454 clk_disable_unprepare(mainck); 455 456 return 0; 457 } 458 459 static struct platform_driver sdhci_at91_driver = { 460 .driver = { 461 .name = "sdhci-at91", 462 .of_match_table = sdhci_at91_dt_match, 463 .pm = &sdhci_at91_dev_pm_ops, 464 }, 465 .probe = sdhci_at91_probe, 466 .remove = sdhci_at91_remove, 467 }; 468 469 module_platform_driver(sdhci_at91_driver); 470 471 MODULE_DESCRIPTION("SDHCI driver for at91"); 472 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); 473 MODULE_LICENSE("GPL v2"); 474