19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2bb5f8ea4Sludovic.desroches@atmel.com /* 3bb5f8ea4Sludovic.desroches@atmel.com * Atmel SDMMC controller driver. 4bb5f8ea4Sludovic.desroches@atmel.com * 5bb5f8ea4Sludovic.desroches@atmel.com * Copyright (C) 2015 Atmel, 6bb5f8ea4Sludovic.desroches@atmel.com * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7bb5f8ea4Sludovic.desroches@atmel.com */ 8bb5f8ea4Sludovic.desroches@atmel.com 9bb5f8ea4Sludovic.desroches@atmel.com #include <linux/clk.h> 104e289a7dSLudovic Desroches #include <linux/delay.h> 11bb5f8ea4Sludovic.desroches@atmel.com #include <linux/err.h> 12bb5f8ea4Sludovic.desroches@atmel.com #include <linux/io.h> 134406433dSLudovic Desroches #include <linux/kernel.h> 14bb5f8ea4Sludovic.desroches@atmel.com #include <linux/mmc/host.h> 1564e5cd72Sludovic.desroches@atmel.com #include <linux/mmc/slot-gpio.h> 16bb5f8ea4Sludovic.desroches@atmel.com #include <linux/module.h> 17bb5f8ea4Sludovic.desroches@atmel.com #include <linux/of.h> 18bb5f8ea4Sludovic.desroches@atmel.com #include <linux/of_device.h> 19f5f17813Sludovic.desroches@atmel.com #include <linux/pm.h> 20f5f17813Sludovic.desroches@atmel.com #include <linux/pm_runtime.h> 21bb5f8ea4Sludovic.desroches@atmel.com 22bb5f8ea4Sludovic.desroches@atmel.com #include "sdhci-pltfm.h" 23bb5f8ea4Sludovic.desroches@atmel.com 24d0918764SLudovic Desroches #define SDMMC_MC1R 0x204 25d0918764SLudovic Desroches #define SDMMC_MC1R_DDR BIT(3) 267a1e3f14SLudovic Desroches #define SDMMC_MC1R_FCD BIT(7) 27bb5f8ea4Sludovic.desroches@atmel.com #define SDMMC_CACR 0x230 28bb5f8ea4Sludovic.desroches@atmel.com #define SDMMC_CACR_CAPWREN BIT(0) 29bb5f8ea4Sludovic.desroches@atmel.com #define SDMMC_CACR_KEY (0x46 << 8) 30727d836aSNicolas Ferre #define SDMMC_CALCR 0x240 31727d836aSNicolas Ferre #define SDMMC_CALCR_EN BIT(0) 32727d836aSNicolas Ferre #define SDMMC_CALCR_ALWYSON BIT(4) 33bb5f8ea4Sludovic.desroches@atmel.com 344406433dSLudovic Desroches #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */ 354406433dSLudovic Desroches 363976656dSLudovic Desroches struct sdhci_at91_soc_data { 373976656dSLudovic Desroches const struct sdhci_pltfm_data *pdata; 383976656dSLudovic Desroches bool baseclk_is_generated_internally; 393976656dSLudovic Desroches unsigned int divider_for_baseclk; 403976656dSLudovic Desroches }; 413976656dSLudovic Desroches 42bb5f8ea4Sludovic.desroches@atmel.com struct sdhci_at91_priv { 433976656dSLudovic Desroches const struct sdhci_at91_soc_data *soc_data; 44bb5f8ea4Sludovic.desroches@atmel.com struct clk *hclock; 45bb5f8ea4Sludovic.desroches@atmel.com struct clk *gck; 46bb5f8ea4Sludovic.desroches@atmel.com struct clk *mainck; 47e2b372ebSQuentin Schulz bool restore_needed; 48727d836aSNicolas Ferre bool cal_always_on; 49bb5f8ea4Sludovic.desroches@atmel.com }; 50bb5f8ea4Sludovic.desroches@atmel.com 517a1e3f14SLudovic Desroches static void sdhci_at91_set_force_card_detect(struct sdhci_host *host) 527a1e3f14SLudovic Desroches { 537a1e3f14SLudovic Desroches u8 mc1r; 547a1e3f14SLudovic Desroches 557a1e3f14SLudovic Desroches mc1r = readb(host->ioaddr + SDMMC_MC1R); 567a1e3f14SLudovic Desroches mc1r |= SDMMC_MC1R_FCD; 577a1e3f14SLudovic Desroches writeb(mc1r, host->ioaddr + SDMMC_MC1R); 587a1e3f14SLudovic Desroches } 597a1e3f14SLudovic Desroches 604e289a7dSLudovic Desroches static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock) 614e289a7dSLudovic Desroches { 624e289a7dSLudovic Desroches u16 clk; 634e289a7dSLudovic Desroches unsigned long timeout; 644e289a7dSLudovic Desroches 654e289a7dSLudovic Desroches host->mmc->actual_clock = 0; 664e289a7dSLudovic Desroches 674e289a7dSLudovic Desroches /* 684e289a7dSLudovic Desroches * There is no requirement to disable the internal clock before 694e289a7dSLudovic Desroches * changing the SD clock configuration. Moreover, disabling the 704e289a7dSLudovic Desroches * internal clock, changing the configuration and re-enabling the 714e289a7dSLudovic Desroches * internal clock causes some bugs. It can prevent to get the internal 724e289a7dSLudovic Desroches * clock stable flag ready and an unexpected switch to the base clock 734e289a7dSLudovic Desroches * when using presets. 744e289a7dSLudovic Desroches */ 754e289a7dSLudovic Desroches clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 764e289a7dSLudovic Desroches clk &= SDHCI_CLOCK_INT_EN; 774e289a7dSLudovic Desroches sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 784e289a7dSLudovic Desroches 794e289a7dSLudovic Desroches if (clock == 0) 804e289a7dSLudovic Desroches return; 814e289a7dSLudovic Desroches 824e289a7dSLudovic Desroches clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 834e289a7dSLudovic Desroches 844e289a7dSLudovic Desroches clk |= SDHCI_CLOCK_INT_EN; 854e289a7dSLudovic Desroches sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 864e289a7dSLudovic Desroches 874e289a7dSLudovic Desroches /* Wait max 20 ms */ 884e289a7dSLudovic Desroches timeout = 20; 894e289a7dSLudovic Desroches while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 904e289a7dSLudovic Desroches & SDHCI_CLOCK_INT_STABLE)) { 914e289a7dSLudovic Desroches if (timeout == 0) { 924e289a7dSLudovic Desroches pr_err("%s: Internal clock never stabilised.\n", 934e289a7dSLudovic Desroches mmc_hostname(host->mmc)); 944e289a7dSLudovic Desroches return; 954e289a7dSLudovic Desroches } 964e289a7dSLudovic Desroches timeout--; 974e289a7dSLudovic Desroches mdelay(1); 984e289a7dSLudovic Desroches } 994e289a7dSLudovic Desroches 1004e289a7dSLudovic Desroches clk |= SDHCI_CLOCK_CARD_EN; 1014e289a7dSLudovic Desroches sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1024e289a7dSLudovic Desroches } 1034e289a7dSLudovic Desroches 1042ce0c7b6SRomain Izard /* 1052ce0c7b6SRomain Izard * In this specific implementation of the SDHCI controller, the power register 1062ce0c7b6SRomain Izard * needs to have a valid voltage set even when the power supply is managed by 1072ce0c7b6SRomain Izard * an external regulator. 1082ce0c7b6SRomain Izard */ 1092ce0c7b6SRomain Izard static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode, 1102ce0c7b6SRomain Izard unsigned short vdd) 1112ce0c7b6SRomain Izard { 1122ce0c7b6SRomain Izard if (!IS_ERR(host->mmc->supply.vmmc)) { 1132ce0c7b6SRomain Izard struct mmc_host *mmc = host->mmc; 1142ce0c7b6SRomain Izard 1152ce0c7b6SRomain Izard mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 1162ce0c7b6SRomain Izard } 1172ce0c7b6SRomain Izard sdhci_set_power_noreg(host, mode, vdd); 1182ce0c7b6SRomain Izard } 1192ce0c7b6SRomain Izard 120519c51afSColin Ian King static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, 121519c51afSColin Ian King unsigned int timing) 122d0918764SLudovic Desroches { 123d0918764SLudovic Desroches if (timing == MMC_TIMING_MMC_DDR52) 124d0918764SLudovic Desroches sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R); 125d0918764SLudovic Desroches sdhci_set_uhs_signaling(host, timing); 126d0918764SLudovic Desroches } 127d0918764SLudovic Desroches 1287a1e3f14SLudovic Desroches static void sdhci_at91_reset(struct sdhci_host *host, u8 mask) 1297a1e3f14SLudovic Desroches { 130727d836aSNicolas Ferre struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 131727d836aSNicolas Ferre struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 132727d836aSNicolas Ferre 1337a1e3f14SLudovic Desroches sdhci_reset(host, mask); 1347a1e3f14SLudovic Desroches 1357a1e3f14SLudovic Desroches if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 1367a1e3f14SLudovic Desroches sdhci_at91_set_force_card_detect(host); 137727d836aSNicolas Ferre 138727d836aSNicolas Ferre if (priv->cal_always_on && (mask & SDHCI_RESET_ALL)) 139727d836aSNicolas Ferre sdhci_writel(host, SDMMC_CALCR_ALWYSON | SDMMC_CALCR_EN, 140727d836aSNicolas Ferre SDMMC_CALCR); 1417a1e3f14SLudovic Desroches } 1427a1e3f14SLudovic Desroches 143bb5f8ea4Sludovic.desroches@atmel.com static const struct sdhci_ops sdhci_at91_sama5d2_ops = { 1444e289a7dSLudovic Desroches .set_clock = sdhci_at91_set_clock, 145bb5f8ea4Sludovic.desroches@atmel.com .set_bus_width = sdhci_set_bus_width, 1467a1e3f14SLudovic Desroches .reset = sdhci_at91_reset, 147d0918764SLudovic Desroches .set_uhs_signaling = sdhci_at91_set_uhs_signaling, 1482ce0c7b6SRomain Izard .set_power = sdhci_at91_set_power, 149bb5f8ea4Sludovic.desroches@atmel.com }; 150bb5f8ea4Sludovic.desroches@atmel.com 1513976656dSLudovic Desroches static const struct sdhci_pltfm_data sdhci_sama5d2_pdata = { 152bb5f8ea4Sludovic.desroches@atmel.com .ops = &sdhci_at91_sama5d2_ops, 153bb5f8ea4Sludovic.desroches@atmel.com }; 154bb5f8ea4Sludovic.desroches@atmel.com 1553976656dSLudovic Desroches static const struct sdhci_at91_soc_data soc_data_sama5d2 = { 1563976656dSLudovic Desroches .pdata = &sdhci_sama5d2_pdata, 1573976656dSLudovic Desroches .baseclk_is_generated_internally = false, 1583976656dSLudovic Desroches }; 1593976656dSLudovic Desroches 1603976656dSLudovic Desroches static const struct sdhci_at91_soc_data soc_data_sam9x60 = { 1613976656dSLudovic Desroches .pdata = &sdhci_sama5d2_pdata, 1623976656dSLudovic Desroches .baseclk_is_generated_internally = true, 1633976656dSLudovic Desroches .divider_for_baseclk = 2, 1643976656dSLudovic Desroches }; 1653976656dSLudovic Desroches 166bb5f8ea4Sludovic.desroches@atmel.com static const struct of_device_id sdhci_at91_dt_match[] = { 167bb5f8ea4Sludovic.desroches@atmel.com { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, 1683976656dSLudovic Desroches { .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 }, 169bb5f8ea4Sludovic.desroches@atmel.com {} 170bb5f8ea4Sludovic.desroches@atmel.com }; 171d9943c68SJavier Martinez Canillas MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match); 172bb5f8ea4Sludovic.desroches@atmel.com 173c8a019e7SQuentin Schulz static int sdhci_at91_set_clks_presets(struct device *dev) 174c8a019e7SQuentin Schulz { 175c8a019e7SQuentin Schulz struct sdhci_host *host = dev_get_drvdata(dev); 176c8a019e7SQuentin Schulz struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 177c8a019e7SQuentin Schulz struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 178c8a019e7SQuentin Schulz unsigned int caps0, caps1; 179c8a019e7SQuentin Schulz unsigned int clk_base, clk_mul; 1803976656dSLudovic Desroches unsigned int gck_rate, clk_base_rate; 181c8a019e7SQuentin Schulz unsigned int preset_div; 182c8a019e7SQuentin Schulz 183c8a019e7SQuentin Schulz clk_prepare_enable(priv->hclock); 184c8a019e7SQuentin Schulz caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); 185c8a019e7SQuentin Schulz caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); 1863976656dSLudovic Desroches 1873976656dSLudovic Desroches gck_rate = clk_get_rate(priv->gck); 1883976656dSLudovic Desroches if (priv->soc_data->baseclk_is_generated_internally) 1893976656dSLudovic Desroches clk_base_rate = gck_rate / priv->soc_data->divider_for_baseclk; 1903976656dSLudovic Desroches else 1913976656dSLudovic Desroches clk_base_rate = clk_get_rate(priv->mainck); 1923976656dSLudovic Desroches 1933976656dSLudovic Desroches clk_base = clk_base_rate / 1000000; 1943976656dSLudovic Desroches clk_mul = gck_rate / clk_base_rate - 1; 1953976656dSLudovic Desroches 1963976656dSLudovic Desroches caps0 &= ~SDHCI_CLOCK_V3_BASE_MASK; 1973976656dSLudovic Desroches caps0 |= (clk_base << SDHCI_CLOCK_BASE_SHIFT) & SDHCI_CLOCK_V3_BASE_MASK; 1983976656dSLudovic Desroches caps1 &= ~SDHCI_CLOCK_MUL_MASK; 1993976656dSLudovic Desroches caps1 |= (clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK; 200c8a019e7SQuentin Schulz /* Set capabilities in r/w mode. */ 2013976656dSLudovic Desroches writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR); 2023976656dSLudovic Desroches writel(caps0, host->ioaddr + SDHCI_CAPABILITIES); 203c8a019e7SQuentin Schulz writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1); 204c8a019e7SQuentin Schulz /* Set capabilities in ro mode. */ 205c8a019e7SQuentin Schulz writel(0, host->ioaddr + SDMMC_CACR); 2063976656dSLudovic Desroches 2073976656dSLudovic Desroches dev_info(dev, "update clk mul to %u as gck rate is %u Hz and clk base is %u Hz\n", 2083976656dSLudovic Desroches clk_mul, gck_rate, clk_base_rate); 209c8a019e7SQuentin Schulz 210c8a019e7SQuentin Schulz /* 211c8a019e7SQuentin Schulz * We have to set preset values because it depends on the clk_mul 212c8a019e7SQuentin Schulz * value. Moreover, SDR104 is supported in a degraded mode since the 213c8a019e7SQuentin Schulz * maximum sd clock value is 120 MHz instead of 208 MHz. For that 214c8a019e7SQuentin Schulz * reason, we need to use presets to support SDR104. 215c8a019e7SQuentin Schulz */ 2163976656dSLudovic Desroches preset_div = DIV_ROUND_UP(gck_rate, 24000000) - 1; 217c8a019e7SQuentin Schulz writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 218c8a019e7SQuentin Schulz host->ioaddr + SDHCI_PRESET_FOR_SDR12); 2193976656dSLudovic Desroches preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; 220c8a019e7SQuentin Schulz writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 221c8a019e7SQuentin Schulz host->ioaddr + SDHCI_PRESET_FOR_SDR25); 2223976656dSLudovic Desroches preset_div = DIV_ROUND_UP(gck_rate, 100000000) - 1; 223c8a019e7SQuentin Schulz writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 224c8a019e7SQuentin Schulz host->ioaddr + SDHCI_PRESET_FOR_SDR50); 2253976656dSLudovic Desroches preset_div = DIV_ROUND_UP(gck_rate, 120000000) - 1; 226c8a019e7SQuentin Schulz writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 227c8a019e7SQuentin Schulz host->ioaddr + SDHCI_PRESET_FOR_SDR104); 2283976656dSLudovic Desroches preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; 229c8a019e7SQuentin Schulz writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 230c8a019e7SQuentin Schulz host->ioaddr + SDHCI_PRESET_FOR_DDR50); 231c8a019e7SQuentin Schulz 232c8a019e7SQuentin Schulz clk_prepare_enable(priv->mainck); 233c8a019e7SQuentin Schulz clk_prepare_enable(priv->gck); 234c8a019e7SQuentin Schulz 235c8a019e7SQuentin Schulz return 0; 236c8a019e7SQuentin Schulz } 237c8a019e7SQuentin Schulz 238e2b372ebSQuentin Schulz #ifdef CONFIG_PM_SLEEP 239e2b372ebSQuentin Schulz static int sdhci_at91_suspend(struct device *dev) 240e2b372ebSQuentin Schulz { 241e2b372ebSQuentin Schulz struct sdhci_host *host = dev_get_drvdata(dev); 242e2b372ebSQuentin Schulz struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 243e2b372ebSQuentin Schulz struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 244e2b372ebSQuentin Schulz int ret; 245e2b372ebSQuentin Schulz 246e2b372ebSQuentin Schulz ret = pm_runtime_force_suspend(dev); 247e2b372ebSQuentin Schulz 248e2b372ebSQuentin Schulz priv->restore_needed = true; 249e2b372ebSQuentin Schulz 250e2b372ebSQuentin Schulz return ret; 251e2b372ebSQuentin Schulz } 252e2b372ebSQuentin Schulz #endif /* CONFIG_PM_SLEEP */ 253e2b372ebSQuentin Schulz 254f5f17813Sludovic.desroches@atmel.com #ifdef CONFIG_PM 255f5f17813Sludovic.desroches@atmel.com static int sdhci_at91_runtime_suspend(struct device *dev) 256f5f17813Sludovic.desroches@atmel.com { 257f5f17813Sludovic.desroches@atmel.com struct sdhci_host *host = dev_get_drvdata(dev); 258f5f17813Sludovic.desroches@atmel.com struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 25910f1c135SJisheng Zhang struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 260f5f17813Sludovic.desroches@atmel.com int ret; 261f5f17813Sludovic.desroches@atmel.com 262f5f17813Sludovic.desroches@atmel.com ret = sdhci_runtime_suspend_host(host); 263f5f17813Sludovic.desroches@atmel.com 264d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 265d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 266d38dcad4SAdrian Hunter 267f5f17813Sludovic.desroches@atmel.com clk_disable_unprepare(priv->gck); 268f5f17813Sludovic.desroches@atmel.com clk_disable_unprepare(priv->hclock); 269f5f17813Sludovic.desroches@atmel.com clk_disable_unprepare(priv->mainck); 270f5f17813Sludovic.desroches@atmel.com 271f5f17813Sludovic.desroches@atmel.com return ret; 272f5f17813Sludovic.desroches@atmel.com } 273f5f17813Sludovic.desroches@atmel.com 274f5f17813Sludovic.desroches@atmel.com static int sdhci_at91_runtime_resume(struct device *dev) 275f5f17813Sludovic.desroches@atmel.com { 276f5f17813Sludovic.desroches@atmel.com struct sdhci_host *host = dev_get_drvdata(dev); 277f5f17813Sludovic.desroches@atmel.com struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 27810f1c135SJisheng Zhang struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 279f5f17813Sludovic.desroches@atmel.com int ret; 280f5f17813Sludovic.desroches@atmel.com 281e2b372ebSQuentin Schulz if (priv->restore_needed) { 282e2b372ebSQuentin Schulz ret = sdhci_at91_set_clks_presets(dev); 283e2b372ebSQuentin Schulz if (ret) 284e2b372ebSQuentin Schulz return ret; 285e2b372ebSQuentin Schulz 286e2b372ebSQuentin Schulz priv->restore_needed = false; 287e2b372ebSQuentin Schulz goto out; 288e2b372ebSQuentin Schulz } 289e2b372ebSQuentin Schulz 290f5f17813Sludovic.desroches@atmel.com ret = clk_prepare_enable(priv->mainck); 291f5f17813Sludovic.desroches@atmel.com if (ret) { 292f5f17813Sludovic.desroches@atmel.com dev_err(dev, "can't enable mainck\n"); 293f5f17813Sludovic.desroches@atmel.com return ret; 294f5f17813Sludovic.desroches@atmel.com } 295f5f17813Sludovic.desroches@atmel.com 296f5f17813Sludovic.desroches@atmel.com ret = clk_prepare_enable(priv->hclock); 297f5f17813Sludovic.desroches@atmel.com if (ret) { 298f5f17813Sludovic.desroches@atmel.com dev_err(dev, "can't enable hclock\n"); 299f5f17813Sludovic.desroches@atmel.com return ret; 300f5f17813Sludovic.desroches@atmel.com } 301f5f17813Sludovic.desroches@atmel.com 302f5f17813Sludovic.desroches@atmel.com ret = clk_prepare_enable(priv->gck); 303f5f17813Sludovic.desroches@atmel.com if (ret) { 304f5f17813Sludovic.desroches@atmel.com dev_err(dev, "can't enable gck\n"); 305f5f17813Sludovic.desroches@atmel.com return ret; 306f5f17813Sludovic.desroches@atmel.com } 307f5f17813Sludovic.desroches@atmel.com 308e2b372ebSQuentin Schulz out: 309c6303c5dSBaolin Wang return sdhci_runtime_resume_host(host, 0); 310f5f17813Sludovic.desroches@atmel.com } 311f5f17813Sludovic.desroches@atmel.com #endif /* CONFIG_PM */ 312f5f17813Sludovic.desroches@atmel.com 313f5f17813Sludovic.desroches@atmel.com static const struct dev_pm_ops sdhci_at91_dev_pm_ops = { 314e2b372ebSQuentin Schulz SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume) 315f5f17813Sludovic.desroches@atmel.com SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend, 316f5f17813Sludovic.desroches@atmel.com sdhci_at91_runtime_resume, 317f5f17813Sludovic.desroches@atmel.com NULL) 318f5f17813Sludovic.desroches@atmel.com }; 319f5f17813Sludovic.desroches@atmel.com 320bb5f8ea4Sludovic.desroches@atmel.com static int sdhci_at91_probe(struct platform_device *pdev) 321bb5f8ea4Sludovic.desroches@atmel.com { 322bb5f8ea4Sludovic.desroches@atmel.com const struct of_device_id *match; 3233976656dSLudovic Desroches const struct sdhci_at91_soc_data *soc_data; 324bb5f8ea4Sludovic.desroches@atmel.com struct sdhci_host *host; 325bb5f8ea4Sludovic.desroches@atmel.com struct sdhci_pltfm_host *pltfm_host; 326bb5f8ea4Sludovic.desroches@atmel.com struct sdhci_at91_priv *priv; 327bb5f8ea4Sludovic.desroches@atmel.com int ret; 328bb5f8ea4Sludovic.desroches@atmel.com 329bb5f8ea4Sludovic.desroches@atmel.com match = of_match_device(sdhci_at91_dt_match, &pdev->dev); 330bb5f8ea4Sludovic.desroches@atmel.com if (!match) 331bb5f8ea4Sludovic.desroches@atmel.com return -EINVAL; 332bb5f8ea4Sludovic.desroches@atmel.com soc_data = match->data; 333bb5f8ea4Sludovic.desroches@atmel.com 3343976656dSLudovic Desroches host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*priv)); 33510f1c135SJisheng Zhang if (IS_ERR(host)) 33610f1c135SJisheng Zhang return PTR_ERR(host); 33710f1c135SJisheng Zhang 33810f1c135SJisheng Zhang pltfm_host = sdhci_priv(host); 33910f1c135SJisheng Zhang priv = sdhci_pltfm_priv(pltfm_host); 3403976656dSLudovic Desroches priv->soc_data = soc_data; 341bb5f8ea4Sludovic.desroches@atmel.com 342bb5f8ea4Sludovic.desroches@atmel.com priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); 343bb5f8ea4Sludovic.desroches@atmel.com if (IS_ERR(priv->mainck)) { 3443976656dSLudovic Desroches if (soc_data->baseclk_is_generated_internally) { 3453976656dSLudovic Desroches priv->mainck = NULL; 3463976656dSLudovic Desroches } else { 347bb5f8ea4Sludovic.desroches@atmel.com dev_err(&pdev->dev, "failed to get baseclk\n"); 348a04184ceSMichał Mirosław ret = PTR_ERR(priv->mainck); 349a04184ceSMichał Mirosław goto sdhci_pltfm_free; 350bb5f8ea4Sludovic.desroches@atmel.com } 3513976656dSLudovic Desroches } 352bb5f8ea4Sludovic.desroches@atmel.com 353bb5f8ea4Sludovic.desroches@atmel.com priv->hclock = devm_clk_get(&pdev->dev, "hclock"); 354bb5f8ea4Sludovic.desroches@atmel.com if (IS_ERR(priv->hclock)) { 355bb5f8ea4Sludovic.desroches@atmel.com dev_err(&pdev->dev, "failed to get hclock\n"); 356a04184ceSMichał Mirosław ret = PTR_ERR(priv->hclock); 357a04184ceSMichał Mirosław goto sdhci_pltfm_free; 358bb5f8ea4Sludovic.desroches@atmel.com } 359bb5f8ea4Sludovic.desroches@atmel.com 360bb5f8ea4Sludovic.desroches@atmel.com priv->gck = devm_clk_get(&pdev->dev, "multclk"); 361bb5f8ea4Sludovic.desroches@atmel.com if (IS_ERR(priv->gck)) { 362bb5f8ea4Sludovic.desroches@atmel.com dev_err(&pdev->dev, "failed to get multclk\n"); 363a04184ceSMichał Mirosław ret = PTR_ERR(priv->gck); 364a04184ceSMichał Mirosław goto sdhci_pltfm_free; 365bb5f8ea4Sludovic.desroches@atmel.com } 366bb5f8ea4Sludovic.desroches@atmel.com 367c8a019e7SQuentin Schulz ret = sdhci_at91_set_clks_presets(&pdev->dev); 368c8a019e7SQuentin Schulz if (ret) 369c8a019e7SQuentin Schulz goto sdhci_pltfm_free; 370bb5f8ea4Sludovic.desroches@atmel.com 371e2b372ebSQuentin Schulz priv->restore_needed = false; 372e2b372ebSQuentin Schulz 373727d836aSNicolas Ferre /* 374727d836aSNicolas Ferre * if SDCAL pin is wrongly connected, we must enable 375727d836aSNicolas Ferre * the analog calibration cell permanently. 376727d836aSNicolas Ferre */ 377727d836aSNicolas Ferre priv->cal_always_on = 378727d836aSNicolas Ferre device_property_read_bool(&pdev->dev, 379727d836aSNicolas Ferre "microchip,sdcal-inverted"); 380727d836aSNicolas Ferre 381bb5f8ea4Sludovic.desroches@atmel.com ret = mmc_of_parse(host->mmc); 382bb5f8ea4Sludovic.desroches@atmel.com if (ret) 383bb5f8ea4Sludovic.desroches@atmel.com goto clocks_disable_unprepare; 384bb5f8ea4Sludovic.desroches@atmel.com 385bb5f8ea4Sludovic.desroches@atmel.com sdhci_get_of_property(pdev); 386bb5f8ea4Sludovic.desroches@atmel.com 387f5f17813Sludovic.desroches@atmel.com pm_runtime_get_noresume(&pdev->dev); 388f5f17813Sludovic.desroches@atmel.com pm_runtime_set_active(&pdev->dev); 389f5f17813Sludovic.desroches@atmel.com pm_runtime_enable(&pdev->dev); 390f5f17813Sludovic.desroches@atmel.com pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 391f5f17813Sludovic.desroches@atmel.com pm_runtime_use_autosuspend(&pdev->dev); 392f5f17813Sludovic.desroches@atmel.com 3937871aa60SEugen Hristev /* HS200 is broken at this moment */ 394fed23c58SEugen Hristev host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 3957871aa60SEugen Hristev 396bb5f8ea4Sludovic.desroches@atmel.com ret = sdhci_add_host(host); 397bb5f8ea4Sludovic.desroches@atmel.com if (ret) 398f5f17813Sludovic.desroches@atmel.com goto pm_runtime_disable; 399f5f17813Sludovic.desroches@atmel.com 40064e5cd72Sludovic.desroches@atmel.com /* 40164e5cd72Sludovic.desroches@atmel.com * When calling sdhci_runtime_suspend_host(), the sdhci layer makes 40264e5cd72Sludovic.desroches@atmel.com * the assumption that all the clocks of the controller are disabled. 40364e5cd72Sludovic.desroches@atmel.com * It means we can't get irq from it when it is runtime suspended. 40464e5cd72Sludovic.desroches@atmel.com * For that reason, it is not planned to wake-up on a card detect irq 40564e5cd72Sludovic.desroches@atmel.com * from the controller. 40664e5cd72Sludovic.desroches@atmel.com * If we want to use runtime PM and to be able to wake-up on card 40764e5cd72Sludovic.desroches@atmel.com * insertion, we have to use a GPIO for the card detection or we can 40864e5cd72Sludovic.desroches@atmel.com * use polling. Be aware that using polling will resume/suspend the 40964e5cd72Sludovic.desroches@atmel.com * controller between each attempt. 41064e5cd72Sludovic.desroches@atmel.com * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries 41164e5cd72Sludovic.desroches@atmel.com * to enable polling via device tree with broken-cd property. 41264e5cd72Sludovic.desroches@atmel.com */ 413860951c5SJaehoon Chung if (mmc_card_is_removable(host->mmc) && 414287980e4SArnd Bergmann mmc_gpio_get_cd(host->mmc) < 0) { 41564e5cd72Sludovic.desroches@atmel.com host->mmc->caps |= MMC_CAP_NEEDS_POLL; 41664e5cd72Sludovic.desroches@atmel.com host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 41764e5cd72Sludovic.desroches@atmel.com } 41864e5cd72Sludovic.desroches@atmel.com 4197a1e3f14SLudovic Desroches /* 4207a1e3f14SLudovic Desroches * If the device attached to the MMC bus is not removable, it is safer 4217a1e3f14SLudovic Desroches * to set the Force Card Detect bit. People often don't connect the 4227a1e3f14SLudovic Desroches * card detect signal and use this pin for another purpose. If the card 4237a1e3f14SLudovic Desroches * detect pin is not muxed to SDHCI controller, a default value is 4247a1e3f14SLudovic Desroches * used. This value can be different from a SoC revision to another 4257a1e3f14SLudovic Desroches * one. Problems come when this default value is not card present. To 4267a1e3f14SLudovic Desroches * avoid this case, if the device is non removable then the card 4277a1e3f14SLudovic Desroches * detection procedure using the SDMCC_CD signal is bypassed. 4287a1e3f14SLudovic Desroches * This bit is reset when a software reset for all command is performed 4297a1e3f14SLudovic Desroches * so we need to implement our own reset function to set back this bit. 4307a1e3f14SLudovic Desroches */ 4317a1e3f14SLudovic Desroches if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 4327a1e3f14SLudovic Desroches sdhci_at91_set_force_card_detect(host); 4337a1e3f14SLudovic Desroches 434f5f17813Sludovic.desroches@atmel.com pm_runtime_put_autosuspend(&pdev->dev); 435bb5f8ea4Sludovic.desroches@atmel.com 436bb5f8ea4Sludovic.desroches@atmel.com return 0; 437bb5f8ea4Sludovic.desroches@atmel.com 438f5f17813Sludovic.desroches@atmel.com pm_runtime_disable: 439f5f17813Sludovic.desroches@atmel.com pm_runtime_disable(&pdev->dev); 440f5f17813Sludovic.desroches@atmel.com pm_runtime_set_suspended(&pdev->dev); 4412df9d58fSJisheng Zhang pm_runtime_put_noidle(&pdev->dev); 442bb5f8ea4Sludovic.desroches@atmel.com clocks_disable_unprepare: 443bb5f8ea4Sludovic.desroches@atmel.com clk_disable_unprepare(priv->gck); 444bb5f8ea4Sludovic.desroches@atmel.com clk_disable_unprepare(priv->mainck); 445bb5f8ea4Sludovic.desroches@atmel.com clk_disable_unprepare(priv->hclock); 446c8a019e7SQuentin Schulz sdhci_pltfm_free: 447bb5f8ea4Sludovic.desroches@atmel.com sdhci_pltfm_free(pdev); 448bb5f8ea4Sludovic.desroches@atmel.com return ret; 449bb5f8ea4Sludovic.desroches@atmel.com } 450bb5f8ea4Sludovic.desroches@atmel.com 451bb5f8ea4Sludovic.desroches@atmel.com static int sdhci_at91_remove(struct platform_device *pdev) 452bb5f8ea4Sludovic.desroches@atmel.com { 453bb5f8ea4Sludovic.desroches@atmel.com struct sdhci_host *host = platform_get_drvdata(pdev); 454bb5f8ea4Sludovic.desroches@atmel.com struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 45510f1c135SJisheng Zhang struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 45610f1c135SJisheng Zhang struct clk *gck = priv->gck; 45710f1c135SJisheng Zhang struct clk *hclock = priv->hclock; 45810f1c135SJisheng Zhang struct clk *mainck = priv->mainck; 459bb5f8ea4Sludovic.desroches@atmel.com 460f5f17813Sludovic.desroches@atmel.com pm_runtime_get_sync(&pdev->dev); 461f5f17813Sludovic.desroches@atmel.com pm_runtime_disable(&pdev->dev); 462f5f17813Sludovic.desroches@atmel.com pm_runtime_put_noidle(&pdev->dev); 463f5f17813Sludovic.desroches@atmel.com 464bb5f8ea4Sludovic.desroches@atmel.com sdhci_pltfm_unregister(pdev); 465bb5f8ea4Sludovic.desroches@atmel.com 46610f1c135SJisheng Zhang clk_disable_unprepare(gck); 46710f1c135SJisheng Zhang clk_disable_unprepare(hclock); 46810f1c135SJisheng Zhang clk_disable_unprepare(mainck); 469bb5f8ea4Sludovic.desroches@atmel.com 470bb5f8ea4Sludovic.desroches@atmel.com return 0; 471bb5f8ea4Sludovic.desroches@atmel.com } 472bb5f8ea4Sludovic.desroches@atmel.com 473bb5f8ea4Sludovic.desroches@atmel.com static struct platform_driver sdhci_at91_driver = { 474bb5f8ea4Sludovic.desroches@atmel.com .driver = { 475bb5f8ea4Sludovic.desroches@atmel.com .name = "sdhci-at91", 476bb5f8ea4Sludovic.desroches@atmel.com .of_match_table = sdhci_at91_dt_match, 477f5f17813Sludovic.desroches@atmel.com .pm = &sdhci_at91_dev_pm_ops, 478bb5f8ea4Sludovic.desroches@atmel.com }, 479bb5f8ea4Sludovic.desroches@atmel.com .probe = sdhci_at91_probe, 480bb5f8ea4Sludovic.desroches@atmel.com .remove = sdhci_at91_remove, 481bb5f8ea4Sludovic.desroches@atmel.com }; 482bb5f8ea4Sludovic.desroches@atmel.com 483bb5f8ea4Sludovic.desroches@atmel.com module_platform_driver(sdhci_at91_driver); 484bb5f8ea4Sludovic.desroches@atmel.com 485bb5f8ea4Sludovic.desroches@atmel.com MODULE_DESCRIPTION("SDHCI driver for at91"); 486bb5f8ea4Sludovic.desroches@atmel.com MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); 487bb5f8ea4Sludovic.desroches@atmel.com MODULE_LICENSE("GPL v2"); 488