1 /* 2 * Arasan Secure Digital Host Controller Interface. 3 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu> 4 * Copyright (c) 2012 Wind River Systems, Inc. 5 * Copyright (C) 2013 Pengutronix e.K. 6 * Copyright (C) 2013 Xilinx Inc. 7 * 8 * Based on sdhci-of-esdhc.c 9 * 10 * Copyright (c) 2007 Freescale Semiconductor, Inc. 11 * Copyright (c) 2009 MontaVista Software, Inc. 12 * 13 * Authors: Xiaobo Xie <X.Xie@freescale.com> 14 * Anton Vorontsov <avorontsov@ru.mvista.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or (at 19 * your option) any later version. 20 */ 21 22 #include <linux/clk-provider.h> 23 #include <linux/mfd/syscon.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/phy/phy.h> 27 #include <linux/regmap.h> 28 #include "sdhci-pltfm.h" 29 #include <linux/of.h> 30 31 #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 32 33 #define VENDOR_ENHANCED_STROBE BIT(0) 34 35 #define PHY_CLK_TOO_SLOW_HZ 400000 36 37 /* 38 * On some SoCs the syscon area has a feature where the upper 16-bits of 39 * each 32-bit register act as a write mask for the lower 16-bits. This allows 40 * atomic updates of the register without locking. This macro is used on SoCs 41 * that have that feature. 42 */ 43 #define HIWORD_UPDATE(val, mask, shift) \ 44 ((val) << (shift) | (mask) << ((shift) + 16)) 45 46 /** 47 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map 48 * 49 * @reg: Offset within the syscon of the register containing this field 50 * @width: Number of bits for this field 51 * @shift: Bit offset within @reg of this field (or -1 if not avail) 52 */ 53 struct sdhci_arasan_soc_ctl_field { 54 u32 reg; 55 u16 width; 56 s16 shift; 57 }; 58 59 /** 60 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers 61 * 62 * It's up to the licensee of the Arsan IP block to make these available 63 * somewhere if needed. Presumably these will be scattered somewhere that's 64 * accessible via the syscon API. 65 * 66 * @baseclkfreq: Where to find corecfg_baseclkfreq 67 * @clockmultiplier: Where to find corecfg_clockmultiplier 68 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon 69 */ 70 struct sdhci_arasan_soc_ctl_map { 71 struct sdhci_arasan_soc_ctl_field baseclkfreq; 72 struct sdhci_arasan_soc_ctl_field clockmultiplier; 73 bool hiword_update; 74 }; 75 76 /** 77 * struct sdhci_arasan_data 78 * @host: Pointer to the main SDHCI host structure. 79 * @clk_ahb: Pointer to the AHB clock 80 * @phy: Pointer to the generic phy 81 * @is_phy_on: True if the PHY is on; false if not. 82 * @sdcardclk_hw: Struct for the clock we might provide to a PHY. 83 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. 84 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. 85 * @soc_ctl_map: Map to get offsets into soc_ctl registers. 86 */ 87 struct sdhci_arasan_data { 88 struct sdhci_host *host; 89 struct clk *clk_ahb; 90 struct phy *phy; 91 bool is_phy_on; 92 93 struct clk_hw sdcardclk_hw; 94 struct clk *sdcardclk; 95 96 struct regmap *soc_ctl_base; 97 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; 98 unsigned int quirks; /* Arasan deviations from spec */ 99 100 /* Controller does not have CD wired and will not function normally without */ 101 #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0) 102 }; 103 104 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = { 105 .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 }, 106 .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0}, 107 .hiword_update = true, 108 }; 109 110 /** 111 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers 112 * 113 * This function allows writing to fields in sdhci_arasan_soc_ctl_map. 114 * Note that if a field is specified as not available (shift < 0) then 115 * this function will silently return an error code. It will be noisy 116 * and print errors for any other (unexpected) errors. 117 * 118 * @host: The sdhci_host 119 * @fld: The field to write to 120 * @val: The value to write 121 */ 122 static int sdhci_arasan_syscon_write(struct sdhci_host *host, 123 const struct sdhci_arasan_soc_ctl_field *fld, 124 u32 val) 125 { 126 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 127 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 128 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; 129 u32 reg = fld->reg; 130 u16 width = fld->width; 131 s16 shift = fld->shift; 132 int ret; 133 134 /* 135 * Silently return errors for shift < 0 so caller doesn't have 136 * to check for fields which are optional. For fields that 137 * are required then caller needs to do something special 138 * anyway. 139 */ 140 if (shift < 0) 141 return -EINVAL; 142 143 if (sdhci_arasan->soc_ctl_map->hiword_update) 144 ret = regmap_write(soc_ctl_base, reg, 145 HIWORD_UPDATE(val, GENMASK(width, 0), 146 shift)); 147 else 148 ret = regmap_update_bits(soc_ctl_base, reg, 149 GENMASK(shift + width, shift), 150 val << shift); 151 152 /* Yell about (unexpected) regmap errors */ 153 if (ret) 154 pr_warn("%s: Regmap write fail: %d\n", 155 mmc_hostname(host->mmc), ret); 156 157 return ret; 158 } 159 160 static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host) 161 { 162 unsigned long freq; 163 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 164 165 /* SDHCI timeout clock is in kHz */ 166 freq = DIV_ROUND_UP(clk_get_rate(pltfm_host->clk), 1000); 167 168 /* or in MHz */ 169 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT) 170 freq = DIV_ROUND_UP(freq, 1000); 171 172 return freq; 173 } 174 175 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) 176 { 177 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 178 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 179 bool ctrl_phy = false; 180 181 if (!IS_ERR(sdhci_arasan->phy)) { 182 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) { 183 /* 184 * If PHY off, set clock to max speed and power PHY on. 185 * 186 * Although PHY docs apparently suggest power cycling 187 * when changing the clock the PHY doesn't like to be 188 * powered on while at low speeds like those used in ID 189 * mode. Even worse is powering the PHY on while the 190 * clock is off. 191 * 192 * To workaround the PHY limitations, the best we can 193 * do is to power it on at a faster speed and then slam 194 * through low speeds without power cycling. 195 */ 196 sdhci_set_clock(host, host->max_clk); 197 spin_unlock_irq(&host->lock); 198 phy_power_on(sdhci_arasan->phy); 199 spin_lock_irq(&host->lock); 200 sdhci_arasan->is_phy_on = true; 201 202 /* 203 * We'll now fall through to the below case with 204 * ctrl_phy = false (so we won't turn off/on). The 205 * sdhci_set_clock() will set the real clock. 206 */ 207 } else if (clock > PHY_CLK_TOO_SLOW_HZ) { 208 /* 209 * At higher clock speeds the PHY is fine being power 210 * cycled and docs say you _should_ power cycle when 211 * changing clock speeds. 212 */ 213 ctrl_phy = true; 214 } 215 } 216 217 if (ctrl_phy && sdhci_arasan->is_phy_on) { 218 spin_unlock_irq(&host->lock); 219 phy_power_off(sdhci_arasan->phy); 220 spin_lock_irq(&host->lock); 221 sdhci_arasan->is_phy_on = false; 222 } 223 224 sdhci_set_clock(host, clock); 225 226 if (ctrl_phy) { 227 spin_unlock_irq(&host->lock); 228 phy_power_on(sdhci_arasan->phy); 229 spin_lock_irq(&host->lock); 230 sdhci_arasan->is_phy_on = true; 231 } 232 } 233 234 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc, 235 struct mmc_ios *ios) 236 { 237 u32 vendor; 238 struct sdhci_host *host = mmc_priv(mmc); 239 240 vendor = readl(host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER); 241 if (ios->enhanced_strobe) 242 vendor |= VENDOR_ENHANCED_STROBE; 243 else 244 vendor &= ~VENDOR_ENHANCED_STROBE; 245 246 writel(vendor, host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER); 247 } 248 249 static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) 250 { 251 u8 ctrl; 252 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 253 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 254 255 sdhci_reset(host, mask); 256 257 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { 258 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 259 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 260 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 261 } 262 } 263 264 static int sdhci_arasan_voltage_switch(struct mmc_host *mmc, 265 struct mmc_ios *ios) 266 { 267 switch (ios->signal_voltage) { 268 case MMC_SIGNAL_VOLTAGE_180: 269 /* 270 * Plese don't switch to 1V8 as arasan,5.1 doesn't 271 * actually refer to this setting to indicate the 272 * signal voltage and the state machine will be broken 273 * actually if we force to enable 1V8. That's something 274 * like broken quirk but we could work around here. 275 */ 276 return 0; 277 case MMC_SIGNAL_VOLTAGE_330: 278 case MMC_SIGNAL_VOLTAGE_120: 279 /* We don't support 3V3 and 1V2 */ 280 break; 281 } 282 283 return -EINVAL; 284 } 285 286 static struct sdhci_ops sdhci_arasan_ops = { 287 .set_clock = sdhci_arasan_set_clock, 288 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 289 .get_timeout_clock = sdhci_arasan_get_timeout_clock, 290 .set_bus_width = sdhci_set_bus_width, 291 .reset = sdhci_arasan_reset, 292 .set_uhs_signaling = sdhci_set_uhs_signaling, 293 }; 294 295 static struct sdhci_pltfm_data sdhci_arasan_pdata = { 296 .ops = &sdhci_arasan_ops, 297 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 298 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 299 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 300 }; 301 302 #ifdef CONFIG_PM_SLEEP 303 /** 304 * sdhci_arasan_suspend - Suspend method for the driver 305 * @dev: Address of the device structure 306 * Returns 0 on success and error value on error 307 * 308 * Put the device in a low power state. 309 */ 310 static int sdhci_arasan_suspend(struct device *dev) 311 { 312 struct platform_device *pdev = to_platform_device(dev); 313 struct sdhci_host *host = platform_get_drvdata(pdev); 314 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 315 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 316 int ret; 317 318 ret = sdhci_suspend_host(host); 319 if (ret) 320 return ret; 321 322 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) { 323 ret = phy_power_off(sdhci_arasan->phy); 324 if (ret) { 325 dev_err(dev, "Cannot power off phy.\n"); 326 sdhci_resume_host(host); 327 return ret; 328 } 329 sdhci_arasan->is_phy_on = false; 330 } 331 332 clk_disable(pltfm_host->clk); 333 clk_disable(sdhci_arasan->clk_ahb); 334 335 return 0; 336 } 337 338 /** 339 * sdhci_arasan_resume - Resume method for the driver 340 * @dev: Address of the device structure 341 * Returns 0 on success and error value on error 342 * 343 * Resume operation after suspend 344 */ 345 static int sdhci_arasan_resume(struct device *dev) 346 { 347 struct platform_device *pdev = to_platform_device(dev); 348 struct sdhci_host *host = platform_get_drvdata(pdev); 349 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 350 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 351 int ret; 352 353 ret = clk_enable(sdhci_arasan->clk_ahb); 354 if (ret) { 355 dev_err(dev, "Cannot enable AHB clock.\n"); 356 return ret; 357 } 358 359 ret = clk_enable(pltfm_host->clk); 360 if (ret) { 361 dev_err(dev, "Cannot enable SD clock.\n"); 362 return ret; 363 } 364 365 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) { 366 ret = phy_power_on(sdhci_arasan->phy); 367 if (ret) { 368 dev_err(dev, "Cannot power on phy.\n"); 369 return ret; 370 } 371 sdhci_arasan->is_phy_on = true; 372 } 373 374 return sdhci_resume_host(host); 375 } 376 #endif /* ! CONFIG_PM_SLEEP */ 377 378 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend, 379 sdhci_arasan_resume); 380 381 static const struct of_device_id sdhci_arasan_of_match[] = { 382 /* SoC-specific compatible strings w/ soc_ctl_map */ 383 { 384 .compatible = "rockchip,rk3399-sdhci-5.1", 385 .data = &rk3399_soc_ctl_map, 386 }, 387 388 /* Generic compatible below here */ 389 { .compatible = "arasan,sdhci-8.9a" }, 390 { .compatible = "arasan,sdhci-5.1" }, 391 { .compatible = "arasan,sdhci-4.9a" }, 392 393 { /* sentinel */ } 394 }; 395 MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); 396 397 /** 398 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate 399 * 400 * Return the current actual rate of the SD card clock. This can be used 401 * to communicate with out PHY. 402 * 403 * @hw: Pointer to the hardware clock structure. 404 * @parent_rate The parent rate (should be rate of clk_xin). 405 * Returns the card clock rate. 406 */ 407 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw, 408 unsigned long parent_rate) 409 410 { 411 struct sdhci_arasan_data *sdhci_arasan = 412 container_of(hw, struct sdhci_arasan_data, sdcardclk_hw); 413 struct sdhci_host *host = sdhci_arasan->host; 414 415 return host->mmc->actual_clock; 416 } 417 418 static const struct clk_ops arasan_sdcardclk_ops = { 419 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, 420 }; 421 422 /** 423 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier 424 * 425 * The corecfg_clockmultiplier is supposed to contain clock multiplier 426 * value of programmable clock generator. 427 * 428 * NOTES: 429 * - Many existing devices don't seem to do this and work fine. To keep 430 * compatibility for old hardware where the device tree doesn't provide a 431 * register map, this function is a noop if a soc_ctl_map hasn't been provided 432 * for this platform. 433 * - The value of corecfg_clockmultiplier should sync with that of corresponding 434 * value reading from sdhci_capability_register. So this function is called 435 * once at probe time and never called again. 436 * 437 * @host: The sdhci_host 438 */ 439 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host, 440 u32 value) 441 { 442 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 443 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 444 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = 445 sdhci_arasan->soc_ctl_map; 446 447 /* Having a map is optional */ 448 if (!soc_ctl_map) 449 return; 450 451 /* If we have a map, we expect to have a syscon */ 452 if (!sdhci_arasan->soc_ctl_base) { 453 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", 454 mmc_hostname(host->mmc)); 455 return; 456 } 457 458 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value); 459 } 460 461 /** 462 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq 463 * 464 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This 465 * function can be used to make that happen. 466 * 467 * NOTES: 468 * - Many existing devices don't seem to do this and work fine. To keep 469 * compatibility for old hardware where the device tree doesn't provide a 470 * register map, this function is a noop if a soc_ctl_map hasn't been provided 471 * for this platform. 472 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider 473 * to achieve lower clock rates. That means that this function is called once 474 * at probe time and never called again. 475 * 476 * @host: The sdhci_host 477 */ 478 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) 479 { 480 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 481 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 482 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = 483 sdhci_arasan->soc_ctl_map; 484 u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000); 485 486 /* Having a map is optional */ 487 if (!soc_ctl_map) 488 return; 489 490 /* If we have a map, we expect to have a syscon */ 491 if (!sdhci_arasan->soc_ctl_base) { 492 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", 493 mmc_hostname(host->mmc)); 494 return; 495 } 496 497 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); 498 } 499 500 /** 501 * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use 502 * 503 * Some PHY devices need to know what the actual card clock is. In order for 504 * them to find out, we'll provide a clock through the common clock framework 505 * for them to query. 506 * 507 * Note: without seriously re-architecting SDHCI's clock code and testing on 508 * all platforms, there's no way to create a totally beautiful clock here 509 * with all clock ops implemented. Instead, we'll just create a clock that can 510 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock 511 * framework that we're doing things behind its back. This should be sufficient 512 * to create nice clean device tree bindings and later (if needed) we can try 513 * re-architecting SDHCI if we see some benefit to it. 514 * 515 * @sdhci_arasan: Our private data structure. 516 * @clk_xin: Pointer to the functional clock 517 * @dev: Pointer to our struct device. 518 * Returns 0 on success and error value on error 519 */ 520 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, 521 struct clk *clk_xin, 522 struct device *dev) 523 { 524 struct device_node *np = dev->of_node; 525 struct clk_init_data sdcardclk_init; 526 const char *parent_clk_name; 527 int ret; 528 529 /* Providing a clock to the PHY is optional; no error if missing */ 530 if (!of_find_property(np, "#clock-cells", NULL)) 531 return 0; 532 533 ret = of_property_read_string_index(np, "clock-output-names", 0, 534 &sdcardclk_init.name); 535 if (ret) { 536 dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); 537 return ret; 538 } 539 540 parent_clk_name = __clk_get_name(clk_xin); 541 sdcardclk_init.parent_names = &parent_clk_name; 542 sdcardclk_init.num_parents = 1; 543 sdcardclk_init.flags = CLK_GET_RATE_NOCACHE; 544 sdcardclk_init.ops = &arasan_sdcardclk_ops; 545 546 sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init; 547 sdhci_arasan->sdcardclk = 548 devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw); 549 sdhci_arasan->sdcardclk_hw.init = NULL; 550 551 ret = of_clk_add_provider(np, of_clk_src_simple_get, 552 sdhci_arasan->sdcardclk); 553 if (ret) 554 dev_err(dev, "Failed to add clock provider\n"); 555 556 return ret; 557 } 558 559 /** 560 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk() 561 * 562 * Should be called any time we're exiting and sdhci_arasan_register_sdclk() 563 * returned success. 564 * 565 * @dev: Pointer to our struct device. 566 */ 567 static void sdhci_arasan_unregister_sdclk(struct device *dev) 568 { 569 struct device_node *np = dev->of_node; 570 571 if (!of_find_property(np, "#clock-cells", NULL)) 572 return; 573 574 of_clk_del_provider(dev->of_node); 575 } 576 577 static int sdhci_arasan_probe(struct platform_device *pdev) 578 { 579 int ret; 580 const struct of_device_id *match; 581 struct device_node *node; 582 struct clk *clk_xin; 583 struct sdhci_host *host; 584 struct sdhci_pltfm_host *pltfm_host; 585 struct sdhci_arasan_data *sdhci_arasan; 586 struct device_node *np = pdev->dev.of_node; 587 588 host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata, 589 sizeof(*sdhci_arasan)); 590 if (IS_ERR(host)) 591 return PTR_ERR(host); 592 593 pltfm_host = sdhci_priv(host); 594 sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 595 sdhci_arasan->host = host; 596 597 match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node); 598 sdhci_arasan->soc_ctl_map = match->data; 599 600 node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0); 601 if (node) { 602 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); 603 of_node_put(node); 604 605 if (IS_ERR(sdhci_arasan->soc_ctl_base)) { 606 ret = PTR_ERR(sdhci_arasan->soc_ctl_base); 607 if (ret != -EPROBE_DEFER) 608 dev_err(&pdev->dev, "Can't get syscon: %d\n", 609 ret); 610 goto err_pltfm_free; 611 } 612 } 613 614 sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb"); 615 if (IS_ERR(sdhci_arasan->clk_ahb)) { 616 dev_err(&pdev->dev, "clk_ahb clock not found.\n"); 617 ret = PTR_ERR(sdhci_arasan->clk_ahb); 618 goto err_pltfm_free; 619 } 620 621 clk_xin = devm_clk_get(&pdev->dev, "clk_xin"); 622 if (IS_ERR(clk_xin)) { 623 dev_err(&pdev->dev, "clk_xin clock not found.\n"); 624 ret = PTR_ERR(clk_xin); 625 goto err_pltfm_free; 626 } 627 628 ret = clk_prepare_enable(sdhci_arasan->clk_ahb); 629 if (ret) { 630 dev_err(&pdev->dev, "Unable to enable AHB clock.\n"); 631 goto err_pltfm_free; 632 } 633 634 ret = clk_prepare_enable(clk_xin); 635 if (ret) { 636 dev_err(&pdev->dev, "Unable to enable SD clock.\n"); 637 goto clk_dis_ahb; 638 } 639 640 sdhci_get_of_property(pdev); 641 642 if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) 643 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; 644 645 pltfm_host->clk = clk_xin; 646 647 if (of_device_is_compatible(pdev->dev.of_node, 648 "rockchip,rk3399-sdhci-5.1")) 649 sdhci_arasan_update_clockmultiplier(host, 0x0); 650 651 sdhci_arasan_update_baseclkfreq(host); 652 653 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev); 654 if (ret) 655 goto clk_disable_all; 656 657 ret = mmc_of_parse(host->mmc); 658 if (ret) { 659 dev_err(&pdev->dev, "parsing dt failed (%u)\n", ret); 660 goto unreg_clk; 661 } 662 663 sdhci_arasan->phy = ERR_PTR(-ENODEV); 664 if (of_device_is_compatible(pdev->dev.of_node, 665 "arasan,sdhci-5.1")) { 666 sdhci_arasan->phy = devm_phy_get(&pdev->dev, 667 "phy_arasan"); 668 if (IS_ERR(sdhci_arasan->phy)) { 669 ret = PTR_ERR(sdhci_arasan->phy); 670 dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n"); 671 goto unreg_clk; 672 } 673 674 ret = phy_init(sdhci_arasan->phy); 675 if (ret < 0) { 676 dev_err(&pdev->dev, "phy_init err.\n"); 677 goto unreg_clk; 678 } 679 680 host->mmc_host_ops.hs400_enhanced_strobe = 681 sdhci_arasan_hs400_enhanced_strobe; 682 host->mmc_host_ops.start_signal_voltage_switch = 683 sdhci_arasan_voltage_switch; 684 } 685 686 ret = sdhci_add_host(host); 687 if (ret) 688 goto err_add_host; 689 690 return 0; 691 692 err_add_host: 693 if (!IS_ERR(sdhci_arasan->phy)) 694 phy_exit(sdhci_arasan->phy); 695 unreg_clk: 696 sdhci_arasan_unregister_sdclk(&pdev->dev); 697 clk_disable_all: 698 clk_disable_unprepare(clk_xin); 699 clk_dis_ahb: 700 clk_disable_unprepare(sdhci_arasan->clk_ahb); 701 err_pltfm_free: 702 sdhci_pltfm_free(pdev); 703 return ret; 704 } 705 706 static int sdhci_arasan_remove(struct platform_device *pdev) 707 { 708 int ret; 709 struct sdhci_host *host = platform_get_drvdata(pdev); 710 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 711 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 712 struct clk *clk_ahb = sdhci_arasan->clk_ahb; 713 714 if (!IS_ERR(sdhci_arasan->phy)) { 715 if (sdhci_arasan->is_phy_on) 716 phy_power_off(sdhci_arasan->phy); 717 phy_exit(sdhci_arasan->phy); 718 } 719 720 sdhci_arasan_unregister_sdclk(&pdev->dev); 721 722 ret = sdhci_pltfm_unregister(pdev); 723 724 clk_disable_unprepare(clk_ahb); 725 726 return ret; 727 } 728 729 static struct platform_driver sdhci_arasan_driver = { 730 .driver = { 731 .name = "sdhci-arasan", 732 .of_match_table = sdhci_arasan_of_match, 733 .pm = &sdhci_arasan_dev_pm_ops, 734 }, 735 .probe = sdhci_arasan_probe, 736 .remove = sdhci_arasan_remove, 737 }; 738 739 module_platform_driver(sdhci_arasan_driver); 740 741 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller"); 742 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>"); 743 MODULE_LICENSE("GPL"); 744