1 /* 2 * Arasan Secure Digital Host Controller Interface. 3 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu> 4 * Copyright (c) 2012 Wind River Systems, Inc. 5 * Copyright (C) 2013 Pengutronix e.K. 6 * Copyright (C) 2013 Xilinx Inc. 7 * 8 * Based on sdhci-of-esdhc.c 9 * 10 * Copyright (c) 2007 Freescale Semiconductor, Inc. 11 * Copyright (c) 2009 MontaVista Software, Inc. 12 * 13 * Authors: Xiaobo Xie <X.Xie@freescale.com> 14 * Anton Vorontsov <avorontsov@ru.mvista.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or (at 19 * your option) any later version. 20 */ 21 22 #include <linux/clk-provider.h> 23 #include <linux/mfd/syscon.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/phy/phy.h> 27 #include <linux/regmap.h> 28 #include <linux/of.h> 29 30 #include "cqhci.h" 31 #include "sdhci-pltfm.h" 32 33 #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 34 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 35 #define VENDOR_ENHANCED_STROBE BIT(0) 36 37 #define PHY_CLK_TOO_SLOW_HZ 400000 38 39 /* 40 * On some SoCs the syscon area has a feature where the upper 16-bits of 41 * each 32-bit register act as a write mask for the lower 16-bits. This allows 42 * atomic updates of the register without locking. This macro is used on SoCs 43 * that have that feature. 44 */ 45 #define HIWORD_UPDATE(val, mask, shift) \ 46 ((val) << (shift) | (mask) << ((shift) + 16)) 47 48 /** 49 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map 50 * 51 * @reg: Offset within the syscon of the register containing this field 52 * @width: Number of bits for this field 53 * @shift: Bit offset within @reg of this field (or -1 if not avail) 54 */ 55 struct sdhci_arasan_soc_ctl_field { 56 u32 reg; 57 u16 width; 58 s16 shift; 59 }; 60 61 /** 62 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers 63 * 64 * It's up to the licensee of the Arsan IP block to make these available 65 * somewhere if needed. Presumably these will be scattered somewhere that's 66 * accessible via the syscon API. 67 * 68 * @baseclkfreq: Where to find corecfg_baseclkfreq 69 * @clockmultiplier: Where to find corecfg_clockmultiplier 70 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon 71 */ 72 struct sdhci_arasan_soc_ctl_map { 73 struct sdhci_arasan_soc_ctl_field baseclkfreq; 74 struct sdhci_arasan_soc_ctl_field clockmultiplier; 75 bool hiword_update; 76 }; 77 78 /** 79 * struct sdhci_arasan_data 80 * @host: Pointer to the main SDHCI host structure. 81 * @clk_ahb: Pointer to the AHB clock 82 * @phy: Pointer to the generic phy 83 * @is_phy_on: True if the PHY is on; false if not. 84 * @sdcardclk_hw: Struct for the clock we might provide to a PHY. 85 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. 86 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. 87 * @soc_ctl_map: Map to get offsets into soc_ctl registers. 88 */ 89 struct sdhci_arasan_data { 90 struct sdhci_host *host; 91 struct clk *clk_ahb; 92 struct phy *phy; 93 bool is_phy_on; 94 95 bool has_cqe; 96 struct clk_hw sdcardclk_hw; 97 struct clk *sdcardclk; 98 99 struct regmap *soc_ctl_base; 100 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; 101 unsigned int quirks; /* Arasan deviations from spec */ 102 103 /* Controller does not have CD wired and will not function normally without */ 104 #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0) 105 }; 106 107 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = { 108 .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 }, 109 .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0}, 110 .hiword_update = true, 111 }; 112 113 /** 114 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers 115 * 116 * This function allows writing to fields in sdhci_arasan_soc_ctl_map. 117 * Note that if a field is specified as not available (shift < 0) then 118 * this function will silently return an error code. It will be noisy 119 * and print errors for any other (unexpected) errors. 120 * 121 * @host: The sdhci_host 122 * @fld: The field to write to 123 * @val: The value to write 124 */ 125 static int sdhci_arasan_syscon_write(struct sdhci_host *host, 126 const struct sdhci_arasan_soc_ctl_field *fld, 127 u32 val) 128 { 129 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 130 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 131 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; 132 u32 reg = fld->reg; 133 u16 width = fld->width; 134 s16 shift = fld->shift; 135 int ret; 136 137 /* 138 * Silently return errors for shift < 0 so caller doesn't have 139 * to check for fields which are optional. For fields that 140 * are required then caller needs to do something special 141 * anyway. 142 */ 143 if (shift < 0) 144 return -EINVAL; 145 146 if (sdhci_arasan->soc_ctl_map->hiword_update) 147 ret = regmap_write(soc_ctl_base, reg, 148 HIWORD_UPDATE(val, GENMASK(width, 0), 149 shift)); 150 else 151 ret = regmap_update_bits(soc_ctl_base, reg, 152 GENMASK(shift + width, shift), 153 val << shift); 154 155 /* Yell about (unexpected) regmap errors */ 156 if (ret) 157 pr_warn("%s: Regmap write fail: %d\n", 158 mmc_hostname(host->mmc), ret); 159 160 return ret; 161 } 162 163 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) 164 { 165 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 166 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 167 bool ctrl_phy = false; 168 169 if (!IS_ERR(sdhci_arasan->phy)) { 170 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) { 171 /* 172 * If PHY off, set clock to max speed and power PHY on. 173 * 174 * Although PHY docs apparently suggest power cycling 175 * when changing the clock the PHY doesn't like to be 176 * powered on while at low speeds like those used in ID 177 * mode. Even worse is powering the PHY on while the 178 * clock is off. 179 * 180 * To workaround the PHY limitations, the best we can 181 * do is to power it on at a faster speed and then slam 182 * through low speeds without power cycling. 183 */ 184 sdhci_set_clock(host, host->max_clk); 185 phy_power_on(sdhci_arasan->phy); 186 sdhci_arasan->is_phy_on = true; 187 188 /* 189 * We'll now fall through to the below case with 190 * ctrl_phy = false (so we won't turn off/on). The 191 * sdhci_set_clock() will set the real clock. 192 */ 193 } else if (clock > PHY_CLK_TOO_SLOW_HZ) { 194 /* 195 * At higher clock speeds the PHY is fine being power 196 * cycled and docs say you _should_ power cycle when 197 * changing clock speeds. 198 */ 199 ctrl_phy = true; 200 } 201 } 202 203 if (ctrl_phy && sdhci_arasan->is_phy_on) { 204 phy_power_off(sdhci_arasan->phy); 205 sdhci_arasan->is_phy_on = false; 206 } 207 208 sdhci_set_clock(host, clock); 209 210 if (ctrl_phy) { 211 phy_power_on(sdhci_arasan->phy); 212 sdhci_arasan->is_phy_on = true; 213 } 214 } 215 216 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc, 217 struct mmc_ios *ios) 218 { 219 u32 vendor; 220 struct sdhci_host *host = mmc_priv(mmc); 221 222 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER); 223 if (ios->enhanced_strobe) 224 vendor |= VENDOR_ENHANCED_STROBE; 225 else 226 vendor &= ~VENDOR_ENHANCED_STROBE; 227 228 sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER); 229 } 230 231 static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) 232 { 233 u8 ctrl; 234 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 235 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 236 237 sdhci_reset(host, mask); 238 239 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { 240 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 241 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 242 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 243 } 244 } 245 246 static int sdhci_arasan_voltage_switch(struct mmc_host *mmc, 247 struct mmc_ios *ios) 248 { 249 switch (ios->signal_voltage) { 250 case MMC_SIGNAL_VOLTAGE_180: 251 /* 252 * Plese don't switch to 1V8 as arasan,5.1 doesn't 253 * actually refer to this setting to indicate the 254 * signal voltage and the state machine will be broken 255 * actually if we force to enable 1V8. That's something 256 * like broken quirk but we could work around here. 257 */ 258 return 0; 259 case MMC_SIGNAL_VOLTAGE_330: 260 case MMC_SIGNAL_VOLTAGE_120: 261 /* We don't support 3V3 and 1V2 */ 262 break; 263 } 264 265 return -EINVAL; 266 } 267 268 static void sdhci_arasan_set_power(struct sdhci_host *host, unsigned char mode, 269 unsigned short vdd) 270 { 271 if (!IS_ERR(host->mmc->supply.vmmc)) { 272 struct mmc_host *mmc = host->mmc; 273 274 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 275 } 276 sdhci_set_power_noreg(host, mode, vdd); 277 } 278 279 static const struct sdhci_ops sdhci_arasan_ops = { 280 .set_clock = sdhci_arasan_set_clock, 281 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 282 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 283 .set_bus_width = sdhci_set_bus_width, 284 .reset = sdhci_arasan_reset, 285 .set_uhs_signaling = sdhci_set_uhs_signaling, 286 .set_power = sdhci_arasan_set_power, 287 }; 288 289 static const struct sdhci_pltfm_data sdhci_arasan_pdata = { 290 .ops = &sdhci_arasan_ops, 291 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 292 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 293 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | 294 SDHCI_QUIRK2_STOP_WITH_TC, 295 }; 296 297 static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask) 298 { 299 int cmd_error = 0; 300 int data_error = 0; 301 302 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 303 return intmask; 304 305 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 306 307 return 0; 308 } 309 310 static void sdhci_arasan_dumpregs(struct mmc_host *mmc) 311 { 312 sdhci_dumpregs(mmc_priv(mmc)); 313 } 314 315 static void sdhci_arasan_cqe_enable(struct mmc_host *mmc) 316 { 317 struct sdhci_host *host = mmc_priv(mmc); 318 u32 reg; 319 320 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 321 while (reg & SDHCI_DATA_AVAILABLE) { 322 sdhci_readl(host, SDHCI_BUFFER); 323 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 324 } 325 326 sdhci_cqe_enable(mmc); 327 } 328 329 static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = { 330 .enable = sdhci_arasan_cqe_enable, 331 .disable = sdhci_cqe_disable, 332 .dumpregs = sdhci_arasan_dumpregs, 333 }; 334 335 static const struct sdhci_ops sdhci_arasan_cqe_ops = { 336 .set_clock = sdhci_arasan_set_clock, 337 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 338 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 339 .set_bus_width = sdhci_set_bus_width, 340 .reset = sdhci_arasan_reset, 341 .set_uhs_signaling = sdhci_set_uhs_signaling, 342 .set_power = sdhci_arasan_set_power, 343 .irq = sdhci_arasan_cqhci_irq, 344 }; 345 346 static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = { 347 .ops = &sdhci_arasan_cqe_ops, 348 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 349 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 350 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 351 }; 352 353 #ifdef CONFIG_PM_SLEEP 354 /** 355 * sdhci_arasan_suspend - Suspend method for the driver 356 * @dev: Address of the device structure 357 * Returns 0 on success and error value on error 358 * 359 * Put the device in a low power state. 360 */ 361 static int sdhci_arasan_suspend(struct device *dev) 362 { 363 struct sdhci_host *host = dev_get_drvdata(dev); 364 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 365 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 366 int ret; 367 368 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 369 mmc_retune_needed(host->mmc); 370 371 if (sdhci_arasan->has_cqe) { 372 ret = cqhci_suspend(host->mmc); 373 if (ret) 374 return ret; 375 } 376 377 ret = sdhci_suspend_host(host); 378 if (ret) 379 return ret; 380 381 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) { 382 ret = phy_power_off(sdhci_arasan->phy); 383 if (ret) { 384 dev_err(dev, "Cannot power off phy.\n"); 385 sdhci_resume_host(host); 386 return ret; 387 } 388 sdhci_arasan->is_phy_on = false; 389 } 390 391 clk_disable(pltfm_host->clk); 392 clk_disable(sdhci_arasan->clk_ahb); 393 394 return 0; 395 } 396 397 /** 398 * sdhci_arasan_resume - Resume method for the driver 399 * @dev: Address of the device structure 400 * Returns 0 on success and error value on error 401 * 402 * Resume operation after suspend 403 */ 404 static int sdhci_arasan_resume(struct device *dev) 405 { 406 struct sdhci_host *host = dev_get_drvdata(dev); 407 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 408 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 409 int ret; 410 411 ret = clk_enable(sdhci_arasan->clk_ahb); 412 if (ret) { 413 dev_err(dev, "Cannot enable AHB clock.\n"); 414 return ret; 415 } 416 417 ret = clk_enable(pltfm_host->clk); 418 if (ret) { 419 dev_err(dev, "Cannot enable SD clock.\n"); 420 return ret; 421 } 422 423 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) { 424 ret = phy_power_on(sdhci_arasan->phy); 425 if (ret) { 426 dev_err(dev, "Cannot power on phy.\n"); 427 return ret; 428 } 429 sdhci_arasan->is_phy_on = true; 430 } 431 432 ret = sdhci_resume_host(host); 433 if (ret) { 434 dev_err(dev, "Cannot resume host.\n"); 435 return ret; 436 } 437 438 if (sdhci_arasan->has_cqe) 439 return cqhci_resume(host->mmc); 440 441 return 0; 442 } 443 #endif /* ! CONFIG_PM_SLEEP */ 444 445 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend, 446 sdhci_arasan_resume); 447 448 static const struct of_device_id sdhci_arasan_of_match[] = { 449 /* SoC-specific compatible strings w/ soc_ctl_map */ 450 { 451 .compatible = "rockchip,rk3399-sdhci-5.1", 452 .data = &rk3399_soc_ctl_map, 453 }, 454 455 /* Generic compatible below here */ 456 { .compatible = "arasan,sdhci-8.9a" }, 457 { .compatible = "arasan,sdhci-5.1" }, 458 { .compatible = "arasan,sdhci-4.9a" }, 459 460 { /* sentinel */ } 461 }; 462 MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); 463 464 /** 465 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate 466 * 467 * Return the current actual rate of the SD card clock. This can be used 468 * to communicate with out PHY. 469 * 470 * @hw: Pointer to the hardware clock structure. 471 * @parent_rate The parent rate (should be rate of clk_xin). 472 * Returns the card clock rate. 473 */ 474 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw, 475 unsigned long parent_rate) 476 477 { 478 struct sdhci_arasan_data *sdhci_arasan = 479 container_of(hw, struct sdhci_arasan_data, sdcardclk_hw); 480 struct sdhci_host *host = sdhci_arasan->host; 481 482 return host->mmc->actual_clock; 483 } 484 485 static const struct clk_ops arasan_sdcardclk_ops = { 486 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, 487 }; 488 489 /** 490 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier 491 * 492 * The corecfg_clockmultiplier is supposed to contain clock multiplier 493 * value of programmable clock generator. 494 * 495 * NOTES: 496 * - Many existing devices don't seem to do this and work fine. To keep 497 * compatibility for old hardware where the device tree doesn't provide a 498 * register map, this function is a noop if a soc_ctl_map hasn't been provided 499 * for this platform. 500 * - The value of corecfg_clockmultiplier should sync with that of corresponding 501 * value reading from sdhci_capability_register. So this function is called 502 * once at probe time and never called again. 503 * 504 * @host: The sdhci_host 505 */ 506 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host, 507 u32 value) 508 { 509 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 510 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 511 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = 512 sdhci_arasan->soc_ctl_map; 513 514 /* Having a map is optional */ 515 if (!soc_ctl_map) 516 return; 517 518 /* If we have a map, we expect to have a syscon */ 519 if (!sdhci_arasan->soc_ctl_base) { 520 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", 521 mmc_hostname(host->mmc)); 522 return; 523 } 524 525 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value); 526 } 527 528 /** 529 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq 530 * 531 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This 532 * function can be used to make that happen. 533 * 534 * NOTES: 535 * - Many existing devices don't seem to do this and work fine. To keep 536 * compatibility for old hardware where the device tree doesn't provide a 537 * register map, this function is a noop if a soc_ctl_map hasn't been provided 538 * for this platform. 539 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider 540 * to achieve lower clock rates. That means that this function is called once 541 * at probe time and never called again. 542 * 543 * @host: The sdhci_host 544 */ 545 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) 546 { 547 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 548 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 549 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = 550 sdhci_arasan->soc_ctl_map; 551 u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000); 552 553 /* Having a map is optional */ 554 if (!soc_ctl_map) 555 return; 556 557 /* If we have a map, we expect to have a syscon */ 558 if (!sdhci_arasan->soc_ctl_base) { 559 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", 560 mmc_hostname(host->mmc)); 561 return; 562 } 563 564 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); 565 } 566 567 /** 568 * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use 569 * 570 * Some PHY devices need to know what the actual card clock is. In order for 571 * them to find out, we'll provide a clock through the common clock framework 572 * for them to query. 573 * 574 * Note: without seriously re-architecting SDHCI's clock code and testing on 575 * all platforms, there's no way to create a totally beautiful clock here 576 * with all clock ops implemented. Instead, we'll just create a clock that can 577 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock 578 * framework that we're doing things behind its back. This should be sufficient 579 * to create nice clean device tree bindings and later (if needed) we can try 580 * re-architecting SDHCI if we see some benefit to it. 581 * 582 * @sdhci_arasan: Our private data structure. 583 * @clk_xin: Pointer to the functional clock 584 * @dev: Pointer to our struct device. 585 * Returns 0 on success and error value on error 586 */ 587 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, 588 struct clk *clk_xin, 589 struct device *dev) 590 { 591 struct device_node *np = dev->of_node; 592 struct clk_init_data sdcardclk_init; 593 const char *parent_clk_name; 594 int ret; 595 596 /* Providing a clock to the PHY is optional; no error if missing */ 597 if (!of_find_property(np, "#clock-cells", NULL)) 598 return 0; 599 600 ret = of_property_read_string_index(np, "clock-output-names", 0, 601 &sdcardclk_init.name); 602 if (ret) { 603 dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); 604 return ret; 605 } 606 607 parent_clk_name = __clk_get_name(clk_xin); 608 sdcardclk_init.parent_names = &parent_clk_name; 609 sdcardclk_init.num_parents = 1; 610 sdcardclk_init.flags = CLK_GET_RATE_NOCACHE; 611 sdcardclk_init.ops = &arasan_sdcardclk_ops; 612 613 sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init; 614 sdhci_arasan->sdcardclk = 615 devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw); 616 sdhci_arasan->sdcardclk_hw.init = NULL; 617 618 ret = of_clk_add_provider(np, of_clk_src_simple_get, 619 sdhci_arasan->sdcardclk); 620 if (ret) 621 dev_err(dev, "Failed to add clock provider\n"); 622 623 return ret; 624 } 625 626 /** 627 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk() 628 * 629 * Should be called any time we're exiting and sdhci_arasan_register_sdclk() 630 * returned success. 631 * 632 * @dev: Pointer to our struct device. 633 */ 634 static void sdhci_arasan_unregister_sdclk(struct device *dev) 635 { 636 struct device_node *np = dev->of_node; 637 638 if (!of_find_property(np, "#clock-cells", NULL)) 639 return; 640 641 of_clk_del_provider(dev->of_node); 642 } 643 644 static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan) 645 { 646 struct sdhci_host *host = sdhci_arasan->host; 647 struct cqhci_host *cq_host; 648 bool dma64; 649 int ret; 650 651 if (!sdhci_arasan->has_cqe) 652 return sdhci_add_host(host); 653 654 ret = sdhci_setup_host(host); 655 if (ret) 656 return ret; 657 658 cq_host = devm_kzalloc(host->mmc->parent, 659 sizeof(*cq_host), GFP_KERNEL); 660 if (!cq_host) { 661 ret = -ENOMEM; 662 goto cleanup; 663 } 664 665 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; 666 cq_host->ops = &sdhci_arasan_cqhci_ops; 667 668 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 669 if (dma64) 670 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 671 672 ret = cqhci_init(cq_host, host->mmc, dma64); 673 if (ret) 674 goto cleanup; 675 676 ret = __sdhci_add_host(host); 677 if (ret) 678 goto cleanup; 679 680 return 0; 681 682 cleanup: 683 sdhci_cleanup_host(host); 684 return ret; 685 } 686 687 static int sdhci_arasan_probe(struct platform_device *pdev) 688 { 689 int ret; 690 const struct of_device_id *match; 691 struct device_node *node; 692 struct clk *clk_xin; 693 struct sdhci_host *host; 694 struct sdhci_pltfm_host *pltfm_host; 695 struct sdhci_arasan_data *sdhci_arasan; 696 struct device_node *np = pdev->dev.of_node; 697 const struct sdhci_pltfm_data *pdata; 698 699 if (of_device_is_compatible(pdev->dev.of_node, "arasan,sdhci-5.1")) 700 pdata = &sdhci_arasan_cqe_pdata; 701 else 702 pdata = &sdhci_arasan_pdata; 703 704 host = sdhci_pltfm_init(pdev, pdata, sizeof(*sdhci_arasan)); 705 706 if (IS_ERR(host)) 707 return PTR_ERR(host); 708 709 pltfm_host = sdhci_priv(host); 710 sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 711 sdhci_arasan->host = host; 712 713 match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node); 714 sdhci_arasan->soc_ctl_map = match->data; 715 716 node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0); 717 if (node) { 718 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); 719 of_node_put(node); 720 721 if (IS_ERR(sdhci_arasan->soc_ctl_base)) { 722 ret = PTR_ERR(sdhci_arasan->soc_ctl_base); 723 if (ret != -EPROBE_DEFER) 724 dev_err(&pdev->dev, "Can't get syscon: %d\n", 725 ret); 726 goto err_pltfm_free; 727 } 728 } 729 730 sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb"); 731 if (IS_ERR(sdhci_arasan->clk_ahb)) { 732 dev_err(&pdev->dev, "clk_ahb clock not found.\n"); 733 ret = PTR_ERR(sdhci_arasan->clk_ahb); 734 goto err_pltfm_free; 735 } 736 737 clk_xin = devm_clk_get(&pdev->dev, "clk_xin"); 738 if (IS_ERR(clk_xin)) { 739 dev_err(&pdev->dev, "clk_xin clock not found.\n"); 740 ret = PTR_ERR(clk_xin); 741 goto err_pltfm_free; 742 } 743 744 ret = clk_prepare_enable(sdhci_arasan->clk_ahb); 745 if (ret) { 746 dev_err(&pdev->dev, "Unable to enable AHB clock.\n"); 747 goto err_pltfm_free; 748 } 749 750 ret = clk_prepare_enable(clk_xin); 751 if (ret) { 752 dev_err(&pdev->dev, "Unable to enable SD clock.\n"); 753 goto clk_dis_ahb; 754 } 755 756 sdhci_get_of_property(pdev); 757 758 if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) 759 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; 760 761 pltfm_host->clk = clk_xin; 762 763 if (of_device_is_compatible(pdev->dev.of_node, 764 "rockchip,rk3399-sdhci-5.1")) 765 sdhci_arasan_update_clockmultiplier(host, 0x0); 766 767 sdhci_arasan_update_baseclkfreq(host); 768 769 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev); 770 if (ret) 771 goto clk_disable_all; 772 773 ret = mmc_of_parse(host->mmc); 774 if (ret) { 775 dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret); 776 goto unreg_clk; 777 } 778 779 sdhci_arasan->phy = ERR_PTR(-ENODEV); 780 if (of_device_is_compatible(pdev->dev.of_node, 781 "arasan,sdhci-5.1")) { 782 sdhci_arasan->phy = devm_phy_get(&pdev->dev, 783 "phy_arasan"); 784 if (IS_ERR(sdhci_arasan->phy)) { 785 ret = PTR_ERR(sdhci_arasan->phy); 786 dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n"); 787 goto unreg_clk; 788 } 789 790 ret = phy_init(sdhci_arasan->phy); 791 if (ret < 0) { 792 dev_err(&pdev->dev, "phy_init err.\n"); 793 goto unreg_clk; 794 } 795 796 host->mmc_host_ops.hs400_enhanced_strobe = 797 sdhci_arasan_hs400_enhanced_strobe; 798 host->mmc_host_ops.start_signal_voltage_switch = 799 sdhci_arasan_voltage_switch; 800 sdhci_arasan->has_cqe = true; 801 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 802 } 803 804 ret = sdhci_arasan_add_host(sdhci_arasan); 805 if (ret) 806 goto err_add_host; 807 808 return 0; 809 810 err_add_host: 811 if (!IS_ERR(sdhci_arasan->phy)) 812 phy_exit(sdhci_arasan->phy); 813 unreg_clk: 814 sdhci_arasan_unregister_sdclk(&pdev->dev); 815 clk_disable_all: 816 clk_disable_unprepare(clk_xin); 817 clk_dis_ahb: 818 clk_disable_unprepare(sdhci_arasan->clk_ahb); 819 err_pltfm_free: 820 sdhci_pltfm_free(pdev); 821 return ret; 822 } 823 824 static int sdhci_arasan_remove(struct platform_device *pdev) 825 { 826 int ret; 827 struct sdhci_host *host = platform_get_drvdata(pdev); 828 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 829 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 830 struct clk *clk_ahb = sdhci_arasan->clk_ahb; 831 832 if (!IS_ERR(sdhci_arasan->phy)) { 833 if (sdhci_arasan->is_phy_on) 834 phy_power_off(sdhci_arasan->phy); 835 phy_exit(sdhci_arasan->phy); 836 } 837 838 sdhci_arasan_unregister_sdclk(&pdev->dev); 839 840 ret = sdhci_pltfm_unregister(pdev); 841 842 clk_disable_unprepare(clk_ahb); 843 844 return ret; 845 } 846 847 static struct platform_driver sdhci_arasan_driver = { 848 .driver = { 849 .name = "sdhci-arasan", 850 .of_match_table = sdhci_arasan_of_match, 851 .pm = &sdhci_arasan_dev_pm_ops, 852 }, 853 .probe = sdhci_arasan_probe, 854 .remove = sdhci_arasan_remove, 855 }; 856 857 module_platform_driver(sdhci_arasan_driver); 858 859 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller"); 860 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>"); 861 MODULE_LICENSE("GPL"); 862