1 /* 2 * Arasan Secure Digital Host Controller Interface. 3 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu> 4 * Copyright (c) 2012 Wind River Systems, Inc. 5 * Copyright (C) 2013 Pengutronix e.K. 6 * Copyright (C) 2013 Xilinx Inc. 7 * 8 * Based on sdhci-of-esdhc.c 9 * 10 * Copyright (c) 2007 Freescale Semiconductor, Inc. 11 * Copyright (c) 2009 MontaVista Software, Inc. 12 * 13 * Authors: Xiaobo Xie <X.Xie@freescale.com> 14 * Anton Vorontsov <avorontsov@ru.mvista.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or (at 19 * your option) any later version. 20 */ 21 22 #include <linux/clk-provider.h> 23 #include <linux/mfd/syscon.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/phy/phy.h> 27 #include <linux/regmap.h> 28 #include <linux/of.h> 29 30 #include "cqhci.h" 31 #include "sdhci-pltfm.h" 32 33 #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 34 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 35 #define VENDOR_ENHANCED_STROBE BIT(0) 36 37 #define PHY_CLK_TOO_SLOW_HZ 400000 38 39 /* 40 * On some SoCs the syscon area has a feature where the upper 16-bits of 41 * each 32-bit register act as a write mask for the lower 16-bits. This allows 42 * atomic updates of the register without locking. This macro is used on SoCs 43 * that have that feature. 44 */ 45 #define HIWORD_UPDATE(val, mask, shift) \ 46 ((val) << (shift) | (mask) << ((shift) + 16)) 47 48 /** 49 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map 50 * 51 * @reg: Offset within the syscon of the register containing this field 52 * @width: Number of bits for this field 53 * @shift: Bit offset within @reg of this field (or -1 if not avail) 54 */ 55 struct sdhci_arasan_soc_ctl_field { 56 u32 reg; 57 u16 width; 58 s16 shift; 59 }; 60 61 /** 62 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers 63 * 64 * It's up to the licensee of the Arsan IP block to make these available 65 * somewhere if needed. Presumably these will be scattered somewhere that's 66 * accessible via the syscon API. 67 * 68 * @baseclkfreq: Where to find corecfg_baseclkfreq 69 * @clockmultiplier: Where to find corecfg_clockmultiplier 70 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon 71 */ 72 struct sdhci_arasan_soc_ctl_map { 73 struct sdhci_arasan_soc_ctl_field baseclkfreq; 74 struct sdhci_arasan_soc_ctl_field clockmultiplier; 75 bool hiword_update; 76 }; 77 78 /** 79 * struct sdhci_arasan_data 80 * @host: Pointer to the main SDHCI host structure. 81 * @clk_ahb: Pointer to the AHB clock 82 * @phy: Pointer to the generic phy 83 * @is_phy_on: True if the PHY is on; false if not. 84 * @sdcardclk_hw: Struct for the clock we might provide to a PHY. 85 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. 86 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. 87 * @soc_ctl_map: Map to get offsets into soc_ctl registers. 88 */ 89 struct sdhci_arasan_data { 90 struct sdhci_host *host; 91 struct clk *clk_ahb; 92 struct phy *phy; 93 bool is_phy_on; 94 95 bool has_cqe; 96 struct clk_hw sdcardclk_hw; 97 struct clk *sdcardclk; 98 99 struct regmap *soc_ctl_base; 100 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; 101 unsigned int quirks; /* Arasan deviations from spec */ 102 103 /* Controller does not have CD wired and will not function normally without */ 104 #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0) 105 /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the 106 * internal clock even when the clock isn't stable */ 107 #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1) 108 }; 109 110 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = { 111 .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 }, 112 .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0}, 113 .hiword_update = true, 114 }; 115 116 /** 117 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers 118 * 119 * This function allows writing to fields in sdhci_arasan_soc_ctl_map. 120 * Note that if a field is specified as not available (shift < 0) then 121 * this function will silently return an error code. It will be noisy 122 * and print errors for any other (unexpected) errors. 123 * 124 * @host: The sdhci_host 125 * @fld: The field to write to 126 * @val: The value to write 127 */ 128 static int sdhci_arasan_syscon_write(struct sdhci_host *host, 129 const struct sdhci_arasan_soc_ctl_field *fld, 130 u32 val) 131 { 132 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 133 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 134 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; 135 u32 reg = fld->reg; 136 u16 width = fld->width; 137 s16 shift = fld->shift; 138 int ret; 139 140 /* 141 * Silently return errors for shift < 0 so caller doesn't have 142 * to check for fields which are optional. For fields that 143 * are required then caller needs to do something special 144 * anyway. 145 */ 146 if (shift < 0) 147 return -EINVAL; 148 149 if (sdhci_arasan->soc_ctl_map->hiword_update) 150 ret = regmap_write(soc_ctl_base, reg, 151 HIWORD_UPDATE(val, GENMASK(width, 0), 152 shift)); 153 else 154 ret = regmap_update_bits(soc_ctl_base, reg, 155 GENMASK(shift + width, shift), 156 val << shift); 157 158 /* Yell about (unexpected) regmap errors */ 159 if (ret) 160 pr_warn("%s: Regmap write fail: %d\n", 161 mmc_hostname(host->mmc), ret); 162 163 return ret; 164 } 165 166 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) 167 { 168 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 169 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 170 bool ctrl_phy = false; 171 172 if (!IS_ERR(sdhci_arasan->phy)) { 173 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) { 174 /* 175 * If PHY off, set clock to max speed and power PHY on. 176 * 177 * Although PHY docs apparently suggest power cycling 178 * when changing the clock the PHY doesn't like to be 179 * powered on while at low speeds like those used in ID 180 * mode. Even worse is powering the PHY on while the 181 * clock is off. 182 * 183 * To workaround the PHY limitations, the best we can 184 * do is to power it on at a faster speed and then slam 185 * through low speeds without power cycling. 186 */ 187 sdhci_set_clock(host, host->max_clk); 188 phy_power_on(sdhci_arasan->phy); 189 sdhci_arasan->is_phy_on = true; 190 191 /* 192 * We'll now fall through to the below case with 193 * ctrl_phy = false (so we won't turn off/on). The 194 * sdhci_set_clock() will set the real clock. 195 */ 196 } else if (clock > PHY_CLK_TOO_SLOW_HZ) { 197 /* 198 * At higher clock speeds the PHY is fine being power 199 * cycled and docs say you _should_ power cycle when 200 * changing clock speeds. 201 */ 202 ctrl_phy = true; 203 } 204 } 205 206 if (ctrl_phy && sdhci_arasan->is_phy_on) { 207 phy_power_off(sdhci_arasan->phy); 208 sdhci_arasan->is_phy_on = false; 209 } 210 211 sdhci_set_clock(host, clock); 212 213 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE) 214 /* 215 * Some controllers immediately report SDHCI_CLOCK_INT_STABLE 216 * after enabling the clock even though the clock is not 217 * stable. Trying to use a clock without waiting here results 218 * in EILSEQ while detecting some older/slower cards. The 219 * chosen delay is the maximum delay from sdhci_set_clock. 220 */ 221 msleep(20); 222 223 if (ctrl_phy) { 224 phy_power_on(sdhci_arasan->phy); 225 sdhci_arasan->is_phy_on = true; 226 } 227 } 228 229 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc, 230 struct mmc_ios *ios) 231 { 232 u32 vendor; 233 struct sdhci_host *host = mmc_priv(mmc); 234 235 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER); 236 if (ios->enhanced_strobe) 237 vendor |= VENDOR_ENHANCED_STROBE; 238 else 239 vendor &= ~VENDOR_ENHANCED_STROBE; 240 241 sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER); 242 } 243 244 static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) 245 { 246 u8 ctrl; 247 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 248 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 249 250 sdhci_reset(host, mask); 251 252 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { 253 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 254 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 255 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 256 } 257 } 258 259 static int sdhci_arasan_voltage_switch(struct mmc_host *mmc, 260 struct mmc_ios *ios) 261 { 262 switch (ios->signal_voltage) { 263 case MMC_SIGNAL_VOLTAGE_180: 264 /* 265 * Plese don't switch to 1V8 as arasan,5.1 doesn't 266 * actually refer to this setting to indicate the 267 * signal voltage and the state machine will be broken 268 * actually if we force to enable 1V8. That's something 269 * like broken quirk but we could work around here. 270 */ 271 return 0; 272 case MMC_SIGNAL_VOLTAGE_330: 273 case MMC_SIGNAL_VOLTAGE_120: 274 /* We don't support 3V3 and 1V2 */ 275 break; 276 } 277 278 return -EINVAL; 279 } 280 281 static void sdhci_arasan_set_power(struct sdhci_host *host, unsigned char mode, 282 unsigned short vdd) 283 { 284 if (!IS_ERR(host->mmc->supply.vmmc)) { 285 struct mmc_host *mmc = host->mmc; 286 287 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 288 } 289 sdhci_set_power_noreg(host, mode, vdd); 290 } 291 292 static const struct sdhci_ops sdhci_arasan_ops = { 293 .set_clock = sdhci_arasan_set_clock, 294 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 295 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 296 .set_bus_width = sdhci_set_bus_width, 297 .reset = sdhci_arasan_reset, 298 .set_uhs_signaling = sdhci_set_uhs_signaling, 299 .set_power = sdhci_arasan_set_power, 300 }; 301 302 static const struct sdhci_pltfm_data sdhci_arasan_pdata = { 303 .ops = &sdhci_arasan_ops, 304 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 305 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 306 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | 307 SDHCI_QUIRK2_STOP_WITH_TC, 308 }; 309 310 static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask) 311 { 312 int cmd_error = 0; 313 int data_error = 0; 314 315 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 316 return intmask; 317 318 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 319 320 return 0; 321 } 322 323 static void sdhci_arasan_dumpregs(struct mmc_host *mmc) 324 { 325 sdhci_dumpregs(mmc_priv(mmc)); 326 } 327 328 static void sdhci_arasan_cqe_enable(struct mmc_host *mmc) 329 { 330 struct sdhci_host *host = mmc_priv(mmc); 331 u32 reg; 332 333 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 334 while (reg & SDHCI_DATA_AVAILABLE) { 335 sdhci_readl(host, SDHCI_BUFFER); 336 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 337 } 338 339 sdhci_cqe_enable(mmc); 340 } 341 342 static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = { 343 .enable = sdhci_arasan_cqe_enable, 344 .disable = sdhci_cqe_disable, 345 .dumpregs = sdhci_arasan_dumpregs, 346 }; 347 348 static const struct sdhci_ops sdhci_arasan_cqe_ops = { 349 .set_clock = sdhci_arasan_set_clock, 350 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 351 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 352 .set_bus_width = sdhci_set_bus_width, 353 .reset = sdhci_arasan_reset, 354 .set_uhs_signaling = sdhci_set_uhs_signaling, 355 .set_power = sdhci_arasan_set_power, 356 .irq = sdhci_arasan_cqhci_irq, 357 }; 358 359 static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = { 360 .ops = &sdhci_arasan_cqe_ops, 361 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 362 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 363 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 364 }; 365 366 #ifdef CONFIG_PM_SLEEP 367 /** 368 * sdhci_arasan_suspend - Suspend method for the driver 369 * @dev: Address of the device structure 370 * Returns 0 on success and error value on error 371 * 372 * Put the device in a low power state. 373 */ 374 static int sdhci_arasan_suspend(struct device *dev) 375 { 376 struct sdhci_host *host = dev_get_drvdata(dev); 377 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 378 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 379 int ret; 380 381 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 382 mmc_retune_needed(host->mmc); 383 384 if (sdhci_arasan->has_cqe) { 385 ret = cqhci_suspend(host->mmc); 386 if (ret) 387 return ret; 388 } 389 390 ret = sdhci_suspend_host(host); 391 if (ret) 392 return ret; 393 394 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) { 395 ret = phy_power_off(sdhci_arasan->phy); 396 if (ret) { 397 dev_err(dev, "Cannot power off phy.\n"); 398 sdhci_resume_host(host); 399 return ret; 400 } 401 sdhci_arasan->is_phy_on = false; 402 } 403 404 clk_disable(pltfm_host->clk); 405 clk_disable(sdhci_arasan->clk_ahb); 406 407 return 0; 408 } 409 410 /** 411 * sdhci_arasan_resume - Resume method for the driver 412 * @dev: Address of the device structure 413 * Returns 0 on success and error value on error 414 * 415 * Resume operation after suspend 416 */ 417 static int sdhci_arasan_resume(struct device *dev) 418 { 419 struct sdhci_host *host = dev_get_drvdata(dev); 420 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 421 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 422 int ret; 423 424 ret = clk_enable(sdhci_arasan->clk_ahb); 425 if (ret) { 426 dev_err(dev, "Cannot enable AHB clock.\n"); 427 return ret; 428 } 429 430 ret = clk_enable(pltfm_host->clk); 431 if (ret) { 432 dev_err(dev, "Cannot enable SD clock.\n"); 433 return ret; 434 } 435 436 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) { 437 ret = phy_power_on(sdhci_arasan->phy); 438 if (ret) { 439 dev_err(dev, "Cannot power on phy.\n"); 440 return ret; 441 } 442 sdhci_arasan->is_phy_on = true; 443 } 444 445 ret = sdhci_resume_host(host); 446 if (ret) { 447 dev_err(dev, "Cannot resume host.\n"); 448 return ret; 449 } 450 451 if (sdhci_arasan->has_cqe) 452 return cqhci_resume(host->mmc); 453 454 return 0; 455 } 456 #endif /* ! CONFIG_PM_SLEEP */ 457 458 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend, 459 sdhci_arasan_resume); 460 461 static const struct of_device_id sdhci_arasan_of_match[] = { 462 /* SoC-specific compatible strings w/ soc_ctl_map */ 463 { 464 .compatible = "rockchip,rk3399-sdhci-5.1", 465 .data = &rk3399_soc_ctl_map, 466 }, 467 468 /* Generic compatible below here */ 469 { .compatible = "arasan,sdhci-8.9a" }, 470 { .compatible = "arasan,sdhci-5.1" }, 471 { .compatible = "arasan,sdhci-4.9a" }, 472 473 { /* sentinel */ } 474 }; 475 MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); 476 477 /** 478 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate 479 * 480 * Return the current actual rate of the SD card clock. This can be used 481 * to communicate with out PHY. 482 * 483 * @hw: Pointer to the hardware clock structure. 484 * @parent_rate The parent rate (should be rate of clk_xin). 485 * Returns the card clock rate. 486 */ 487 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw, 488 unsigned long parent_rate) 489 490 { 491 struct sdhci_arasan_data *sdhci_arasan = 492 container_of(hw, struct sdhci_arasan_data, sdcardclk_hw); 493 struct sdhci_host *host = sdhci_arasan->host; 494 495 return host->mmc->actual_clock; 496 } 497 498 static const struct clk_ops arasan_sdcardclk_ops = { 499 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, 500 }; 501 502 /** 503 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier 504 * 505 * The corecfg_clockmultiplier is supposed to contain clock multiplier 506 * value of programmable clock generator. 507 * 508 * NOTES: 509 * - Many existing devices don't seem to do this and work fine. To keep 510 * compatibility for old hardware where the device tree doesn't provide a 511 * register map, this function is a noop if a soc_ctl_map hasn't been provided 512 * for this platform. 513 * - The value of corecfg_clockmultiplier should sync with that of corresponding 514 * value reading from sdhci_capability_register. So this function is called 515 * once at probe time and never called again. 516 * 517 * @host: The sdhci_host 518 */ 519 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host, 520 u32 value) 521 { 522 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 523 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 524 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = 525 sdhci_arasan->soc_ctl_map; 526 527 /* Having a map is optional */ 528 if (!soc_ctl_map) 529 return; 530 531 /* If we have a map, we expect to have a syscon */ 532 if (!sdhci_arasan->soc_ctl_base) { 533 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", 534 mmc_hostname(host->mmc)); 535 return; 536 } 537 538 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value); 539 } 540 541 /** 542 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq 543 * 544 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This 545 * function can be used to make that happen. 546 * 547 * NOTES: 548 * - Many existing devices don't seem to do this and work fine. To keep 549 * compatibility for old hardware where the device tree doesn't provide a 550 * register map, this function is a noop if a soc_ctl_map hasn't been provided 551 * for this platform. 552 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider 553 * to achieve lower clock rates. That means that this function is called once 554 * at probe time and never called again. 555 * 556 * @host: The sdhci_host 557 */ 558 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) 559 { 560 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 561 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 562 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = 563 sdhci_arasan->soc_ctl_map; 564 u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000); 565 566 /* Having a map is optional */ 567 if (!soc_ctl_map) 568 return; 569 570 /* If we have a map, we expect to have a syscon */ 571 if (!sdhci_arasan->soc_ctl_base) { 572 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", 573 mmc_hostname(host->mmc)); 574 return; 575 } 576 577 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); 578 } 579 580 /** 581 * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use 582 * 583 * Some PHY devices need to know what the actual card clock is. In order for 584 * them to find out, we'll provide a clock through the common clock framework 585 * for them to query. 586 * 587 * Note: without seriously re-architecting SDHCI's clock code and testing on 588 * all platforms, there's no way to create a totally beautiful clock here 589 * with all clock ops implemented. Instead, we'll just create a clock that can 590 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock 591 * framework that we're doing things behind its back. This should be sufficient 592 * to create nice clean device tree bindings and later (if needed) we can try 593 * re-architecting SDHCI if we see some benefit to it. 594 * 595 * @sdhci_arasan: Our private data structure. 596 * @clk_xin: Pointer to the functional clock 597 * @dev: Pointer to our struct device. 598 * Returns 0 on success and error value on error 599 */ 600 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, 601 struct clk *clk_xin, 602 struct device *dev) 603 { 604 struct device_node *np = dev->of_node; 605 struct clk_init_data sdcardclk_init; 606 const char *parent_clk_name; 607 int ret; 608 609 /* Providing a clock to the PHY is optional; no error if missing */ 610 if (!of_find_property(np, "#clock-cells", NULL)) 611 return 0; 612 613 ret = of_property_read_string_index(np, "clock-output-names", 0, 614 &sdcardclk_init.name); 615 if (ret) { 616 dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); 617 return ret; 618 } 619 620 parent_clk_name = __clk_get_name(clk_xin); 621 sdcardclk_init.parent_names = &parent_clk_name; 622 sdcardclk_init.num_parents = 1; 623 sdcardclk_init.flags = CLK_GET_RATE_NOCACHE; 624 sdcardclk_init.ops = &arasan_sdcardclk_ops; 625 626 sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init; 627 sdhci_arasan->sdcardclk = 628 devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw); 629 sdhci_arasan->sdcardclk_hw.init = NULL; 630 631 ret = of_clk_add_provider(np, of_clk_src_simple_get, 632 sdhci_arasan->sdcardclk); 633 if (ret) 634 dev_err(dev, "Failed to add clock provider\n"); 635 636 return ret; 637 } 638 639 /** 640 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk() 641 * 642 * Should be called any time we're exiting and sdhci_arasan_register_sdclk() 643 * returned success. 644 * 645 * @dev: Pointer to our struct device. 646 */ 647 static void sdhci_arasan_unregister_sdclk(struct device *dev) 648 { 649 struct device_node *np = dev->of_node; 650 651 if (!of_find_property(np, "#clock-cells", NULL)) 652 return; 653 654 of_clk_del_provider(dev->of_node); 655 } 656 657 static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan) 658 { 659 struct sdhci_host *host = sdhci_arasan->host; 660 struct cqhci_host *cq_host; 661 bool dma64; 662 int ret; 663 664 if (!sdhci_arasan->has_cqe) 665 return sdhci_add_host(host); 666 667 ret = sdhci_setup_host(host); 668 if (ret) 669 return ret; 670 671 cq_host = devm_kzalloc(host->mmc->parent, 672 sizeof(*cq_host), GFP_KERNEL); 673 if (!cq_host) { 674 ret = -ENOMEM; 675 goto cleanup; 676 } 677 678 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; 679 cq_host->ops = &sdhci_arasan_cqhci_ops; 680 681 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 682 if (dma64) 683 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 684 685 ret = cqhci_init(cq_host, host->mmc, dma64); 686 if (ret) 687 goto cleanup; 688 689 ret = __sdhci_add_host(host); 690 if (ret) 691 goto cleanup; 692 693 return 0; 694 695 cleanup: 696 sdhci_cleanup_host(host); 697 return ret; 698 } 699 700 static int sdhci_arasan_probe(struct platform_device *pdev) 701 { 702 int ret; 703 const struct of_device_id *match; 704 struct device_node *node; 705 struct clk *clk_xin; 706 struct sdhci_host *host; 707 struct sdhci_pltfm_host *pltfm_host; 708 struct sdhci_arasan_data *sdhci_arasan; 709 struct device_node *np = pdev->dev.of_node; 710 const struct sdhci_pltfm_data *pdata; 711 712 if (of_device_is_compatible(pdev->dev.of_node, "arasan,sdhci-5.1")) 713 pdata = &sdhci_arasan_cqe_pdata; 714 else 715 pdata = &sdhci_arasan_pdata; 716 717 host = sdhci_pltfm_init(pdev, pdata, sizeof(*sdhci_arasan)); 718 719 if (IS_ERR(host)) 720 return PTR_ERR(host); 721 722 pltfm_host = sdhci_priv(host); 723 sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 724 sdhci_arasan->host = host; 725 726 match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node); 727 sdhci_arasan->soc_ctl_map = match->data; 728 729 node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0); 730 if (node) { 731 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); 732 of_node_put(node); 733 734 if (IS_ERR(sdhci_arasan->soc_ctl_base)) { 735 ret = PTR_ERR(sdhci_arasan->soc_ctl_base); 736 if (ret != -EPROBE_DEFER) 737 dev_err(&pdev->dev, "Can't get syscon: %d\n", 738 ret); 739 goto err_pltfm_free; 740 } 741 } 742 743 sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb"); 744 if (IS_ERR(sdhci_arasan->clk_ahb)) { 745 dev_err(&pdev->dev, "clk_ahb clock not found.\n"); 746 ret = PTR_ERR(sdhci_arasan->clk_ahb); 747 goto err_pltfm_free; 748 } 749 750 clk_xin = devm_clk_get(&pdev->dev, "clk_xin"); 751 if (IS_ERR(clk_xin)) { 752 dev_err(&pdev->dev, "clk_xin clock not found.\n"); 753 ret = PTR_ERR(clk_xin); 754 goto err_pltfm_free; 755 } 756 757 ret = clk_prepare_enable(sdhci_arasan->clk_ahb); 758 if (ret) { 759 dev_err(&pdev->dev, "Unable to enable AHB clock.\n"); 760 goto err_pltfm_free; 761 } 762 763 ret = clk_prepare_enable(clk_xin); 764 if (ret) { 765 dev_err(&pdev->dev, "Unable to enable SD clock.\n"); 766 goto clk_dis_ahb; 767 } 768 769 sdhci_get_of_property(pdev); 770 771 if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) 772 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; 773 774 if (of_property_read_bool(np, "xlnx,int-clock-stable-broken")) 775 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE; 776 777 pltfm_host->clk = clk_xin; 778 779 if (of_device_is_compatible(pdev->dev.of_node, 780 "rockchip,rk3399-sdhci-5.1")) 781 sdhci_arasan_update_clockmultiplier(host, 0x0); 782 783 sdhci_arasan_update_baseclkfreq(host); 784 785 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev); 786 if (ret) 787 goto clk_disable_all; 788 789 ret = mmc_of_parse(host->mmc); 790 if (ret) { 791 dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret); 792 goto unreg_clk; 793 } 794 795 sdhci_arasan->phy = ERR_PTR(-ENODEV); 796 if (of_device_is_compatible(pdev->dev.of_node, 797 "arasan,sdhci-5.1")) { 798 sdhci_arasan->phy = devm_phy_get(&pdev->dev, 799 "phy_arasan"); 800 if (IS_ERR(sdhci_arasan->phy)) { 801 ret = PTR_ERR(sdhci_arasan->phy); 802 dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n"); 803 goto unreg_clk; 804 } 805 806 ret = phy_init(sdhci_arasan->phy); 807 if (ret < 0) { 808 dev_err(&pdev->dev, "phy_init err.\n"); 809 goto unreg_clk; 810 } 811 812 host->mmc_host_ops.hs400_enhanced_strobe = 813 sdhci_arasan_hs400_enhanced_strobe; 814 host->mmc_host_ops.start_signal_voltage_switch = 815 sdhci_arasan_voltage_switch; 816 sdhci_arasan->has_cqe = true; 817 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 818 } 819 820 ret = sdhci_arasan_add_host(sdhci_arasan); 821 if (ret) 822 goto err_add_host; 823 824 return 0; 825 826 err_add_host: 827 if (!IS_ERR(sdhci_arasan->phy)) 828 phy_exit(sdhci_arasan->phy); 829 unreg_clk: 830 sdhci_arasan_unregister_sdclk(&pdev->dev); 831 clk_disable_all: 832 clk_disable_unprepare(clk_xin); 833 clk_dis_ahb: 834 clk_disable_unprepare(sdhci_arasan->clk_ahb); 835 err_pltfm_free: 836 sdhci_pltfm_free(pdev); 837 return ret; 838 } 839 840 static int sdhci_arasan_remove(struct platform_device *pdev) 841 { 842 int ret; 843 struct sdhci_host *host = platform_get_drvdata(pdev); 844 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 845 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 846 struct clk *clk_ahb = sdhci_arasan->clk_ahb; 847 848 if (!IS_ERR(sdhci_arasan->phy)) { 849 if (sdhci_arasan->is_phy_on) 850 phy_power_off(sdhci_arasan->phy); 851 phy_exit(sdhci_arasan->phy); 852 } 853 854 sdhci_arasan_unregister_sdclk(&pdev->dev); 855 856 ret = sdhci_pltfm_unregister(pdev); 857 858 clk_disable_unprepare(clk_ahb); 859 860 return ret; 861 } 862 863 static struct platform_driver sdhci_arasan_driver = { 864 .driver = { 865 .name = "sdhci-arasan", 866 .of_match_table = sdhci_arasan_of_match, 867 .pm = &sdhci_arasan_dev_pm_ops, 868 }, 869 .probe = sdhci_arasan_probe, 870 .remove = sdhci_arasan_remove, 871 }; 872 873 module_platform_driver(sdhci_arasan_driver); 874 875 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller"); 876 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>"); 877 MODULE_LICENSE("GPL"); 878