1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Arasan Secure Digital Host Controller Interface.
4  * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
5  * Copyright (c) 2012 Wind River Systems, Inc.
6  * Copyright (C) 2013 Pengutronix e.K.
7  * Copyright (C) 2013 Xilinx Inc.
8  *
9  * Based on sdhci-of-esdhc.c
10  *
11  * Copyright (c) 2007 Freescale Semiconductor, Inc.
12  * Copyright (c) 2009 MontaVista Software, Inc.
13  *
14  * Authors: Xiaobo Xie <X.Xie@freescale.com>
15  *	    Anton Vorontsov <avorontsov@ru.mvista.com>
16  */
17 
18 #include <linux/clk-provider.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/phy/phy.h>
23 #include <linux/regmap.h>
24 #include <linux/of.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
26 
27 #include "cqhci.h"
28 #include "sdhci-pltfm.h"
29 
30 #define SDHCI_ARASAN_VENDOR_REGISTER	0x78
31 
32 #define SDHCI_ARASAN_ITAPDLY_REGISTER	0xF0F8
33 #define SDHCI_ARASAN_ITAPDLY_SEL_MASK	0xFF
34 
35 #define SDHCI_ARASAN_OTAPDLY_REGISTER	0xF0FC
36 #define SDHCI_ARASAN_OTAPDLY_SEL_MASK	0x3F
37 
38 #define SDHCI_ARASAN_CQE_BASE_ADDR	0x200
39 #define VENDOR_ENHANCED_STROBE		BIT(0)
40 
41 #define PHY_CLK_TOO_SLOW_HZ		400000
42 
43 #define SDHCI_ITAPDLY_CHGWIN		0x200
44 #define SDHCI_ITAPDLY_ENABLE		0x100
45 #define SDHCI_OTAPDLY_ENABLE		0x40
46 
47 /* Default settings for ZynqMP Clock Phases */
48 #define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63,  0,   0, 183, 54,  0, 0}
49 #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
50 
51 #define VERSAL_ICLK_PHASE {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0}
52 #define VERSAL_OCLK_PHASE {0,  60, 48, 0, 48, 72, 90, 36, 60, 90, 0}
53 
54 /*
55  * On some SoCs the syscon area has a feature where the upper 16-bits of
56  * each 32-bit register act as a write mask for the lower 16-bits.  This allows
57  * atomic updates of the register without locking.  This macro is used on SoCs
58  * that have that feature.
59  */
60 #define HIWORD_UPDATE(val, mask, shift) \
61 		((val) << (shift) | (mask) << ((shift) + 16))
62 
63 /**
64  * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
65  *
66  * @reg:	Offset within the syscon of the register containing this field
67  * @width:	Number of bits for this field
68  * @shift:	Bit offset within @reg of this field (or -1 if not avail)
69  */
70 struct sdhci_arasan_soc_ctl_field {
71 	u32 reg;
72 	u16 width;
73 	s16 shift;
74 };
75 
76 /**
77  * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
78  *
79  * @baseclkfreq:	Where to find corecfg_baseclkfreq
80  * @clockmultiplier:	Where to find corecfg_clockmultiplier
81  * @support64b:		Where to find SUPPORT64B bit
82  * @hiword_update:	If true, use HIWORD_UPDATE to access the syscon
83  *
84  * It's up to the licensee of the Arsan IP block to make these available
85  * somewhere if needed.  Presumably these will be scattered somewhere that's
86  * accessible via the syscon API.
87  */
88 struct sdhci_arasan_soc_ctl_map {
89 	struct sdhci_arasan_soc_ctl_field	baseclkfreq;
90 	struct sdhci_arasan_soc_ctl_field	clockmultiplier;
91 	struct sdhci_arasan_soc_ctl_field	support64b;
92 	bool					hiword_update;
93 };
94 
95 /**
96  * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller
97  *
98  * @sdcardclk_ops:	The output clock related operations
99  * @sampleclk_ops:	The sample clock related operations
100  */
101 struct sdhci_arasan_clk_ops {
102 	const struct clk_ops *sdcardclk_ops;
103 	const struct clk_ops *sampleclk_ops;
104 };
105 
106 /**
107  * struct sdhci_arasan_clk_data - Arasan Controller Clock Data.
108  *
109  * @sdcardclk_hw:	Struct for the clock we might provide to a PHY.
110  * @sdcardclk:		Pointer to normal 'struct clock' for sdcardclk_hw.
111  * @sampleclk_hw:	Struct for the clock we might provide to a PHY.
112  * @sampleclk:		Pointer to normal 'struct clock' for sampleclk_hw.
113  * @clk_phase_in:	Array of Input Clock Phase Delays for all speed modes
114  * @clk_phase_out:	Array of Output Clock Phase Delays for all speed modes
115  * @set_clk_delays:	Function pointer for setting Clock Delays
116  * @clk_of_data:	Platform specific runtime clock data storage pointer
117  */
118 struct sdhci_arasan_clk_data {
119 	struct clk_hw	sdcardclk_hw;
120 	struct clk      *sdcardclk;
121 	struct clk_hw	sampleclk_hw;
122 	struct clk      *sampleclk;
123 	int		clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
124 	int		clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
125 	void		(*set_clk_delays)(struct sdhci_host *host);
126 	void		*clk_of_data;
127 };
128 
129 /**
130  * struct sdhci_arasan_data - Arasan Controller Data
131  *
132  * @host:		Pointer to the main SDHCI host structure.
133  * @clk_ahb:		Pointer to the AHB clock
134  * @phy:		Pointer to the generic phy
135  * @is_phy_on:		True if the PHY is on; false if not.
136  * @has_cqe:		True if controller has command queuing engine.
137  * @clk_data:		Struct for the Arasan Controller Clock Data.
138  * @clk_ops:		Struct for the Arasan Controller Clock Operations.
139  * @soc_ctl_base:	Pointer to regmap for syscon for soc_ctl registers.
140  * @soc_ctl_map:	Map to get offsets into soc_ctl registers.
141  * @quirks:		Arasan deviations from spec.
142  */
143 struct sdhci_arasan_data {
144 	struct sdhci_host *host;
145 	struct clk	*clk_ahb;
146 	struct phy	*phy;
147 	bool		is_phy_on;
148 
149 	bool		has_cqe;
150 	struct sdhci_arasan_clk_data clk_data;
151 	const struct sdhci_arasan_clk_ops *clk_ops;
152 
153 	struct regmap	*soc_ctl_base;
154 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
155 	unsigned int	quirks;
156 
157 /* Controller does not have CD wired and will not function normally without */
158 #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST	BIT(0)
159 /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the
160  * internal clock even when the clock isn't stable */
161 #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1)
162 /*
163  * Some of the Arasan variations might not have timing requirements
164  * met at 25MHz for Default Speed mode, those controllers work at
165  * 19MHz instead
166  */
167 #define SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN BIT(2)
168 };
169 
170 struct sdhci_arasan_of_data {
171 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
172 	const struct sdhci_pltfm_data *pdata;
173 	const struct sdhci_arasan_clk_ops *clk_ops;
174 };
175 
176 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
177 	.baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
178 	.clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
179 	.hiword_update = true,
180 };
181 
182 static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = {
183 	.baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 },
184 	.clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
185 	.hiword_update = false,
186 };
187 
188 static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
189 	.baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 },
190 	.clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
191 	.hiword_update = false,
192 };
193 
194 static const struct sdhci_arasan_soc_ctl_map thunderbay_soc_ctl_map = {
195 	.baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
196 	.clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
197 	.support64b = { .reg = 0x4, .width = 1, .shift = 24 },
198 	.hiword_update = false,
199 };
200 
201 static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = {
202 	.baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
203 	.clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
204 	.support64b = { .reg = 0x4, .width = 1, .shift = 24 },
205 	.hiword_update = false,
206 };
207 
208 /**
209  * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
210  *
211  * @host:	The sdhci_host
212  * @fld:	The field to write to
213  * @val:	The value to write
214  *
215  * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
216  * Note that if a field is specified as not available (shift < 0) then
217  * this function will silently return an error code.  It will be noisy
218  * and print errors for any other (unexpected) errors.
219  *
220  * Return: 0 on success and error value on error
221  */
222 static int sdhci_arasan_syscon_write(struct sdhci_host *host,
223 				   const struct sdhci_arasan_soc_ctl_field *fld,
224 				   u32 val)
225 {
226 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
227 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
228 	struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
229 	u32 reg = fld->reg;
230 	u16 width = fld->width;
231 	s16 shift = fld->shift;
232 	int ret;
233 
234 	/*
235 	 * Silently return errors for shift < 0 so caller doesn't have
236 	 * to check for fields which are optional.  For fields that
237 	 * are required then caller needs to do something special
238 	 * anyway.
239 	 */
240 	if (shift < 0)
241 		return -EINVAL;
242 
243 	if (sdhci_arasan->soc_ctl_map->hiword_update)
244 		ret = regmap_write(soc_ctl_base, reg,
245 				   HIWORD_UPDATE(val, GENMASK(width, 0),
246 						 shift));
247 	else
248 		ret = regmap_update_bits(soc_ctl_base, reg,
249 					 GENMASK(shift + width, shift),
250 					 val << shift);
251 
252 	/* Yell about (unexpected) regmap errors */
253 	if (ret)
254 		pr_warn("%s: Regmap write fail: %d\n",
255 			 mmc_hostname(host->mmc), ret);
256 
257 	return ret;
258 }
259 
260 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
261 {
262 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
263 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
264 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
265 	bool ctrl_phy = false;
266 
267 	if (!IS_ERR(sdhci_arasan->phy)) {
268 		if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
269 			/*
270 			 * If PHY off, set clock to max speed and power PHY on.
271 			 *
272 			 * Although PHY docs apparently suggest power cycling
273 			 * when changing the clock the PHY doesn't like to be
274 			 * powered on while at low speeds like those used in ID
275 			 * mode.  Even worse is powering the PHY on while the
276 			 * clock is off.
277 			 *
278 			 * To workaround the PHY limitations, the best we can
279 			 * do is to power it on at a faster speed and then slam
280 			 * through low speeds without power cycling.
281 			 */
282 			sdhci_set_clock(host, host->max_clk);
283 			if (phy_power_on(sdhci_arasan->phy)) {
284 				pr_err("%s: Cannot power on phy.\n",
285 				       mmc_hostname(host->mmc));
286 				return;
287 			}
288 
289 			sdhci_arasan->is_phy_on = true;
290 
291 			/*
292 			 * We'll now fall through to the below case with
293 			 * ctrl_phy = false (so we won't turn off/on).  The
294 			 * sdhci_set_clock() will set the real clock.
295 			 */
296 		} else if (clock > PHY_CLK_TOO_SLOW_HZ) {
297 			/*
298 			 * At higher clock speeds the PHY is fine being power
299 			 * cycled and docs say you _should_ power cycle when
300 			 * changing clock speeds.
301 			 */
302 			ctrl_phy = true;
303 		}
304 	}
305 
306 	if (ctrl_phy && sdhci_arasan->is_phy_on) {
307 		phy_power_off(sdhci_arasan->phy);
308 		sdhci_arasan->is_phy_on = false;
309 	}
310 
311 	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN) {
312 		/*
313 		 * Some of the Arasan variations might not have timing
314 		 * requirements met at 25MHz for Default Speed mode,
315 		 * those controllers work at 19MHz instead.
316 		 */
317 		if (clock == DEFAULT_SPEED_MAX_DTR)
318 			clock = (DEFAULT_SPEED_MAX_DTR * 19) / 25;
319 	}
320 
321 	/* Set the Input and Output Clock Phase Delays */
322 	if (clk_data->set_clk_delays)
323 		clk_data->set_clk_delays(host);
324 
325 	sdhci_set_clock(host, clock);
326 
327 	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
328 		/*
329 		 * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
330 		 * after enabling the clock even though the clock is not
331 		 * stable. Trying to use a clock without waiting here results
332 		 * in EILSEQ while detecting some older/slower cards. The
333 		 * chosen delay is the maximum delay from sdhci_set_clock.
334 		 */
335 		msleep(20);
336 
337 	if (ctrl_phy) {
338 		if (phy_power_on(sdhci_arasan->phy)) {
339 			pr_err("%s: Cannot power on phy.\n",
340 			       mmc_hostname(host->mmc));
341 			return;
342 		}
343 
344 		sdhci_arasan->is_phy_on = true;
345 	}
346 }
347 
348 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
349 					struct mmc_ios *ios)
350 {
351 	u32 vendor;
352 	struct sdhci_host *host = mmc_priv(mmc);
353 
354 	vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER);
355 	if (ios->enhanced_strobe)
356 		vendor |= VENDOR_ENHANCED_STROBE;
357 	else
358 		vendor &= ~VENDOR_ENHANCED_STROBE;
359 
360 	sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER);
361 }
362 
363 static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
364 {
365 	u8 ctrl;
366 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
367 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
368 
369 	sdhci_reset(host, mask);
370 
371 	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
372 		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
373 		ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
374 		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
375 	}
376 }
377 
378 static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
379 				       struct mmc_ios *ios)
380 {
381 	switch (ios->signal_voltage) {
382 	case MMC_SIGNAL_VOLTAGE_180:
383 		/*
384 		 * Plese don't switch to 1V8 as arasan,5.1 doesn't
385 		 * actually refer to this setting to indicate the
386 		 * signal voltage and the state machine will be broken
387 		 * actually if we force to enable 1V8. That's something
388 		 * like broken quirk but we could work around here.
389 		 */
390 		return 0;
391 	case MMC_SIGNAL_VOLTAGE_330:
392 	case MMC_SIGNAL_VOLTAGE_120:
393 		/* We don't support 3V3 and 1V2 */
394 		break;
395 	}
396 
397 	return -EINVAL;
398 }
399 
400 static const struct sdhci_ops sdhci_arasan_ops = {
401 	.set_clock = sdhci_arasan_set_clock,
402 	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
403 	.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
404 	.set_bus_width = sdhci_set_bus_width,
405 	.reset = sdhci_arasan_reset,
406 	.set_uhs_signaling = sdhci_set_uhs_signaling,
407 	.set_power = sdhci_set_power_and_bus_voltage,
408 };
409 
410 static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
411 {
412 	int cmd_error = 0;
413 	int data_error = 0;
414 
415 	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
416 		return intmask;
417 
418 	cqhci_irq(host->mmc, intmask, cmd_error, data_error);
419 
420 	return 0;
421 }
422 
423 static void sdhci_arasan_dumpregs(struct mmc_host *mmc)
424 {
425 	sdhci_dumpregs(mmc_priv(mmc));
426 }
427 
428 static void sdhci_arasan_cqe_enable(struct mmc_host *mmc)
429 {
430 	struct sdhci_host *host = mmc_priv(mmc);
431 	u32 reg;
432 
433 	reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
434 	while (reg & SDHCI_DATA_AVAILABLE) {
435 		sdhci_readl(host, SDHCI_BUFFER);
436 		reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
437 	}
438 
439 	sdhci_cqe_enable(mmc);
440 }
441 
442 static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = {
443 	.enable         = sdhci_arasan_cqe_enable,
444 	.disable        = sdhci_cqe_disable,
445 	.dumpregs       = sdhci_arasan_dumpregs,
446 };
447 
448 static const struct sdhci_ops sdhci_arasan_cqe_ops = {
449 	.set_clock = sdhci_arasan_set_clock,
450 	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
451 	.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
452 	.set_bus_width = sdhci_set_bus_width,
453 	.reset = sdhci_arasan_reset,
454 	.set_uhs_signaling = sdhci_set_uhs_signaling,
455 	.set_power = sdhci_set_power_and_bus_voltage,
456 	.irq = sdhci_arasan_cqhci_irq,
457 };
458 
459 static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
460 	.ops = &sdhci_arasan_cqe_ops,
461 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
462 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
463 			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
464 };
465 
466 static const struct sdhci_pltfm_data sdhci_arasan_thunderbay_pdata = {
467 	.ops = &sdhci_arasan_cqe_ops,
468 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
469 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
470 		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
471 		SDHCI_QUIRK2_STOP_WITH_TC |
472 		SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
473 };
474 
475 #ifdef CONFIG_PM_SLEEP
476 /**
477  * sdhci_arasan_suspend - Suspend method for the driver
478  * @dev:	Address of the device structure
479  *
480  * Put the device in a low power state.
481  *
482  * Return: 0 on success and error value on error
483  */
484 static int sdhci_arasan_suspend(struct device *dev)
485 {
486 	struct sdhci_host *host = dev_get_drvdata(dev);
487 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
488 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
489 	int ret;
490 
491 	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
492 		mmc_retune_needed(host->mmc);
493 
494 	if (sdhci_arasan->has_cqe) {
495 		ret = cqhci_suspend(host->mmc);
496 		if (ret)
497 			return ret;
498 	}
499 
500 	ret = sdhci_suspend_host(host);
501 	if (ret)
502 		return ret;
503 
504 	if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
505 		ret = phy_power_off(sdhci_arasan->phy);
506 		if (ret) {
507 			dev_err(dev, "Cannot power off phy.\n");
508 			if (sdhci_resume_host(host))
509 				dev_err(dev, "Cannot resume host.\n");
510 
511 			return ret;
512 		}
513 		sdhci_arasan->is_phy_on = false;
514 	}
515 
516 	clk_disable(pltfm_host->clk);
517 	clk_disable(sdhci_arasan->clk_ahb);
518 
519 	return 0;
520 }
521 
522 /**
523  * sdhci_arasan_resume - Resume method for the driver
524  * @dev:	Address of the device structure
525  *
526  * Resume operation after suspend
527  *
528  * Return: 0 on success and error value on error
529  */
530 static int sdhci_arasan_resume(struct device *dev)
531 {
532 	struct sdhci_host *host = dev_get_drvdata(dev);
533 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
534 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
535 	int ret;
536 
537 	ret = clk_enable(sdhci_arasan->clk_ahb);
538 	if (ret) {
539 		dev_err(dev, "Cannot enable AHB clock.\n");
540 		return ret;
541 	}
542 
543 	ret = clk_enable(pltfm_host->clk);
544 	if (ret) {
545 		dev_err(dev, "Cannot enable SD clock.\n");
546 		return ret;
547 	}
548 
549 	if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
550 		ret = phy_power_on(sdhci_arasan->phy);
551 		if (ret) {
552 			dev_err(dev, "Cannot power on phy.\n");
553 			return ret;
554 		}
555 		sdhci_arasan->is_phy_on = true;
556 	}
557 
558 	ret = sdhci_resume_host(host);
559 	if (ret) {
560 		dev_err(dev, "Cannot resume host.\n");
561 		return ret;
562 	}
563 
564 	if (sdhci_arasan->has_cqe)
565 		return cqhci_resume(host->mmc);
566 
567 	return 0;
568 }
569 #endif /* ! CONFIG_PM_SLEEP */
570 
571 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
572 			 sdhci_arasan_resume);
573 
574 /**
575  * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
576  *
577  * @hw:			Pointer to the hardware clock structure.
578  * @parent_rate:		The parent rate (should be rate of clk_xin).
579  *
580  * Return the current actual rate of the SD card clock.  This can be used
581  * to communicate with out PHY.
582  *
583  * Return: The card clock rate.
584  */
585 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
586 						      unsigned long parent_rate)
587 {
588 	struct sdhci_arasan_clk_data *clk_data =
589 		container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
590 	struct sdhci_arasan_data *sdhci_arasan =
591 		container_of(clk_data, struct sdhci_arasan_data, clk_data);
592 	struct sdhci_host *host = sdhci_arasan->host;
593 
594 	return host->mmc->actual_clock;
595 }
596 
597 static const struct clk_ops arasan_sdcardclk_ops = {
598 	.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
599 };
600 
601 /**
602  * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
603  *
604  * @hw:			Pointer to the hardware clock structure.
605  * @parent_rate:		The parent rate (should be rate of clk_xin).
606  *
607  * Return the current actual rate of the sampling clock.  This can be used
608  * to communicate with out PHY.
609  *
610  * Return: The sample clock rate.
611  */
612 static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw,
613 						      unsigned long parent_rate)
614 {
615 	struct sdhci_arasan_clk_data *clk_data =
616 		container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
617 	struct sdhci_arasan_data *sdhci_arasan =
618 		container_of(clk_data, struct sdhci_arasan_data, clk_data);
619 	struct sdhci_host *host = sdhci_arasan->host;
620 
621 	return host->mmc->actual_clock;
622 }
623 
624 static const struct clk_ops arasan_sampleclk_ops = {
625 	.recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
626 };
627 
628 /**
629  * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
630  *
631  * @hw:			Pointer to the hardware clock structure.
632  * @degrees:		The clock phase shift between 0 - 359.
633  *
634  * Set the SD Output Clock Tap Delays for Output path
635  *
636  * Return: 0 on success and error value on error
637  */
638 static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
639 {
640 	struct sdhci_arasan_clk_data *clk_data =
641 		container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
642 	struct sdhci_arasan_data *sdhci_arasan =
643 		container_of(clk_data, struct sdhci_arasan_data, clk_data);
644 	struct sdhci_host *host = sdhci_arasan->host;
645 	const char *clk_name = clk_hw_get_name(hw);
646 	u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
647 	u8 tap_delay, tap_max = 0;
648 	int ret;
649 
650 	/* This is applicable for SDHCI_SPEC_300 and above */
651 	if (host->version < SDHCI_SPEC_300)
652 		return 0;
653 
654 	switch (host->timing) {
655 	case MMC_TIMING_MMC_HS:
656 	case MMC_TIMING_SD_HS:
657 	case MMC_TIMING_UHS_SDR25:
658 	case MMC_TIMING_UHS_DDR50:
659 	case MMC_TIMING_MMC_DDR52:
660 		/* For 50MHz clock, 30 Taps are available */
661 		tap_max = 30;
662 		break;
663 	case MMC_TIMING_UHS_SDR50:
664 		/* For 100MHz clock, 15 Taps are available */
665 		tap_max = 15;
666 		break;
667 	case MMC_TIMING_UHS_SDR104:
668 	case MMC_TIMING_MMC_HS200:
669 		/* For 200MHz clock, 8 Taps are available */
670 		tap_max = 8;
671 		break;
672 	default:
673 		break;
674 	}
675 
676 	tap_delay = (degrees * tap_max) / 360;
677 
678 	/* Set the Clock Phase */
679 	ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay);
680 	if (ret)
681 		pr_err("Error setting Output Tap Delay\n");
682 
683 	/* Release DLL Reset */
684 	zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_RELEASE);
685 
686 	return ret;
687 }
688 
689 static const struct clk_ops zynqmp_sdcardclk_ops = {
690 	.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
691 	.set_phase = sdhci_zynqmp_sdcardclk_set_phase,
692 };
693 
694 /**
695  * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
696  *
697  * @hw:			Pointer to the hardware clock structure.
698  * @degrees:		The clock phase shift between 0 - 359.
699  *
700  * Set the SD Input Clock Tap Delays for Input path
701  *
702  * Return: 0 on success and error value on error
703  */
704 static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees)
705 {
706 	struct sdhci_arasan_clk_data *clk_data =
707 		container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
708 	struct sdhci_arasan_data *sdhci_arasan =
709 		container_of(clk_data, struct sdhci_arasan_data, clk_data);
710 	struct sdhci_host *host = sdhci_arasan->host;
711 	const char *clk_name = clk_hw_get_name(hw);
712 	u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1;
713 	u8 tap_delay, tap_max = 0;
714 	int ret;
715 
716 	/* This is applicable for SDHCI_SPEC_300 and above */
717 	if (host->version < SDHCI_SPEC_300)
718 		return 0;
719 
720 	/* Assert DLL Reset */
721 	zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_ASSERT);
722 
723 	switch (host->timing) {
724 	case MMC_TIMING_MMC_HS:
725 	case MMC_TIMING_SD_HS:
726 	case MMC_TIMING_UHS_SDR25:
727 	case MMC_TIMING_UHS_DDR50:
728 	case MMC_TIMING_MMC_DDR52:
729 		/* For 50MHz clock, 120 Taps are available */
730 		tap_max = 120;
731 		break;
732 	case MMC_TIMING_UHS_SDR50:
733 		/* For 100MHz clock, 60 Taps are available */
734 		tap_max = 60;
735 		break;
736 	case MMC_TIMING_UHS_SDR104:
737 	case MMC_TIMING_MMC_HS200:
738 		/* For 200MHz clock, 30 Taps are available */
739 		tap_max = 30;
740 		break;
741 	default:
742 		break;
743 	}
744 
745 	tap_delay = (degrees * tap_max) / 360;
746 
747 	/* Set the Clock Phase */
748 	ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_INPUT, tap_delay);
749 	if (ret)
750 		pr_err("Error setting Input Tap Delay\n");
751 
752 	return ret;
753 }
754 
755 static const struct clk_ops zynqmp_sampleclk_ops = {
756 	.recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
757 	.set_phase = sdhci_zynqmp_sampleclk_set_phase,
758 };
759 
760 /**
761  * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
762  *
763  * @hw:			Pointer to the hardware clock structure.
764  * @degrees:		The clock phase shift between 0 - 359.
765  *
766  * Set the SD Output Clock Tap Delays for Output path
767  *
768  * Return: 0 on success and error value on error
769  */
770 static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
771 {
772 	struct sdhci_arasan_clk_data *clk_data =
773 		container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
774 	struct sdhci_arasan_data *sdhci_arasan =
775 		container_of(clk_data, struct sdhci_arasan_data, clk_data);
776 	struct sdhci_host *host = sdhci_arasan->host;
777 	u8 tap_delay, tap_max = 0;
778 
779 	/* This is applicable for SDHCI_SPEC_300 and above */
780 	if (host->version < SDHCI_SPEC_300)
781 		return 0;
782 
783 	switch (host->timing) {
784 	case MMC_TIMING_MMC_HS:
785 	case MMC_TIMING_SD_HS:
786 	case MMC_TIMING_UHS_SDR25:
787 	case MMC_TIMING_UHS_DDR50:
788 	case MMC_TIMING_MMC_DDR52:
789 		/* For 50MHz clock, 30 Taps are available */
790 		tap_max = 30;
791 		break;
792 	case MMC_TIMING_UHS_SDR50:
793 		/* For 100MHz clock, 15 Taps are available */
794 		tap_max = 15;
795 		break;
796 	case MMC_TIMING_UHS_SDR104:
797 	case MMC_TIMING_MMC_HS200:
798 		/* For 200MHz clock, 8 Taps are available */
799 		tap_max = 8;
800 		break;
801 	default:
802 		break;
803 	}
804 
805 	tap_delay = (degrees * tap_max) / 360;
806 
807 	/* Set the Clock Phase */
808 	if (tap_delay) {
809 		u32 regval;
810 
811 		regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
812 		regval |= SDHCI_OTAPDLY_ENABLE;
813 		sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
814 		regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
815 		regval |= tap_delay;
816 		sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
817 	}
818 
819 	return 0;
820 }
821 
822 static const struct clk_ops versal_sdcardclk_ops = {
823 	.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
824 	.set_phase = sdhci_versal_sdcardclk_set_phase,
825 };
826 
827 /**
828  * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
829  *
830  * @hw:			Pointer to the hardware clock structure.
831  * @degrees:		The clock phase shift between 0 - 359.
832  *
833  * Set the SD Input Clock Tap Delays for Input path
834  *
835  * Return: 0 on success and error value on error
836  */
837 static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees)
838 {
839 	struct sdhci_arasan_clk_data *clk_data =
840 		container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
841 	struct sdhci_arasan_data *sdhci_arasan =
842 		container_of(clk_data, struct sdhci_arasan_data, clk_data);
843 	struct sdhci_host *host = sdhci_arasan->host;
844 	u8 tap_delay, tap_max = 0;
845 
846 	/* This is applicable for SDHCI_SPEC_300 and above */
847 	if (host->version < SDHCI_SPEC_300)
848 		return 0;
849 
850 	switch (host->timing) {
851 	case MMC_TIMING_MMC_HS:
852 	case MMC_TIMING_SD_HS:
853 	case MMC_TIMING_UHS_SDR25:
854 	case MMC_TIMING_UHS_DDR50:
855 	case MMC_TIMING_MMC_DDR52:
856 		/* For 50MHz clock, 120 Taps are available */
857 		tap_max = 120;
858 		break;
859 	case MMC_TIMING_UHS_SDR50:
860 		/* For 100MHz clock, 60 Taps are available */
861 		tap_max = 60;
862 		break;
863 	case MMC_TIMING_UHS_SDR104:
864 	case MMC_TIMING_MMC_HS200:
865 		/* For 200MHz clock, 30 Taps are available */
866 		tap_max = 30;
867 		break;
868 	default:
869 		break;
870 	}
871 
872 	tap_delay = (degrees * tap_max) / 360;
873 
874 	/* Set the Clock Phase */
875 	if (tap_delay) {
876 		u32 regval;
877 
878 		regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
879 		regval |= SDHCI_ITAPDLY_CHGWIN;
880 		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
881 		regval |= SDHCI_ITAPDLY_ENABLE;
882 		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
883 		regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
884 		regval |= tap_delay;
885 		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
886 		regval &= ~SDHCI_ITAPDLY_CHGWIN;
887 		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
888 	}
889 
890 	return 0;
891 }
892 
893 static const struct clk_ops versal_sampleclk_ops = {
894 	.recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
895 	.set_phase = sdhci_versal_sampleclk_set_phase,
896 };
897 
898 static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid)
899 {
900 	u16 clk;
901 
902 	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
903 	clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
904 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
905 
906 	/* Issue DLL Reset */
907 	zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE);
908 
909 	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
910 
911 	sdhci_enable_clk(host, clk);
912 }
913 
914 static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode)
915 {
916 	struct sdhci_host *host = mmc_priv(mmc);
917 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
918 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
919 	struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;
920 	const char *clk_name = clk_hw_get_name(hw);
921 	u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 :
922 							   NODE_SD_1;
923 	int err;
924 
925 	/* ZynqMP SD controller does not perform auto tuning in DDR50 mode */
926 	if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
927 		return 0;
928 
929 	arasan_zynqmp_dll_reset(host, device_id);
930 
931 	err = sdhci_execute_tuning(mmc, opcode);
932 	if (err)
933 		return err;
934 
935 	arasan_zynqmp_dll_reset(host, device_id);
936 
937 	return 0;
938 }
939 
940 /**
941  * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
942  *
943  * @host:		The sdhci_host
944  * @value:		The value to write
945  *
946  * The corecfg_clockmultiplier is supposed to contain clock multiplier
947  * value of programmable clock generator.
948  *
949  * NOTES:
950  * - Many existing devices don't seem to do this and work fine.  To keep
951  *   compatibility for old hardware where the device tree doesn't provide a
952  *   register map, this function is a noop if a soc_ctl_map hasn't been provided
953  *   for this platform.
954  * - The value of corecfg_clockmultiplier should sync with that of corresponding
955  *   value reading from sdhci_capability_register. So this function is called
956  *   once at probe time and never called again.
957  */
958 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
959 						u32 value)
960 {
961 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
962 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
963 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
964 		sdhci_arasan->soc_ctl_map;
965 
966 	/* Having a map is optional */
967 	if (!soc_ctl_map)
968 		return;
969 
970 	/* If we have a map, we expect to have a syscon */
971 	if (!sdhci_arasan->soc_ctl_base) {
972 		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
973 			mmc_hostname(host->mmc));
974 		return;
975 	}
976 
977 	sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
978 }
979 
980 /**
981  * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
982  *
983  * @host:		The sdhci_host
984  *
985  * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin.  This
986  * function can be used to make that happen.
987  *
988  * NOTES:
989  * - Many existing devices don't seem to do this and work fine.  To keep
990  *   compatibility for old hardware where the device tree doesn't provide a
991  *   register map, this function is a noop if a soc_ctl_map hasn't been provided
992  *   for this platform.
993  * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
994  *   to achieve lower clock rates.  That means that this function is called once
995  *   at probe time and never called again.
996  */
997 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
998 {
999 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1000 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1001 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
1002 		sdhci_arasan->soc_ctl_map;
1003 	u32 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000);
1004 
1005 	/* Having a map is optional */
1006 	if (!soc_ctl_map)
1007 		return;
1008 
1009 	/* If we have a map, we expect to have a syscon */
1010 	if (!sdhci_arasan->soc_ctl_base) {
1011 		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
1012 			mmc_hostname(host->mmc));
1013 		return;
1014 	}
1015 
1016 	sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
1017 }
1018 
1019 static void sdhci_arasan_set_clk_delays(struct sdhci_host *host)
1020 {
1021 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1022 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1023 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1024 
1025 	clk_set_phase(clk_data->sampleclk,
1026 		      clk_data->clk_phase_in[host->timing]);
1027 	clk_set_phase(clk_data->sdcardclk,
1028 		      clk_data->clk_phase_out[host->timing]);
1029 }
1030 
1031 static void arasan_dt_read_clk_phase(struct device *dev,
1032 				     struct sdhci_arasan_clk_data *clk_data,
1033 				     unsigned int timing, const char *prop)
1034 {
1035 	struct device_node *np = dev->of_node;
1036 
1037 	u32 clk_phase[2] = {0};
1038 	int ret;
1039 
1040 	/*
1041 	 * Read Tap Delay values from DT, if the DT does not contain the
1042 	 * Tap Values then use the pre-defined values.
1043 	 */
1044 	ret = of_property_read_variable_u32_array(np, prop, &clk_phase[0],
1045 						  2, 0);
1046 	if (ret < 0) {
1047 		dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
1048 			prop, clk_data->clk_phase_in[timing],
1049 			clk_data->clk_phase_out[timing]);
1050 		return;
1051 	}
1052 
1053 	/* The values read are Input and Output Clock Delays in order */
1054 	clk_data->clk_phase_in[timing] = clk_phase[0];
1055 	clk_data->clk_phase_out[timing] = clk_phase[1];
1056 }
1057 
1058 /**
1059  * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
1060  *
1061  * @dev:		Pointer to our struct device.
1062  * @clk_data:		Pointer to the Clock Data structure
1063  *
1064  * Called at initialization to parse the values of Clock Delays.
1065  */
1066 static void arasan_dt_parse_clk_phases(struct device *dev,
1067 				       struct sdhci_arasan_clk_data *clk_data)
1068 {
1069 	u32 mio_bank = 0;
1070 	int i;
1071 
1072 	/*
1073 	 * This has been kept as a pointer and is assigned a function here.
1074 	 * So that different controller variants can assign their own handling
1075 	 * function.
1076 	 */
1077 	clk_data->set_clk_delays = sdhci_arasan_set_clk_delays;
1078 
1079 	if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {
1080 		u32 zynqmp_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1081 			ZYNQMP_ICLK_PHASE;
1082 		u32 zynqmp_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1083 			ZYNQMP_OCLK_PHASE;
1084 
1085 		of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank);
1086 		if (mio_bank == 2) {
1087 			zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90;
1088 			zynqmp_oclk_phase[MMC_TIMING_MMC_HS200] = 90;
1089 		}
1090 
1091 		for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1092 			clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i];
1093 			clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i];
1094 		}
1095 	}
1096 
1097 	if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) {
1098 		u32 versal_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1099 			VERSAL_ICLK_PHASE;
1100 		u32 versal_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1101 			VERSAL_OCLK_PHASE;
1102 
1103 		for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1104 			clk_data->clk_phase_in[i] = versal_iclk_phase[i];
1105 			clk_data->clk_phase_out[i] = versal_oclk_phase[i];
1106 		}
1107 	}
1108 
1109 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY,
1110 				 "clk-phase-legacy");
1111 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS,
1112 				 "clk-phase-mmc-hs");
1113 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS,
1114 				 "clk-phase-sd-hs");
1115 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12,
1116 				 "clk-phase-uhs-sdr12");
1117 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25,
1118 				 "clk-phase-uhs-sdr25");
1119 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50,
1120 				 "clk-phase-uhs-sdr50");
1121 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104,
1122 				 "clk-phase-uhs-sdr104");
1123 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50,
1124 				 "clk-phase-uhs-ddr50");
1125 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52,
1126 				 "clk-phase-mmc-ddr52");
1127 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200,
1128 				 "clk-phase-mmc-hs200");
1129 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400,
1130 				 "clk-phase-mmc-hs400");
1131 }
1132 
1133 static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
1134 	.ops = &sdhci_arasan_ops,
1135 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1136 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1137 			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1138 			SDHCI_QUIRK2_STOP_WITH_TC,
1139 };
1140 
1141 static const struct sdhci_arasan_clk_ops arasan_clk_ops = {
1142 	.sdcardclk_ops = &arasan_sdcardclk_ops,
1143 	.sampleclk_ops = &arasan_sampleclk_ops,
1144 };
1145 
1146 static struct sdhci_arasan_of_data sdhci_arasan_generic_data = {
1147 	.pdata = &sdhci_arasan_pdata,
1148 	.clk_ops = &arasan_clk_ops,
1149 };
1150 
1151 static const struct sdhci_arasan_of_data sdhci_arasan_thunderbay_data = {
1152 	.soc_ctl_map = &thunderbay_soc_ctl_map,
1153 	.pdata = &sdhci_arasan_thunderbay_pdata,
1154 	.clk_ops = &arasan_clk_ops,
1155 };
1156 
1157 static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
1158 	.ops = &sdhci_arasan_cqe_ops,
1159 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1160 		SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1161 		SDHCI_QUIRK_NO_LED |
1162 		SDHCI_QUIRK_32BIT_DMA_ADDR |
1163 		SDHCI_QUIRK_32BIT_DMA_SIZE |
1164 		SDHCI_QUIRK_32BIT_ADMA_SIZE,
1165 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1166 		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1167 		SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1168 		SDHCI_QUIRK2_STOP_WITH_TC |
1169 		SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1170 };
1171 
1172 static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = {
1173 	.ops = &sdhci_arasan_ops,
1174 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1175 		SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1176 		SDHCI_QUIRK_NO_LED |
1177 		SDHCI_QUIRK_32BIT_DMA_ADDR |
1178 		SDHCI_QUIRK_32BIT_DMA_SIZE |
1179 		SDHCI_QUIRK_32BIT_ADMA_SIZE,
1180 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1181 		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1182 		SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1183 		SDHCI_QUIRK2_STOP_WITH_TC |
1184 		SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1185 };
1186 
1187 static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = {
1188 	.ops = &sdhci_arasan_ops,
1189 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1190 		SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1191 		SDHCI_QUIRK_NO_LED |
1192 		SDHCI_QUIRK_32BIT_DMA_ADDR |
1193 		SDHCI_QUIRK_32BIT_DMA_SIZE |
1194 		SDHCI_QUIRK_32BIT_ADMA_SIZE,
1195 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1196 		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1197 		SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1198 		SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1199 };
1200 
1201 static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
1202 	.soc_ctl_map = &rk3399_soc_ctl_map,
1203 	.pdata = &sdhci_arasan_cqe_pdata,
1204 	.clk_ops = &arasan_clk_ops,
1205 };
1206 
1207 static struct sdhci_arasan_of_data intel_lgm_emmc_data = {
1208 	.soc_ctl_map = &intel_lgm_emmc_soc_ctl_map,
1209 	.pdata = &sdhci_arasan_cqe_pdata,
1210 	.clk_ops = &arasan_clk_ops,
1211 };
1212 
1213 static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
1214 	.soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map,
1215 	.pdata = &sdhci_arasan_cqe_pdata,
1216 	.clk_ops = &arasan_clk_ops,
1217 };
1218 
1219 static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = {
1220 	.ops = &sdhci_arasan_ops,
1221 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1222 			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1223 			SDHCI_QUIRK2_STOP_WITH_TC,
1224 };
1225 
1226 static const struct sdhci_arasan_clk_ops zynqmp_clk_ops = {
1227 	.sdcardclk_ops = &zynqmp_sdcardclk_ops,
1228 	.sampleclk_ops = &zynqmp_sampleclk_ops,
1229 };
1230 
1231 static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = {
1232 	.pdata = &sdhci_arasan_zynqmp_pdata,
1233 	.clk_ops = &zynqmp_clk_ops,
1234 };
1235 
1236 static const struct sdhci_arasan_clk_ops versal_clk_ops = {
1237 	.sdcardclk_ops = &versal_sdcardclk_ops,
1238 	.sampleclk_ops = &versal_sampleclk_ops,
1239 };
1240 
1241 static struct sdhci_arasan_of_data sdhci_arasan_versal_data = {
1242 	.pdata = &sdhci_arasan_zynqmp_pdata,
1243 	.clk_ops = &versal_clk_ops,
1244 };
1245 
1246 static struct sdhci_arasan_of_data intel_keembay_emmc_data = {
1247 	.soc_ctl_map = &intel_keembay_soc_ctl_map,
1248 	.pdata = &sdhci_keembay_emmc_pdata,
1249 	.clk_ops = &arasan_clk_ops,
1250 };
1251 
1252 static struct sdhci_arasan_of_data intel_keembay_sd_data = {
1253 	.soc_ctl_map = &intel_keembay_soc_ctl_map,
1254 	.pdata = &sdhci_keembay_sd_pdata,
1255 	.clk_ops = &arasan_clk_ops,
1256 };
1257 
1258 static struct sdhci_arasan_of_data intel_keembay_sdio_data = {
1259 	.soc_ctl_map = &intel_keembay_soc_ctl_map,
1260 	.pdata = &sdhci_keembay_sdio_pdata,
1261 	.clk_ops = &arasan_clk_ops,
1262 };
1263 
1264 static const struct of_device_id sdhci_arasan_of_match[] = {
1265 	/* SoC-specific compatible strings w/ soc_ctl_map */
1266 	{
1267 		.compatible = "rockchip,rk3399-sdhci-5.1",
1268 		.data = &sdhci_arasan_rk3399_data,
1269 	},
1270 	{
1271 		.compatible = "intel,lgm-sdhci-5.1-emmc",
1272 		.data = &intel_lgm_emmc_data,
1273 	},
1274 	{
1275 		.compatible = "intel,lgm-sdhci-5.1-sdxc",
1276 		.data = &intel_lgm_sdxc_data,
1277 	},
1278 	{
1279 		.compatible = "intel,keembay-sdhci-5.1-emmc",
1280 		.data = &intel_keembay_emmc_data,
1281 	},
1282 	{
1283 		.compatible = "intel,keembay-sdhci-5.1-sd",
1284 		.data = &intel_keembay_sd_data,
1285 	},
1286 	{
1287 		.compatible = "intel,keembay-sdhci-5.1-sdio",
1288 		.data = &intel_keembay_sdio_data,
1289 	},
1290 	{
1291 		.compatible = "intel,thunderbay-sdhci-5.1",
1292 		.data = &sdhci_arasan_thunderbay_data,
1293 	},
1294 	/* Generic compatible below here */
1295 	{
1296 		.compatible = "arasan,sdhci-8.9a",
1297 		.data = &sdhci_arasan_generic_data,
1298 	},
1299 	{
1300 		.compatible = "arasan,sdhci-5.1",
1301 		.data = &sdhci_arasan_generic_data,
1302 	},
1303 	{
1304 		.compatible = "arasan,sdhci-4.9a",
1305 		.data = &sdhci_arasan_generic_data,
1306 	},
1307 	{
1308 		.compatible = "xlnx,zynqmp-8.9a",
1309 		.data = &sdhci_arasan_zynqmp_data,
1310 	},
1311 	{
1312 		.compatible = "xlnx,versal-8.9a",
1313 		.data = &sdhci_arasan_versal_data,
1314 	},
1315 	{ /* sentinel */ }
1316 };
1317 MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
1318 
1319 /**
1320  * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
1321  *
1322  * @sdhci_arasan:	Our private data structure.
1323  * @clk_xin:		Pointer to the functional clock
1324  * @dev:		Pointer to our struct device.
1325  *
1326  * Some PHY devices need to know what the actual card clock is.  In order for
1327  * them to find out, we'll provide a clock through the common clock framework
1328  * for them to query.
1329  *
1330  * Return: 0 on success and error value on error
1331  */
1332 static int
1333 sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan,
1334 				struct clk *clk_xin,
1335 				struct device *dev)
1336 {
1337 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1338 	struct device_node *np = dev->of_node;
1339 	struct clk_init_data sdcardclk_init;
1340 	const char *parent_clk_name;
1341 	int ret;
1342 
1343 	ret = of_property_read_string_index(np, "clock-output-names", 0,
1344 					    &sdcardclk_init.name);
1345 	if (ret) {
1346 		dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1347 		return ret;
1348 	}
1349 
1350 	parent_clk_name = __clk_get_name(clk_xin);
1351 	sdcardclk_init.parent_names = &parent_clk_name;
1352 	sdcardclk_init.num_parents = 1;
1353 	sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
1354 	sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops;
1355 
1356 	clk_data->sdcardclk_hw.init = &sdcardclk_init;
1357 	clk_data->sdcardclk =
1358 		devm_clk_register(dev, &clk_data->sdcardclk_hw);
1359 	if (IS_ERR(clk_data->sdcardclk))
1360 		return PTR_ERR(clk_data->sdcardclk);
1361 	clk_data->sdcardclk_hw.init = NULL;
1362 
1363 	ret = of_clk_add_provider(np, of_clk_src_simple_get,
1364 				  clk_data->sdcardclk);
1365 	if (ret)
1366 		dev_err(dev, "Failed to add sdcard clock provider\n");
1367 
1368 	return ret;
1369 }
1370 
1371 /**
1372  * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
1373  *
1374  * @sdhci_arasan:	Our private data structure.
1375  * @clk_xin:		Pointer to the functional clock
1376  * @dev:		Pointer to our struct device.
1377  *
1378  * Some PHY devices need to know what the actual card clock is.  In order for
1379  * them to find out, we'll provide a clock through the common clock framework
1380  * for them to query.
1381  *
1382  * Return: 0 on success and error value on error
1383  */
1384 static int
1385 sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan,
1386 				struct clk *clk_xin,
1387 				struct device *dev)
1388 {
1389 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1390 	struct device_node *np = dev->of_node;
1391 	struct clk_init_data sampleclk_init;
1392 	const char *parent_clk_name;
1393 	int ret;
1394 
1395 	ret = of_property_read_string_index(np, "clock-output-names", 1,
1396 					    &sampleclk_init.name);
1397 	if (ret) {
1398 		dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1399 		return ret;
1400 	}
1401 
1402 	parent_clk_name = __clk_get_name(clk_xin);
1403 	sampleclk_init.parent_names = &parent_clk_name;
1404 	sampleclk_init.num_parents = 1;
1405 	sampleclk_init.flags = CLK_GET_RATE_NOCACHE;
1406 	sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops;
1407 
1408 	clk_data->sampleclk_hw.init = &sampleclk_init;
1409 	clk_data->sampleclk =
1410 		devm_clk_register(dev, &clk_data->sampleclk_hw);
1411 	if (IS_ERR(clk_data->sampleclk))
1412 		return PTR_ERR(clk_data->sampleclk);
1413 	clk_data->sampleclk_hw.init = NULL;
1414 
1415 	ret = of_clk_add_provider(np, of_clk_src_simple_get,
1416 				  clk_data->sampleclk);
1417 	if (ret)
1418 		dev_err(dev, "Failed to add sample clock provider\n");
1419 
1420 	return ret;
1421 }
1422 
1423 /**
1424  * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
1425  *
1426  * @dev:		Pointer to our struct device.
1427  *
1428  * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
1429  * returned success.
1430  */
1431 static void sdhci_arasan_unregister_sdclk(struct device *dev)
1432 {
1433 	struct device_node *np = dev->of_node;
1434 
1435 	if (!of_find_property(np, "#clock-cells", NULL))
1436 		return;
1437 
1438 	of_clk_del_provider(dev->of_node);
1439 }
1440 
1441 /**
1442  * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
1443  * @host:		The sdhci_host
1444  * @value:		The value to write
1445  *
1446  * This should be set based on the System Address Bus.
1447  * 0: the Core supports only 32-bit System Address Bus.
1448  * 1: the Core supports 64-bit System Address Bus.
1449  *
1450  * NOTE:
1451  * For Keem Bay, it is required to clear this bit. Its default value is 1'b1.
1452  * Keem Bay does not support 64-bit access.
1453  */
1454 static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value)
1455 {
1456 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1457 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1458 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
1459 
1460 	/* Having a map is optional */
1461 	soc_ctl_map = sdhci_arasan->soc_ctl_map;
1462 	if (!soc_ctl_map)
1463 		return;
1464 
1465 	/* If we have a map, we expect to have a syscon */
1466 	if (!sdhci_arasan->soc_ctl_base) {
1467 		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
1468 			mmc_hostname(host->mmc));
1469 		return;
1470 	}
1471 
1472 	sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value);
1473 }
1474 
1475 /**
1476  * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
1477  *
1478  * @sdhci_arasan:	Our private data structure.
1479  * @clk_xin:		Pointer to the functional clock
1480  * @dev:		Pointer to our struct device.
1481  *
1482  * Some PHY devices need to know what the actual card clock is.  In order for
1483  * them to find out, we'll provide a clock through the common clock framework
1484  * for them to query.
1485  *
1486  * Note: without seriously re-architecting SDHCI's clock code and testing on
1487  * all platforms, there's no way to create a totally beautiful clock here
1488  * with all clock ops implemented.  Instead, we'll just create a clock that can
1489  * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
1490  * framework that we're doing things behind its back.  This should be sufficient
1491  * to create nice clean device tree bindings and later (if needed) we can try
1492  * re-architecting SDHCI if we see some benefit to it.
1493  *
1494  * Return: 0 on success and error value on error
1495  */
1496 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
1497 				       struct clk *clk_xin,
1498 				       struct device *dev)
1499 {
1500 	struct device_node *np = dev->of_node;
1501 	u32 num_clks = 0;
1502 	int ret;
1503 
1504 	/* Providing a clock to the PHY is optional; no error if missing */
1505 	if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
1506 		return 0;
1507 
1508 	ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev);
1509 	if (ret)
1510 		return ret;
1511 
1512 	if (num_clks) {
1513 		ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin,
1514 						      dev);
1515 		if (ret) {
1516 			sdhci_arasan_unregister_sdclk(dev);
1517 			return ret;
1518 		}
1519 	}
1520 
1521 	return 0;
1522 }
1523 
1524 static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
1525 {
1526 	struct sdhci_host *host = sdhci_arasan->host;
1527 	struct cqhci_host *cq_host;
1528 	bool dma64;
1529 	int ret;
1530 
1531 	if (!sdhci_arasan->has_cqe)
1532 		return sdhci_add_host(host);
1533 
1534 	ret = sdhci_setup_host(host);
1535 	if (ret)
1536 		return ret;
1537 
1538 	cq_host = devm_kzalloc(host->mmc->parent,
1539 			       sizeof(*cq_host), GFP_KERNEL);
1540 	if (!cq_host) {
1541 		ret = -ENOMEM;
1542 		goto cleanup;
1543 	}
1544 
1545 	cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
1546 	cq_host->ops = &sdhci_arasan_cqhci_ops;
1547 
1548 	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1549 	if (dma64)
1550 		cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1551 
1552 	ret = cqhci_init(cq_host, host->mmc, dma64);
1553 	if (ret)
1554 		goto cleanup;
1555 
1556 	ret = __sdhci_add_host(host);
1557 	if (ret)
1558 		goto cleanup;
1559 
1560 	return 0;
1561 
1562 cleanup:
1563 	sdhci_cleanup_host(host);
1564 	return ret;
1565 }
1566 
1567 static int sdhci_arasan_probe(struct platform_device *pdev)
1568 {
1569 	int ret;
1570 	struct device_node *node;
1571 	struct clk *clk_xin;
1572 	struct sdhci_host *host;
1573 	struct sdhci_pltfm_host *pltfm_host;
1574 	struct device *dev = &pdev->dev;
1575 	struct device_node *np = dev->of_node;
1576 	struct sdhci_arasan_data *sdhci_arasan;
1577 	const struct sdhci_arasan_of_data *data;
1578 
1579 	data = of_device_get_match_data(dev);
1580 	if (!data)
1581 		return -EINVAL;
1582 
1583 	host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan));
1584 
1585 	if (IS_ERR(host))
1586 		return PTR_ERR(host);
1587 
1588 	pltfm_host = sdhci_priv(host);
1589 	sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1590 	sdhci_arasan->host = host;
1591 
1592 	sdhci_arasan->soc_ctl_map = data->soc_ctl_map;
1593 	sdhci_arasan->clk_ops = data->clk_ops;
1594 
1595 	node = of_parse_phandle(np, "arasan,soc-ctl-syscon", 0);
1596 	if (node) {
1597 		sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
1598 		of_node_put(node);
1599 
1600 		if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
1601 			ret = dev_err_probe(dev,
1602 					    PTR_ERR(sdhci_arasan->soc_ctl_base),
1603 					    "Can't get syscon\n");
1604 			goto err_pltfm_free;
1605 		}
1606 	}
1607 
1608 	sdhci_get_of_property(pdev);
1609 
1610 	sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb");
1611 	if (IS_ERR(sdhci_arasan->clk_ahb)) {
1612 		ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb),
1613 				    "clk_ahb clock not found.\n");
1614 		goto err_pltfm_free;
1615 	}
1616 
1617 	clk_xin = devm_clk_get(dev, "clk_xin");
1618 	if (IS_ERR(clk_xin)) {
1619 		ret = dev_err_probe(dev, PTR_ERR(clk_xin), "clk_xin clock not found.\n");
1620 		goto err_pltfm_free;
1621 	}
1622 
1623 	ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
1624 	if (ret) {
1625 		dev_err(dev, "Unable to enable AHB clock.\n");
1626 		goto err_pltfm_free;
1627 	}
1628 
1629 	/* If clock-frequency property is set, use the provided value */
1630 	if (pltfm_host->clock &&
1631 	    pltfm_host->clock != clk_get_rate(clk_xin)) {
1632 		ret = clk_set_rate(clk_xin, pltfm_host->clock);
1633 		if (ret) {
1634 			dev_err(&pdev->dev, "Failed to set SD clock rate\n");
1635 			goto clk_dis_ahb;
1636 		}
1637 	}
1638 
1639 	ret = clk_prepare_enable(clk_xin);
1640 	if (ret) {
1641 		dev_err(dev, "Unable to enable SD clock.\n");
1642 		goto clk_dis_ahb;
1643 	}
1644 
1645 	if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
1646 		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
1647 
1648 	if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))
1649 		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE;
1650 
1651 	pltfm_host->clk = clk_xin;
1652 
1653 	if (of_device_is_compatible(np, "rockchip,rk3399-sdhci-5.1"))
1654 		sdhci_arasan_update_clockmultiplier(host, 0x0);
1655 
1656 	if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
1657 	    of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
1658 	    of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio") ||
1659 	    of_device_is_compatible(np, "intel,thunderbay-sdhci-5.1")) {
1660 		sdhci_arasan_update_clockmultiplier(host, 0x0);
1661 		sdhci_arasan_update_support64b(host, 0x0);
1662 
1663 		host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1664 	}
1665 
1666 	sdhci_arasan_update_baseclkfreq(host);
1667 
1668 	ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, dev);
1669 	if (ret)
1670 		goto clk_disable_all;
1671 
1672 	if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {
1673 		host->mmc_host_ops.execute_tuning =
1674 			arasan_zynqmp_execute_tuning;
1675 
1676 		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN;
1677 		host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
1678 	}
1679 
1680 	arasan_dt_parse_clk_phases(dev, &sdhci_arasan->clk_data);
1681 
1682 	ret = mmc_of_parse(host->mmc);
1683 	if (ret) {
1684 		ret = dev_err_probe(dev, ret, "parsing dt failed.\n");
1685 		goto unreg_clk;
1686 	}
1687 
1688 	sdhci_arasan->phy = ERR_PTR(-ENODEV);
1689 	if (of_device_is_compatible(np, "arasan,sdhci-5.1")) {
1690 		sdhci_arasan->phy = devm_phy_get(dev, "phy_arasan");
1691 		if (IS_ERR(sdhci_arasan->phy)) {
1692 			ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->phy),
1693 					    "No phy for arasan,sdhci-5.1.\n");
1694 			goto unreg_clk;
1695 		}
1696 
1697 		ret = phy_init(sdhci_arasan->phy);
1698 		if (ret < 0) {
1699 			dev_err(dev, "phy_init err.\n");
1700 			goto unreg_clk;
1701 		}
1702 
1703 		host->mmc_host_ops.hs400_enhanced_strobe =
1704 					sdhci_arasan_hs400_enhanced_strobe;
1705 		host->mmc_host_ops.start_signal_voltage_switch =
1706 					sdhci_arasan_voltage_switch;
1707 		sdhci_arasan->has_cqe = true;
1708 		host->mmc->caps2 |= MMC_CAP2_CQE;
1709 
1710 		if (!of_property_read_bool(np, "disable-cqe-dcmd"))
1711 			host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
1712 	}
1713 
1714 	ret = sdhci_arasan_add_host(sdhci_arasan);
1715 	if (ret)
1716 		goto err_add_host;
1717 
1718 	return 0;
1719 
1720 err_add_host:
1721 	if (!IS_ERR(sdhci_arasan->phy))
1722 		phy_exit(sdhci_arasan->phy);
1723 unreg_clk:
1724 	sdhci_arasan_unregister_sdclk(dev);
1725 clk_disable_all:
1726 	clk_disable_unprepare(clk_xin);
1727 clk_dis_ahb:
1728 	clk_disable_unprepare(sdhci_arasan->clk_ahb);
1729 err_pltfm_free:
1730 	sdhci_pltfm_free(pdev);
1731 	return ret;
1732 }
1733 
1734 static int sdhci_arasan_remove(struct platform_device *pdev)
1735 {
1736 	struct sdhci_host *host = platform_get_drvdata(pdev);
1737 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1738 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1739 	struct clk *clk_ahb = sdhci_arasan->clk_ahb;
1740 
1741 	if (!IS_ERR(sdhci_arasan->phy)) {
1742 		if (sdhci_arasan->is_phy_on)
1743 			phy_power_off(sdhci_arasan->phy);
1744 		phy_exit(sdhci_arasan->phy);
1745 	}
1746 
1747 	sdhci_arasan_unregister_sdclk(&pdev->dev);
1748 
1749 	sdhci_pltfm_unregister(pdev);
1750 
1751 	clk_disable_unprepare(clk_ahb);
1752 
1753 	return 0;
1754 }
1755 
1756 static struct platform_driver sdhci_arasan_driver = {
1757 	.driver = {
1758 		.name = "sdhci-arasan",
1759 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
1760 		.of_match_table = sdhci_arasan_of_match,
1761 		.pm = &sdhci_arasan_dev_pm_ops,
1762 	},
1763 	.probe = sdhci_arasan_probe,
1764 	.remove = sdhci_arasan_remove,
1765 };
1766 
1767 module_platform_driver(sdhci_arasan_driver);
1768 
1769 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
1770 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
1771 MODULE_LICENSE("GPL");
1772