1 /* 2 * Arasan Secure Digital Host Controller Interface. 3 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu> 4 * Copyright (c) 2012 Wind River Systems, Inc. 5 * Copyright (C) 2013 Pengutronix e.K. 6 * Copyright (C) 2013 Xilinx Inc. 7 * 8 * Based on sdhci-of-esdhc.c 9 * 10 * Copyright (c) 2007 Freescale Semiconductor, Inc. 11 * Copyright (c) 2009 MontaVista Software, Inc. 12 * 13 * Authors: Xiaobo Xie <X.Xie@freescale.com> 14 * Anton Vorontsov <avorontsov@ru.mvista.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or (at 19 * your option) any later version. 20 */ 21 22 #include <linux/clk-provider.h> 23 #include <linux/mfd/syscon.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/phy/phy.h> 27 #include <linux/regmap.h> 28 #include <linux/of.h> 29 30 #include "cqhci.h" 31 #include "sdhci-pltfm.h" 32 33 #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 34 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 35 #define VENDOR_ENHANCED_STROBE BIT(0) 36 37 #define PHY_CLK_TOO_SLOW_HZ 400000 38 39 /* 40 * On some SoCs the syscon area has a feature where the upper 16-bits of 41 * each 32-bit register act as a write mask for the lower 16-bits. This allows 42 * atomic updates of the register without locking. This macro is used on SoCs 43 * that have that feature. 44 */ 45 #define HIWORD_UPDATE(val, mask, shift) \ 46 ((val) << (shift) | (mask) << ((shift) + 16)) 47 48 /** 49 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map 50 * 51 * @reg: Offset within the syscon of the register containing this field 52 * @width: Number of bits for this field 53 * @shift: Bit offset within @reg of this field (or -1 if not avail) 54 */ 55 struct sdhci_arasan_soc_ctl_field { 56 u32 reg; 57 u16 width; 58 s16 shift; 59 }; 60 61 /** 62 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers 63 * 64 * It's up to the licensee of the Arsan IP block to make these available 65 * somewhere if needed. Presumably these will be scattered somewhere that's 66 * accessible via the syscon API. 67 * 68 * @baseclkfreq: Where to find corecfg_baseclkfreq 69 * @clockmultiplier: Where to find corecfg_clockmultiplier 70 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon 71 */ 72 struct sdhci_arasan_soc_ctl_map { 73 struct sdhci_arasan_soc_ctl_field baseclkfreq; 74 struct sdhci_arasan_soc_ctl_field clockmultiplier; 75 bool hiword_update; 76 }; 77 78 /** 79 * struct sdhci_arasan_data 80 * @host: Pointer to the main SDHCI host structure. 81 * @clk_ahb: Pointer to the AHB clock 82 * @phy: Pointer to the generic phy 83 * @is_phy_on: True if the PHY is on; false if not. 84 * @sdcardclk_hw: Struct for the clock we might provide to a PHY. 85 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. 86 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. 87 * @soc_ctl_map: Map to get offsets into soc_ctl registers. 88 */ 89 struct sdhci_arasan_data { 90 struct sdhci_host *host; 91 struct clk *clk_ahb; 92 struct phy *phy; 93 bool is_phy_on; 94 95 bool has_cqe; 96 struct clk_hw sdcardclk_hw; 97 struct clk *sdcardclk; 98 99 struct regmap *soc_ctl_base; 100 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; 101 unsigned int quirks; /* Arasan deviations from spec */ 102 103 /* Controller does not have CD wired and will not function normally without */ 104 #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0) 105 /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the 106 * internal clock even when the clock isn't stable */ 107 #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1) 108 }; 109 110 struct sdhci_arasan_of_data { 111 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; 112 const struct sdhci_pltfm_data *pdata; 113 }; 114 115 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = { 116 .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 }, 117 .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0}, 118 .hiword_update = true, 119 }; 120 121 /** 122 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers 123 * 124 * This function allows writing to fields in sdhci_arasan_soc_ctl_map. 125 * Note that if a field is specified as not available (shift < 0) then 126 * this function will silently return an error code. It will be noisy 127 * and print errors for any other (unexpected) errors. 128 * 129 * @host: The sdhci_host 130 * @fld: The field to write to 131 * @val: The value to write 132 */ 133 static int sdhci_arasan_syscon_write(struct sdhci_host *host, 134 const struct sdhci_arasan_soc_ctl_field *fld, 135 u32 val) 136 { 137 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 138 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 139 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; 140 u32 reg = fld->reg; 141 u16 width = fld->width; 142 s16 shift = fld->shift; 143 int ret; 144 145 /* 146 * Silently return errors for shift < 0 so caller doesn't have 147 * to check for fields which are optional. For fields that 148 * are required then caller needs to do something special 149 * anyway. 150 */ 151 if (shift < 0) 152 return -EINVAL; 153 154 if (sdhci_arasan->soc_ctl_map->hiword_update) 155 ret = regmap_write(soc_ctl_base, reg, 156 HIWORD_UPDATE(val, GENMASK(width, 0), 157 shift)); 158 else 159 ret = regmap_update_bits(soc_ctl_base, reg, 160 GENMASK(shift + width, shift), 161 val << shift); 162 163 /* Yell about (unexpected) regmap errors */ 164 if (ret) 165 pr_warn("%s: Regmap write fail: %d\n", 166 mmc_hostname(host->mmc), ret); 167 168 return ret; 169 } 170 171 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) 172 { 173 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 174 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 175 bool ctrl_phy = false; 176 177 if (!IS_ERR(sdhci_arasan->phy)) { 178 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) { 179 /* 180 * If PHY off, set clock to max speed and power PHY on. 181 * 182 * Although PHY docs apparently suggest power cycling 183 * when changing the clock the PHY doesn't like to be 184 * powered on while at low speeds like those used in ID 185 * mode. Even worse is powering the PHY on while the 186 * clock is off. 187 * 188 * To workaround the PHY limitations, the best we can 189 * do is to power it on at a faster speed and then slam 190 * through low speeds without power cycling. 191 */ 192 sdhci_set_clock(host, host->max_clk); 193 phy_power_on(sdhci_arasan->phy); 194 sdhci_arasan->is_phy_on = true; 195 196 /* 197 * We'll now fall through to the below case with 198 * ctrl_phy = false (so we won't turn off/on). The 199 * sdhci_set_clock() will set the real clock. 200 */ 201 } else if (clock > PHY_CLK_TOO_SLOW_HZ) { 202 /* 203 * At higher clock speeds the PHY is fine being power 204 * cycled and docs say you _should_ power cycle when 205 * changing clock speeds. 206 */ 207 ctrl_phy = true; 208 } 209 } 210 211 if (ctrl_phy && sdhci_arasan->is_phy_on) { 212 phy_power_off(sdhci_arasan->phy); 213 sdhci_arasan->is_phy_on = false; 214 } 215 216 sdhci_set_clock(host, clock); 217 218 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE) 219 /* 220 * Some controllers immediately report SDHCI_CLOCK_INT_STABLE 221 * after enabling the clock even though the clock is not 222 * stable. Trying to use a clock without waiting here results 223 * in EILSEQ while detecting some older/slower cards. The 224 * chosen delay is the maximum delay from sdhci_set_clock. 225 */ 226 msleep(20); 227 228 if (ctrl_phy) { 229 phy_power_on(sdhci_arasan->phy); 230 sdhci_arasan->is_phy_on = true; 231 } 232 } 233 234 static void sdhci_arasan_am654_set_clock(struct sdhci_host *host, 235 unsigned int clock) 236 { 237 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 238 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 239 240 if (sdhci_arasan->is_phy_on) { 241 phy_power_off(sdhci_arasan->phy); 242 sdhci_arasan->is_phy_on = false; 243 } 244 245 sdhci_set_clock(host, clock); 246 247 if (clock > PHY_CLK_TOO_SLOW_HZ) { 248 phy_power_on(sdhci_arasan->phy); 249 sdhci_arasan->is_phy_on = true; 250 } 251 } 252 253 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc, 254 struct mmc_ios *ios) 255 { 256 u32 vendor; 257 struct sdhci_host *host = mmc_priv(mmc); 258 259 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER); 260 if (ios->enhanced_strobe) 261 vendor |= VENDOR_ENHANCED_STROBE; 262 else 263 vendor &= ~VENDOR_ENHANCED_STROBE; 264 265 sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER); 266 } 267 268 static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) 269 { 270 u8 ctrl; 271 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 272 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 273 274 sdhci_reset(host, mask); 275 276 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { 277 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 278 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 279 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 280 } 281 } 282 283 static int sdhci_arasan_voltage_switch(struct mmc_host *mmc, 284 struct mmc_ios *ios) 285 { 286 switch (ios->signal_voltage) { 287 case MMC_SIGNAL_VOLTAGE_180: 288 /* 289 * Plese don't switch to 1V8 as arasan,5.1 doesn't 290 * actually refer to this setting to indicate the 291 * signal voltage and the state machine will be broken 292 * actually if we force to enable 1V8. That's something 293 * like broken quirk but we could work around here. 294 */ 295 return 0; 296 case MMC_SIGNAL_VOLTAGE_330: 297 case MMC_SIGNAL_VOLTAGE_120: 298 /* We don't support 3V3 and 1V2 */ 299 break; 300 } 301 302 return -EINVAL; 303 } 304 305 static void sdhci_arasan_set_power(struct sdhci_host *host, unsigned char mode, 306 unsigned short vdd) 307 { 308 if (!IS_ERR(host->mmc->supply.vmmc)) { 309 struct mmc_host *mmc = host->mmc; 310 311 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 312 } 313 sdhci_set_power_noreg(host, mode, vdd); 314 } 315 316 static const struct sdhci_ops sdhci_arasan_ops = { 317 .set_clock = sdhci_arasan_set_clock, 318 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 319 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 320 .set_bus_width = sdhci_set_bus_width, 321 .reset = sdhci_arasan_reset, 322 .set_uhs_signaling = sdhci_set_uhs_signaling, 323 .set_power = sdhci_arasan_set_power, 324 }; 325 326 static const struct sdhci_pltfm_data sdhci_arasan_pdata = { 327 .ops = &sdhci_arasan_ops, 328 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 329 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 330 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | 331 SDHCI_QUIRK2_STOP_WITH_TC, 332 }; 333 334 static struct sdhci_arasan_of_data sdhci_arasan_data = { 335 .pdata = &sdhci_arasan_pdata, 336 }; 337 338 static const struct sdhci_ops sdhci_arasan_am654_ops = { 339 .set_clock = sdhci_arasan_am654_set_clock, 340 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 341 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 342 .set_bus_width = sdhci_set_bus_width, 343 .reset = sdhci_arasan_reset, 344 .set_uhs_signaling = sdhci_set_uhs_signaling, 345 }; 346 347 static const struct sdhci_pltfm_data sdhci_arasan_am654_pdata = { 348 .ops = &sdhci_arasan_am654_ops, 349 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | 350 SDHCI_QUIRK_INVERTED_WRITE_PROTECT | 351 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 352 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 353 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | 354 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400, 355 }; 356 357 static const struct sdhci_arasan_of_data sdhci_arasan_am654_data = { 358 .pdata = &sdhci_arasan_am654_pdata, 359 }; 360 361 static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask) 362 { 363 int cmd_error = 0; 364 int data_error = 0; 365 366 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 367 return intmask; 368 369 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 370 371 return 0; 372 } 373 374 static void sdhci_arasan_dumpregs(struct mmc_host *mmc) 375 { 376 sdhci_dumpregs(mmc_priv(mmc)); 377 } 378 379 static void sdhci_arasan_cqe_enable(struct mmc_host *mmc) 380 { 381 struct sdhci_host *host = mmc_priv(mmc); 382 u32 reg; 383 384 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 385 while (reg & SDHCI_DATA_AVAILABLE) { 386 sdhci_readl(host, SDHCI_BUFFER); 387 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 388 } 389 390 sdhci_cqe_enable(mmc); 391 } 392 393 static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = { 394 .enable = sdhci_arasan_cqe_enable, 395 .disable = sdhci_cqe_disable, 396 .dumpregs = sdhci_arasan_dumpregs, 397 }; 398 399 static const struct sdhci_ops sdhci_arasan_cqe_ops = { 400 .set_clock = sdhci_arasan_set_clock, 401 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 402 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 403 .set_bus_width = sdhci_set_bus_width, 404 .reset = sdhci_arasan_reset, 405 .set_uhs_signaling = sdhci_set_uhs_signaling, 406 .set_power = sdhci_arasan_set_power, 407 .irq = sdhci_arasan_cqhci_irq, 408 }; 409 410 static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = { 411 .ops = &sdhci_arasan_cqe_ops, 412 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 413 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 414 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 415 }; 416 417 static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = { 418 .soc_ctl_map = &rk3399_soc_ctl_map, 419 .pdata = &sdhci_arasan_cqe_pdata, 420 }; 421 422 #ifdef CONFIG_PM_SLEEP 423 /** 424 * sdhci_arasan_suspend - Suspend method for the driver 425 * @dev: Address of the device structure 426 * Returns 0 on success and error value on error 427 * 428 * Put the device in a low power state. 429 */ 430 static int sdhci_arasan_suspend(struct device *dev) 431 { 432 struct sdhci_host *host = dev_get_drvdata(dev); 433 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 434 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 435 int ret; 436 437 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 438 mmc_retune_needed(host->mmc); 439 440 if (sdhci_arasan->has_cqe) { 441 ret = cqhci_suspend(host->mmc); 442 if (ret) 443 return ret; 444 } 445 446 ret = sdhci_suspend_host(host); 447 if (ret) 448 return ret; 449 450 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) { 451 ret = phy_power_off(sdhci_arasan->phy); 452 if (ret) { 453 dev_err(dev, "Cannot power off phy.\n"); 454 sdhci_resume_host(host); 455 return ret; 456 } 457 sdhci_arasan->is_phy_on = false; 458 } 459 460 clk_disable(pltfm_host->clk); 461 clk_disable(sdhci_arasan->clk_ahb); 462 463 return 0; 464 } 465 466 /** 467 * sdhci_arasan_resume - Resume method for the driver 468 * @dev: Address of the device structure 469 * Returns 0 on success and error value on error 470 * 471 * Resume operation after suspend 472 */ 473 static int sdhci_arasan_resume(struct device *dev) 474 { 475 struct sdhci_host *host = dev_get_drvdata(dev); 476 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 477 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 478 int ret; 479 480 ret = clk_enable(sdhci_arasan->clk_ahb); 481 if (ret) { 482 dev_err(dev, "Cannot enable AHB clock.\n"); 483 return ret; 484 } 485 486 ret = clk_enable(pltfm_host->clk); 487 if (ret) { 488 dev_err(dev, "Cannot enable SD clock.\n"); 489 return ret; 490 } 491 492 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) { 493 ret = phy_power_on(sdhci_arasan->phy); 494 if (ret) { 495 dev_err(dev, "Cannot power on phy.\n"); 496 return ret; 497 } 498 sdhci_arasan->is_phy_on = true; 499 } 500 501 ret = sdhci_resume_host(host); 502 if (ret) { 503 dev_err(dev, "Cannot resume host.\n"); 504 return ret; 505 } 506 507 if (sdhci_arasan->has_cqe) 508 return cqhci_resume(host->mmc); 509 510 return 0; 511 } 512 #endif /* ! CONFIG_PM_SLEEP */ 513 514 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend, 515 sdhci_arasan_resume); 516 517 static const struct of_device_id sdhci_arasan_of_match[] = { 518 /* SoC-specific compatible strings w/ soc_ctl_map */ 519 { 520 .compatible = "rockchip,rk3399-sdhci-5.1", 521 .data = &sdhci_arasan_rk3399_data, 522 }, 523 { 524 .compatible = "ti,am654-sdhci-5.1", 525 .data = &sdhci_arasan_am654_data, 526 }, 527 /* Generic compatible below here */ 528 { 529 .compatible = "arasan,sdhci-8.9a", 530 .data = &sdhci_arasan_data, 531 }, 532 { 533 .compatible = "arasan,sdhci-5.1", 534 .data = &sdhci_arasan_data, 535 }, 536 { 537 .compatible = "arasan,sdhci-4.9a", 538 .data = &sdhci_arasan_data, 539 }, 540 { /* sentinel */ } 541 }; 542 MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); 543 544 /** 545 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate 546 * 547 * Return the current actual rate of the SD card clock. This can be used 548 * to communicate with out PHY. 549 * 550 * @hw: Pointer to the hardware clock structure. 551 * @parent_rate The parent rate (should be rate of clk_xin). 552 * Returns the card clock rate. 553 */ 554 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw, 555 unsigned long parent_rate) 556 557 { 558 struct sdhci_arasan_data *sdhci_arasan = 559 container_of(hw, struct sdhci_arasan_data, sdcardclk_hw); 560 struct sdhci_host *host = sdhci_arasan->host; 561 562 return host->mmc->actual_clock; 563 } 564 565 static const struct clk_ops arasan_sdcardclk_ops = { 566 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, 567 }; 568 569 /** 570 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier 571 * 572 * The corecfg_clockmultiplier is supposed to contain clock multiplier 573 * value of programmable clock generator. 574 * 575 * NOTES: 576 * - Many existing devices don't seem to do this and work fine. To keep 577 * compatibility for old hardware where the device tree doesn't provide a 578 * register map, this function is a noop if a soc_ctl_map hasn't been provided 579 * for this platform. 580 * - The value of corecfg_clockmultiplier should sync with that of corresponding 581 * value reading from sdhci_capability_register. So this function is called 582 * once at probe time and never called again. 583 * 584 * @host: The sdhci_host 585 */ 586 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host, 587 u32 value) 588 { 589 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 590 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 591 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = 592 sdhci_arasan->soc_ctl_map; 593 594 /* Having a map is optional */ 595 if (!soc_ctl_map) 596 return; 597 598 /* If we have a map, we expect to have a syscon */ 599 if (!sdhci_arasan->soc_ctl_base) { 600 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", 601 mmc_hostname(host->mmc)); 602 return; 603 } 604 605 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value); 606 } 607 608 /** 609 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq 610 * 611 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This 612 * function can be used to make that happen. 613 * 614 * NOTES: 615 * - Many existing devices don't seem to do this and work fine. To keep 616 * compatibility for old hardware where the device tree doesn't provide a 617 * register map, this function is a noop if a soc_ctl_map hasn't been provided 618 * for this platform. 619 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider 620 * to achieve lower clock rates. That means that this function is called once 621 * at probe time and never called again. 622 * 623 * @host: The sdhci_host 624 */ 625 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) 626 { 627 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 628 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 629 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = 630 sdhci_arasan->soc_ctl_map; 631 u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000); 632 633 /* Having a map is optional */ 634 if (!soc_ctl_map) 635 return; 636 637 /* If we have a map, we expect to have a syscon */ 638 if (!sdhci_arasan->soc_ctl_base) { 639 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", 640 mmc_hostname(host->mmc)); 641 return; 642 } 643 644 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); 645 } 646 647 /** 648 * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use 649 * 650 * Some PHY devices need to know what the actual card clock is. In order for 651 * them to find out, we'll provide a clock through the common clock framework 652 * for them to query. 653 * 654 * Note: without seriously re-architecting SDHCI's clock code and testing on 655 * all platforms, there's no way to create a totally beautiful clock here 656 * with all clock ops implemented. Instead, we'll just create a clock that can 657 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock 658 * framework that we're doing things behind its back. This should be sufficient 659 * to create nice clean device tree bindings and later (if needed) we can try 660 * re-architecting SDHCI if we see some benefit to it. 661 * 662 * @sdhci_arasan: Our private data structure. 663 * @clk_xin: Pointer to the functional clock 664 * @dev: Pointer to our struct device. 665 * Returns 0 on success and error value on error 666 */ 667 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, 668 struct clk *clk_xin, 669 struct device *dev) 670 { 671 struct device_node *np = dev->of_node; 672 struct clk_init_data sdcardclk_init; 673 const char *parent_clk_name; 674 int ret; 675 676 /* Providing a clock to the PHY is optional; no error if missing */ 677 if (!of_find_property(np, "#clock-cells", NULL)) 678 return 0; 679 680 ret = of_property_read_string_index(np, "clock-output-names", 0, 681 &sdcardclk_init.name); 682 if (ret) { 683 dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); 684 return ret; 685 } 686 687 parent_clk_name = __clk_get_name(clk_xin); 688 sdcardclk_init.parent_names = &parent_clk_name; 689 sdcardclk_init.num_parents = 1; 690 sdcardclk_init.flags = CLK_GET_RATE_NOCACHE; 691 sdcardclk_init.ops = &arasan_sdcardclk_ops; 692 693 sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init; 694 sdhci_arasan->sdcardclk = 695 devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw); 696 sdhci_arasan->sdcardclk_hw.init = NULL; 697 698 ret = of_clk_add_provider(np, of_clk_src_simple_get, 699 sdhci_arasan->sdcardclk); 700 if (ret) 701 dev_err(dev, "Failed to add clock provider\n"); 702 703 return ret; 704 } 705 706 /** 707 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk() 708 * 709 * Should be called any time we're exiting and sdhci_arasan_register_sdclk() 710 * returned success. 711 * 712 * @dev: Pointer to our struct device. 713 */ 714 static void sdhci_arasan_unregister_sdclk(struct device *dev) 715 { 716 struct device_node *np = dev->of_node; 717 718 if (!of_find_property(np, "#clock-cells", NULL)) 719 return; 720 721 of_clk_del_provider(dev->of_node); 722 } 723 724 static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan) 725 { 726 struct sdhci_host *host = sdhci_arasan->host; 727 struct cqhci_host *cq_host; 728 bool dma64; 729 int ret; 730 731 if (!sdhci_arasan->has_cqe) 732 return sdhci_add_host(host); 733 734 ret = sdhci_setup_host(host); 735 if (ret) 736 return ret; 737 738 cq_host = devm_kzalloc(host->mmc->parent, 739 sizeof(*cq_host), GFP_KERNEL); 740 if (!cq_host) { 741 ret = -ENOMEM; 742 goto cleanup; 743 } 744 745 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; 746 cq_host->ops = &sdhci_arasan_cqhci_ops; 747 748 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 749 if (dma64) 750 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 751 752 ret = cqhci_init(cq_host, host->mmc, dma64); 753 if (ret) 754 goto cleanup; 755 756 ret = __sdhci_add_host(host); 757 if (ret) 758 goto cleanup; 759 760 return 0; 761 762 cleanup: 763 sdhci_cleanup_host(host); 764 return ret; 765 } 766 767 static int sdhci_arasan_probe(struct platform_device *pdev) 768 { 769 int ret; 770 const struct of_device_id *match; 771 struct device_node *node; 772 struct clk *clk_xin; 773 struct sdhci_host *host; 774 struct sdhci_pltfm_host *pltfm_host; 775 struct sdhci_arasan_data *sdhci_arasan; 776 struct device_node *np = pdev->dev.of_node; 777 const struct sdhci_arasan_of_data *data; 778 779 match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node); 780 data = match->data; 781 host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan)); 782 783 if (IS_ERR(host)) 784 return PTR_ERR(host); 785 786 pltfm_host = sdhci_priv(host); 787 sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 788 sdhci_arasan->host = host; 789 790 sdhci_arasan->soc_ctl_map = data->soc_ctl_map; 791 792 node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0); 793 if (node) { 794 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); 795 of_node_put(node); 796 797 if (IS_ERR(sdhci_arasan->soc_ctl_base)) { 798 ret = PTR_ERR(sdhci_arasan->soc_ctl_base); 799 if (ret != -EPROBE_DEFER) 800 dev_err(&pdev->dev, "Can't get syscon: %d\n", 801 ret); 802 goto err_pltfm_free; 803 } 804 } 805 806 sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb"); 807 if (IS_ERR(sdhci_arasan->clk_ahb)) { 808 dev_err(&pdev->dev, "clk_ahb clock not found.\n"); 809 ret = PTR_ERR(sdhci_arasan->clk_ahb); 810 goto err_pltfm_free; 811 } 812 813 clk_xin = devm_clk_get(&pdev->dev, "clk_xin"); 814 if (IS_ERR(clk_xin)) { 815 dev_err(&pdev->dev, "clk_xin clock not found.\n"); 816 ret = PTR_ERR(clk_xin); 817 goto err_pltfm_free; 818 } 819 820 ret = clk_prepare_enable(sdhci_arasan->clk_ahb); 821 if (ret) { 822 dev_err(&pdev->dev, "Unable to enable AHB clock.\n"); 823 goto err_pltfm_free; 824 } 825 826 ret = clk_prepare_enable(clk_xin); 827 if (ret) { 828 dev_err(&pdev->dev, "Unable to enable SD clock.\n"); 829 goto clk_dis_ahb; 830 } 831 832 sdhci_get_of_property(pdev); 833 834 if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) 835 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; 836 837 if (of_property_read_bool(np, "xlnx,int-clock-stable-broken")) 838 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE; 839 840 pltfm_host->clk = clk_xin; 841 842 if (of_device_is_compatible(pdev->dev.of_node, 843 "rockchip,rk3399-sdhci-5.1")) 844 sdhci_arasan_update_clockmultiplier(host, 0x0); 845 846 sdhci_arasan_update_baseclkfreq(host); 847 848 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev); 849 if (ret) 850 goto clk_disable_all; 851 852 ret = mmc_of_parse(host->mmc); 853 if (ret) { 854 if (ret != -EPROBE_DEFER) 855 dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret); 856 goto unreg_clk; 857 } 858 859 sdhci_arasan->phy = ERR_PTR(-ENODEV); 860 if (of_device_is_compatible(pdev->dev.of_node, 861 "arasan,sdhci-5.1")) { 862 sdhci_arasan->phy = devm_phy_get(&pdev->dev, 863 "phy_arasan"); 864 if (IS_ERR(sdhci_arasan->phy)) { 865 ret = PTR_ERR(sdhci_arasan->phy); 866 dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n"); 867 goto unreg_clk; 868 } 869 870 ret = phy_init(sdhci_arasan->phy); 871 if (ret < 0) { 872 dev_err(&pdev->dev, "phy_init err.\n"); 873 goto unreg_clk; 874 } 875 876 host->mmc_host_ops.hs400_enhanced_strobe = 877 sdhci_arasan_hs400_enhanced_strobe; 878 host->mmc_host_ops.start_signal_voltage_switch = 879 sdhci_arasan_voltage_switch; 880 sdhci_arasan->has_cqe = true; 881 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 882 } 883 884 ret = sdhci_arasan_add_host(sdhci_arasan); 885 if (ret) 886 goto err_add_host; 887 888 return 0; 889 890 err_add_host: 891 if (!IS_ERR(sdhci_arasan->phy)) 892 phy_exit(sdhci_arasan->phy); 893 unreg_clk: 894 sdhci_arasan_unregister_sdclk(&pdev->dev); 895 clk_disable_all: 896 clk_disable_unprepare(clk_xin); 897 clk_dis_ahb: 898 clk_disable_unprepare(sdhci_arasan->clk_ahb); 899 err_pltfm_free: 900 sdhci_pltfm_free(pdev); 901 return ret; 902 } 903 904 static int sdhci_arasan_remove(struct platform_device *pdev) 905 { 906 int ret; 907 struct sdhci_host *host = platform_get_drvdata(pdev); 908 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 909 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 910 struct clk *clk_ahb = sdhci_arasan->clk_ahb; 911 912 if (!IS_ERR(sdhci_arasan->phy)) { 913 if (sdhci_arasan->is_phy_on) 914 phy_power_off(sdhci_arasan->phy); 915 phy_exit(sdhci_arasan->phy); 916 } 917 918 sdhci_arasan_unregister_sdclk(&pdev->dev); 919 920 ret = sdhci_pltfm_unregister(pdev); 921 922 clk_disable_unprepare(clk_ahb); 923 924 return ret; 925 } 926 927 static struct platform_driver sdhci_arasan_driver = { 928 .driver = { 929 .name = "sdhci-arasan", 930 .of_match_table = sdhci_arasan_of_match, 931 .pm = &sdhci_arasan_dev_pm_ops, 932 }, 933 .probe = sdhci_arasan_probe, 934 .remove = sdhci_arasan_remove, 935 }; 936 937 module_platform_driver(sdhci_arasan_driver); 938 939 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller"); 940 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>"); 941 MODULE_LICENSE("GPL"); 942