1 /*
2  * Arasan Secure Digital Host Controller Interface.
3  * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
4  * Copyright (c) 2012 Wind River Systems, Inc.
5  * Copyright (C) 2013 Pengutronix e.K.
6  * Copyright (C) 2013 Xilinx Inc.
7  *
8  * Based on sdhci-of-esdhc.c
9  *
10  * Copyright (c) 2007 Freescale Semiconductor, Inc.
11  * Copyright (c) 2009 MontaVista Software, Inc.
12  *
13  * Authors: Xiaobo Xie <X.Xie@freescale.com>
14  *	    Anton Vorontsov <avorontsov@ru.mvista.com>
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License as published by
18  * the Free Software Foundation; either version 2 of the License, or (at
19  * your option) any later version.
20  */
21 
22 #include <linux/clk-provider.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/phy/phy.h>
27 #include <linux/regmap.h>
28 #include "sdhci-pltfm.h"
29 #include <linux/of.h>
30 
31 #define SDHCI_ARASAN_CLK_CTRL_OFFSET	0x2c
32 #define SDHCI_ARASAN_VENDOR_REGISTER	0x78
33 
34 #define VENDOR_ENHANCED_STROBE		BIT(0)
35 #define CLK_CTRL_TIMEOUT_SHIFT		16
36 #define CLK_CTRL_TIMEOUT_MASK		(0xf << CLK_CTRL_TIMEOUT_SHIFT)
37 #define CLK_CTRL_TIMEOUT_MIN_EXP	13
38 
39 #define PHY_CLK_TOO_SLOW_HZ		400000
40 
41 /*
42  * On some SoCs the syscon area has a feature where the upper 16-bits of
43  * each 32-bit register act as a write mask for the lower 16-bits.  This allows
44  * atomic updates of the register without locking.  This macro is used on SoCs
45  * that have that feature.
46  */
47 #define HIWORD_UPDATE(val, mask, shift) \
48 		((val) << (shift) | (mask) << ((shift) + 16))
49 
50 /**
51  * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
52  *
53  * @reg:	Offset within the syscon of the register containing this field
54  * @width:	Number of bits for this field
55  * @shift:	Bit offset within @reg of this field (or -1 if not avail)
56  */
57 struct sdhci_arasan_soc_ctl_field {
58 	u32 reg;
59 	u16 width;
60 	s16 shift;
61 };
62 
63 /**
64  * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
65  *
66  * It's up to the licensee of the Arsan IP block to make these available
67  * somewhere if needed.  Presumably these will be scattered somewhere that's
68  * accessible via the syscon API.
69  *
70  * @baseclkfreq:	Where to find corecfg_baseclkfreq
71  * @clockmultiplier:	Where to find corecfg_clockmultiplier
72  * @hiword_update:	If true, use HIWORD_UPDATE to access the syscon
73  */
74 struct sdhci_arasan_soc_ctl_map {
75 	struct sdhci_arasan_soc_ctl_field	baseclkfreq;
76 	struct sdhci_arasan_soc_ctl_field	clockmultiplier;
77 	bool					hiword_update;
78 };
79 
80 /**
81  * struct sdhci_arasan_data
82  * @host:		Pointer to the main SDHCI host structure.
83  * @clk_ahb:		Pointer to the AHB clock
84  * @phy:		Pointer to the generic phy
85  * @is_phy_on:		True if the PHY is on; false if not.
86  * @sdcardclk_hw:	Struct for the clock we might provide to a PHY.
87  * @sdcardclk:		Pointer to normal 'struct clock' for sdcardclk_hw.
88  * @soc_ctl_base:	Pointer to regmap for syscon for soc_ctl registers.
89  * @soc_ctl_map:	Map to get offsets into soc_ctl registers.
90  */
91 struct sdhci_arasan_data {
92 	struct sdhci_host *host;
93 	struct clk	*clk_ahb;
94 	struct phy	*phy;
95 	bool		is_phy_on;
96 
97 	struct clk_hw	sdcardclk_hw;
98 	struct clk      *sdcardclk;
99 
100 	struct regmap	*soc_ctl_base;
101 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
102 	unsigned int	quirks; /* Arasan deviations from spec */
103 
104 /* Controller does not have CD wired and will not function normally without */
105 #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST	BIT(0)
106 };
107 
108 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
109 	.baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
110 	.clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
111 	.hiword_update = true,
112 };
113 
114 /**
115  * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
116  *
117  * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
118  * Note that if a field is specified as not available (shift < 0) then
119  * this function will silently return an error code.  It will be noisy
120  * and print errors for any other (unexpected) errors.
121  *
122  * @host:	The sdhci_host
123  * @fld:	The field to write to
124  * @val:	The value to write
125  */
126 static int sdhci_arasan_syscon_write(struct sdhci_host *host,
127 				   const struct sdhci_arasan_soc_ctl_field *fld,
128 				   u32 val)
129 {
130 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
131 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
132 	struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
133 	u32 reg = fld->reg;
134 	u16 width = fld->width;
135 	s16 shift = fld->shift;
136 	int ret;
137 
138 	/*
139 	 * Silently return errors for shift < 0 so caller doesn't have
140 	 * to check for fields which are optional.  For fields that
141 	 * are required then caller needs to do something special
142 	 * anyway.
143 	 */
144 	if (shift < 0)
145 		return -EINVAL;
146 
147 	if (sdhci_arasan->soc_ctl_map->hiword_update)
148 		ret = regmap_write(soc_ctl_base, reg,
149 				   HIWORD_UPDATE(val, GENMASK(width, 0),
150 						 shift));
151 	else
152 		ret = regmap_update_bits(soc_ctl_base, reg,
153 					 GENMASK(shift + width, shift),
154 					 val << shift);
155 
156 	/* Yell about (unexpected) regmap errors */
157 	if (ret)
158 		pr_warn("%s: Regmap write fail: %d\n",
159 			 mmc_hostname(host->mmc), ret);
160 
161 	return ret;
162 }
163 
164 static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host)
165 {
166 	u32 div;
167 	unsigned long freq;
168 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
169 
170 	div = readl(host->ioaddr + SDHCI_ARASAN_CLK_CTRL_OFFSET);
171 	div = (div & CLK_CTRL_TIMEOUT_MASK) >> CLK_CTRL_TIMEOUT_SHIFT;
172 
173 	freq = clk_get_rate(pltfm_host->clk);
174 	freq /= 1 << (CLK_CTRL_TIMEOUT_MIN_EXP + div);
175 
176 	return freq;
177 }
178 
179 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
180 {
181 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
182 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
183 	bool ctrl_phy = false;
184 
185 	if (!IS_ERR(sdhci_arasan->phy)) {
186 		if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
187 			/*
188 			 * If PHY off, set clock to max speed and power PHY on.
189 			 *
190 			 * Although PHY docs apparently suggest power cycling
191 			 * when changing the clock the PHY doesn't like to be
192 			 * powered on while at low speeds like those used in ID
193 			 * mode.  Even worse is powering the PHY on while the
194 			 * clock is off.
195 			 *
196 			 * To workaround the PHY limitations, the best we can
197 			 * do is to power it on at a faster speed and then slam
198 			 * through low speeds without power cycling.
199 			 */
200 			sdhci_set_clock(host, host->max_clk);
201 			spin_unlock_irq(&host->lock);
202 			phy_power_on(sdhci_arasan->phy);
203 			spin_lock_irq(&host->lock);
204 			sdhci_arasan->is_phy_on = true;
205 
206 			/*
207 			 * We'll now fall through to the below case with
208 			 * ctrl_phy = false (so we won't turn off/on).  The
209 			 * sdhci_set_clock() will set the real clock.
210 			 */
211 		} else if (clock > PHY_CLK_TOO_SLOW_HZ) {
212 			/*
213 			 * At higher clock speeds the PHY is fine being power
214 			 * cycled and docs say you _should_ power cycle when
215 			 * changing clock speeds.
216 			 */
217 			ctrl_phy = true;
218 		}
219 	}
220 
221 	if (ctrl_phy && sdhci_arasan->is_phy_on) {
222 		spin_unlock_irq(&host->lock);
223 		phy_power_off(sdhci_arasan->phy);
224 		spin_lock_irq(&host->lock);
225 		sdhci_arasan->is_phy_on = false;
226 	}
227 
228 	sdhci_set_clock(host, clock);
229 
230 	if (ctrl_phy) {
231 		spin_unlock_irq(&host->lock);
232 		phy_power_on(sdhci_arasan->phy);
233 		spin_lock_irq(&host->lock);
234 		sdhci_arasan->is_phy_on = true;
235 	}
236 }
237 
238 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
239 					struct mmc_ios *ios)
240 {
241 	u32 vendor;
242 	struct sdhci_host *host = mmc_priv(mmc);
243 
244 	vendor = readl(host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER);
245 	if (ios->enhanced_strobe)
246 		vendor |= VENDOR_ENHANCED_STROBE;
247 	else
248 		vendor &= ~VENDOR_ENHANCED_STROBE;
249 
250 	writel(vendor, host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER);
251 }
252 
253 static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
254 {
255 	u8 ctrl;
256 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
257 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
258 
259 	sdhci_reset(host, mask);
260 
261 	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
262 		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
263 		ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
264 		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
265 	}
266 }
267 
268 static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
269 				       struct mmc_ios *ios)
270 {
271 	switch (ios->signal_voltage) {
272 	case MMC_SIGNAL_VOLTAGE_180:
273 		/*
274 		 * Plese don't switch to 1V8 as arasan,5.1 doesn't
275 		 * actually refer to this setting to indicate the
276 		 * signal voltage and the state machine will be broken
277 		 * actually if we force to enable 1V8. That's something
278 		 * like broken quirk but we could work around here.
279 		 */
280 		return 0;
281 	case MMC_SIGNAL_VOLTAGE_330:
282 	case MMC_SIGNAL_VOLTAGE_120:
283 		/* We don't support 3V3 and 1V2 */
284 		break;
285 	}
286 
287 	return -EINVAL;
288 }
289 
290 static struct sdhci_ops sdhci_arasan_ops = {
291 	.set_clock = sdhci_arasan_set_clock,
292 	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
293 	.get_timeout_clock = sdhci_arasan_get_timeout_clock,
294 	.set_bus_width = sdhci_set_bus_width,
295 	.reset = sdhci_arasan_reset,
296 	.set_uhs_signaling = sdhci_set_uhs_signaling,
297 };
298 
299 static struct sdhci_pltfm_data sdhci_arasan_pdata = {
300 	.ops = &sdhci_arasan_ops,
301 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
302 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
303 			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
304 };
305 
306 #ifdef CONFIG_PM_SLEEP
307 /**
308  * sdhci_arasan_suspend - Suspend method for the driver
309  * @dev:	Address of the device structure
310  * Returns 0 on success and error value on error
311  *
312  * Put the device in a low power state.
313  */
314 static int sdhci_arasan_suspend(struct device *dev)
315 {
316 	struct platform_device *pdev = to_platform_device(dev);
317 	struct sdhci_host *host = platform_get_drvdata(pdev);
318 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
319 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
320 	int ret;
321 
322 	ret = sdhci_suspend_host(host);
323 	if (ret)
324 		return ret;
325 
326 	if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
327 		ret = phy_power_off(sdhci_arasan->phy);
328 		if (ret) {
329 			dev_err(dev, "Cannot power off phy.\n");
330 			sdhci_resume_host(host);
331 			return ret;
332 		}
333 		sdhci_arasan->is_phy_on = false;
334 	}
335 
336 	clk_disable(pltfm_host->clk);
337 	clk_disable(sdhci_arasan->clk_ahb);
338 
339 	return 0;
340 }
341 
342 /**
343  * sdhci_arasan_resume - Resume method for the driver
344  * @dev:	Address of the device structure
345  * Returns 0 on success and error value on error
346  *
347  * Resume operation after suspend
348  */
349 static int sdhci_arasan_resume(struct device *dev)
350 {
351 	struct platform_device *pdev = to_platform_device(dev);
352 	struct sdhci_host *host = platform_get_drvdata(pdev);
353 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
354 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
355 	int ret;
356 
357 	ret = clk_enable(sdhci_arasan->clk_ahb);
358 	if (ret) {
359 		dev_err(dev, "Cannot enable AHB clock.\n");
360 		return ret;
361 	}
362 
363 	ret = clk_enable(pltfm_host->clk);
364 	if (ret) {
365 		dev_err(dev, "Cannot enable SD clock.\n");
366 		return ret;
367 	}
368 
369 	if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
370 		ret = phy_power_on(sdhci_arasan->phy);
371 		if (ret) {
372 			dev_err(dev, "Cannot power on phy.\n");
373 			return ret;
374 		}
375 		sdhci_arasan->is_phy_on = true;
376 	}
377 
378 	return sdhci_resume_host(host);
379 }
380 #endif /* ! CONFIG_PM_SLEEP */
381 
382 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
383 			 sdhci_arasan_resume);
384 
385 static const struct of_device_id sdhci_arasan_of_match[] = {
386 	/* SoC-specific compatible strings w/ soc_ctl_map */
387 	{
388 		.compatible = "rockchip,rk3399-sdhci-5.1",
389 		.data = &rk3399_soc_ctl_map,
390 	},
391 
392 	/* Generic compatible below here */
393 	{ .compatible = "arasan,sdhci-8.9a" },
394 	{ .compatible = "arasan,sdhci-5.1" },
395 	{ .compatible = "arasan,sdhci-4.9a" },
396 
397 	{ /* sentinel */ }
398 };
399 MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
400 
401 /**
402  * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
403  *
404  * Return the current actual rate of the SD card clock.  This can be used
405  * to communicate with out PHY.
406  *
407  * @hw:			Pointer to the hardware clock structure.
408  * @parent_rate		The parent rate (should be rate of clk_xin).
409  * Returns the card clock rate.
410  */
411 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
412 						      unsigned long parent_rate)
413 
414 {
415 	struct sdhci_arasan_data *sdhci_arasan =
416 		container_of(hw, struct sdhci_arasan_data, sdcardclk_hw);
417 	struct sdhci_host *host = sdhci_arasan->host;
418 
419 	return host->mmc->actual_clock;
420 }
421 
422 static const struct clk_ops arasan_sdcardclk_ops = {
423 	.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
424 };
425 
426 /**
427  * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
428  *
429  * The corecfg_clockmultiplier is supposed to contain clock multiplier
430  * value of programmable clock generator.
431  *
432  * NOTES:
433  * - Many existing devices don't seem to do this and work fine.  To keep
434  *   compatibility for old hardware where the device tree doesn't provide a
435  *   register map, this function is a noop if a soc_ctl_map hasn't been provided
436  *   for this platform.
437  * - The value of corecfg_clockmultiplier should sync with that of corresponding
438  *   value reading from sdhci_capability_register. So this function is called
439  *   once at probe time and never called again.
440  *
441  * @host:		The sdhci_host
442  */
443 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
444 						u32 value)
445 {
446 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
447 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
448 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
449 		sdhci_arasan->soc_ctl_map;
450 
451 	/* Having a map is optional */
452 	if (!soc_ctl_map)
453 		return;
454 
455 	/* If we have a map, we expect to have a syscon */
456 	if (!sdhci_arasan->soc_ctl_base) {
457 		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
458 			mmc_hostname(host->mmc));
459 		return;
460 	}
461 
462 	sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
463 }
464 
465 /**
466  * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
467  *
468  * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin.  This
469  * function can be used to make that happen.
470  *
471  * NOTES:
472  * - Many existing devices don't seem to do this and work fine.  To keep
473  *   compatibility for old hardware where the device tree doesn't provide a
474  *   register map, this function is a noop if a soc_ctl_map hasn't been provided
475  *   for this platform.
476  * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
477  *   to achieve lower clock rates.  That means that this function is called once
478  *   at probe time and never called again.
479  *
480  * @host:		The sdhci_host
481  */
482 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
483 {
484 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
485 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
486 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
487 		sdhci_arasan->soc_ctl_map;
488 	u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);
489 
490 	/* Having a map is optional */
491 	if (!soc_ctl_map)
492 		return;
493 
494 	/* If we have a map, we expect to have a syscon */
495 	if (!sdhci_arasan->soc_ctl_base) {
496 		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
497 			mmc_hostname(host->mmc));
498 		return;
499 	}
500 
501 	sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
502 }
503 
504 /**
505  * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use
506  *
507  * Some PHY devices need to know what the actual card clock is.  In order for
508  * them to find out, we'll provide a clock through the common clock framework
509  * for them to query.
510  *
511  * Note: without seriously re-architecting SDHCI's clock code and testing on
512  * all platforms, there's no way to create a totally beautiful clock here
513  * with all clock ops implemented.  Instead, we'll just create a clock that can
514  * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
515  * framework that we're doing things behind its back.  This should be sufficient
516  * to create nice clean device tree bindings and later (if needed) we can try
517  * re-architecting SDHCI if we see some benefit to it.
518  *
519  * @sdhci_arasan:	Our private data structure.
520  * @clk_xin:		Pointer to the functional clock
521  * @dev:		Pointer to our struct device.
522  * Returns 0 on success and error value on error
523  */
524 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
525 				       struct clk *clk_xin,
526 				       struct device *dev)
527 {
528 	struct device_node *np = dev->of_node;
529 	struct clk_init_data sdcardclk_init;
530 	const char *parent_clk_name;
531 	int ret;
532 
533 	/* Providing a clock to the PHY is optional; no error if missing */
534 	if (!of_find_property(np, "#clock-cells", NULL))
535 		return 0;
536 
537 	ret = of_property_read_string_index(np, "clock-output-names", 0,
538 					    &sdcardclk_init.name);
539 	if (ret) {
540 		dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
541 		return ret;
542 	}
543 
544 	parent_clk_name = __clk_get_name(clk_xin);
545 	sdcardclk_init.parent_names = &parent_clk_name;
546 	sdcardclk_init.num_parents = 1;
547 	sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
548 	sdcardclk_init.ops = &arasan_sdcardclk_ops;
549 
550 	sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init;
551 	sdhci_arasan->sdcardclk =
552 		devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw);
553 	sdhci_arasan->sdcardclk_hw.init = NULL;
554 
555 	ret = of_clk_add_provider(np, of_clk_src_simple_get,
556 				  sdhci_arasan->sdcardclk);
557 	if (ret)
558 		dev_err(dev, "Failed to add clock provider\n");
559 
560 	return ret;
561 }
562 
563 /**
564  * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
565  *
566  * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
567  * returned success.
568  *
569  * @dev:		Pointer to our struct device.
570  */
571 static void sdhci_arasan_unregister_sdclk(struct device *dev)
572 {
573 	struct device_node *np = dev->of_node;
574 
575 	if (!of_find_property(np, "#clock-cells", NULL))
576 		return;
577 
578 	of_clk_del_provider(dev->of_node);
579 }
580 
581 static int sdhci_arasan_probe(struct platform_device *pdev)
582 {
583 	int ret;
584 	const struct of_device_id *match;
585 	struct device_node *node;
586 	struct clk *clk_xin;
587 	struct sdhci_host *host;
588 	struct sdhci_pltfm_host *pltfm_host;
589 	struct sdhci_arasan_data *sdhci_arasan;
590 	struct device_node *np = pdev->dev.of_node;
591 
592 	host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata,
593 				sizeof(*sdhci_arasan));
594 	if (IS_ERR(host))
595 		return PTR_ERR(host);
596 
597 	pltfm_host = sdhci_priv(host);
598 	sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
599 	sdhci_arasan->host = host;
600 
601 	match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node);
602 	sdhci_arasan->soc_ctl_map = match->data;
603 
604 	node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0);
605 	if (node) {
606 		sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
607 		of_node_put(node);
608 
609 		if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
610 			ret = PTR_ERR(sdhci_arasan->soc_ctl_base);
611 			if (ret != -EPROBE_DEFER)
612 				dev_err(&pdev->dev, "Can't get syscon: %d\n",
613 					ret);
614 			goto err_pltfm_free;
615 		}
616 	}
617 
618 	sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
619 	if (IS_ERR(sdhci_arasan->clk_ahb)) {
620 		dev_err(&pdev->dev, "clk_ahb clock not found.\n");
621 		ret = PTR_ERR(sdhci_arasan->clk_ahb);
622 		goto err_pltfm_free;
623 	}
624 
625 	clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
626 	if (IS_ERR(clk_xin)) {
627 		dev_err(&pdev->dev, "clk_xin clock not found.\n");
628 		ret = PTR_ERR(clk_xin);
629 		goto err_pltfm_free;
630 	}
631 
632 	ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
633 	if (ret) {
634 		dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
635 		goto err_pltfm_free;
636 	}
637 
638 	ret = clk_prepare_enable(clk_xin);
639 	if (ret) {
640 		dev_err(&pdev->dev, "Unable to enable SD clock.\n");
641 		goto clk_dis_ahb;
642 	}
643 
644 	sdhci_get_of_property(pdev);
645 
646 	if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
647 		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
648 
649 	pltfm_host->clk = clk_xin;
650 
651 	if (of_device_is_compatible(pdev->dev.of_node,
652 				    "rockchip,rk3399-sdhci-5.1"))
653 		sdhci_arasan_update_clockmultiplier(host, 0x0);
654 
655 	sdhci_arasan_update_baseclkfreq(host);
656 
657 	ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
658 	if (ret)
659 		goto clk_disable_all;
660 
661 	ret = mmc_of_parse(host->mmc);
662 	if (ret) {
663 		dev_err(&pdev->dev, "parsing dt failed (%u)\n", ret);
664 		goto unreg_clk;
665 	}
666 
667 	sdhci_arasan->phy = ERR_PTR(-ENODEV);
668 	if (of_device_is_compatible(pdev->dev.of_node,
669 				    "arasan,sdhci-5.1")) {
670 		sdhci_arasan->phy = devm_phy_get(&pdev->dev,
671 						 "phy_arasan");
672 		if (IS_ERR(sdhci_arasan->phy)) {
673 			ret = PTR_ERR(sdhci_arasan->phy);
674 			dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");
675 			goto unreg_clk;
676 		}
677 
678 		ret = phy_init(sdhci_arasan->phy);
679 		if (ret < 0) {
680 			dev_err(&pdev->dev, "phy_init err.\n");
681 			goto unreg_clk;
682 		}
683 
684 		host->mmc_host_ops.hs400_enhanced_strobe =
685 					sdhci_arasan_hs400_enhanced_strobe;
686 		host->mmc_host_ops.start_signal_voltage_switch =
687 					sdhci_arasan_voltage_switch;
688 	}
689 
690 	ret = sdhci_add_host(host);
691 	if (ret)
692 		goto err_add_host;
693 
694 	return 0;
695 
696 err_add_host:
697 	if (!IS_ERR(sdhci_arasan->phy))
698 		phy_exit(sdhci_arasan->phy);
699 unreg_clk:
700 	sdhci_arasan_unregister_sdclk(&pdev->dev);
701 clk_disable_all:
702 	clk_disable_unprepare(clk_xin);
703 clk_dis_ahb:
704 	clk_disable_unprepare(sdhci_arasan->clk_ahb);
705 err_pltfm_free:
706 	sdhci_pltfm_free(pdev);
707 	return ret;
708 }
709 
710 static int sdhci_arasan_remove(struct platform_device *pdev)
711 {
712 	int ret;
713 	struct sdhci_host *host = platform_get_drvdata(pdev);
714 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
715 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
716 	struct clk *clk_ahb = sdhci_arasan->clk_ahb;
717 
718 	if (!IS_ERR(sdhci_arasan->phy)) {
719 		if (sdhci_arasan->is_phy_on)
720 			phy_power_off(sdhci_arasan->phy);
721 		phy_exit(sdhci_arasan->phy);
722 	}
723 
724 	sdhci_arasan_unregister_sdclk(&pdev->dev);
725 
726 	ret = sdhci_pltfm_unregister(pdev);
727 
728 	clk_disable_unprepare(clk_ahb);
729 
730 	return ret;
731 }
732 
733 static struct platform_driver sdhci_arasan_driver = {
734 	.driver = {
735 		.name = "sdhci-arasan",
736 		.of_match_table = sdhci_arasan_of_match,
737 		.pm = &sdhci_arasan_dev_pm_ops,
738 	},
739 	.probe = sdhci_arasan_probe,
740 	.remove = sdhci_arasan_remove,
741 };
742 
743 module_platform_driver(sdhci_arasan_driver);
744 
745 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
746 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
747 MODULE_LICENSE("GPL");
748