1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Arasan Secure Digital Host Controller Interface.
4  * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
5  * Copyright (c) 2012 Wind River Systems, Inc.
6  * Copyright (C) 2013 Pengutronix e.K.
7  * Copyright (C) 2013 Xilinx Inc.
8  *
9  * Based on sdhci-of-esdhc.c
10  *
11  * Copyright (c) 2007 Freescale Semiconductor, Inc.
12  * Copyright (c) 2009 MontaVista Software, Inc.
13  *
14  * Authors: Xiaobo Xie <X.Xie@freescale.com>
15  *	    Anton Vorontsov <avorontsov@ru.mvista.com>
16  */
17 
18 #include <linux/clk-provider.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/phy/phy.h>
23 #include <linux/regmap.h>
24 #include <linux/of.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
26 
27 #include "cqhci.h"
28 #include "sdhci-pltfm.h"
29 
30 #define SDHCI_ARASAN_VENDOR_REGISTER	0x78
31 
32 #define SDHCI_ARASAN_ITAPDLY_REGISTER	0xF0F8
33 #define SDHCI_ARASAN_ITAPDLY_SEL_MASK	0xFF
34 
35 #define SDHCI_ARASAN_OTAPDLY_REGISTER	0xF0FC
36 #define SDHCI_ARASAN_OTAPDLY_SEL_MASK	0x3F
37 
38 #define SDHCI_ARASAN_CQE_BASE_ADDR	0x200
39 #define VENDOR_ENHANCED_STROBE		BIT(0)
40 
41 #define PHY_CLK_TOO_SLOW_HZ		400000
42 
43 #define SDHCI_ITAPDLY_CHGWIN		0x200
44 #define SDHCI_ITAPDLY_ENABLE		0x100
45 #define SDHCI_OTAPDLY_ENABLE		0x40
46 
47 /* Default settings for ZynqMP Clock Phases */
48 #define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63,  0,   0, 183, 54,  0, 0}
49 #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
50 
51 #define VERSAL_ICLK_PHASE {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0}
52 #define VERSAL_OCLK_PHASE {0,  60, 48, 0, 48, 72, 90, 36, 60, 90, 0}
53 
54 /*
55  * On some SoCs the syscon area has a feature where the upper 16-bits of
56  * each 32-bit register act as a write mask for the lower 16-bits.  This allows
57  * atomic updates of the register without locking.  This macro is used on SoCs
58  * that have that feature.
59  */
60 #define HIWORD_UPDATE(val, mask, shift) \
61 		((val) << (shift) | (mask) << ((shift) + 16))
62 
63 /**
64  * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
65  *
66  * @reg:	Offset within the syscon of the register containing this field
67  * @width:	Number of bits for this field
68  * @shift:	Bit offset within @reg of this field (or -1 if not avail)
69  */
70 struct sdhci_arasan_soc_ctl_field {
71 	u32 reg;
72 	u16 width;
73 	s16 shift;
74 };
75 
76 /**
77  * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
78  *
79  * @baseclkfreq:	Where to find corecfg_baseclkfreq
80  * @clockmultiplier:	Where to find corecfg_clockmultiplier
81  * @support64b:		Where to find SUPPORT64B bit
82  * @hiword_update:	If true, use HIWORD_UPDATE to access the syscon
83  *
84  * It's up to the licensee of the Arsan IP block to make these available
85  * somewhere if needed.  Presumably these will be scattered somewhere that's
86  * accessible via the syscon API.
87  */
88 struct sdhci_arasan_soc_ctl_map {
89 	struct sdhci_arasan_soc_ctl_field	baseclkfreq;
90 	struct sdhci_arasan_soc_ctl_field	clockmultiplier;
91 	struct sdhci_arasan_soc_ctl_field	support64b;
92 	bool					hiword_update;
93 };
94 
95 /**
96  * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller
97  *
98  * @sdcardclk_ops:	The output clock related operations
99  * @sampleclk_ops:	The sample clock related operations
100  */
101 struct sdhci_arasan_clk_ops {
102 	const struct clk_ops *sdcardclk_ops;
103 	const struct clk_ops *sampleclk_ops;
104 };
105 
106 /**
107  * struct sdhci_arasan_clk_data - Arasan Controller Clock Data.
108  *
109  * @sdcardclk_hw:	Struct for the clock we might provide to a PHY.
110  * @sdcardclk:		Pointer to normal 'struct clock' for sdcardclk_hw.
111  * @sampleclk_hw:	Struct for the clock we might provide to a PHY.
112  * @sampleclk:		Pointer to normal 'struct clock' for sampleclk_hw.
113  * @clk_phase_in:	Array of Input Clock Phase Delays for all speed modes
114  * @clk_phase_out:	Array of Output Clock Phase Delays for all speed modes
115  * @set_clk_delays:	Function pointer for setting Clock Delays
116  * @clk_of_data:	Platform specific runtime clock data storage pointer
117  */
118 struct sdhci_arasan_clk_data {
119 	struct clk_hw	sdcardclk_hw;
120 	struct clk      *sdcardclk;
121 	struct clk_hw	sampleclk_hw;
122 	struct clk      *sampleclk;
123 	int		clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
124 	int		clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
125 	void		(*set_clk_delays)(struct sdhci_host *host);
126 	void		*clk_of_data;
127 };
128 
129 /**
130  * struct sdhci_arasan_data - Arasan Controller Data
131  *
132  * @host:		Pointer to the main SDHCI host structure.
133  * @clk_ahb:		Pointer to the AHB clock
134  * @phy:		Pointer to the generic phy
135  * @is_phy_on:		True if the PHY is on; false if not.
136  * @has_cqe:		True if controller has command queuing engine.
137  * @clk_data:		Struct for the Arasan Controller Clock Data.
138  * @clk_ops:		Struct for the Arasan Controller Clock Operations.
139  * @soc_ctl_base:	Pointer to regmap for syscon for soc_ctl registers.
140  * @soc_ctl_map:	Map to get offsets into soc_ctl registers.
141  * @quirks:		Arasan deviations from spec.
142  */
143 struct sdhci_arasan_data {
144 	struct sdhci_host *host;
145 	struct clk	*clk_ahb;
146 	struct phy	*phy;
147 	bool		is_phy_on;
148 
149 	bool		has_cqe;
150 	struct sdhci_arasan_clk_data clk_data;
151 	const struct sdhci_arasan_clk_ops *clk_ops;
152 
153 	struct regmap	*soc_ctl_base;
154 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
155 	unsigned int	quirks;
156 
157 /* Controller does not have CD wired and will not function normally without */
158 #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST	BIT(0)
159 /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the
160  * internal clock even when the clock isn't stable */
161 #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1)
162 };
163 
164 struct sdhci_arasan_of_data {
165 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
166 	const struct sdhci_pltfm_data *pdata;
167 	const struct sdhci_arasan_clk_ops *clk_ops;
168 };
169 
170 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
171 	.baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
172 	.clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
173 	.hiword_update = true,
174 };
175 
176 static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = {
177 	.baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 },
178 	.clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
179 	.hiword_update = false,
180 };
181 
182 static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
183 	.baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 },
184 	.clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
185 	.hiword_update = false,
186 };
187 
188 static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = {
189 	.baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
190 	.clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
191 	.support64b = { .reg = 0x4, .width = 1, .shift = 24 },
192 	.hiword_update = false,
193 };
194 
195 /**
196  * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
197  *
198  * @host:	The sdhci_host
199  * @fld:	The field to write to
200  * @val:	The value to write
201  *
202  * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
203  * Note that if a field is specified as not available (shift < 0) then
204  * this function will silently return an error code.  It will be noisy
205  * and print errors for any other (unexpected) errors.
206  *
207  * Return: 0 on success and error value on error
208  */
209 static int sdhci_arasan_syscon_write(struct sdhci_host *host,
210 				   const struct sdhci_arasan_soc_ctl_field *fld,
211 				   u32 val)
212 {
213 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
214 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
215 	struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
216 	u32 reg = fld->reg;
217 	u16 width = fld->width;
218 	s16 shift = fld->shift;
219 	int ret;
220 
221 	/*
222 	 * Silently return errors for shift < 0 so caller doesn't have
223 	 * to check for fields which are optional.  For fields that
224 	 * are required then caller needs to do something special
225 	 * anyway.
226 	 */
227 	if (shift < 0)
228 		return -EINVAL;
229 
230 	if (sdhci_arasan->soc_ctl_map->hiword_update)
231 		ret = regmap_write(soc_ctl_base, reg,
232 				   HIWORD_UPDATE(val, GENMASK(width, 0),
233 						 shift));
234 	else
235 		ret = regmap_update_bits(soc_ctl_base, reg,
236 					 GENMASK(shift + width, shift),
237 					 val << shift);
238 
239 	/* Yell about (unexpected) regmap errors */
240 	if (ret)
241 		pr_warn("%s: Regmap write fail: %d\n",
242 			 mmc_hostname(host->mmc), ret);
243 
244 	return ret;
245 }
246 
247 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
248 {
249 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
250 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
251 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
252 	bool ctrl_phy = false;
253 
254 	if (!IS_ERR(sdhci_arasan->phy)) {
255 		if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
256 			/*
257 			 * If PHY off, set clock to max speed and power PHY on.
258 			 *
259 			 * Although PHY docs apparently suggest power cycling
260 			 * when changing the clock the PHY doesn't like to be
261 			 * powered on while at low speeds like those used in ID
262 			 * mode.  Even worse is powering the PHY on while the
263 			 * clock is off.
264 			 *
265 			 * To workaround the PHY limitations, the best we can
266 			 * do is to power it on at a faster speed and then slam
267 			 * through low speeds without power cycling.
268 			 */
269 			sdhci_set_clock(host, host->max_clk);
270 			phy_power_on(sdhci_arasan->phy);
271 			sdhci_arasan->is_phy_on = true;
272 
273 			/*
274 			 * We'll now fall through to the below case with
275 			 * ctrl_phy = false (so we won't turn off/on).  The
276 			 * sdhci_set_clock() will set the real clock.
277 			 */
278 		} else if (clock > PHY_CLK_TOO_SLOW_HZ) {
279 			/*
280 			 * At higher clock speeds the PHY is fine being power
281 			 * cycled and docs say you _should_ power cycle when
282 			 * changing clock speeds.
283 			 */
284 			ctrl_phy = true;
285 		}
286 	}
287 
288 	if (ctrl_phy && sdhci_arasan->is_phy_on) {
289 		phy_power_off(sdhci_arasan->phy);
290 		sdhci_arasan->is_phy_on = false;
291 	}
292 
293 	/* Set the Input and Output Clock Phase Delays */
294 	if (clk_data->set_clk_delays)
295 		clk_data->set_clk_delays(host);
296 
297 	sdhci_set_clock(host, clock);
298 
299 	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
300 		/*
301 		 * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
302 		 * after enabling the clock even though the clock is not
303 		 * stable. Trying to use a clock without waiting here results
304 		 * in EILSEQ while detecting some older/slower cards. The
305 		 * chosen delay is the maximum delay from sdhci_set_clock.
306 		 */
307 		msleep(20);
308 
309 	if (ctrl_phy) {
310 		phy_power_on(sdhci_arasan->phy);
311 		sdhci_arasan->is_phy_on = true;
312 	}
313 }
314 
315 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
316 					struct mmc_ios *ios)
317 {
318 	u32 vendor;
319 	struct sdhci_host *host = mmc_priv(mmc);
320 
321 	vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER);
322 	if (ios->enhanced_strobe)
323 		vendor |= VENDOR_ENHANCED_STROBE;
324 	else
325 		vendor &= ~VENDOR_ENHANCED_STROBE;
326 
327 	sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER);
328 }
329 
330 static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
331 {
332 	u8 ctrl;
333 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
334 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
335 
336 	sdhci_reset(host, mask);
337 
338 	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
339 		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
340 		ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
341 		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
342 	}
343 }
344 
345 static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
346 				       struct mmc_ios *ios)
347 {
348 	switch (ios->signal_voltage) {
349 	case MMC_SIGNAL_VOLTAGE_180:
350 		/*
351 		 * Plese don't switch to 1V8 as arasan,5.1 doesn't
352 		 * actually refer to this setting to indicate the
353 		 * signal voltage and the state machine will be broken
354 		 * actually if we force to enable 1V8. That's something
355 		 * like broken quirk but we could work around here.
356 		 */
357 		return 0;
358 	case MMC_SIGNAL_VOLTAGE_330:
359 	case MMC_SIGNAL_VOLTAGE_120:
360 		/* We don't support 3V3 and 1V2 */
361 		break;
362 	}
363 
364 	return -EINVAL;
365 }
366 
367 static const struct sdhci_ops sdhci_arasan_ops = {
368 	.set_clock = sdhci_arasan_set_clock,
369 	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
370 	.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
371 	.set_bus_width = sdhci_set_bus_width,
372 	.reset = sdhci_arasan_reset,
373 	.set_uhs_signaling = sdhci_set_uhs_signaling,
374 	.set_power = sdhci_set_power_and_bus_voltage,
375 };
376 
377 static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
378 {
379 	int cmd_error = 0;
380 	int data_error = 0;
381 
382 	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
383 		return intmask;
384 
385 	cqhci_irq(host->mmc, intmask, cmd_error, data_error);
386 
387 	return 0;
388 }
389 
390 static void sdhci_arasan_dumpregs(struct mmc_host *mmc)
391 {
392 	sdhci_dumpregs(mmc_priv(mmc));
393 }
394 
395 static void sdhci_arasan_cqe_enable(struct mmc_host *mmc)
396 {
397 	struct sdhci_host *host = mmc_priv(mmc);
398 	u32 reg;
399 
400 	reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
401 	while (reg & SDHCI_DATA_AVAILABLE) {
402 		sdhci_readl(host, SDHCI_BUFFER);
403 		reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
404 	}
405 
406 	sdhci_cqe_enable(mmc);
407 }
408 
409 static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = {
410 	.enable         = sdhci_arasan_cqe_enable,
411 	.disable        = sdhci_cqe_disable,
412 	.dumpregs       = sdhci_arasan_dumpregs,
413 };
414 
415 static const struct sdhci_ops sdhci_arasan_cqe_ops = {
416 	.set_clock = sdhci_arasan_set_clock,
417 	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
418 	.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
419 	.set_bus_width = sdhci_set_bus_width,
420 	.reset = sdhci_arasan_reset,
421 	.set_uhs_signaling = sdhci_set_uhs_signaling,
422 	.set_power = sdhci_set_power_and_bus_voltage,
423 	.irq = sdhci_arasan_cqhci_irq,
424 };
425 
426 static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
427 	.ops = &sdhci_arasan_cqe_ops,
428 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
429 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
430 			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
431 };
432 
433 #ifdef CONFIG_PM_SLEEP
434 /**
435  * sdhci_arasan_suspend - Suspend method for the driver
436  * @dev:	Address of the device structure
437  *
438  * Put the device in a low power state.
439  *
440  * Return: 0 on success and error value on error
441  */
442 static int sdhci_arasan_suspend(struct device *dev)
443 {
444 	struct sdhci_host *host = dev_get_drvdata(dev);
445 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
446 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
447 	int ret;
448 
449 	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
450 		mmc_retune_needed(host->mmc);
451 
452 	if (sdhci_arasan->has_cqe) {
453 		ret = cqhci_suspend(host->mmc);
454 		if (ret)
455 			return ret;
456 	}
457 
458 	ret = sdhci_suspend_host(host);
459 	if (ret)
460 		return ret;
461 
462 	if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
463 		ret = phy_power_off(sdhci_arasan->phy);
464 		if (ret) {
465 			dev_err(dev, "Cannot power off phy.\n");
466 			sdhci_resume_host(host);
467 			return ret;
468 		}
469 		sdhci_arasan->is_phy_on = false;
470 	}
471 
472 	clk_disable(pltfm_host->clk);
473 	clk_disable(sdhci_arasan->clk_ahb);
474 
475 	return 0;
476 }
477 
478 /**
479  * sdhci_arasan_resume - Resume method for the driver
480  * @dev:	Address of the device structure
481  *
482  * Resume operation after suspend
483  *
484  * Return: 0 on success and error value on error
485  */
486 static int sdhci_arasan_resume(struct device *dev)
487 {
488 	struct sdhci_host *host = dev_get_drvdata(dev);
489 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
490 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
491 	int ret;
492 
493 	ret = clk_enable(sdhci_arasan->clk_ahb);
494 	if (ret) {
495 		dev_err(dev, "Cannot enable AHB clock.\n");
496 		return ret;
497 	}
498 
499 	ret = clk_enable(pltfm_host->clk);
500 	if (ret) {
501 		dev_err(dev, "Cannot enable SD clock.\n");
502 		return ret;
503 	}
504 
505 	if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
506 		ret = phy_power_on(sdhci_arasan->phy);
507 		if (ret) {
508 			dev_err(dev, "Cannot power on phy.\n");
509 			return ret;
510 		}
511 		sdhci_arasan->is_phy_on = true;
512 	}
513 
514 	ret = sdhci_resume_host(host);
515 	if (ret) {
516 		dev_err(dev, "Cannot resume host.\n");
517 		return ret;
518 	}
519 
520 	if (sdhci_arasan->has_cqe)
521 		return cqhci_resume(host->mmc);
522 
523 	return 0;
524 }
525 #endif /* ! CONFIG_PM_SLEEP */
526 
527 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
528 			 sdhci_arasan_resume);
529 
530 /**
531  * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
532  *
533  * @hw:			Pointer to the hardware clock structure.
534  * @parent_rate:		The parent rate (should be rate of clk_xin).
535  *
536  * Return the current actual rate of the SD card clock.  This can be used
537  * to communicate with out PHY.
538  *
539  * Return: The card clock rate.
540  */
541 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
542 						      unsigned long parent_rate)
543 {
544 	struct sdhci_arasan_clk_data *clk_data =
545 		container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
546 	struct sdhci_arasan_data *sdhci_arasan =
547 		container_of(clk_data, struct sdhci_arasan_data, clk_data);
548 	struct sdhci_host *host = sdhci_arasan->host;
549 
550 	return host->mmc->actual_clock;
551 }
552 
553 static const struct clk_ops arasan_sdcardclk_ops = {
554 	.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
555 };
556 
557 /**
558  * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
559  *
560  * @hw:			Pointer to the hardware clock structure.
561  * @parent_rate:		The parent rate (should be rate of clk_xin).
562  *
563  * Return the current actual rate of the sampling clock.  This can be used
564  * to communicate with out PHY.
565  *
566  * Return: The sample clock rate.
567  */
568 static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw,
569 						      unsigned long parent_rate)
570 {
571 	struct sdhci_arasan_clk_data *clk_data =
572 		container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
573 	struct sdhci_arasan_data *sdhci_arasan =
574 		container_of(clk_data, struct sdhci_arasan_data, clk_data);
575 	struct sdhci_host *host = sdhci_arasan->host;
576 
577 	return host->mmc->actual_clock;
578 }
579 
580 static const struct clk_ops arasan_sampleclk_ops = {
581 	.recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
582 };
583 
584 /**
585  * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
586  *
587  * @hw:			Pointer to the hardware clock structure.
588  * @degrees:		The clock phase shift between 0 - 359.
589  *
590  * Set the SD Output Clock Tap Delays for Output path
591  *
592  * Return: 0 on success and error value on error
593  */
594 static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
595 {
596 	struct sdhci_arasan_clk_data *clk_data =
597 		container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
598 	struct sdhci_arasan_data *sdhci_arasan =
599 		container_of(clk_data, struct sdhci_arasan_data, clk_data);
600 	struct sdhci_host *host = sdhci_arasan->host;
601 	const char *clk_name = clk_hw_get_name(hw);
602 	u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
603 	u8 tap_delay, tap_max = 0;
604 	int ret;
605 
606 	/* This is applicable for SDHCI_SPEC_300 and above */
607 	if (host->version < SDHCI_SPEC_300)
608 		return 0;
609 
610 	switch (host->timing) {
611 	case MMC_TIMING_MMC_HS:
612 	case MMC_TIMING_SD_HS:
613 	case MMC_TIMING_UHS_SDR25:
614 	case MMC_TIMING_UHS_DDR50:
615 	case MMC_TIMING_MMC_DDR52:
616 		/* For 50MHz clock, 30 Taps are available */
617 		tap_max = 30;
618 		break;
619 	case MMC_TIMING_UHS_SDR50:
620 		/* For 100MHz clock, 15 Taps are available */
621 		tap_max = 15;
622 		break;
623 	case MMC_TIMING_UHS_SDR104:
624 	case MMC_TIMING_MMC_HS200:
625 		/* For 200MHz clock, 8 Taps are available */
626 		tap_max = 8;
627 	default:
628 		break;
629 	}
630 
631 	tap_delay = (degrees * tap_max) / 360;
632 
633 	/* Set the Clock Phase */
634 	ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay);
635 	if (ret)
636 		pr_err("Error setting Output Tap Delay\n");
637 
638 	/* Release DLL Reset */
639 	zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_RELEASE);
640 
641 	return ret;
642 }
643 
644 static const struct clk_ops zynqmp_sdcardclk_ops = {
645 	.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
646 	.set_phase = sdhci_zynqmp_sdcardclk_set_phase,
647 };
648 
649 /**
650  * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
651  *
652  * @hw:			Pointer to the hardware clock structure.
653  * @degrees:		The clock phase shift between 0 - 359.
654  *
655  * Set the SD Input Clock Tap Delays for Input path
656  *
657  * Return: 0 on success and error value on error
658  */
659 static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees)
660 {
661 	struct sdhci_arasan_clk_data *clk_data =
662 		container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
663 	struct sdhci_arasan_data *sdhci_arasan =
664 		container_of(clk_data, struct sdhci_arasan_data, clk_data);
665 	struct sdhci_host *host = sdhci_arasan->host;
666 	const char *clk_name = clk_hw_get_name(hw);
667 	u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1;
668 	u8 tap_delay, tap_max = 0;
669 	int ret;
670 
671 	/* This is applicable for SDHCI_SPEC_300 and above */
672 	if (host->version < SDHCI_SPEC_300)
673 		return 0;
674 
675 	/* Assert DLL Reset */
676 	zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_ASSERT);
677 
678 	switch (host->timing) {
679 	case MMC_TIMING_MMC_HS:
680 	case MMC_TIMING_SD_HS:
681 	case MMC_TIMING_UHS_SDR25:
682 	case MMC_TIMING_UHS_DDR50:
683 	case MMC_TIMING_MMC_DDR52:
684 		/* For 50MHz clock, 120 Taps are available */
685 		tap_max = 120;
686 		break;
687 	case MMC_TIMING_UHS_SDR50:
688 		/* For 100MHz clock, 60 Taps are available */
689 		tap_max = 60;
690 		break;
691 	case MMC_TIMING_UHS_SDR104:
692 	case MMC_TIMING_MMC_HS200:
693 		/* For 200MHz clock, 30 Taps are available */
694 		tap_max = 30;
695 	default:
696 		break;
697 	}
698 
699 	tap_delay = (degrees * tap_max) / 360;
700 
701 	/* Set the Clock Phase */
702 	ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_INPUT, tap_delay);
703 	if (ret)
704 		pr_err("Error setting Input Tap Delay\n");
705 
706 	return ret;
707 }
708 
709 static const struct clk_ops zynqmp_sampleclk_ops = {
710 	.recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
711 	.set_phase = sdhci_zynqmp_sampleclk_set_phase,
712 };
713 
714 /**
715  * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
716  *
717  * @hw:			Pointer to the hardware clock structure.
718  * @degrees:		The clock phase shift between 0 - 359.
719  *
720  * Set the SD Output Clock Tap Delays for Output path
721  *
722  * Return: 0 on success and error value on error
723  */
724 static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
725 {
726 	struct sdhci_arasan_clk_data *clk_data =
727 		container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
728 	struct sdhci_arasan_data *sdhci_arasan =
729 		container_of(clk_data, struct sdhci_arasan_data, clk_data);
730 	struct sdhci_host *host = sdhci_arasan->host;
731 	u8 tap_delay, tap_max = 0;
732 
733 	/* This is applicable for SDHCI_SPEC_300 and above */
734 	if (host->version < SDHCI_SPEC_300)
735 		return 0;
736 
737 	switch (host->timing) {
738 	case MMC_TIMING_MMC_HS:
739 	case MMC_TIMING_SD_HS:
740 	case MMC_TIMING_UHS_SDR25:
741 	case MMC_TIMING_UHS_DDR50:
742 	case MMC_TIMING_MMC_DDR52:
743 		/* For 50MHz clock, 30 Taps are available */
744 		tap_max = 30;
745 		break;
746 	case MMC_TIMING_UHS_SDR50:
747 		/* For 100MHz clock, 15 Taps are available */
748 		tap_max = 15;
749 		break;
750 	case MMC_TIMING_UHS_SDR104:
751 	case MMC_TIMING_MMC_HS200:
752 		/* For 200MHz clock, 8 Taps are available */
753 		tap_max = 8;
754 	default:
755 		break;
756 	}
757 
758 	tap_delay = (degrees * tap_max) / 360;
759 
760 	/* Set the Clock Phase */
761 	if (tap_delay) {
762 		u32 regval;
763 
764 		regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
765 		regval |= SDHCI_OTAPDLY_ENABLE;
766 		sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
767 		regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
768 		regval |= tap_delay;
769 		sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
770 	}
771 
772 	return 0;
773 }
774 
775 static const struct clk_ops versal_sdcardclk_ops = {
776 	.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
777 	.set_phase = sdhci_versal_sdcardclk_set_phase,
778 };
779 
780 /**
781  * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
782  *
783  * @hw:			Pointer to the hardware clock structure.
784  * @degrees:		The clock phase shift between 0 - 359.
785  *
786  * Set the SD Input Clock Tap Delays for Input path
787  *
788  * Return: 0 on success and error value on error
789  */
790 static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees)
791 {
792 	struct sdhci_arasan_clk_data *clk_data =
793 		container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
794 	struct sdhci_arasan_data *sdhci_arasan =
795 		container_of(clk_data, struct sdhci_arasan_data, clk_data);
796 	struct sdhci_host *host = sdhci_arasan->host;
797 	u8 tap_delay, tap_max = 0;
798 
799 	/* This is applicable for SDHCI_SPEC_300 and above */
800 	if (host->version < SDHCI_SPEC_300)
801 		return 0;
802 
803 	switch (host->timing) {
804 	case MMC_TIMING_MMC_HS:
805 	case MMC_TIMING_SD_HS:
806 	case MMC_TIMING_UHS_SDR25:
807 	case MMC_TIMING_UHS_DDR50:
808 	case MMC_TIMING_MMC_DDR52:
809 		/* For 50MHz clock, 120 Taps are available */
810 		tap_max = 120;
811 		break;
812 	case MMC_TIMING_UHS_SDR50:
813 		/* For 100MHz clock, 60 Taps are available */
814 		tap_max = 60;
815 		break;
816 	case MMC_TIMING_UHS_SDR104:
817 	case MMC_TIMING_MMC_HS200:
818 		/* For 200MHz clock, 30 Taps are available */
819 		tap_max = 30;
820 	default:
821 		break;
822 	}
823 
824 	tap_delay = (degrees * tap_max) / 360;
825 
826 	/* Set the Clock Phase */
827 	if (tap_delay) {
828 		u32 regval;
829 
830 		regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
831 		regval |= SDHCI_ITAPDLY_CHGWIN;
832 		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
833 		regval |= SDHCI_ITAPDLY_ENABLE;
834 		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
835 		regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
836 		regval |= tap_delay;
837 		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
838 		regval &= ~SDHCI_ITAPDLY_CHGWIN;
839 		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
840 	}
841 
842 	return 0;
843 }
844 
845 static const struct clk_ops versal_sampleclk_ops = {
846 	.recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
847 	.set_phase = sdhci_versal_sampleclk_set_phase,
848 };
849 
850 static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid)
851 {
852 	u16 clk;
853 
854 	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
855 	clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
856 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
857 
858 	/* Issue DLL Reset */
859 	zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE);
860 
861 	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
862 
863 	sdhci_enable_clk(host, clk);
864 }
865 
866 static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode)
867 {
868 	struct sdhci_host *host = mmc_priv(mmc);
869 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
870 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
871 	struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;
872 	const char *clk_name = clk_hw_get_name(hw);
873 	u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 :
874 							   NODE_SD_1;
875 	int err;
876 
877 	arasan_zynqmp_dll_reset(host, device_id);
878 
879 	err = sdhci_execute_tuning(mmc, opcode);
880 	if (err)
881 		return err;
882 
883 	arasan_zynqmp_dll_reset(host, device_id);
884 
885 	return 0;
886 }
887 
888 /**
889  * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
890  *
891  * @host:		The sdhci_host
892  * @value:		The value to write
893  *
894  * The corecfg_clockmultiplier is supposed to contain clock multiplier
895  * value of programmable clock generator.
896  *
897  * NOTES:
898  * - Many existing devices don't seem to do this and work fine.  To keep
899  *   compatibility for old hardware where the device tree doesn't provide a
900  *   register map, this function is a noop if a soc_ctl_map hasn't been provided
901  *   for this platform.
902  * - The value of corecfg_clockmultiplier should sync with that of corresponding
903  *   value reading from sdhci_capability_register. So this function is called
904  *   once at probe time and never called again.
905  */
906 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
907 						u32 value)
908 {
909 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
910 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
911 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
912 		sdhci_arasan->soc_ctl_map;
913 
914 	/* Having a map is optional */
915 	if (!soc_ctl_map)
916 		return;
917 
918 	/* If we have a map, we expect to have a syscon */
919 	if (!sdhci_arasan->soc_ctl_base) {
920 		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
921 			mmc_hostname(host->mmc));
922 		return;
923 	}
924 
925 	sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
926 }
927 
928 /**
929  * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
930  *
931  * @host:		The sdhci_host
932  *
933  * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin.  This
934  * function can be used to make that happen.
935  *
936  * NOTES:
937  * - Many existing devices don't seem to do this and work fine.  To keep
938  *   compatibility for old hardware where the device tree doesn't provide a
939  *   register map, this function is a noop if a soc_ctl_map hasn't been provided
940  *   for this platform.
941  * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
942  *   to achieve lower clock rates.  That means that this function is called once
943  *   at probe time and never called again.
944  */
945 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
946 {
947 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
948 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
949 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
950 		sdhci_arasan->soc_ctl_map;
951 	u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);
952 
953 	/* Having a map is optional */
954 	if (!soc_ctl_map)
955 		return;
956 
957 	/* If we have a map, we expect to have a syscon */
958 	if (!sdhci_arasan->soc_ctl_base) {
959 		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
960 			mmc_hostname(host->mmc));
961 		return;
962 	}
963 
964 	sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
965 }
966 
967 static void sdhci_arasan_set_clk_delays(struct sdhci_host *host)
968 {
969 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
970 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
971 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
972 
973 	clk_set_phase(clk_data->sampleclk,
974 		      clk_data->clk_phase_in[host->timing]);
975 	clk_set_phase(clk_data->sdcardclk,
976 		      clk_data->clk_phase_out[host->timing]);
977 }
978 
979 static void arasan_dt_read_clk_phase(struct device *dev,
980 				     struct sdhci_arasan_clk_data *clk_data,
981 				     unsigned int timing, const char *prop)
982 {
983 	struct device_node *np = dev->of_node;
984 
985 	int clk_phase[2] = {0};
986 
987 	/*
988 	 * Read Tap Delay values from DT, if the DT does not contain the
989 	 * Tap Values then use the pre-defined values.
990 	 */
991 	if (of_property_read_variable_u32_array(np, prop, &clk_phase[0],
992 						2, 0)) {
993 		dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
994 			prop, clk_data->clk_phase_in[timing],
995 			clk_data->clk_phase_out[timing]);
996 		return;
997 	}
998 
999 	/* The values read are Input and Output Clock Delays in order */
1000 	clk_data->clk_phase_in[timing] = clk_phase[0];
1001 	clk_data->clk_phase_out[timing] = clk_phase[1];
1002 }
1003 
1004 /**
1005  * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
1006  *
1007  * @dev:		Pointer to our struct device.
1008  * @clk_data:		Pointer to the Clock Data structure
1009  *
1010  * Called at initialization to parse the values of Clock Delays.
1011  */
1012 static void arasan_dt_parse_clk_phases(struct device *dev,
1013 				       struct sdhci_arasan_clk_data *clk_data)
1014 {
1015 	u32 mio_bank = 0;
1016 	int i;
1017 
1018 	/*
1019 	 * This has been kept as a pointer and is assigned a function here.
1020 	 * So that different controller variants can assign their own handling
1021 	 * function.
1022 	 */
1023 	clk_data->set_clk_delays = sdhci_arasan_set_clk_delays;
1024 
1025 	if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {
1026 		u32 zynqmp_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1027 			ZYNQMP_ICLK_PHASE;
1028 		u32 zynqmp_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1029 			ZYNQMP_OCLK_PHASE;
1030 
1031 		of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank);
1032 		if (mio_bank == 2) {
1033 			zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90;
1034 			zynqmp_oclk_phase[MMC_TIMING_MMC_HS200] = 90;
1035 		}
1036 
1037 		for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1038 			clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i];
1039 			clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i];
1040 		}
1041 	}
1042 
1043 	if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) {
1044 		u32 versal_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1045 			VERSAL_ICLK_PHASE;
1046 		u32 versal_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1047 			VERSAL_OCLK_PHASE;
1048 
1049 		for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1050 			clk_data->clk_phase_in[i] = versal_iclk_phase[i];
1051 			clk_data->clk_phase_out[i] = versal_oclk_phase[i];
1052 		}
1053 	}
1054 
1055 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY,
1056 				 "clk-phase-legacy");
1057 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS,
1058 				 "clk-phase-mmc-hs");
1059 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS,
1060 				 "clk-phase-sd-hs");
1061 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12,
1062 				 "clk-phase-uhs-sdr12");
1063 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25,
1064 				 "clk-phase-uhs-sdr25");
1065 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50,
1066 				 "clk-phase-uhs-sdr50");
1067 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104,
1068 				 "clk-phase-uhs-sdr104");
1069 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50,
1070 				 "clk-phase-uhs-ddr50");
1071 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52,
1072 				 "clk-phase-mmc-ddr52");
1073 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200,
1074 				 "clk-phase-mmc-hs200");
1075 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400,
1076 				 "clk-phase-mmc-hs400");
1077 }
1078 
1079 static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
1080 	.ops = &sdhci_arasan_ops,
1081 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1082 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1083 			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1084 			SDHCI_QUIRK2_STOP_WITH_TC,
1085 };
1086 
1087 static const struct sdhci_arasan_clk_ops arasan_clk_ops = {
1088 	.sdcardclk_ops = &arasan_sdcardclk_ops,
1089 	.sampleclk_ops = &arasan_sampleclk_ops,
1090 };
1091 
1092 static struct sdhci_arasan_of_data sdhci_arasan_generic_data = {
1093 	.pdata = &sdhci_arasan_pdata,
1094 	.clk_ops = &arasan_clk_ops,
1095 };
1096 
1097 static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
1098 	.ops = &sdhci_arasan_cqe_ops,
1099 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1100 		SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1101 		SDHCI_QUIRK_NO_LED |
1102 		SDHCI_QUIRK_32BIT_DMA_ADDR |
1103 		SDHCI_QUIRK_32BIT_DMA_SIZE |
1104 		SDHCI_QUIRK_32BIT_ADMA_SIZE,
1105 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1106 		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1107 		SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1108 		SDHCI_QUIRK2_STOP_WITH_TC |
1109 		SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1110 };
1111 
1112 static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = {
1113 	.ops = &sdhci_arasan_ops,
1114 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1115 		SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1116 		SDHCI_QUIRK_NO_LED |
1117 		SDHCI_QUIRK_32BIT_DMA_ADDR |
1118 		SDHCI_QUIRK_32BIT_DMA_SIZE |
1119 		SDHCI_QUIRK_32BIT_ADMA_SIZE,
1120 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1121 		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1122 		SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1123 		SDHCI_QUIRK2_STOP_WITH_TC |
1124 		SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1125 };
1126 
1127 static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = {
1128 	.ops = &sdhci_arasan_ops,
1129 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1130 		SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1131 		SDHCI_QUIRK_NO_LED |
1132 		SDHCI_QUIRK_32BIT_DMA_ADDR |
1133 		SDHCI_QUIRK_32BIT_DMA_SIZE |
1134 		SDHCI_QUIRK_32BIT_ADMA_SIZE,
1135 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1136 		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1137 		SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1138 		SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1139 };
1140 
1141 static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
1142 	.soc_ctl_map = &rk3399_soc_ctl_map,
1143 	.pdata = &sdhci_arasan_cqe_pdata,
1144 	.clk_ops = &arasan_clk_ops,
1145 };
1146 
1147 static struct sdhci_arasan_of_data intel_lgm_emmc_data = {
1148 	.soc_ctl_map = &intel_lgm_emmc_soc_ctl_map,
1149 	.pdata = &sdhci_arasan_cqe_pdata,
1150 	.clk_ops = &arasan_clk_ops,
1151 };
1152 
1153 static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
1154 	.soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map,
1155 	.pdata = &sdhci_arasan_cqe_pdata,
1156 	.clk_ops = &arasan_clk_ops,
1157 };
1158 
1159 static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = {
1160 	.ops = &sdhci_arasan_ops,
1161 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1162 			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1163 			SDHCI_QUIRK2_STOP_WITH_TC,
1164 };
1165 
1166 static const struct sdhci_arasan_clk_ops zynqmp_clk_ops = {
1167 	.sdcardclk_ops = &zynqmp_sdcardclk_ops,
1168 	.sampleclk_ops = &zynqmp_sampleclk_ops,
1169 };
1170 
1171 static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = {
1172 	.pdata = &sdhci_arasan_zynqmp_pdata,
1173 	.clk_ops = &zynqmp_clk_ops,
1174 };
1175 
1176 static const struct sdhci_arasan_clk_ops versal_clk_ops = {
1177 	.sdcardclk_ops = &versal_sdcardclk_ops,
1178 	.sampleclk_ops = &versal_sampleclk_ops,
1179 };
1180 
1181 static struct sdhci_arasan_of_data sdhci_arasan_versal_data = {
1182 	.pdata = &sdhci_arasan_zynqmp_pdata,
1183 	.clk_ops = &versal_clk_ops,
1184 };
1185 
1186 static struct sdhci_arasan_of_data intel_keembay_emmc_data = {
1187 	.soc_ctl_map = &intel_keembay_soc_ctl_map,
1188 	.pdata = &sdhci_keembay_emmc_pdata,
1189 };
1190 
1191 static struct sdhci_arasan_of_data intel_keembay_sd_data = {
1192 	.soc_ctl_map = &intel_keembay_soc_ctl_map,
1193 	.pdata = &sdhci_keembay_sd_pdata,
1194 };
1195 
1196 static struct sdhci_arasan_of_data intel_keembay_sdio_data = {
1197 	.soc_ctl_map = &intel_keembay_soc_ctl_map,
1198 	.pdata = &sdhci_keembay_sdio_pdata,
1199 };
1200 
1201 static const struct of_device_id sdhci_arasan_of_match[] = {
1202 	/* SoC-specific compatible strings w/ soc_ctl_map */
1203 	{
1204 		.compatible = "rockchip,rk3399-sdhci-5.1",
1205 		.data = &sdhci_arasan_rk3399_data,
1206 	},
1207 	{
1208 		.compatible = "intel,lgm-sdhci-5.1-emmc",
1209 		.data = &intel_lgm_emmc_data,
1210 	},
1211 	{
1212 		.compatible = "intel,lgm-sdhci-5.1-sdxc",
1213 		.data = &intel_lgm_sdxc_data,
1214 	},
1215 	{
1216 		.compatible = "intel,keembay-sdhci-5.1-emmc",
1217 		.data = &intel_keembay_emmc_data,
1218 	},
1219 	{
1220 		.compatible = "intel,keembay-sdhci-5.1-sd",
1221 		.data = &intel_keembay_sd_data,
1222 	},
1223 	{
1224 		.compatible = "intel,keembay-sdhci-5.1-sdio",
1225 		.data = &intel_keembay_sdio_data,
1226 	},
1227 	/* Generic compatible below here */
1228 	{
1229 		.compatible = "arasan,sdhci-8.9a",
1230 		.data = &sdhci_arasan_generic_data,
1231 	},
1232 	{
1233 		.compatible = "arasan,sdhci-5.1",
1234 		.data = &sdhci_arasan_generic_data,
1235 	},
1236 	{
1237 		.compatible = "arasan,sdhci-4.9a",
1238 		.data = &sdhci_arasan_generic_data,
1239 	},
1240 	{
1241 		.compatible = "xlnx,zynqmp-8.9a",
1242 		.data = &sdhci_arasan_zynqmp_data,
1243 	},
1244 	{
1245 		.compatible = "xlnx,versal-8.9a",
1246 		.data = &sdhci_arasan_versal_data,
1247 	},
1248 	{ /* sentinel */ }
1249 };
1250 MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
1251 
1252 /**
1253  * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
1254  *
1255  * @sdhci_arasan:	Our private data structure.
1256  * @clk_xin:		Pointer to the functional clock
1257  * @dev:		Pointer to our struct device.
1258  *
1259  * Some PHY devices need to know what the actual card clock is.  In order for
1260  * them to find out, we'll provide a clock through the common clock framework
1261  * for them to query.
1262  *
1263  * Return: 0 on success and error value on error
1264  */
1265 static int
1266 sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan,
1267 				struct clk *clk_xin,
1268 				struct device *dev)
1269 {
1270 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1271 	struct device_node *np = dev->of_node;
1272 	struct clk_init_data sdcardclk_init;
1273 	const char *parent_clk_name;
1274 	int ret;
1275 
1276 	ret = of_property_read_string_index(np, "clock-output-names", 0,
1277 					    &sdcardclk_init.name);
1278 	if (ret) {
1279 		dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1280 		return ret;
1281 	}
1282 
1283 	parent_clk_name = __clk_get_name(clk_xin);
1284 	sdcardclk_init.parent_names = &parent_clk_name;
1285 	sdcardclk_init.num_parents = 1;
1286 	sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
1287 	sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops;
1288 
1289 	clk_data->sdcardclk_hw.init = &sdcardclk_init;
1290 	clk_data->sdcardclk =
1291 		devm_clk_register(dev, &clk_data->sdcardclk_hw);
1292 	if (IS_ERR(clk_data->sdcardclk))
1293 		return PTR_ERR(clk_data->sdcardclk);
1294 	clk_data->sdcardclk_hw.init = NULL;
1295 
1296 	ret = of_clk_add_provider(np, of_clk_src_simple_get,
1297 				  clk_data->sdcardclk);
1298 	if (ret)
1299 		dev_err(dev, "Failed to add sdcard clock provider\n");
1300 
1301 	return ret;
1302 }
1303 
1304 /**
1305  * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
1306  *
1307  * @sdhci_arasan:	Our private data structure.
1308  * @clk_xin:		Pointer to the functional clock
1309  * @dev:		Pointer to our struct device.
1310  *
1311  * Some PHY devices need to know what the actual card clock is.  In order for
1312  * them to find out, we'll provide a clock through the common clock framework
1313  * for them to query.
1314  *
1315  * Return: 0 on success and error value on error
1316  */
1317 static int
1318 sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan,
1319 				struct clk *clk_xin,
1320 				struct device *dev)
1321 {
1322 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1323 	struct device_node *np = dev->of_node;
1324 	struct clk_init_data sampleclk_init;
1325 	const char *parent_clk_name;
1326 	int ret;
1327 
1328 	ret = of_property_read_string_index(np, "clock-output-names", 1,
1329 					    &sampleclk_init.name);
1330 	if (ret) {
1331 		dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1332 		return ret;
1333 	}
1334 
1335 	parent_clk_name = __clk_get_name(clk_xin);
1336 	sampleclk_init.parent_names = &parent_clk_name;
1337 	sampleclk_init.num_parents = 1;
1338 	sampleclk_init.flags = CLK_GET_RATE_NOCACHE;
1339 	sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops;
1340 
1341 	clk_data->sampleclk_hw.init = &sampleclk_init;
1342 	clk_data->sampleclk =
1343 		devm_clk_register(dev, &clk_data->sampleclk_hw);
1344 	if (IS_ERR(clk_data->sampleclk))
1345 		return PTR_ERR(clk_data->sampleclk);
1346 	clk_data->sampleclk_hw.init = NULL;
1347 
1348 	ret = of_clk_add_provider(np, of_clk_src_simple_get,
1349 				  clk_data->sampleclk);
1350 	if (ret)
1351 		dev_err(dev, "Failed to add sample clock provider\n");
1352 
1353 	return ret;
1354 }
1355 
1356 /**
1357  * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
1358  *
1359  * @dev:		Pointer to our struct device.
1360  *
1361  * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
1362  * returned success.
1363  */
1364 static void sdhci_arasan_unregister_sdclk(struct device *dev)
1365 {
1366 	struct device_node *np = dev->of_node;
1367 
1368 	if (!of_find_property(np, "#clock-cells", NULL))
1369 		return;
1370 
1371 	of_clk_del_provider(dev->of_node);
1372 }
1373 
1374 /**
1375  * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
1376  *
1377  * This should be set based on the System Address Bus.
1378  * 0: the Core supports only 32-bit System Address Bus.
1379  * 1: the Core supports 64-bit System Address Bus.
1380  *
1381  * NOTES:
1382  * - For Keem Bay, it is required to clear this bit. Its default value is 1'b1.
1383  *   Keem Bay does not support 64-bit access.
1384  *
1385  * @host:		The sdhci_host
1386  * @value:		The value to write
1387  */
1388 static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value)
1389 {
1390 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1391 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1392 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
1393 		sdhci_arasan->soc_ctl_map;
1394 
1395 	/* Having a map is optional */
1396 	if (!soc_ctl_map)
1397 		return;
1398 
1399 	/* If we have a map, we expect to have a syscon */
1400 	if (!sdhci_arasan->soc_ctl_base) {
1401 		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
1402 			mmc_hostname(host->mmc));
1403 		return;
1404 	}
1405 
1406 	sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value);
1407 }
1408 
1409 /**
1410  * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
1411  *
1412  * @sdhci_arasan:	Our private data structure.
1413  * @clk_xin:		Pointer to the functional clock
1414  * @dev:		Pointer to our struct device.
1415  *
1416  * Some PHY devices need to know what the actual card clock is.  In order for
1417  * them to find out, we'll provide a clock through the common clock framework
1418  * for them to query.
1419  *
1420  * Note: without seriously re-architecting SDHCI's clock code and testing on
1421  * all platforms, there's no way to create a totally beautiful clock here
1422  * with all clock ops implemented.  Instead, we'll just create a clock that can
1423  * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
1424  * framework that we're doing things behind its back.  This should be sufficient
1425  * to create nice clean device tree bindings and later (if needed) we can try
1426  * re-architecting SDHCI if we see some benefit to it.
1427  *
1428  * Return: 0 on success and error value on error
1429  */
1430 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
1431 				       struct clk *clk_xin,
1432 				       struct device *dev)
1433 {
1434 	struct device_node *np = dev->of_node;
1435 	u32 num_clks = 0;
1436 	int ret;
1437 
1438 	/* Providing a clock to the PHY is optional; no error if missing */
1439 	if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
1440 		return 0;
1441 
1442 	ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev);
1443 	if (ret)
1444 		return ret;
1445 
1446 	if (num_clks) {
1447 		ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin,
1448 						      dev);
1449 		if (ret) {
1450 			sdhci_arasan_unregister_sdclk(dev);
1451 			return ret;
1452 		}
1453 	}
1454 
1455 	return 0;
1456 }
1457 
1458 static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
1459 {
1460 	struct sdhci_host *host = sdhci_arasan->host;
1461 	struct cqhci_host *cq_host;
1462 	bool dma64;
1463 	int ret;
1464 
1465 	if (!sdhci_arasan->has_cqe)
1466 		return sdhci_add_host(host);
1467 
1468 	ret = sdhci_setup_host(host);
1469 	if (ret)
1470 		return ret;
1471 
1472 	cq_host = devm_kzalloc(host->mmc->parent,
1473 			       sizeof(*cq_host), GFP_KERNEL);
1474 	if (!cq_host) {
1475 		ret = -ENOMEM;
1476 		goto cleanup;
1477 	}
1478 
1479 	cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
1480 	cq_host->ops = &sdhci_arasan_cqhci_ops;
1481 
1482 	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1483 	if (dma64)
1484 		cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1485 
1486 	ret = cqhci_init(cq_host, host->mmc, dma64);
1487 	if (ret)
1488 		goto cleanup;
1489 
1490 	ret = __sdhci_add_host(host);
1491 	if (ret)
1492 		goto cleanup;
1493 
1494 	return 0;
1495 
1496 cleanup:
1497 	sdhci_cleanup_host(host);
1498 	return ret;
1499 }
1500 
1501 static int sdhci_arasan_probe(struct platform_device *pdev)
1502 {
1503 	int ret;
1504 	const struct of_device_id *match;
1505 	struct device_node *node;
1506 	struct clk *clk_xin;
1507 	struct sdhci_host *host;
1508 	struct sdhci_pltfm_host *pltfm_host;
1509 	struct sdhci_arasan_data *sdhci_arasan;
1510 	struct device_node *np = pdev->dev.of_node;
1511 	const struct sdhci_arasan_of_data *data;
1512 
1513 	match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node);
1514 	data = match->data;
1515 	host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan));
1516 
1517 	if (IS_ERR(host))
1518 		return PTR_ERR(host);
1519 
1520 	pltfm_host = sdhci_priv(host);
1521 	sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1522 	sdhci_arasan->host = host;
1523 
1524 	sdhci_arasan->soc_ctl_map = data->soc_ctl_map;
1525 	sdhci_arasan->clk_ops = data->clk_ops;
1526 
1527 	node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0);
1528 	if (node) {
1529 		sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
1530 		of_node_put(node);
1531 
1532 		if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
1533 			ret = dev_err_probe(&pdev->dev,
1534 					    PTR_ERR(sdhci_arasan->soc_ctl_base),
1535 					    "Can't get syscon\n");
1536 			goto err_pltfm_free;
1537 		}
1538 	}
1539 
1540 	sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
1541 	if (IS_ERR(sdhci_arasan->clk_ahb)) {
1542 		dev_err(&pdev->dev, "clk_ahb clock not found.\n");
1543 		ret = PTR_ERR(sdhci_arasan->clk_ahb);
1544 		goto err_pltfm_free;
1545 	}
1546 
1547 	clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
1548 	if (IS_ERR(clk_xin)) {
1549 		dev_err(&pdev->dev, "clk_xin clock not found.\n");
1550 		ret = PTR_ERR(clk_xin);
1551 		goto err_pltfm_free;
1552 	}
1553 
1554 	ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
1555 	if (ret) {
1556 		dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
1557 		goto err_pltfm_free;
1558 	}
1559 
1560 	ret = clk_prepare_enable(clk_xin);
1561 	if (ret) {
1562 		dev_err(&pdev->dev, "Unable to enable SD clock.\n");
1563 		goto clk_dis_ahb;
1564 	}
1565 
1566 	sdhci_get_of_property(pdev);
1567 
1568 	if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
1569 		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
1570 
1571 	if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))
1572 		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE;
1573 
1574 	pltfm_host->clk = clk_xin;
1575 
1576 	if (of_device_is_compatible(pdev->dev.of_node,
1577 				    "rockchip,rk3399-sdhci-5.1"))
1578 		sdhci_arasan_update_clockmultiplier(host, 0x0);
1579 
1580 	if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
1581 	    of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
1582 	    of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {
1583 		sdhci_arasan_update_clockmultiplier(host, 0x0);
1584 		sdhci_arasan_update_support64b(host, 0x0);
1585 
1586 		host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1587 	}
1588 
1589 	sdhci_arasan_update_baseclkfreq(host);
1590 
1591 	ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
1592 	if (ret)
1593 		goto clk_disable_all;
1594 
1595 	if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {
1596 		host->mmc_host_ops.execute_tuning =
1597 			arasan_zynqmp_execute_tuning;
1598 	}
1599 
1600 	arasan_dt_parse_clk_phases(&pdev->dev, &sdhci_arasan->clk_data);
1601 
1602 	ret = mmc_of_parse(host->mmc);
1603 	if (ret) {
1604 		if (ret != -EPROBE_DEFER)
1605 			dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret);
1606 		goto unreg_clk;
1607 	}
1608 
1609 	sdhci_arasan->phy = ERR_PTR(-ENODEV);
1610 	if (of_device_is_compatible(pdev->dev.of_node,
1611 				    "arasan,sdhci-5.1")) {
1612 		sdhci_arasan->phy = devm_phy_get(&pdev->dev,
1613 						 "phy_arasan");
1614 		if (IS_ERR(sdhci_arasan->phy)) {
1615 			ret = PTR_ERR(sdhci_arasan->phy);
1616 			dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");
1617 			goto unreg_clk;
1618 		}
1619 
1620 		ret = phy_init(sdhci_arasan->phy);
1621 		if (ret < 0) {
1622 			dev_err(&pdev->dev, "phy_init err.\n");
1623 			goto unreg_clk;
1624 		}
1625 
1626 		host->mmc_host_ops.hs400_enhanced_strobe =
1627 					sdhci_arasan_hs400_enhanced_strobe;
1628 		host->mmc_host_ops.start_signal_voltage_switch =
1629 					sdhci_arasan_voltage_switch;
1630 		sdhci_arasan->has_cqe = true;
1631 		host->mmc->caps2 |= MMC_CAP2_CQE;
1632 
1633 		if (!of_property_read_bool(np, "disable-cqe-dcmd"))
1634 			host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
1635 	}
1636 
1637 	ret = sdhci_arasan_add_host(sdhci_arasan);
1638 	if (ret)
1639 		goto err_add_host;
1640 
1641 	return 0;
1642 
1643 err_add_host:
1644 	if (!IS_ERR(sdhci_arasan->phy))
1645 		phy_exit(sdhci_arasan->phy);
1646 unreg_clk:
1647 	sdhci_arasan_unregister_sdclk(&pdev->dev);
1648 clk_disable_all:
1649 	clk_disable_unprepare(clk_xin);
1650 clk_dis_ahb:
1651 	clk_disable_unprepare(sdhci_arasan->clk_ahb);
1652 err_pltfm_free:
1653 	sdhci_pltfm_free(pdev);
1654 	return ret;
1655 }
1656 
1657 static int sdhci_arasan_remove(struct platform_device *pdev)
1658 {
1659 	int ret;
1660 	struct sdhci_host *host = platform_get_drvdata(pdev);
1661 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1662 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1663 	struct clk *clk_ahb = sdhci_arasan->clk_ahb;
1664 
1665 	if (!IS_ERR(sdhci_arasan->phy)) {
1666 		if (sdhci_arasan->is_phy_on)
1667 			phy_power_off(sdhci_arasan->phy);
1668 		phy_exit(sdhci_arasan->phy);
1669 	}
1670 
1671 	sdhci_arasan_unregister_sdclk(&pdev->dev);
1672 
1673 	ret = sdhci_pltfm_unregister(pdev);
1674 
1675 	clk_disable_unprepare(clk_ahb);
1676 
1677 	return ret;
1678 }
1679 
1680 static struct platform_driver sdhci_arasan_driver = {
1681 	.driver = {
1682 		.name = "sdhci-arasan",
1683 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
1684 		.of_match_table = sdhci_arasan_of_match,
1685 		.pm = &sdhci_arasan_dev_pm_ops,
1686 	},
1687 	.probe = sdhci_arasan_probe,
1688 	.remove = sdhci_arasan_remove,
1689 };
1690 
1691 module_platform_driver(sdhci_arasan_driver);
1692 
1693 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
1694 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
1695 MODULE_LICENSE("GPL");
1696