1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Arasan Secure Digital Host Controller Interface.
4  * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
5  * Copyright (c) 2012 Wind River Systems, Inc.
6  * Copyright (C) 2013 Pengutronix e.K.
7  * Copyright (C) 2013 Xilinx Inc.
8  *
9  * Based on sdhci-of-esdhc.c
10  *
11  * Copyright (c) 2007 Freescale Semiconductor, Inc.
12  * Copyright (c) 2009 MontaVista Software, Inc.
13  *
14  * Authors: Xiaobo Xie <X.Xie@freescale.com>
15  *	    Anton Vorontsov <avorontsov@ru.mvista.com>
16  */
17 
18 #include <linux/clk-provider.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/phy/phy.h>
23 #include <linux/regmap.h>
24 #include <linux/of.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
26 
27 #include "cqhci.h"
28 #include "sdhci-pltfm.h"
29 
30 #define SDHCI_ARASAN_VENDOR_REGISTER	0x78
31 
32 #define SDHCI_ARASAN_ITAPDLY_REGISTER	0xF0F8
33 #define SDHCI_ARASAN_OTAPDLY_REGISTER	0xF0FC
34 
35 #define SDHCI_ARASAN_CQE_BASE_ADDR	0x200
36 #define VENDOR_ENHANCED_STROBE		BIT(0)
37 
38 #define PHY_CLK_TOO_SLOW_HZ		400000
39 
40 #define SDHCI_ITAPDLY_CHGWIN		0x200
41 #define SDHCI_ITAPDLY_ENABLE		0x100
42 #define SDHCI_OTAPDLY_ENABLE		0x40
43 
44 /* Default settings for ZynqMP Clock Phases */
45 #define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63,  0,   0, 183, 54,  0, 0}
46 #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
47 
48 #define VERSAL_ICLK_PHASE {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0}
49 #define VERSAL_OCLK_PHASE {0,  60, 48, 0, 48, 72, 90, 36, 60, 90, 0}
50 
51 /*
52  * On some SoCs the syscon area has a feature where the upper 16-bits of
53  * each 32-bit register act as a write mask for the lower 16-bits.  This allows
54  * atomic updates of the register without locking.  This macro is used on SoCs
55  * that have that feature.
56  */
57 #define HIWORD_UPDATE(val, mask, shift) \
58 		((val) << (shift) | (mask) << ((shift) + 16))
59 
60 /**
61  * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
62  *
63  * @reg:	Offset within the syscon of the register containing this field
64  * @width:	Number of bits for this field
65  * @shift:	Bit offset within @reg of this field (or -1 if not avail)
66  */
67 struct sdhci_arasan_soc_ctl_field {
68 	u32 reg;
69 	u16 width;
70 	s16 shift;
71 };
72 
73 /**
74  * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
75  *
76  * @baseclkfreq:	Where to find corecfg_baseclkfreq
77  * @clockmultiplier:	Where to find corecfg_clockmultiplier
78  * @support64b:		Where to find SUPPORT64B bit
79  * @hiword_update:	If true, use HIWORD_UPDATE to access the syscon
80  *
81  * It's up to the licensee of the Arsan IP block to make these available
82  * somewhere if needed.  Presumably these will be scattered somewhere that's
83  * accessible via the syscon API.
84  */
85 struct sdhci_arasan_soc_ctl_map {
86 	struct sdhci_arasan_soc_ctl_field	baseclkfreq;
87 	struct sdhci_arasan_soc_ctl_field	clockmultiplier;
88 	struct sdhci_arasan_soc_ctl_field	support64b;
89 	bool					hiword_update;
90 };
91 
92 /**
93  * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller
94  *
95  * @sdcardclk_ops:	The output clock related operations
96  * @sampleclk_ops:	The sample clock related operations
97  */
98 struct sdhci_arasan_clk_ops {
99 	const struct clk_ops *sdcardclk_ops;
100 	const struct clk_ops *sampleclk_ops;
101 };
102 
103 /**
104  * struct sdhci_arasan_clk_data - Arasan Controller Clock Data.
105  *
106  * @sdcardclk_hw:	Struct for the clock we might provide to a PHY.
107  * @sdcardclk:		Pointer to normal 'struct clock' for sdcardclk_hw.
108  * @sampleclk_hw:	Struct for the clock we might provide to a PHY.
109  * @sampleclk:		Pointer to normal 'struct clock' for sampleclk_hw.
110  * @clk_phase_in:	Array of Input Clock Phase Delays for all speed modes
111  * @clk_phase_out:	Array of Output Clock Phase Delays for all speed modes
112  * @set_clk_delays:	Function pointer for setting Clock Delays
113  * @clk_of_data:	Platform specific runtime clock data storage pointer
114  */
115 struct sdhci_arasan_clk_data {
116 	struct clk_hw	sdcardclk_hw;
117 	struct clk      *sdcardclk;
118 	struct clk_hw	sampleclk_hw;
119 	struct clk      *sampleclk;
120 	int		clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
121 	int		clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
122 	void		(*set_clk_delays)(struct sdhci_host *host);
123 	void		*clk_of_data;
124 };
125 
126 /**
127  * struct sdhci_arasan_data - Arasan Controller Data
128  *
129  * @host:		Pointer to the main SDHCI host structure.
130  * @clk_ahb:		Pointer to the AHB clock
131  * @phy:		Pointer to the generic phy
132  * @is_phy_on:		True if the PHY is on; false if not.
133  * @has_cqe:		True if controller has command queuing engine.
134  * @clk_data:		Struct for the Arasan Controller Clock Data.
135  * @clk_ops:		Struct for the Arasan Controller Clock Operations.
136  * @soc_ctl_base:	Pointer to regmap for syscon for soc_ctl registers.
137  * @soc_ctl_map:	Map to get offsets into soc_ctl registers.
138  * @quirks:		Arasan deviations from spec.
139  */
140 struct sdhci_arasan_data {
141 	struct sdhci_host *host;
142 	struct clk	*clk_ahb;
143 	struct phy	*phy;
144 	bool		is_phy_on;
145 
146 	bool		has_cqe;
147 	struct sdhci_arasan_clk_data clk_data;
148 	const struct sdhci_arasan_clk_ops *clk_ops;
149 
150 	struct regmap	*soc_ctl_base;
151 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
152 	unsigned int	quirks;
153 
154 /* Controller does not have CD wired and will not function normally without */
155 #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST	BIT(0)
156 /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the
157  * internal clock even when the clock isn't stable */
158 #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1)
159 };
160 
161 struct sdhci_arasan_of_data {
162 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
163 	const struct sdhci_pltfm_data *pdata;
164 	const struct sdhci_arasan_clk_ops *clk_ops;
165 };
166 
167 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
168 	.baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
169 	.clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
170 	.hiword_update = true,
171 };
172 
173 static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = {
174 	.baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 },
175 	.clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
176 	.hiword_update = false,
177 };
178 
179 static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
180 	.baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 },
181 	.clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
182 	.hiword_update = false,
183 };
184 
185 static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = {
186 	.baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
187 	.clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
188 	.support64b = { .reg = 0x4, .width = 1, .shift = 24 },
189 	.hiword_update = false,
190 };
191 
192 /**
193  * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
194  *
195  * @host:	The sdhci_host
196  * @fld:	The field to write to
197  * @val:	The value to write
198  *
199  * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
200  * Note that if a field is specified as not available (shift < 0) then
201  * this function will silently return an error code.  It will be noisy
202  * and print errors for any other (unexpected) errors.
203  *
204  * Return: 0 on success and error value on error
205  */
206 static int sdhci_arasan_syscon_write(struct sdhci_host *host,
207 				   const struct sdhci_arasan_soc_ctl_field *fld,
208 				   u32 val)
209 {
210 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
211 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
212 	struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
213 	u32 reg = fld->reg;
214 	u16 width = fld->width;
215 	s16 shift = fld->shift;
216 	int ret;
217 
218 	/*
219 	 * Silently return errors for shift < 0 so caller doesn't have
220 	 * to check for fields which are optional.  For fields that
221 	 * are required then caller needs to do something special
222 	 * anyway.
223 	 */
224 	if (shift < 0)
225 		return -EINVAL;
226 
227 	if (sdhci_arasan->soc_ctl_map->hiword_update)
228 		ret = regmap_write(soc_ctl_base, reg,
229 				   HIWORD_UPDATE(val, GENMASK(width, 0),
230 						 shift));
231 	else
232 		ret = regmap_update_bits(soc_ctl_base, reg,
233 					 GENMASK(shift + width, shift),
234 					 val << shift);
235 
236 	/* Yell about (unexpected) regmap errors */
237 	if (ret)
238 		pr_warn("%s: Regmap write fail: %d\n",
239 			 mmc_hostname(host->mmc), ret);
240 
241 	return ret;
242 }
243 
244 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
245 {
246 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
247 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
248 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
249 	bool ctrl_phy = false;
250 
251 	if (!IS_ERR(sdhci_arasan->phy)) {
252 		if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
253 			/*
254 			 * If PHY off, set clock to max speed and power PHY on.
255 			 *
256 			 * Although PHY docs apparently suggest power cycling
257 			 * when changing the clock the PHY doesn't like to be
258 			 * powered on while at low speeds like those used in ID
259 			 * mode.  Even worse is powering the PHY on while the
260 			 * clock is off.
261 			 *
262 			 * To workaround the PHY limitations, the best we can
263 			 * do is to power it on at a faster speed and then slam
264 			 * through low speeds without power cycling.
265 			 */
266 			sdhci_set_clock(host, host->max_clk);
267 			phy_power_on(sdhci_arasan->phy);
268 			sdhci_arasan->is_phy_on = true;
269 
270 			/*
271 			 * We'll now fall through to the below case with
272 			 * ctrl_phy = false (so we won't turn off/on).  The
273 			 * sdhci_set_clock() will set the real clock.
274 			 */
275 		} else if (clock > PHY_CLK_TOO_SLOW_HZ) {
276 			/*
277 			 * At higher clock speeds the PHY is fine being power
278 			 * cycled and docs say you _should_ power cycle when
279 			 * changing clock speeds.
280 			 */
281 			ctrl_phy = true;
282 		}
283 	}
284 
285 	if (ctrl_phy && sdhci_arasan->is_phy_on) {
286 		phy_power_off(sdhci_arasan->phy);
287 		sdhci_arasan->is_phy_on = false;
288 	}
289 
290 	/* Set the Input and Output Clock Phase Delays */
291 	if (clk_data->set_clk_delays)
292 		clk_data->set_clk_delays(host);
293 
294 	sdhci_set_clock(host, clock);
295 
296 	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
297 		/*
298 		 * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
299 		 * after enabling the clock even though the clock is not
300 		 * stable. Trying to use a clock without waiting here results
301 		 * in EILSEQ while detecting some older/slower cards. The
302 		 * chosen delay is the maximum delay from sdhci_set_clock.
303 		 */
304 		msleep(20);
305 
306 	if (ctrl_phy) {
307 		phy_power_on(sdhci_arasan->phy);
308 		sdhci_arasan->is_phy_on = true;
309 	}
310 }
311 
312 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
313 					struct mmc_ios *ios)
314 {
315 	u32 vendor;
316 	struct sdhci_host *host = mmc_priv(mmc);
317 
318 	vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER);
319 	if (ios->enhanced_strobe)
320 		vendor |= VENDOR_ENHANCED_STROBE;
321 	else
322 		vendor &= ~VENDOR_ENHANCED_STROBE;
323 
324 	sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER);
325 }
326 
327 static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
328 {
329 	u8 ctrl;
330 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
331 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
332 
333 	sdhci_reset(host, mask);
334 
335 	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
336 		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
337 		ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
338 		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
339 	}
340 }
341 
342 static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
343 				       struct mmc_ios *ios)
344 {
345 	switch (ios->signal_voltage) {
346 	case MMC_SIGNAL_VOLTAGE_180:
347 		/*
348 		 * Plese don't switch to 1V8 as arasan,5.1 doesn't
349 		 * actually refer to this setting to indicate the
350 		 * signal voltage and the state machine will be broken
351 		 * actually if we force to enable 1V8. That's something
352 		 * like broken quirk but we could work around here.
353 		 */
354 		return 0;
355 	case MMC_SIGNAL_VOLTAGE_330:
356 	case MMC_SIGNAL_VOLTAGE_120:
357 		/* We don't support 3V3 and 1V2 */
358 		break;
359 	}
360 
361 	return -EINVAL;
362 }
363 
364 static const struct sdhci_ops sdhci_arasan_ops = {
365 	.set_clock = sdhci_arasan_set_clock,
366 	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
367 	.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
368 	.set_bus_width = sdhci_set_bus_width,
369 	.reset = sdhci_arasan_reset,
370 	.set_uhs_signaling = sdhci_set_uhs_signaling,
371 	.set_power = sdhci_set_power_and_bus_voltage,
372 };
373 
374 static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
375 {
376 	int cmd_error = 0;
377 	int data_error = 0;
378 
379 	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
380 		return intmask;
381 
382 	cqhci_irq(host->mmc, intmask, cmd_error, data_error);
383 
384 	return 0;
385 }
386 
387 static void sdhci_arasan_dumpregs(struct mmc_host *mmc)
388 {
389 	sdhci_dumpregs(mmc_priv(mmc));
390 }
391 
392 static void sdhci_arasan_cqe_enable(struct mmc_host *mmc)
393 {
394 	struct sdhci_host *host = mmc_priv(mmc);
395 	u32 reg;
396 
397 	reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
398 	while (reg & SDHCI_DATA_AVAILABLE) {
399 		sdhci_readl(host, SDHCI_BUFFER);
400 		reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
401 	}
402 
403 	sdhci_cqe_enable(mmc);
404 }
405 
406 static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = {
407 	.enable         = sdhci_arasan_cqe_enable,
408 	.disable        = sdhci_cqe_disable,
409 	.dumpregs       = sdhci_arasan_dumpregs,
410 };
411 
412 static const struct sdhci_ops sdhci_arasan_cqe_ops = {
413 	.set_clock = sdhci_arasan_set_clock,
414 	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
415 	.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
416 	.set_bus_width = sdhci_set_bus_width,
417 	.reset = sdhci_arasan_reset,
418 	.set_uhs_signaling = sdhci_set_uhs_signaling,
419 	.set_power = sdhci_set_power_and_bus_voltage,
420 	.irq = sdhci_arasan_cqhci_irq,
421 };
422 
423 static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
424 	.ops = &sdhci_arasan_cqe_ops,
425 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
426 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
427 			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
428 };
429 
430 #ifdef CONFIG_PM_SLEEP
431 /**
432  * sdhci_arasan_suspend - Suspend method for the driver
433  * @dev:	Address of the device structure
434  *
435  * Put the device in a low power state.
436  *
437  * Return: 0 on success and error value on error
438  */
439 static int sdhci_arasan_suspend(struct device *dev)
440 {
441 	struct sdhci_host *host = dev_get_drvdata(dev);
442 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
443 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
444 	int ret;
445 
446 	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
447 		mmc_retune_needed(host->mmc);
448 
449 	if (sdhci_arasan->has_cqe) {
450 		ret = cqhci_suspend(host->mmc);
451 		if (ret)
452 			return ret;
453 	}
454 
455 	ret = sdhci_suspend_host(host);
456 	if (ret)
457 		return ret;
458 
459 	if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
460 		ret = phy_power_off(sdhci_arasan->phy);
461 		if (ret) {
462 			dev_err(dev, "Cannot power off phy.\n");
463 			sdhci_resume_host(host);
464 			return ret;
465 		}
466 		sdhci_arasan->is_phy_on = false;
467 	}
468 
469 	clk_disable(pltfm_host->clk);
470 	clk_disable(sdhci_arasan->clk_ahb);
471 
472 	return 0;
473 }
474 
475 /**
476  * sdhci_arasan_resume - Resume method for the driver
477  * @dev:	Address of the device structure
478  *
479  * Resume operation after suspend
480  *
481  * Return: 0 on success and error value on error
482  */
483 static int sdhci_arasan_resume(struct device *dev)
484 {
485 	struct sdhci_host *host = dev_get_drvdata(dev);
486 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
487 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
488 	int ret;
489 
490 	ret = clk_enable(sdhci_arasan->clk_ahb);
491 	if (ret) {
492 		dev_err(dev, "Cannot enable AHB clock.\n");
493 		return ret;
494 	}
495 
496 	ret = clk_enable(pltfm_host->clk);
497 	if (ret) {
498 		dev_err(dev, "Cannot enable SD clock.\n");
499 		return ret;
500 	}
501 
502 	if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
503 		ret = phy_power_on(sdhci_arasan->phy);
504 		if (ret) {
505 			dev_err(dev, "Cannot power on phy.\n");
506 			return ret;
507 		}
508 		sdhci_arasan->is_phy_on = true;
509 	}
510 
511 	ret = sdhci_resume_host(host);
512 	if (ret) {
513 		dev_err(dev, "Cannot resume host.\n");
514 		return ret;
515 	}
516 
517 	if (sdhci_arasan->has_cqe)
518 		return cqhci_resume(host->mmc);
519 
520 	return 0;
521 }
522 #endif /* ! CONFIG_PM_SLEEP */
523 
524 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
525 			 sdhci_arasan_resume);
526 
527 /**
528  * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
529  *
530  * @hw:			Pointer to the hardware clock structure.
531  * @parent_rate:		The parent rate (should be rate of clk_xin).
532  *
533  * Return the current actual rate of the SD card clock.  This can be used
534  * to communicate with out PHY.
535  *
536  * Return: The card clock rate.
537  */
538 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
539 						      unsigned long parent_rate)
540 {
541 	struct sdhci_arasan_clk_data *clk_data =
542 		container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
543 	struct sdhci_arasan_data *sdhci_arasan =
544 		container_of(clk_data, struct sdhci_arasan_data, clk_data);
545 	struct sdhci_host *host = sdhci_arasan->host;
546 
547 	return host->mmc->actual_clock;
548 }
549 
550 static const struct clk_ops arasan_sdcardclk_ops = {
551 	.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
552 };
553 
554 /**
555  * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
556  *
557  * @hw:			Pointer to the hardware clock structure.
558  * @parent_rate:		The parent rate (should be rate of clk_xin).
559  *
560  * Return the current actual rate of the sampling clock.  This can be used
561  * to communicate with out PHY.
562  *
563  * Return: The sample clock rate.
564  */
565 static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw,
566 						      unsigned long parent_rate)
567 {
568 	struct sdhci_arasan_clk_data *clk_data =
569 		container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
570 	struct sdhci_arasan_data *sdhci_arasan =
571 		container_of(clk_data, struct sdhci_arasan_data, clk_data);
572 	struct sdhci_host *host = sdhci_arasan->host;
573 
574 	return host->mmc->actual_clock;
575 }
576 
577 static const struct clk_ops arasan_sampleclk_ops = {
578 	.recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
579 };
580 
581 /**
582  * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
583  *
584  * @hw:			Pointer to the hardware clock structure.
585  * @degrees:		The clock phase shift between 0 - 359.
586  *
587  * Set the SD Output Clock Tap Delays for Output path
588  *
589  * Return: 0 on success and error value on error
590  */
591 static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
592 {
593 	struct sdhci_arasan_clk_data *clk_data =
594 		container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
595 	struct sdhci_arasan_data *sdhci_arasan =
596 		container_of(clk_data, struct sdhci_arasan_data, clk_data);
597 	struct sdhci_host *host = sdhci_arasan->host;
598 	const char *clk_name = clk_hw_get_name(hw);
599 	u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
600 	u8 tap_delay, tap_max = 0;
601 	int ret;
602 
603 	/*
604 	 * This is applicable for SDHCI_SPEC_300 and above
605 	 * ZynqMP does not set phase for <=25MHz clock.
606 	 * If degrees is zero, no need to do anything.
607 	 */
608 	if (host->version < SDHCI_SPEC_300 ||
609 	    host->timing == MMC_TIMING_LEGACY ||
610 	    host->timing == MMC_TIMING_UHS_SDR12 || !degrees)
611 		return 0;
612 
613 	switch (host->timing) {
614 	case MMC_TIMING_MMC_HS:
615 	case MMC_TIMING_SD_HS:
616 	case MMC_TIMING_UHS_SDR25:
617 	case MMC_TIMING_UHS_DDR50:
618 	case MMC_TIMING_MMC_DDR52:
619 		/* For 50MHz clock, 30 Taps are available */
620 		tap_max = 30;
621 		break;
622 	case MMC_TIMING_UHS_SDR50:
623 		/* For 100MHz clock, 15 Taps are available */
624 		tap_max = 15;
625 		break;
626 	case MMC_TIMING_UHS_SDR104:
627 	case MMC_TIMING_MMC_HS200:
628 		/* For 200MHz clock, 8 Taps are available */
629 		tap_max = 8;
630 	default:
631 		break;
632 	}
633 
634 	tap_delay = (degrees * tap_max) / 360;
635 
636 	/* Set the Clock Phase */
637 	ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay);
638 	if (ret)
639 		pr_err("Error setting Output Tap Delay\n");
640 
641 	return ret;
642 }
643 
644 static const struct clk_ops zynqmp_sdcardclk_ops = {
645 	.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
646 	.set_phase = sdhci_zynqmp_sdcardclk_set_phase,
647 };
648 
649 /**
650  * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
651  *
652  * @hw:			Pointer to the hardware clock structure.
653  * @degrees:		The clock phase shift between 0 - 359.
654  *
655  * Set the SD Input Clock Tap Delays for Input path
656  *
657  * Return: 0 on success and error value on error
658  */
659 static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees)
660 {
661 	struct sdhci_arasan_clk_data *clk_data =
662 		container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
663 	struct sdhci_arasan_data *sdhci_arasan =
664 		container_of(clk_data, struct sdhci_arasan_data, clk_data);
665 	struct sdhci_host *host = sdhci_arasan->host;
666 	const char *clk_name = clk_hw_get_name(hw);
667 	u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1;
668 	u8 tap_delay, tap_max = 0;
669 	int ret;
670 
671 	/*
672 	 * This is applicable for SDHCI_SPEC_300 and above
673 	 * ZynqMP does not set phase for <=25MHz clock.
674 	 * If degrees is zero, no need to do anything.
675 	 */
676 	if (host->version < SDHCI_SPEC_300 ||
677 	    host->timing == MMC_TIMING_LEGACY ||
678 	    host->timing == MMC_TIMING_UHS_SDR12 || !degrees)
679 		return 0;
680 
681 	switch (host->timing) {
682 	case MMC_TIMING_MMC_HS:
683 	case MMC_TIMING_SD_HS:
684 	case MMC_TIMING_UHS_SDR25:
685 	case MMC_TIMING_UHS_DDR50:
686 	case MMC_TIMING_MMC_DDR52:
687 		/* For 50MHz clock, 120 Taps are available */
688 		tap_max = 120;
689 		break;
690 	case MMC_TIMING_UHS_SDR50:
691 		/* For 100MHz clock, 60 Taps are available */
692 		tap_max = 60;
693 		break;
694 	case MMC_TIMING_UHS_SDR104:
695 	case MMC_TIMING_MMC_HS200:
696 		/* For 200MHz clock, 30 Taps are available */
697 		tap_max = 30;
698 	default:
699 		break;
700 	}
701 
702 	tap_delay = (degrees * tap_max) / 360;
703 
704 	/* Set the Clock Phase */
705 	ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_INPUT, tap_delay);
706 	if (ret)
707 		pr_err("Error setting Input Tap Delay\n");
708 
709 	return ret;
710 }
711 
712 static const struct clk_ops zynqmp_sampleclk_ops = {
713 	.recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
714 	.set_phase = sdhci_zynqmp_sampleclk_set_phase,
715 };
716 
717 /**
718  * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
719  *
720  * @hw:			Pointer to the hardware clock structure.
721  * @degrees:		The clock phase shift between 0 - 359.
722  *
723  * Set the SD Output Clock Tap Delays for Output path
724  *
725  * Return: 0 on success and error value on error
726  */
727 static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
728 {
729 	struct sdhci_arasan_clk_data *clk_data =
730 		container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
731 	struct sdhci_arasan_data *sdhci_arasan =
732 		container_of(clk_data, struct sdhci_arasan_data, clk_data);
733 	struct sdhci_host *host = sdhci_arasan->host;
734 	u8 tap_delay, tap_max = 0;
735 
736 	/*
737 	 * This is applicable for SDHCI_SPEC_300 and above
738 	 * Versal does not set phase for <=25MHz clock.
739 	 * If degrees is zero, no need to do anything.
740 	 */
741 	if (host->version < SDHCI_SPEC_300 ||
742 	    host->timing == MMC_TIMING_LEGACY ||
743 	    host->timing == MMC_TIMING_UHS_SDR12 || !degrees)
744 		return 0;
745 
746 	switch (host->timing) {
747 	case MMC_TIMING_MMC_HS:
748 	case MMC_TIMING_SD_HS:
749 	case MMC_TIMING_UHS_SDR25:
750 	case MMC_TIMING_UHS_DDR50:
751 	case MMC_TIMING_MMC_DDR52:
752 		/* For 50MHz clock, 30 Taps are available */
753 		tap_max = 30;
754 		break;
755 	case MMC_TIMING_UHS_SDR50:
756 		/* For 100MHz clock, 15 Taps are available */
757 		tap_max = 15;
758 		break;
759 	case MMC_TIMING_UHS_SDR104:
760 	case MMC_TIMING_MMC_HS200:
761 		/* For 200MHz clock, 8 Taps are available */
762 		tap_max = 8;
763 	default:
764 		break;
765 	}
766 
767 	tap_delay = (degrees * tap_max) / 360;
768 
769 	/* Set the Clock Phase */
770 	if (tap_delay) {
771 		u32 regval;
772 
773 		regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
774 		regval |= SDHCI_OTAPDLY_ENABLE;
775 		sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
776 		regval |= tap_delay;
777 		sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
778 	}
779 
780 	return 0;
781 }
782 
783 static const struct clk_ops versal_sdcardclk_ops = {
784 	.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
785 	.set_phase = sdhci_versal_sdcardclk_set_phase,
786 };
787 
788 /**
789  * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
790  *
791  * @hw:			Pointer to the hardware clock structure.
792  * @degrees:		The clock phase shift between 0 - 359.
793  *
794  * Set the SD Input Clock Tap Delays for Input path
795  *
796  * Return: 0 on success and error value on error
797  */
798 static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees)
799 {
800 	struct sdhci_arasan_clk_data *clk_data =
801 		container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
802 	struct sdhci_arasan_data *sdhci_arasan =
803 		container_of(clk_data, struct sdhci_arasan_data, clk_data);
804 	struct sdhci_host *host = sdhci_arasan->host;
805 	u8 tap_delay, tap_max = 0;
806 
807 	/*
808 	 * This is applicable for SDHCI_SPEC_300 and above
809 	 * Versal does not set phase for <=25MHz clock.
810 	 * If degrees is zero, no need to do anything.
811 	 */
812 	if (host->version < SDHCI_SPEC_300 ||
813 	    host->timing == MMC_TIMING_LEGACY ||
814 	    host->timing == MMC_TIMING_UHS_SDR12 || !degrees)
815 		return 0;
816 
817 	switch (host->timing) {
818 	case MMC_TIMING_MMC_HS:
819 	case MMC_TIMING_SD_HS:
820 	case MMC_TIMING_UHS_SDR25:
821 	case MMC_TIMING_UHS_DDR50:
822 	case MMC_TIMING_MMC_DDR52:
823 		/* For 50MHz clock, 120 Taps are available */
824 		tap_max = 120;
825 		break;
826 	case MMC_TIMING_UHS_SDR50:
827 		/* For 100MHz clock, 60 Taps are available */
828 		tap_max = 60;
829 		break;
830 	case MMC_TIMING_UHS_SDR104:
831 	case MMC_TIMING_MMC_HS200:
832 		/* For 200MHz clock, 30 Taps are available */
833 		tap_max = 30;
834 	default:
835 		break;
836 	}
837 
838 	tap_delay = (degrees * tap_max) / 360;
839 
840 	/* Set the Clock Phase */
841 	if (tap_delay) {
842 		u32 regval;
843 
844 		regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
845 		regval |= SDHCI_ITAPDLY_CHGWIN;
846 		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
847 		regval |= SDHCI_ITAPDLY_ENABLE;
848 		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
849 		regval |= tap_delay;
850 		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
851 		regval &= ~SDHCI_ITAPDLY_CHGWIN;
852 		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
853 	}
854 
855 	return 0;
856 }
857 
858 static const struct clk_ops versal_sampleclk_ops = {
859 	.recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
860 	.set_phase = sdhci_versal_sampleclk_set_phase,
861 };
862 
863 static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid)
864 {
865 	u16 clk;
866 
867 	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
868 	clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
869 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
870 
871 	/* Issue DLL Reset */
872 	zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE);
873 
874 	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
875 
876 	sdhci_enable_clk(host, clk);
877 }
878 
879 static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode)
880 {
881 	struct sdhci_host *host = mmc_priv(mmc);
882 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
883 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
884 	struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;
885 	const char *clk_name = clk_hw_get_name(hw);
886 	u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 :
887 							   NODE_SD_1;
888 	int err;
889 
890 	arasan_zynqmp_dll_reset(host, device_id);
891 
892 	err = sdhci_execute_tuning(mmc, opcode);
893 	if (err)
894 		return err;
895 
896 	arasan_zynqmp_dll_reset(host, device_id);
897 
898 	return 0;
899 }
900 
901 /**
902  * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
903  *
904  * @host:		The sdhci_host
905  * @value:		The value to write
906  *
907  * The corecfg_clockmultiplier is supposed to contain clock multiplier
908  * value of programmable clock generator.
909  *
910  * NOTES:
911  * - Many existing devices don't seem to do this and work fine.  To keep
912  *   compatibility for old hardware where the device tree doesn't provide a
913  *   register map, this function is a noop if a soc_ctl_map hasn't been provided
914  *   for this platform.
915  * - The value of corecfg_clockmultiplier should sync with that of corresponding
916  *   value reading from sdhci_capability_register. So this function is called
917  *   once at probe time and never called again.
918  */
919 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
920 						u32 value)
921 {
922 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
923 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
924 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
925 		sdhci_arasan->soc_ctl_map;
926 
927 	/* Having a map is optional */
928 	if (!soc_ctl_map)
929 		return;
930 
931 	/* If we have a map, we expect to have a syscon */
932 	if (!sdhci_arasan->soc_ctl_base) {
933 		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
934 			mmc_hostname(host->mmc));
935 		return;
936 	}
937 
938 	sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
939 }
940 
941 /**
942  * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
943  *
944  * @host:		The sdhci_host
945  *
946  * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin.  This
947  * function can be used to make that happen.
948  *
949  * NOTES:
950  * - Many existing devices don't seem to do this and work fine.  To keep
951  *   compatibility for old hardware where the device tree doesn't provide a
952  *   register map, this function is a noop if a soc_ctl_map hasn't been provided
953  *   for this platform.
954  * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
955  *   to achieve lower clock rates.  That means that this function is called once
956  *   at probe time and never called again.
957  */
958 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
959 {
960 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
961 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
962 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
963 		sdhci_arasan->soc_ctl_map;
964 	u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);
965 
966 	/* Having a map is optional */
967 	if (!soc_ctl_map)
968 		return;
969 
970 	/* If we have a map, we expect to have a syscon */
971 	if (!sdhci_arasan->soc_ctl_base) {
972 		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
973 			mmc_hostname(host->mmc));
974 		return;
975 	}
976 
977 	sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
978 }
979 
980 static void sdhci_arasan_set_clk_delays(struct sdhci_host *host)
981 {
982 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
983 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
984 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
985 
986 	clk_set_phase(clk_data->sampleclk,
987 		      clk_data->clk_phase_in[host->timing]);
988 	clk_set_phase(clk_data->sdcardclk,
989 		      clk_data->clk_phase_out[host->timing]);
990 }
991 
992 static void arasan_dt_read_clk_phase(struct device *dev,
993 				     struct sdhci_arasan_clk_data *clk_data,
994 				     unsigned int timing, const char *prop)
995 {
996 	struct device_node *np = dev->of_node;
997 
998 	int clk_phase[2] = {0};
999 
1000 	/*
1001 	 * Read Tap Delay values from DT, if the DT does not contain the
1002 	 * Tap Values then use the pre-defined values.
1003 	 */
1004 	if (of_property_read_variable_u32_array(np, prop, &clk_phase[0],
1005 						2, 0)) {
1006 		dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
1007 			prop, clk_data->clk_phase_in[timing],
1008 			clk_data->clk_phase_out[timing]);
1009 		return;
1010 	}
1011 
1012 	/* The values read are Input and Output Clock Delays in order */
1013 	clk_data->clk_phase_in[timing] = clk_phase[0];
1014 	clk_data->clk_phase_out[timing] = clk_phase[1];
1015 }
1016 
1017 /**
1018  * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
1019  *
1020  * @dev:		Pointer to our struct device.
1021  * @clk_data:		Pointer to the Clock Data structure
1022  *
1023  * Called at initialization to parse the values of Clock Delays.
1024  */
1025 static void arasan_dt_parse_clk_phases(struct device *dev,
1026 				       struct sdhci_arasan_clk_data *clk_data)
1027 {
1028 	u32 mio_bank = 0;
1029 	int i;
1030 
1031 	/*
1032 	 * This has been kept as a pointer and is assigned a function here.
1033 	 * So that different controller variants can assign their own handling
1034 	 * function.
1035 	 */
1036 	clk_data->set_clk_delays = sdhci_arasan_set_clk_delays;
1037 
1038 	if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {
1039 		u32 zynqmp_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1040 			ZYNQMP_ICLK_PHASE;
1041 		u32 zynqmp_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1042 			ZYNQMP_OCLK_PHASE;
1043 
1044 		of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank);
1045 		if (mio_bank == 2) {
1046 			zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90;
1047 			zynqmp_oclk_phase[MMC_TIMING_MMC_HS200] = 90;
1048 		}
1049 
1050 		for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1051 			clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i];
1052 			clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i];
1053 		}
1054 	}
1055 
1056 	if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) {
1057 		u32 versal_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1058 			VERSAL_ICLK_PHASE;
1059 		u32 versal_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1060 			VERSAL_OCLK_PHASE;
1061 
1062 		for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1063 			clk_data->clk_phase_in[i] = versal_iclk_phase[i];
1064 			clk_data->clk_phase_out[i] = versal_oclk_phase[i];
1065 		}
1066 	}
1067 
1068 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY,
1069 				 "clk-phase-legacy");
1070 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS,
1071 				 "clk-phase-mmc-hs");
1072 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS,
1073 				 "clk-phase-sd-hs");
1074 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12,
1075 				 "clk-phase-uhs-sdr12");
1076 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25,
1077 				 "clk-phase-uhs-sdr25");
1078 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50,
1079 				 "clk-phase-uhs-sdr50");
1080 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104,
1081 				 "clk-phase-uhs-sdr104");
1082 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50,
1083 				 "clk-phase-uhs-ddr50");
1084 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52,
1085 				 "clk-phase-mmc-ddr52");
1086 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200,
1087 				 "clk-phase-mmc-hs200");
1088 	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400,
1089 				 "clk-phase-mmc-hs400");
1090 }
1091 
1092 static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
1093 	.ops = &sdhci_arasan_ops,
1094 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1095 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1096 			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1097 			SDHCI_QUIRK2_STOP_WITH_TC,
1098 };
1099 
1100 static const struct sdhci_arasan_clk_ops arasan_clk_ops = {
1101 	.sdcardclk_ops = &arasan_sdcardclk_ops,
1102 	.sampleclk_ops = &arasan_sampleclk_ops,
1103 };
1104 
1105 static struct sdhci_arasan_of_data sdhci_arasan_generic_data = {
1106 	.pdata = &sdhci_arasan_pdata,
1107 	.clk_ops = &arasan_clk_ops,
1108 };
1109 
1110 static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
1111 	.ops = &sdhci_arasan_cqe_ops,
1112 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1113 		SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1114 		SDHCI_QUIRK_NO_LED |
1115 		SDHCI_QUIRK_32BIT_DMA_ADDR |
1116 		SDHCI_QUIRK_32BIT_DMA_SIZE |
1117 		SDHCI_QUIRK_32BIT_ADMA_SIZE,
1118 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1119 		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1120 		SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1121 		SDHCI_QUIRK2_STOP_WITH_TC |
1122 		SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1123 };
1124 
1125 static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = {
1126 	.ops = &sdhci_arasan_ops,
1127 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1128 		SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1129 		SDHCI_QUIRK_NO_LED |
1130 		SDHCI_QUIRK_32BIT_DMA_ADDR |
1131 		SDHCI_QUIRK_32BIT_DMA_SIZE |
1132 		SDHCI_QUIRK_32BIT_ADMA_SIZE,
1133 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1134 		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1135 		SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1136 		SDHCI_QUIRK2_STOP_WITH_TC |
1137 		SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1138 };
1139 
1140 static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = {
1141 	.ops = &sdhci_arasan_ops,
1142 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1143 		SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1144 		SDHCI_QUIRK_NO_LED |
1145 		SDHCI_QUIRK_32BIT_DMA_ADDR |
1146 		SDHCI_QUIRK_32BIT_DMA_SIZE |
1147 		SDHCI_QUIRK_32BIT_ADMA_SIZE,
1148 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1149 		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1150 		SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1151 		SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1152 };
1153 
1154 static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
1155 	.soc_ctl_map = &rk3399_soc_ctl_map,
1156 	.pdata = &sdhci_arasan_cqe_pdata,
1157 	.clk_ops = &arasan_clk_ops,
1158 };
1159 
1160 static struct sdhci_arasan_of_data intel_lgm_emmc_data = {
1161 	.soc_ctl_map = &intel_lgm_emmc_soc_ctl_map,
1162 	.pdata = &sdhci_arasan_cqe_pdata,
1163 	.clk_ops = &arasan_clk_ops,
1164 };
1165 
1166 static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
1167 	.soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map,
1168 	.pdata = &sdhci_arasan_cqe_pdata,
1169 	.clk_ops = &arasan_clk_ops,
1170 };
1171 
1172 static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = {
1173 	.ops = &sdhci_arasan_ops,
1174 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1175 			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1176 			SDHCI_QUIRK2_STOP_WITH_TC,
1177 };
1178 
1179 static const struct sdhci_arasan_clk_ops zynqmp_clk_ops = {
1180 	.sdcardclk_ops = &zynqmp_sdcardclk_ops,
1181 	.sampleclk_ops = &zynqmp_sampleclk_ops,
1182 };
1183 
1184 static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = {
1185 	.pdata = &sdhci_arasan_zynqmp_pdata,
1186 	.clk_ops = &zynqmp_clk_ops,
1187 };
1188 
1189 static const struct sdhci_arasan_clk_ops versal_clk_ops = {
1190 	.sdcardclk_ops = &versal_sdcardclk_ops,
1191 	.sampleclk_ops = &versal_sampleclk_ops,
1192 };
1193 
1194 static struct sdhci_arasan_of_data sdhci_arasan_versal_data = {
1195 	.pdata = &sdhci_arasan_zynqmp_pdata,
1196 	.clk_ops = &versal_clk_ops,
1197 };
1198 
1199 static struct sdhci_arasan_of_data intel_keembay_emmc_data = {
1200 	.soc_ctl_map = &intel_keembay_soc_ctl_map,
1201 	.pdata = &sdhci_keembay_emmc_pdata,
1202 };
1203 
1204 static struct sdhci_arasan_of_data intel_keembay_sd_data = {
1205 	.soc_ctl_map = &intel_keembay_soc_ctl_map,
1206 	.pdata = &sdhci_keembay_sd_pdata,
1207 };
1208 
1209 static struct sdhci_arasan_of_data intel_keembay_sdio_data = {
1210 	.soc_ctl_map = &intel_keembay_soc_ctl_map,
1211 	.pdata = &sdhci_keembay_sdio_pdata,
1212 };
1213 
1214 static const struct of_device_id sdhci_arasan_of_match[] = {
1215 	/* SoC-specific compatible strings w/ soc_ctl_map */
1216 	{
1217 		.compatible = "rockchip,rk3399-sdhci-5.1",
1218 		.data = &sdhci_arasan_rk3399_data,
1219 	},
1220 	{
1221 		.compatible = "intel,lgm-sdhci-5.1-emmc",
1222 		.data = &intel_lgm_emmc_data,
1223 	},
1224 	{
1225 		.compatible = "intel,lgm-sdhci-5.1-sdxc",
1226 		.data = &intel_lgm_sdxc_data,
1227 	},
1228 	{
1229 		.compatible = "intel,keembay-sdhci-5.1-emmc",
1230 		.data = &intel_keembay_emmc_data,
1231 	},
1232 	{
1233 		.compatible = "intel,keembay-sdhci-5.1-sd",
1234 		.data = &intel_keembay_sd_data,
1235 	},
1236 	{
1237 		.compatible = "intel,keembay-sdhci-5.1-sdio",
1238 		.data = &intel_keembay_sdio_data,
1239 	},
1240 	/* Generic compatible below here */
1241 	{
1242 		.compatible = "arasan,sdhci-8.9a",
1243 		.data = &sdhci_arasan_generic_data,
1244 	},
1245 	{
1246 		.compatible = "arasan,sdhci-5.1",
1247 		.data = &sdhci_arasan_generic_data,
1248 	},
1249 	{
1250 		.compatible = "arasan,sdhci-4.9a",
1251 		.data = &sdhci_arasan_generic_data,
1252 	},
1253 	{
1254 		.compatible = "xlnx,zynqmp-8.9a",
1255 		.data = &sdhci_arasan_zynqmp_data,
1256 	},
1257 	{
1258 		.compatible = "xlnx,versal-8.9a",
1259 		.data = &sdhci_arasan_versal_data,
1260 	},
1261 	{ /* sentinel */ }
1262 };
1263 MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
1264 
1265 /**
1266  * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
1267  *
1268  * @sdhci_arasan:	Our private data structure.
1269  * @clk_xin:		Pointer to the functional clock
1270  * @dev:		Pointer to our struct device.
1271  *
1272  * Some PHY devices need to know what the actual card clock is.  In order for
1273  * them to find out, we'll provide a clock through the common clock framework
1274  * for them to query.
1275  *
1276  * Return: 0 on success and error value on error
1277  */
1278 static int
1279 sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan,
1280 				struct clk *clk_xin,
1281 				struct device *dev)
1282 {
1283 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1284 	struct device_node *np = dev->of_node;
1285 	struct clk_init_data sdcardclk_init;
1286 	const char *parent_clk_name;
1287 	int ret;
1288 
1289 	ret = of_property_read_string_index(np, "clock-output-names", 0,
1290 					    &sdcardclk_init.name);
1291 	if (ret) {
1292 		dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1293 		return ret;
1294 	}
1295 
1296 	parent_clk_name = __clk_get_name(clk_xin);
1297 	sdcardclk_init.parent_names = &parent_clk_name;
1298 	sdcardclk_init.num_parents = 1;
1299 	sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
1300 	sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops;
1301 
1302 	clk_data->sdcardclk_hw.init = &sdcardclk_init;
1303 	clk_data->sdcardclk =
1304 		devm_clk_register(dev, &clk_data->sdcardclk_hw);
1305 	if (IS_ERR(clk_data->sdcardclk))
1306 		return PTR_ERR(clk_data->sdcardclk);
1307 	clk_data->sdcardclk_hw.init = NULL;
1308 
1309 	ret = of_clk_add_provider(np, of_clk_src_simple_get,
1310 				  clk_data->sdcardclk);
1311 	if (ret)
1312 		dev_err(dev, "Failed to add sdcard clock provider\n");
1313 
1314 	return ret;
1315 }
1316 
1317 /**
1318  * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
1319  *
1320  * @sdhci_arasan:	Our private data structure.
1321  * @clk_xin:		Pointer to the functional clock
1322  * @dev:		Pointer to our struct device.
1323  *
1324  * Some PHY devices need to know what the actual card clock is.  In order for
1325  * them to find out, we'll provide a clock through the common clock framework
1326  * for them to query.
1327  *
1328  * Return: 0 on success and error value on error
1329  */
1330 static int
1331 sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan,
1332 				struct clk *clk_xin,
1333 				struct device *dev)
1334 {
1335 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1336 	struct device_node *np = dev->of_node;
1337 	struct clk_init_data sampleclk_init;
1338 	const char *parent_clk_name;
1339 	int ret;
1340 
1341 	ret = of_property_read_string_index(np, "clock-output-names", 1,
1342 					    &sampleclk_init.name);
1343 	if (ret) {
1344 		dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1345 		return ret;
1346 	}
1347 
1348 	parent_clk_name = __clk_get_name(clk_xin);
1349 	sampleclk_init.parent_names = &parent_clk_name;
1350 	sampleclk_init.num_parents = 1;
1351 	sampleclk_init.flags = CLK_GET_RATE_NOCACHE;
1352 	sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops;
1353 
1354 	clk_data->sampleclk_hw.init = &sampleclk_init;
1355 	clk_data->sampleclk =
1356 		devm_clk_register(dev, &clk_data->sampleclk_hw);
1357 	if (IS_ERR(clk_data->sampleclk))
1358 		return PTR_ERR(clk_data->sampleclk);
1359 	clk_data->sampleclk_hw.init = NULL;
1360 
1361 	ret = of_clk_add_provider(np, of_clk_src_simple_get,
1362 				  clk_data->sampleclk);
1363 	if (ret)
1364 		dev_err(dev, "Failed to add sample clock provider\n");
1365 
1366 	return ret;
1367 }
1368 
1369 /**
1370  * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
1371  *
1372  * @dev:		Pointer to our struct device.
1373  *
1374  * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
1375  * returned success.
1376  */
1377 static void sdhci_arasan_unregister_sdclk(struct device *dev)
1378 {
1379 	struct device_node *np = dev->of_node;
1380 
1381 	if (!of_find_property(np, "#clock-cells", NULL))
1382 		return;
1383 
1384 	of_clk_del_provider(dev->of_node);
1385 }
1386 
1387 /**
1388  * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
1389  *
1390  * This should be set based on the System Address Bus.
1391  * 0: the Core supports only 32-bit System Address Bus.
1392  * 1: the Core supports 64-bit System Address Bus.
1393  *
1394  * NOTES:
1395  * - For Keem Bay, it is required to clear this bit. Its default value is 1'b1.
1396  *   Keem Bay does not support 64-bit access.
1397  *
1398  * @host:		The sdhci_host
1399  * @value:		The value to write
1400  */
1401 static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value)
1402 {
1403 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1404 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1405 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
1406 		sdhci_arasan->soc_ctl_map;
1407 
1408 	/* Having a map is optional */
1409 	if (!soc_ctl_map)
1410 		return;
1411 
1412 	/* If we have a map, we expect to have a syscon */
1413 	if (!sdhci_arasan->soc_ctl_base) {
1414 		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
1415 			mmc_hostname(host->mmc));
1416 		return;
1417 	}
1418 
1419 	sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value);
1420 }
1421 
1422 /**
1423  * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
1424  *
1425  * @sdhci_arasan:	Our private data structure.
1426  * @clk_xin:		Pointer to the functional clock
1427  * @dev:		Pointer to our struct device.
1428  *
1429  * Some PHY devices need to know what the actual card clock is.  In order for
1430  * them to find out, we'll provide a clock through the common clock framework
1431  * for them to query.
1432  *
1433  * Note: without seriously re-architecting SDHCI's clock code and testing on
1434  * all platforms, there's no way to create a totally beautiful clock here
1435  * with all clock ops implemented.  Instead, we'll just create a clock that can
1436  * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
1437  * framework that we're doing things behind its back.  This should be sufficient
1438  * to create nice clean device tree bindings and later (if needed) we can try
1439  * re-architecting SDHCI if we see some benefit to it.
1440  *
1441  * Return: 0 on success and error value on error
1442  */
1443 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
1444 				       struct clk *clk_xin,
1445 				       struct device *dev)
1446 {
1447 	struct device_node *np = dev->of_node;
1448 	u32 num_clks = 0;
1449 	int ret;
1450 
1451 	/* Providing a clock to the PHY is optional; no error if missing */
1452 	if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
1453 		return 0;
1454 
1455 	ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev);
1456 	if (ret)
1457 		return ret;
1458 
1459 	if (num_clks) {
1460 		ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin,
1461 						      dev);
1462 		if (ret) {
1463 			sdhci_arasan_unregister_sdclk(dev);
1464 			return ret;
1465 		}
1466 	}
1467 
1468 	return 0;
1469 }
1470 
1471 static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
1472 {
1473 	struct sdhci_host *host = sdhci_arasan->host;
1474 	struct cqhci_host *cq_host;
1475 	bool dma64;
1476 	int ret;
1477 
1478 	if (!sdhci_arasan->has_cqe)
1479 		return sdhci_add_host(host);
1480 
1481 	ret = sdhci_setup_host(host);
1482 	if (ret)
1483 		return ret;
1484 
1485 	cq_host = devm_kzalloc(host->mmc->parent,
1486 			       sizeof(*cq_host), GFP_KERNEL);
1487 	if (!cq_host) {
1488 		ret = -ENOMEM;
1489 		goto cleanup;
1490 	}
1491 
1492 	cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
1493 	cq_host->ops = &sdhci_arasan_cqhci_ops;
1494 
1495 	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1496 	if (dma64)
1497 		cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1498 
1499 	ret = cqhci_init(cq_host, host->mmc, dma64);
1500 	if (ret)
1501 		goto cleanup;
1502 
1503 	ret = __sdhci_add_host(host);
1504 	if (ret)
1505 		goto cleanup;
1506 
1507 	return 0;
1508 
1509 cleanup:
1510 	sdhci_cleanup_host(host);
1511 	return ret;
1512 }
1513 
1514 static int sdhci_arasan_probe(struct platform_device *pdev)
1515 {
1516 	int ret;
1517 	const struct of_device_id *match;
1518 	struct device_node *node;
1519 	struct clk *clk_xin;
1520 	struct sdhci_host *host;
1521 	struct sdhci_pltfm_host *pltfm_host;
1522 	struct sdhci_arasan_data *sdhci_arasan;
1523 	struct device_node *np = pdev->dev.of_node;
1524 	const struct sdhci_arasan_of_data *data;
1525 
1526 	match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node);
1527 	data = match->data;
1528 	host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan));
1529 
1530 	if (IS_ERR(host))
1531 		return PTR_ERR(host);
1532 
1533 	pltfm_host = sdhci_priv(host);
1534 	sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1535 	sdhci_arasan->host = host;
1536 
1537 	sdhci_arasan->soc_ctl_map = data->soc_ctl_map;
1538 	sdhci_arasan->clk_ops = data->clk_ops;
1539 
1540 	node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0);
1541 	if (node) {
1542 		sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
1543 		of_node_put(node);
1544 
1545 		if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
1546 			ret = PTR_ERR(sdhci_arasan->soc_ctl_base);
1547 			if (ret != -EPROBE_DEFER)
1548 				dev_err(&pdev->dev, "Can't get syscon: %d\n",
1549 					ret);
1550 			goto err_pltfm_free;
1551 		}
1552 	}
1553 
1554 	sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
1555 	if (IS_ERR(sdhci_arasan->clk_ahb)) {
1556 		dev_err(&pdev->dev, "clk_ahb clock not found.\n");
1557 		ret = PTR_ERR(sdhci_arasan->clk_ahb);
1558 		goto err_pltfm_free;
1559 	}
1560 
1561 	clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
1562 	if (IS_ERR(clk_xin)) {
1563 		dev_err(&pdev->dev, "clk_xin clock not found.\n");
1564 		ret = PTR_ERR(clk_xin);
1565 		goto err_pltfm_free;
1566 	}
1567 
1568 	ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
1569 	if (ret) {
1570 		dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
1571 		goto err_pltfm_free;
1572 	}
1573 
1574 	ret = clk_prepare_enable(clk_xin);
1575 	if (ret) {
1576 		dev_err(&pdev->dev, "Unable to enable SD clock.\n");
1577 		goto clk_dis_ahb;
1578 	}
1579 
1580 	sdhci_get_of_property(pdev);
1581 
1582 	if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
1583 		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
1584 
1585 	if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))
1586 		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE;
1587 
1588 	pltfm_host->clk = clk_xin;
1589 
1590 	if (of_device_is_compatible(pdev->dev.of_node,
1591 				    "rockchip,rk3399-sdhci-5.1"))
1592 		sdhci_arasan_update_clockmultiplier(host, 0x0);
1593 
1594 	if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
1595 	    of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
1596 	    of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {
1597 		sdhci_arasan_update_clockmultiplier(host, 0x0);
1598 		sdhci_arasan_update_support64b(host, 0x0);
1599 
1600 		host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1601 	}
1602 
1603 	sdhci_arasan_update_baseclkfreq(host);
1604 
1605 	ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
1606 	if (ret)
1607 		goto clk_disable_all;
1608 
1609 	if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {
1610 		host->mmc_host_ops.execute_tuning =
1611 			arasan_zynqmp_execute_tuning;
1612 	}
1613 
1614 	arasan_dt_parse_clk_phases(&pdev->dev, &sdhci_arasan->clk_data);
1615 
1616 	ret = mmc_of_parse(host->mmc);
1617 	if (ret) {
1618 		if (ret != -EPROBE_DEFER)
1619 			dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret);
1620 		goto unreg_clk;
1621 	}
1622 
1623 	sdhci_arasan->phy = ERR_PTR(-ENODEV);
1624 	if (of_device_is_compatible(pdev->dev.of_node,
1625 				    "arasan,sdhci-5.1")) {
1626 		sdhci_arasan->phy = devm_phy_get(&pdev->dev,
1627 						 "phy_arasan");
1628 		if (IS_ERR(sdhci_arasan->phy)) {
1629 			ret = PTR_ERR(sdhci_arasan->phy);
1630 			dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");
1631 			goto unreg_clk;
1632 		}
1633 
1634 		ret = phy_init(sdhci_arasan->phy);
1635 		if (ret < 0) {
1636 			dev_err(&pdev->dev, "phy_init err.\n");
1637 			goto unreg_clk;
1638 		}
1639 
1640 		host->mmc_host_ops.hs400_enhanced_strobe =
1641 					sdhci_arasan_hs400_enhanced_strobe;
1642 		host->mmc_host_ops.start_signal_voltage_switch =
1643 					sdhci_arasan_voltage_switch;
1644 		sdhci_arasan->has_cqe = true;
1645 		host->mmc->caps2 |= MMC_CAP2_CQE;
1646 
1647 		if (!of_property_read_bool(np, "disable-cqe-dcmd"))
1648 			host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
1649 	}
1650 
1651 	ret = sdhci_arasan_add_host(sdhci_arasan);
1652 	if (ret)
1653 		goto err_add_host;
1654 
1655 	return 0;
1656 
1657 err_add_host:
1658 	if (!IS_ERR(sdhci_arasan->phy))
1659 		phy_exit(sdhci_arasan->phy);
1660 unreg_clk:
1661 	sdhci_arasan_unregister_sdclk(&pdev->dev);
1662 clk_disable_all:
1663 	clk_disable_unprepare(clk_xin);
1664 clk_dis_ahb:
1665 	clk_disable_unprepare(sdhci_arasan->clk_ahb);
1666 err_pltfm_free:
1667 	sdhci_pltfm_free(pdev);
1668 	return ret;
1669 }
1670 
1671 static int sdhci_arasan_remove(struct platform_device *pdev)
1672 {
1673 	int ret;
1674 	struct sdhci_host *host = platform_get_drvdata(pdev);
1675 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1676 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1677 	struct clk *clk_ahb = sdhci_arasan->clk_ahb;
1678 
1679 	if (!IS_ERR(sdhci_arasan->phy)) {
1680 		if (sdhci_arasan->is_phy_on)
1681 			phy_power_off(sdhci_arasan->phy);
1682 		phy_exit(sdhci_arasan->phy);
1683 	}
1684 
1685 	sdhci_arasan_unregister_sdclk(&pdev->dev);
1686 
1687 	ret = sdhci_pltfm_unregister(pdev);
1688 
1689 	clk_disable_unprepare(clk_ahb);
1690 
1691 	return ret;
1692 }
1693 
1694 static struct platform_driver sdhci_arasan_driver = {
1695 	.driver = {
1696 		.name = "sdhci-arasan",
1697 		.of_match_table = sdhci_arasan_of_match,
1698 		.pm = &sdhci_arasan_dev_pm_ops,
1699 	},
1700 	.probe = sdhci_arasan_probe,
1701 	.remove = sdhci_arasan_remove,
1702 };
1703 
1704 module_platform_driver(sdhci_arasan_driver);
1705 
1706 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
1707 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
1708 MODULE_LICENSE("GPL");
1709