12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2e3ec3a3dSSoren Brinkmann /* 3e3ec3a3dSSoren Brinkmann * Arasan Secure Digital Host Controller Interface. 4e3ec3a3dSSoren Brinkmann * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu> 5e3ec3a3dSSoren Brinkmann * Copyright (c) 2012 Wind River Systems, Inc. 6e3ec3a3dSSoren Brinkmann * Copyright (C) 2013 Pengutronix e.K. 7e3ec3a3dSSoren Brinkmann * Copyright (C) 2013 Xilinx Inc. 8e3ec3a3dSSoren Brinkmann * 9e3ec3a3dSSoren Brinkmann * Based on sdhci-of-esdhc.c 10e3ec3a3dSSoren Brinkmann * 11e3ec3a3dSSoren Brinkmann * Copyright (c) 2007 Freescale Semiconductor, Inc. 12e3ec3a3dSSoren Brinkmann * Copyright (c) 2009 MontaVista Software, Inc. 13e3ec3a3dSSoren Brinkmann * 14e3ec3a3dSSoren Brinkmann * Authors: Xiaobo Xie <X.Xie@freescale.com> 15e3ec3a3dSSoren Brinkmann * Anton Vorontsov <avorontsov@ru.mvista.com> 16e3ec3a3dSSoren Brinkmann */ 17e3ec3a3dSSoren Brinkmann 18c390f211SDouglas Anderson #include <linux/clk-provider.h> 193ea4666eSDouglas Anderson #include <linux/mfd/syscon.h> 20e3ec3a3dSSoren Brinkmann #include <linux/module.h> 21308f3f8dSSuman Tripathi #include <linux/of_device.h> 2291aa3661SShawn Lin #include <linux/phy/phy.h> 233ea4666eSDouglas Anderson #include <linux/regmap.h> 243794c542SZach Brown #include <linux/of.h> 25e3ec3a3dSSoren Brinkmann 2684362d79SShawn Lin #include "cqhci.h" 2784362d79SShawn Lin #include "sdhci-pltfm.h" 28e3ec3a3dSSoren Brinkmann 2984362d79SShawn Lin #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 3084362d79SShawn Lin #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 31a05c8465SShawn Lin #define VENDOR_ENHANCED_STROBE BIT(0) 32e3ec3a3dSSoren Brinkmann 33b2db9c67SDouglas Anderson #define PHY_CLK_TOO_SLOW_HZ 400000 34b2db9c67SDouglas Anderson 353ea4666eSDouglas Anderson /* 363ea4666eSDouglas Anderson * On some SoCs the syscon area has a feature where the upper 16-bits of 373ea4666eSDouglas Anderson * each 32-bit register act as a write mask for the lower 16-bits. This allows 383ea4666eSDouglas Anderson * atomic updates of the register without locking. This macro is used on SoCs 393ea4666eSDouglas Anderson * that have that feature. 403ea4666eSDouglas Anderson */ 413ea4666eSDouglas Anderson #define HIWORD_UPDATE(val, mask, shift) \ 423ea4666eSDouglas Anderson ((val) << (shift) | (mask) << ((shift) + 16)) 433ea4666eSDouglas Anderson 443ea4666eSDouglas Anderson /** 453ea4666eSDouglas Anderson * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map 463ea4666eSDouglas Anderson * 473ea4666eSDouglas Anderson * @reg: Offset within the syscon of the register containing this field 483ea4666eSDouglas Anderson * @width: Number of bits for this field 493ea4666eSDouglas Anderson * @shift: Bit offset within @reg of this field (or -1 if not avail) 503ea4666eSDouglas Anderson */ 513ea4666eSDouglas Anderson struct sdhci_arasan_soc_ctl_field { 523ea4666eSDouglas Anderson u32 reg; 533ea4666eSDouglas Anderson u16 width; 543ea4666eSDouglas Anderson s16 shift; 553ea4666eSDouglas Anderson }; 563ea4666eSDouglas Anderson 573ea4666eSDouglas Anderson /** 583ea4666eSDouglas Anderson * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers 593ea4666eSDouglas Anderson * 603ea4666eSDouglas Anderson * It's up to the licensee of the Arsan IP block to make these available 613ea4666eSDouglas Anderson * somewhere if needed. Presumably these will be scattered somewhere that's 623ea4666eSDouglas Anderson * accessible via the syscon API. 633ea4666eSDouglas Anderson * 643ea4666eSDouglas Anderson * @baseclkfreq: Where to find corecfg_baseclkfreq 65b2ca77c9SShawn Lin * @clockmultiplier: Where to find corecfg_clockmultiplier 663ea4666eSDouglas Anderson * @hiword_update: If true, use HIWORD_UPDATE to access the syscon 673ea4666eSDouglas Anderson */ 683ea4666eSDouglas Anderson struct sdhci_arasan_soc_ctl_map { 693ea4666eSDouglas Anderson struct sdhci_arasan_soc_ctl_field baseclkfreq; 70b2ca77c9SShawn Lin struct sdhci_arasan_soc_ctl_field clockmultiplier; 713ea4666eSDouglas Anderson bool hiword_update; 723ea4666eSDouglas Anderson }; 733ea4666eSDouglas Anderson 74e3ec3a3dSSoren Brinkmann /** 75e1463618SManish Narani * struct sdhci_arasan_clk_data 76e1463618SManish Narani * @sdcardclk_hw: Struct for the clock we might provide to a PHY. 77e1463618SManish Narani * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. 78e1463618SManish Narani */ 79e1463618SManish Narani struct sdhci_arasan_clk_data { 80e1463618SManish Narani struct clk_hw sdcardclk_hw; 81e1463618SManish Narani struct clk *sdcardclk; 82e1463618SManish Narani }; 83e1463618SManish Narani 84e1463618SManish Narani /** 85e3ec3a3dSSoren Brinkmann * struct sdhci_arasan_data 86c390f211SDouglas Anderson * @host: Pointer to the main SDHCI host structure. 87e3ec3a3dSSoren Brinkmann * @clk_ahb: Pointer to the AHB clock 8891aa3661SShawn Lin * @phy: Pointer to the generic phy 89b2db9c67SDouglas Anderson * @is_phy_on: True if the PHY is on; false if not. 90e1463618SManish Narani * @clk_data: Struct for the Arasan Controller Clock Data. 913ea4666eSDouglas Anderson * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. 923ea4666eSDouglas Anderson * @soc_ctl_map: Map to get offsets into soc_ctl registers. 93e3ec3a3dSSoren Brinkmann */ 94e3ec3a3dSSoren Brinkmann struct sdhci_arasan_data { 95c390f211SDouglas Anderson struct sdhci_host *host; 96e3ec3a3dSSoren Brinkmann struct clk *clk_ahb; 9791aa3661SShawn Lin struct phy *phy; 98b2db9c67SDouglas Anderson bool is_phy_on; 993ea4666eSDouglas Anderson 10084362d79SShawn Lin bool has_cqe; 101e1463618SManish Narani struct sdhci_arasan_clk_data clk_data; 102c390f211SDouglas Anderson 1033ea4666eSDouglas Anderson struct regmap *soc_ctl_base; 1043ea4666eSDouglas Anderson const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; 1053794c542SZach Brown unsigned int quirks; /* Arasan deviations from spec */ 1063794c542SZach Brown 1073794c542SZach Brown /* Controller does not have CD wired and will not function normally without */ 1083794c542SZach Brown #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0) 1093f2c7d5dSHelmut Grohne /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the 1103f2c7d5dSHelmut Grohne * internal clock even when the clock isn't stable */ 1113f2c7d5dSHelmut Grohne #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1) 112e3ec3a3dSSoren Brinkmann }; 113e3ec3a3dSSoren Brinkmann 11406b23ca0SFaiz Abbas struct sdhci_arasan_of_data { 11506b23ca0SFaiz Abbas const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; 11606b23ca0SFaiz Abbas const struct sdhci_pltfm_data *pdata; 11706b23ca0SFaiz Abbas }; 11806b23ca0SFaiz Abbas 1193ea4666eSDouglas Anderson static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = { 1203ea4666eSDouglas Anderson .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 }, 121b2ca77c9SShawn Lin .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0}, 1223ea4666eSDouglas Anderson .hiword_update = true, 1233ea4666eSDouglas Anderson }; 1243ea4666eSDouglas Anderson 1255c1a4f40SRamuthevar Vadivel Muruganx static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = { 1265c1a4f40SRamuthevar Vadivel Muruganx .baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 }, 1275c1a4f40SRamuthevar Vadivel Muruganx .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 }, 1285c1a4f40SRamuthevar Vadivel Muruganx .hiword_update = false, 1295c1a4f40SRamuthevar Vadivel Muruganx }; 1305c1a4f40SRamuthevar Vadivel Muruganx 131d1807ad6SRamuthevar Vadivel Murugan static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = { 132d1807ad6SRamuthevar Vadivel Murugan .baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 }, 133d1807ad6SRamuthevar Vadivel Murugan .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 }, 134d1807ad6SRamuthevar Vadivel Murugan .hiword_update = false, 135d1807ad6SRamuthevar Vadivel Murugan }; 136d1807ad6SRamuthevar Vadivel Murugan 1373ea4666eSDouglas Anderson /** 1383ea4666eSDouglas Anderson * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers 1393ea4666eSDouglas Anderson * 1403ea4666eSDouglas Anderson * This function allows writing to fields in sdhci_arasan_soc_ctl_map. 1413ea4666eSDouglas Anderson * Note that if a field is specified as not available (shift < 0) then 1423ea4666eSDouglas Anderson * this function will silently return an error code. It will be noisy 1433ea4666eSDouglas Anderson * and print errors for any other (unexpected) errors. 1443ea4666eSDouglas Anderson * 1453ea4666eSDouglas Anderson * @host: The sdhci_host 1463ea4666eSDouglas Anderson * @fld: The field to write to 1473ea4666eSDouglas Anderson * @val: The value to write 1483ea4666eSDouglas Anderson */ 1493ea4666eSDouglas Anderson static int sdhci_arasan_syscon_write(struct sdhci_host *host, 1503ea4666eSDouglas Anderson const struct sdhci_arasan_soc_ctl_field *fld, 1513ea4666eSDouglas Anderson u32 val) 1523ea4666eSDouglas Anderson { 1533ea4666eSDouglas Anderson struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1543ea4666eSDouglas Anderson struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 1553ea4666eSDouglas Anderson struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; 1563ea4666eSDouglas Anderson u32 reg = fld->reg; 1573ea4666eSDouglas Anderson u16 width = fld->width; 1583ea4666eSDouglas Anderson s16 shift = fld->shift; 1593ea4666eSDouglas Anderson int ret; 1603ea4666eSDouglas Anderson 1613ea4666eSDouglas Anderson /* 1623ea4666eSDouglas Anderson * Silently return errors for shift < 0 so caller doesn't have 1633ea4666eSDouglas Anderson * to check for fields which are optional. For fields that 1643ea4666eSDouglas Anderson * are required then caller needs to do something special 1653ea4666eSDouglas Anderson * anyway. 1663ea4666eSDouglas Anderson */ 1673ea4666eSDouglas Anderson if (shift < 0) 1683ea4666eSDouglas Anderson return -EINVAL; 1693ea4666eSDouglas Anderson 1703ea4666eSDouglas Anderson if (sdhci_arasan->soc_ctl_map->hiword_update) 1713ea4666eSDouglas Anderson ret = regmap_write(soc_ctl_base, reg, 1723ea4666eSDouglas Anderson HIWORD_UPDATE(val, GENMASK(width, 0), 1733ea4666eSDouglas Anderson shift)); 1743ea4666eSDouglas Anderson else 1753ea4666eSDouglas Anderson ret = regmap_update_bits(soc_ctl_base, reg, 1763ea4666eSDouglas Anderson GENMASK(shift + width, shift), 1773ea4666eSDouglas Anderson val << shift); 1783ea4666eSDouglas Anderson 1793ea4666eSDouglas Anderson /* Yell about (unexpected) regmap errors */ 1803ea4666eSDouglas Anderson if (ret) 1813ea4666eSDouglas Anderson pr_warn("%s: Regmap write fail: %d\n", 1823ea4666eSDouglas Anderson mmc_hostname(host->mmc), ret); 1833ea4666eSDouglas Anderson 1843ea4666eSDouglas Anderson return ret; 1853ea4666eSDouglas Anderson } 1863ea4666eSDouglas Anderson 187802ac39aSShawn Lin static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) 188802ac39aSShawn Lin { 189802ac39aSShawn Lin struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 190802ac39aSShawn Lin struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 1916fc09244SDouglas Anderson bool ctrl_phy = false; 192802ac39aSShawn Lin 193b2db9c67SDouglas Anderson if (!IS_ERR(sdhci_arasan->phy)) { 194b2db9c67SDouglas Anderson if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) { 195b2db9c67SDouglas Anderson /* 196b2db9c67SDouglas Anderson * If PHY off, set clock to max speed and power PHY on. 197b2db9c67SDouglas Anderson * 198b2db9c67SDouglas Anderson * Although PHY docs apparently suggest power cycling 199b2db9c67SDouglas Anderson * when changing the clock the PHY doesn't like to be 200b2db9c67SDouglas Anderson * powered on while at low speeds like those used in ID 201b2db9c67SDouglas Anderson * mode. Even worse is powering the PHY on while the 202b2db9c67SDouglas Anderson * clock is off. 203b2db9c67SDouglas Anderson * 204b2db9c67SDouglas Anderson * To workaround the PHY limitations, the best we can 205b2db9c67SDouglas Anderson * do is to power it on at a faster speed and then slam 206b2db9c67SDouglas Anderson * through low speeds without power cycling. 207b2db9c67SDouglas Anderson */ 208b2db9c67SDouglas Anderson sdhci_set_clock(host, host->max_clk); 209b2db9c67SDouglas Anderson phy_power_on(sdhci_arasan->phy); 210b2db9c67SDouglas Anderson sdhci_arasan->is_phy_on = true; 211802ac39aSShawn Lin 212b2db9c67SDouglas Anderson /* 213b2db9c67SDouglas Anderson * We'll now fall through to the below case with 214b2db9c67SDouglas Anderson * ctrl_phy = false (so we won't turn off/on). The 215b2db9c67SDouglas Anderson * sdhci_set_clock() will set the real clock. 216b2db9c67SDouglas Anderson */ 217b2db9c67SDouglas Anderson } else if (clock > PHY_CLK_TOO_SLOW_HZ) { 218b2db9c67SDouglas Anderson /* 219b2db9c67SDouglas Anderson * At higher clock speeds the PHY is fine being power 220b2db9c67SDouglas Anderson * cycled and docs say you _should_ power cycle when 221b2db9c67SDouglas Anderson * changing clock speeds. 222b2db9c67SDouglas Anderson */ 223b2db9c67SDouglas Anderson ctrl_phy = true; 224b2db9c67SDouglas Anderson } 225b2db9c67SDouglas Anderson } 226b2db9c67SDouglas Anderson 227b2db9c67SDouglas Anderson if (ctrl_phy && sdhci_arasan->is_phy_on) { 228802ac39aSShawn Lin phy_power_off(sdhci_arasan->phy); 229b2db9c67SDouglas Anderson sdhci_arasan->is_phy_on = false; 230802ac39aSShawn Lin } 231802ac39aSShawn Lin 232802ac39aSShawn Lin sdhci_set_clock(host, clock); 233802ac39aSShawn Lin 2343f2c7d5dSHelmut Grohne if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE) 2353f2c7d5dSHelmut Grohne /* 2363f2c7d5dSHelmut Grohne * Some controllers immediately report SDHCI_CLOCK_INT_STABLE 2373f2c7d5dSHelmut Grohne * after enabling the clock even though the clock is not 2383f2c7d5dSHelmut Grohne * stable. Trying to use a clock without waiting here results 2393f2c7d5dSHelmut Grohne * in EILSEQ while detecting some older/slower cards. The 2403f2c7d5dSHelmut Grohne * chosen delay is the maximum delay from sdhci_set_clock. 2413f2c7d5dSHelmut Grohne */ 2423f2c7d5dSHelmut Grohne msleep(20); 2433f2c7d5dSHelmut Grohne 2446fc09244SDouglas Anderson if (ctrl_phy) { 245802ac39aSShawn Lin phy_power_on(sdhci_arasan->phy); 246b2db9c67SDouglas Anderson sdhci_arasan->is_phy_on = true; 247802ac39aSShawn Lin } 248802ac39aSShawn Lin } 249802ac39aSShawn Lin 250a05c8465SShawn Lin static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc, 251a05c8465SShawn Lin struct mmc_ios *ios) 252a05c8465SShawn Lin { 253a05c8465SShawn Lin u32 vendor; 254a05c8465SShawn Lin struct sdhci_host *host = mmc_priv(mmc); 255a05c8465SShawn Lin 2560daf72feSJean-Francois Dagenais vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER); 257a05c8465SShawn Lin if (ios->enhanced_strobe) 258a05c8465SShawn Lin vendor |= VENDOR_ENHANCED_STROBE; 259a05c8465SShawn Lin else 260a05c8465SShawn Lin vendor &= ~VENDOR_ENHANCED_STROBE; 261a05c8465SShawn Lin 2620daf72feSJean-Francois Dagenais sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER); 263a05c8465SShawn Lin } 264a05c8465SShawn Lin 26513d62fd2SWei Yongjun static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) 2663794c542SZach Brown { 2673794c542SZach Brown u8 ctrl; 2683794c542SZach Brown struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 2693794c542SZach Brown struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 2703794c542SZach Brown 2713794c542SZach Brown sdhci_reset(host, mask); 2723794c542SZach Brown 2733794c542SZach Brown if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { 2743794c542SZach Brown ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 2753794c542SZach Brown ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 2763794c542SZach Brown sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2773794c542SZach Brown } 2783794c542SZach Brown } 2793794c542SZach Brown 2808a3bee9bSShawn Lin static int sdhci_arasan_voltage_switch(struct mmc_host *mmc, 2818a3bee9bSShawn Lin struct mmc_ios *ios) 2828a3bee9bSShawn Lin { 2838a3bee9bSShawn Lin switch (ios->signal_voltage) { 2848a3bee9bSShawn Lin case MMC_SIGNAL_VOLTAGE_180: 2858a3bee9bSShawn Lin /* 2868a3bee9bSShawn Lin * Plese don't switch to 1V8 as arasan,5.1 doesn't 2878a3bee9bSShawn Lin * actually refer to this setting to indicate the 2888a3bee9bSShawn Lin * signal voltage and the state machine will be broken 2898a3bee9bSShawn Lin * actually if we force to enable 1V8. That's something 2908a3bee9bSShawn Lin * like broken quirk but we could work around here. 2918a3bee9bSShawn Lin */ 2928a3bee9bSShawn Lin return 0; 2938a3bee9bSShawn Lin case MMC_SIGNAL_VOLTAGE_330: 2948a3bee9bSShawn Lin case MMC_SIGNAL_VOLTAGE_120: 2958a3bee9bSShawn Lin /* We don't support 3V3 and 1V2 */ 2968a3bee9bSShawn Lin break; 2978a3bee9bSShawn Lin } 2988a3bee9bSShawn Lin 2998a3bee9bSShawn Lin return -EINVAL; 3008a3bee9bSShawn Lin } 3018a3bee9bSShawn Lin 302043f2dcaSMilan Stevanovic static void sdhci_arasan_set_power(struct sdhci_host *host, unsigned char mode, 303043f2dcaSMilan Stevanovic unsigned short vdd) 304043f2dcaSMilan Stevanovic { 305043f2dcaSMilan Stevanovic if (!IS_ERR(host->mmc->supply.vmmc)) { 306043f2dcaSMilan Stevanovic struct mmc_host *mmc = host->mmc; 307043f2dcaSMilan Stevanovic 308043f2dcaSMilan Stevanovic mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 309043f2dcaSMilan Stevanovic } 310043f2dcaSMilan Stevanovic sdhci_set_power_noreg(host, mode, vdd); 311043f2dcaSMilan Stevanovic } 312043f2dcaSMilan Stevanovic 313a81dae3aSJulia Lawall static const struct sdhci_ops sdhci_arasan_ops = { 314802ac39aSShawn Lin .set_clock = sdhci_arasan_set_clock, 315e3ec3a3dSSoren Brinkmann .get_max_clock = sdhci_pltfm_clk_get_max_clock, 3168cc35289SShawn Lin .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 3172317f56cSRussell King .set_bus_width = sdhci_set_bus_width, 3183794c542SZach Brown .reset = sdhci_arasan_reset, 31996d7b78cSRussell King .set_uhs_signaling = sdhci_set_uhs_signaling, 320043f2dcaSMilan Stevanovic .set_power = sdhci_arasan_set_power, 321e3ec3a3dSSoren Brinkmann }; 322e3ec3a3dSSoren Brinkmann 323a81dae3aSJulia Lawall static const struct sdhci_pltfm_data sdhci_arasan_pdata = { 324e3ec3a3dSSoren Brinkmann .ops = &sdhci_arasan_ops, 3252d532d45SSuneel Garapati .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 3262d532d45SSuneel Garapati .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 32757aac337SPhil Edworthy SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | 32857aac337SPhil Edworthy SDHCI_QUIRK2_STOP_WITH_TC, 329e3ec3a3dSSoren Brinkmann }; 330e3ec3a3dSSoren Brinkmann 33106b23ca0SFaiz Abbas static struct sdhci_arasan_of_data sdhci_arasan_data = { 33206b23ca0SFaiz Abbas .pdata = &sdhci_arasan_pdata, 33306b23ca0SFaiz Abbas }; 33406b23ca0SFaiz Abbas 33584362d79SShawn Lin static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask) 33684362d79SShawn Lin { 33784362d79SShawn Lin int cmd_error = 0; 33884362d79SShawn Lin int data_error = 0; 33984362d79SShawn Lin 34084362d79SShawn Lin if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 34184362d79SShawn Lin return intmask; 34284362d79SShawn Lin 34384362d79SShawn Lin cqhci_irq(host->mmc, intmask, cmd_error, data_error); 34484362d79SShawn Lin 34584362d79SShawn Lin return 0; 34684362d79SShawn Lin } 34784362d79SShawn Lin 34884362d79SShawn Lin static void sdhci_arasan_dumpregs(struct mmc_host *mmc) 34984362d79SShawn Lin { 35084362d79SShawn Lin sdhci_dumpregs(mmc_priv(mmc)); 35184362d79SShawn Lin } 35284362d79SShawn Lin 35384362d79SShawn Lin static void sdhci_arasan_cqe_enable(struct mmc_host *mmc) 35484362d79SShawn Lin { 35584362d79SShawn Lin struct sdhci_host *host = mmc_priv(mmc); 35684362d79SShawn Lin u32 reg; 35784362d79SShawn Lin 35884362d79SShawn Lin reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 35984362d79SShawn Lin while (reg & SDHCI_DATA_AVAILABLE) { 36084362d79SShawn Lin sdhci_readl(host, SDHCI_BUFFER); 36184362d79SShawn Lin reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 36284362d79SShawn Lin } 36384362d79SShawn Lin 36484362d79SShawn Lin sdhci_cqe_enable(mmc); 36584362d79SShawn Lin } 36684362d79SShawn Lin 36784362d79SShawn Lin static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = { 36884362d79SShawn Lin .enable = sdhci_arasan_cqe_enable, 36984362d79SShawn Lin .disable = sdhci_cqe_disable, 37084362d79SShawn Lin .dumpregs = sdhci_arasan_dumpregs, 37184362d79SShawn Lin }; 37284362d79SShawn Lin 37384362d79SShawn Lin static const struct sdhci_ops sdhci_arasan_cqe_ops = { 37484362d79SShawn Lin .set_clock = sdhci_arasan_set_clock, 37584362d79SShawn Lin .get_max_clock = sdhci_pltfm_clk_get_max_clock, 37684362d79SShawn Lin .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 37784362d79SShawn Lin .set_bus_width = sdhci_set_bus_width, 37884362d79SShawn Lin .reset = sdhci_arasan_reset, 37984362d79SShawn Lin .set_uhs_signaling = sdhci_set_uhs_signaling, 38084362d79SShawn Lin .set_power = sdhci_arasan_set_power, 38184362d79SShawn Lin .irq = sdhci_arasan_cqhci_irq, 38284362d79SShawn Lin }; 38384362d79SShawn Lin 38484362d79SShawn Lin static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = { 38584362d79SShawn Lin .ops = &sdhci_arasan_cqe_ops, 38684362d79SShawn Lin .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 38784362d79SShawn Lin .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 38884362d79SShawn Lin SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 38984362d79SShawn Lin }; 39084362d79SShawn Lin 39106b23ca0SFaiz Abbas static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = { 39206b23ca0SFaiz Abbas .soc_ctl_map = &rk3399_soc_ctl_map, 39306b23ca0SFaiz Abbas .pdata = &sdhci_arasan_cqe_pdata, 39406b23ca0SFaiz Abbas }; 39506b23ca0SFaiz Abbas 3965c1a4f40SRamuthevar Vadivel Muruganx static struct sdhci_arasan_of_data intel_lgm_emmc_data = { 3975c1a4f40SRamuthevar Vadivel Muruganx .soc_ctl_map = &intel_lgm_emmc_soc_ctl_map, 3985c1a4f40SRamuthevar Vadivel Muruganx .pdata = &sdhci_arasan_cqe_pdata, 3995c1a4f40SRamuthevar Vadivel Muruganx }; 4005c1a4f40SRamuthevar Vadivel Muruganx 401d1807ad6SRamuthevar Vadivel Murugan static struct sdhci_arasan_of_data intel_lgm_sdxc_data = { 402d1807ad6SRamuthevar Vadivel Murugan .soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map, 403d1807ad6SRamuthevar Vadivel Murugan .pdata = &sdhci_arasan_cqe_pdata, 404d1807ad6SRamuthevar Vadivel Murugan }; 405d1807ad6SRamuthevar Vadivel Murugan 406e3ec3a3dSSoren Brinkmann #ifdef CONFIG_PM_SLEEP 407e3ec3a3dSSoren Brinkmann /** 408e3ec3a3dSSoren Brinkmann * sdhci_arasan_suspend - Suspend method for the driver 409e3ec3a3dSSoren Brinkmann * @dev: Address of the device structure 410e3ec3a3dSSoren Brinkmann * Returns 0 on success and error value on error 411e3ec3a3dSSoren Brinkmann * 412e3ec3a3dSSoren Brinkmann * Put the device in a low power state. 413e3ec3a3dSSoren Brinkmann */ 414e3ec3a3dSSoren Brinkmann static int sdhci_arasan_suspend(struct device *dev) 415e3ec3a3dSSoren Brinkmann { 416970f2d90SWolfram Sang struct sdhci_host *host = dev_get_drvdata(dev); 417e3ec3a3dSSoren Brinkmann struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 41889211418SJisheng Zhang struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 419e3ec3a3dSSoren Brinkmann int ret; 420e3ec3a3dSSoren Brinkmann 421d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 422d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 423d38dcad4SAdrian Hunter 42484362d79SShawn Lin if (sdhci_arasan->has_cqe) { 42584362d79SShawn Lin ret = cqhci_suspend(host->mmc); 42684362d79SShawn Lin if (ret) 42784362d79SShawn Lin return ret; 42884362d79SShawn Lin } 42984362d79SShawn Lin 430e3ec3a3dSSoren Brinkmann ret = sdhci_suspend_host(host); 431e3ec3a3dSSoren Brinkmann if (ret) 432e3ec3a3dSSoren Brinkmann return ret; 433e3ec3a3dSSoren Brinkmann 434b2db9c67SDouglas Anderson if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) { 43591aa3661SShawn Lin ret = phy_power_off(sdhci_arasan->phy); 43691aa3661SShawn Lin if (ret) { 43791aa3661SShawn Lin dev_err(dev, "Cannot power off phy.\n"); 43891aa3661SShawn Lin sdhci_resume_host(host); 43991aa3661SShawn Lin return ret; 44091aa3661SShawn Lin } 441b2db9c67SDouglas Anderson sdhci_arasan->is_phy_on = false; 44291aa3661SShawn Lin } 44391aa3661SShawn Lin 444e3ec3a3dSSoren Brinkmann clk_disable(pltfm_host->clk); 445e3ec3a3dSSoren Brinkmann clk_disable(sdhci_arasan->clk_ahb); 446e3ec3a3dSSoren Brinkmann 447e3ec3a3dSSoren Brinkmann return 0; 448e3ec3a3dSSoren Brinkmann } 449e3ec3a3dSSoren Brinkmann 450e3ec3a3dSSoren Brinkmann /** 451e3ec3a3dSSoren Brinkmann * sdhci_arasan_resume - Resume method for the driver 452e3ec3a3dSSoren Brinkmann * @dev: Address of the device structure 453e3ec3a3dSSoren Brinkmann * Returns 0 on success and error value on error 454e3ec3a3dSSoren Brinkmann * 455e3ec3a3dSSoren Brinkmann * Resume operation after suspend 456e3ec3a3dSSoren Brinkmann */ 457e3ec3a3dSSoren Brinkmann static int sdhci_arasan_resume(struct device *dev) 458e3ec3a3dSSoren Brinkmann { 459970f2d90SWolfram Sang struct sdhci_host *host = dev_get_drvdata(dev); 460e3ec3a3dSSoren Brinkmann struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 46189211418SJisheng Zhang struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 462e3ec3a3dSSoren Brinkmann int ret; 463e3ec3a3dSSoren Brinkmann 464e3ec3a3dSSoren Brinkmann ret = clk_enable(sdhci_arasan->clk_ahb); 465e3ec3a3dSSoren Brinkmann if (ret) { 466e3ec3a3dSSoren Brinkmann dev_err(dev, "Cannot enable AHB clock.\n"); 467e3ec3a3dSSoren Brinkmann return ret; 468e3ec3a3dSSoren Brinkmann } 469e3ec3a3dSSoren Brinkmann 470e3ec3a3dSSoren Brinkmann ret = clk_enable(pltfm_host->clk); 471e3ec3a3dSSoren Brinkmann if (ret) { 472e3ec3a3dSSoren Brinkmann dev_err(dev, "Cannot enable SD clock.\n"); 473e3ec3a3dSSoren Brinkmann return ret; 474e3ec3a3dSSoren Brinkmann } 475e3ec3a3dSSoren Brinkmann 476b2db9c67SDouglas Anderson if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) { 47791aa3661SShawn Lin ret = phy_power_on(sdhci_arasan->phy); 47891aa3661SShawn Lin if (ret) { 47991aa3661SShawn Lin dev_err(dev, "Cannot power on phy.\n"); 48091aa3661SShawn Lin return ret; 48191aa3661SShawn Lin } 482b2db9c67SDouglas Anderson sdhci_arasan->is_phy_on = true; 48391aa3661SShawn Lin } 48491aa3661SShawn Lin 48584362d79SShawn Lin ret = sdhci_resume_host(host); 48684362d79SShawn Lin if (ret) { 48784362d79SShawn Lin dev_err(dev, "Cannot resume host.\n"); 48884362d79SShawn Lin return ret; 48984362d79SShawn Lin } 49084362d79SShawn Lin 49184362d79SShawn Lin if (sdhci_arasan->has_cqe) 49284362d79SShawn Lin return cqhci_resume(host->mmc); 49384362d79SShawn Lin 49484362d79SShawn Lin return 0; 495e3ec3a3dSSoren Brinkmann } 496e3ec3a3dSSoren Brinkmann #endif /* ! CONFIG_PM_SLEEP */ 497e3ec3a3dSSoren Brinkmann 498e3ec3a3dSSoren Brinkmann static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend, 499e3ec3a3dSSoren Brinkmann sdhci_arasan_resume); 500e3ec3a3dSSoren Brinkmann 5013ea4666eSDouglas Anderson static const struct of_device_id sdhci_arasan_of_match[] = { 5023ea4666eSDouglas Anderson /* SoC-specific compatible strings w/ soc_ctl_map */ 5033ea4666eSDouglas Anderson { 5043ea4666eSDouglas Anderson .compatible = "rockchip,rk3399-sdhci-5.1", 50506b23ca0SFaiz Abbas .data = &sdhci_arasan_rk3399_data, 5063ea4666eSDouglas Anderson }, 5075c1a4f40SRamuthevar Vadivel Muruganx { 5085c1a4f40SRamuthevar Vadivel Muruganx .compatible = "intel,lgm-sdhci-5.1-emmc", 5095c1a4f40SRamuthevar Vadivel Muruganx .data = &intel_lgm_emmc_data, 5105c1a4f40SRamuthevar Vadivel Muruganx }, 511d1807ad6SRamuthevar Vadivel Murugan { 512d1807ad6SRamuthevar Vadivel Murugan .compatible = "intel,lgm-sdhci-5.1-sdxc", 513d1807ad6SRamuthevar Vadivel Murugan .data = &intel_lgm_sdxc_data, 514d1807ad6SRamuthevar Vadivel Murugan }, 5153ea4666eSDouglas Anderson /* Generic compatible below here */ 51606b23ca0SFaiz Abbas { 51706b23ca0SFaiz Abbas .compatible = "arasan,sdhci-8.9a", 51806b23ca0SFaiz Abbas .data = &sdhci_arasan_data, 51906b23ca0SFaiz Abbas }, 52006b23ca0SFaiz Abbas { 52106b23ca0SFaiz Abbas .compatible = "arasan,sdhci-5.1", 52206b23ca0SFaiz Abbas .data = &sdhci_arasan_data, 52306b23ca0SFaiz Abbas }, 52406b23ca0SFaiz Abbas { 52506b23ca0SFaiz Abbas .compatible = "arasan,sdhci-4.9a", 52606b23ca0SFaiz Abbas .data = &sdhci_arasan_data, 52706b23ca0SFaiz Abbas }, 5283ea4666eSDouglas Anderson { /* sentinel */ } 5293ea4666eSDouglas Anderson }; 5303ea4666eSDouglas Anderson MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); 5313ea4666eSDouglas Anderson 5323ea4666eSDouglas Anderson /** 533c390f211SDouglas Anderson * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate 534c390f211SDouglas Anderson * 535c390f211SDouglas Anderson * Return the current actual rate of the SD card clock. This can be used 536c390f211SDouglas Anderson * to communicate with out PHY. 537c390f211SDouglas Anderson * 538c390f211SDouglas Anderson * @hw: Pointer to the hardware clock structure. 539c390f211SDouglas Anderson * @parent_rate The parent rate (should be rate of clk_xin). 540c390f211SDouglas Anderson * Returns the card clock rate. 541c390f211SDouglas Anderson */ 542c390f211SDouglas Anderson static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw, 543c390f211SDouglas Anderson unsigned long parent_rate) 544c390f211SDouglas Anderson 545c390f211SDouglas Anderson { 546e1463618SManish Narani struct sdhci_arasan_clk_data *clk_data = 547e1463618SManish Narani container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw); 548c390f211SDouglas Anderson struct sdhci_arasan_data *sdhci_arasan = 549e1463618SManish Narani container_of(clk_data, struct sdhci_arasan_data, clk_data); 550c390f211SDouglas Anderson struct sdhci_host *host = sdhci_arasan->host; 551c390f211SDouglas Anderson 552c390f211SDouglas Anderson return host->mmc->actual_clock; 553c390f211SDouglas Anderson } 554c390f211SDouglas Anderson 555c390f211SDouglas Anderson static const struct clk_ops arasan_sdcardclk_ops = { 556c390f211SDouglas Anderson .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, 557c390f211SDouglas Anderson }; 558c390f211SDouglas Anderson 559c390f211SDouglas Anderson /** 560b2ca77c9SShawn Lin * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier 561b2ca77c9SShawn Lin * 562b2ca77c9SShawn Lin * The corecfg_clockmultiplier is supposed to contain clock multiplier 563b2ca77c9SShawn Lin * value of programmable clock generator. 564b2ca77c9SShawn Lin * 565b2ca77c9SShawn Lin * NOTES: 566b2ca77c9SShawn Lin * - Many existing devices don't seem to do this and work fine. To keep 567b2ca77c9SShawn Lin * compatibility for old hardware where the device tree doesn't provide a 568b2ca77c9SShawn Lin * register map, this function is a noop if a soc_ctl_map hasn't been provided 569b2ca77c9SShawn Lin * for this platform. 570b2ca77c9SShawn Lin * - The value of corecfg_clockmultiplier should sync with that of corresponding 571b2ca77c9SShawn Lin * value reading from sdhci_capability_register. So this function is called 572b2ca77c9SShawn Lin * once at probe time and never called again. 573b2ca77c9SShawn Lin * 574b2ca77c9SShawn Lin * @host: The sdhci_host 575b2ca77c9SShawn Lin */ 576b2ca77c9SShawn Lin static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host, 577b2ca77c9SShawn Lin u32 value) 578b2ca77c9SShawn Lin { 579b2ca77c9SShawn Lin struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 580b2ca77c9SShawn Lin struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 581b2ca77c9SShawn Lin const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = 582b2ca77c9SShawn Lin sdhci_arasan->soc_ctl_map; 583b2ca77c9SShawn Lin 584b2ca77c9SShawn Lin /* Having a map is optional */ 585b2ca77c9SShawn Lin if (!soc_ctl_map) 586b2ca77c9SShawn Lin return; 587b2ca77c9SShawn Lin 588b2ca77c9SShawn Lin /* If we have a map, we expect to have a syscon */ 589b2ca77c9SShawn Lin if (!sdhci_arasan->soc_ctl_base) { 590b2ca77c9SShawn Lin pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", 591b2ca77c9SShawn Lin mmc_hostname(host->mmc)); 592b2ca77c9SShawn Lin return; 593b2ca77c9SShawn Lin } 594b2ca77c9SShawn Lin 595b2ca77c9SShawn Lin sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value); 596b2ca77c9SShawn Lin } 597b2ca77c9SShawn Lin 598b2ca77c9SShawn Lin /** 5993ea4666eSDouglas Anderson * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq 6003ea4666eSDouglas Anderson * 6013ea4666eSDouglas Anderson * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This 6023ea4666eSDouglas Anderson * function can be used to make that happen. 6033ea4666eSDouglas Anderson * 6043ea4666eSDouglas Anderson * NOTES: 6053ea4666eSDouglas Anderson * - Many existing devices don't seem to do this and work fine. To keep 6063ea4666eSDouglas Anderson * compatibility for old hardware where the device tree doesn't provide a 6073ea4666eSDouglas Anderson * register map, this function is a noop if a soc_ctl_map hasn't been provided 6083ea4666eSDouglas Anderson * for this platform. 6093ea4666eSDouglas Anderson * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider 6103ea4666eSDouglas Anderson * to achieve lower clock rates. That means that this function is called once 6113ea4666eSDouglas Anderson * at probe time and never called again. 6123ea4666eSDouglas Anderson * 6133ea4666eSDouglas Anderson * @host: The sdhci_host 6143ea4666eSDouglas Anderson */ 6153ea4666eSDouglas Anderson static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) 6163ea4666eSDouglas Anderson { 6173ea4666eSDouglas Anderson struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 6183ea4666eSDouglas Anderson struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 6193ea4666eSDouglas Anderson const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = 6203ea4666eSDouglas Anderson sdhci_arasan->soc_ctl_map; 6213ea4666eSDouglas Anderson u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000); 6223ea4666eSDouglas Anderson 6233ea4666eSDouglas Anderson /* Having a map is optional */ 6243ea4666eSDouglas Anderson if (!soc_ctl_map) 6253ea4666eSDouglas Anderson return; 6263ea4666eSDouglas Anderson 6273ea4666eSDouglas Anderson /* If we have a map, we expect to have a syscon */ 6283ea4666eSDouglas Anderson if (!sdhci_arasan->soc_ctl_base) { 6293ea4666eSDouglas Anderson pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", 6303ea4666eSDouglas Anderson mmc_hostname(host->mmc)); 6313ea4666eSDouglas Anderson return; 6323ea4666eSDouglas Anderson } 6333ea4666eSDouglas Anderson 6343ea4666eSDouglas Anderson sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); 6353ea4666eSDouglas Anderson } 6363ea4666eSDouglas Anderson 637c390f211SDouglas Anderson /** 638c390f211SDouglas Anderson * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use 639c390f211SDouglas Anderson * 640c390f211SDouglas Anderson * Some PHY devices need to know what the actual card clock is. In order for 641c390f211SDouglas Anderson * them to find out, we'll provide a clock through the common clock framework 642c390f211SDouglas Anderson * for them to query. 643c390f211SDouglas Anderson * 644c390f211SDouglas Anderson * Note: without seriously re-architecting SDHCI's clock code and testing on 645c390f211SDouglas Anderson * all platforms, there's no way to create a totally beautiful clock here 646c390f211SDouglas Anderson * with all clock ops implemented. Instead, we'll just create a clock that can 647c390f211SDouglas Anderson * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock 648c390f211SDouglas Anderson * framework that we're doing things behind its back. This should be sufficient 649c390f211SDouglas Anderson * to create nice clean device tree bindings and later (if needed) we can try 650c390f211SDouglas Anderson * re-architecting SDHCI if we see some benefit to it. 651c390f211SDouglas Anderson * 652c390f211SDouglas Anderson * @sdhci_arasan: Our private data structure. 653c390f211SDouglas Anderson * @clk_xin: Pointer to the functional clock 654c390f211SDouglas Anderson * @dev: Pointer to our struct device. 655c390f211SDouglas Anderson * Returns 0 on success and error value on error 656c390f211SDouglas Anderson */ 657c390f211SDouglas Anderson static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, 658c390f211SDouglas Anderson struct clk *clk_xin, 659c390f211SDouglas Anderson struct device *dev) 660c390f211SDouglas Anderson { 661e1463618SManish Narani struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; 662c390f211SDouglas Anderson struct device_node *np = dev->of_node; 663c390f211SDouglas Anderson struct clk_init_data sdcardclk_init; 664c390f211SDouglas Anderson const char *parent_clk_name; 665c390f211SDouglas Anderson int ret; 666c390f211SDouglas Anderson 667c390f211SDouglas Anderson /* Providing a clock to the PHY is optional; no error if missing */ 668c390f211SDouglas Anderson if (!of_find_property(np, "#clock-cells", NULL)) 669c390f211SDouglas Anderson return 0; 670c390f211SDouglas Anderson 671c390f211SDouglas Anderson ret = of_property_read_string_index(np, "clock-output-names", 0, 672c390f211SDouglas Anderson &sdcardclk_init.name); 673c390f211SDouglas Anderson if (ret) { 674c390f211SDouglas Anderson dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); 675c390f211SDouglas Anderson return ret; 676c390f211SDouglas Anderson } 677c390f211SDouglas Anderson 678c390f211SDouglas Anderson parent_clk_name = __clk_get_name(clk_xin); 679c390f211SDouglas Anderson sdcardclk_init.parent_names = &parent_clk_name; 680c390f211SDouglas Anderson sdcardclk_init.num_parents = 1; 681c390f211SDouglas Anderson sdcardclk_init.flags = CLK_GET_RATE_NOCACHE; 682c390f211SDouglas Anderson sdcardclk_init.ops = &arasan_sdcardclk_ops; 683c390f211SDouglas Anderson 684e1463618SManish Narani clk_data->sdcardclk_hw.init = &sdcardclk_init; 685e1463618SManish Narani clk_data->sdcardclk = 686e1463618SManish Narani devm_clk_register(dev, &clk_data->sdcardclk_hw); 687e1463618SManish Narani clk_data->sdcardclk_hw.init = NULL; 688c390f211SDouglas Anderson 689c390f211SDouglas Anderson ret = of_clk_add_provider(np, of_clk_src_simple_get, 690e1463618SManish Narani clk_data->sdcardclk); 691c390f211SDouglas Anderson if (ret) 692c390f211SDouglas Anderson dev_err(dev, "Failed to add clock provider\n"); 693c390f211SDouglas Anderson 694c390f211SDouglas Anderson return ret; 695c390f211SDouglas Anderson } 696c390f211SDouglas Anderson 697c390f211SDouglas Anderson /** 698c390f211SDouglas Anderson * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk() 699c390f211SDouglas Anderson * 700c390f211SDouglas Anderson * Should be called any time we're exiting and sdhci_arasan_register_sdclk() 701c390f211SDouglas Anderson * returned success. 702c390f211SDouglas Anderson * 703c390f211SDouglas Anderson * @dev: Pointer to our struct device. 704c390f211SDouglas Anderson */ 705c390f211SDouglas Anderson static void sdhci_arasan_unregister_sdclk(struct device *dev) 706c390f211SDouglas Anderson { 707c390f211SDouglas Anderson struct device_node *np = dev->of_node; 708c390f211SDouglas Anderson 709c390f211SDouglas Anderson if (!of_find_property(np, "#clock-cells", NULL)) 710c390f211SDouglas Anderson return; 711c390f211SDouglas Anderson 712c390f211SDouglas Anderson of_clk_del_provider(dev->of_node); 713c390f211SDouglas Anderson } 714c390f211SDouglas Anderson 71584362d79SShawn Lin static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan) 71684362d79SShawn Lin { 71784362d79SShawn Lin struct sdhci_host *host = sdhci_arasan->host; 71884362d79SShawn Lin struct cqhci_host *cq_host; 71984362d79SShawn Lin bool dma64; 72084362d79SShawn Lin int ret; 72184362d79SShawn Lin 72284362d79SShawn Lin if (!sdhci_arasan->has_cqe) 72384362d79SShawn Lin return sdhci_add_host(host); 72484362d79SShawn Lin 72584362d79SShawn Lin ret = sdhci_setup_host(host); 72684362d79SShawn Lin if (ret) 72784362d79SShawn Lin return ret; 72884362d79SShawn Lin 72984362d79SShawn Lin cq_host = devm_kzalloc(host->mmc->parent, 73084362d79SShawn Lin sizeof(*cq_host), GFP_KERNEL); 73184362d79SShawn Lin if (!cq_host) { 73284362d79SShawn Lin ret = -ENOMEM; 73384362d79SShawn Lin goto cleanup; 73484362d79SShawn Lin } 73584362d79SShawn Lin 73684362d79SShawn Lin cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; 73784362d79SShawn Lin cq_host->ops = &sdhci_arasan_cqhci_ops; 73884362d79SShawn Lin 73984362d79SShawn Lin dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 74084362d79SShawn Lin if (dma64) 74184362d79SShawn Lin cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 74284362d79SShawn Lin 74384362d79SShawn Lin ret = cqhci_init(cq_host, host->mmc, dma64); 74484362d79SShawn Lin if (ret) 74584362d79SShawn Lin goto cleanup; 74684362d79SShawn Lin 74784362d79SShawn Lin ret = __sdhci_add_host(host); 74884362d79SShawn Lin if (ret) 74984362d79SShawn Lin goto cleanup; 75084362d79SShawn Lin 75184362d79SShawn Lin return 0; 75284362d79SShawn Lin 75384362d79SShawn Lin cleanup: 75484362d79SShawn Lin sdhci_cleanup_host(host); 75584362d79SShawn Lin return ret; 75684362d79SShawn Lin } 75784362d79SShawn Lin 758e3ec3a3dSSoren Brinkmann static int sdhci_arasan_probe(struct platform_device *pdev) 759e3ec3a3dSSoren Brinkmann { 760e3ec3a3dSSoren Brinkmann int ret; 7613ea4666eSDouglas Anderson const struct of_device_id *match; 7623ea4666eSDouglas Anderson struct device_node *node; 763e3ec3a3dSSoren Brinkmann struct clk *clk_xin; 764e3ec3a3dSSoren Brinkmann struct sdhci_host *host; 765e3ec3a3dSSoren Brinkmann struct sdhci_pltfm_host *pltfm_host; 766e3ec3a3dSSoren Brinkmann struct sdhci_arasan_data *sdhci_arasan; 7673794c542SZach Brown struct device_node *np = pdev->dev.of_node; 76806b23ca0SFaiz Abbas const struct sdhci_arasan_of_data *data; 769e3ec3a3dSSoren Brinkmann 77006b23ca0SFaiz Abbas match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node); 77106b23ca0SFaiz Abbas data = match->data; 77206b23ca0SFaiz Abbas host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan)); 77384362d79SShawn Lin 77489211418SJisheng Zhang if (IS_ERR(host)) 77589211418SJisheng Zhang return PTR_ERR(host); 77689211418SJisheng Zhang 77789211418SJisheng Zhang pltfm_host = sdhci_priv(host); 77889211418SJisheng Zhang sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 779c390f211SDouglas Anderson sdhci_arasan->host = host; 780e3ec3a3dSSoren Brinkmann 78106b23ca0SFaiz Abbas sdhci_arasan->soc_ctl_map = data->soc_ctl_map; 7823ea4666eSDouglas Anderson 7833ea4666eSDouglas Anderson node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0); 7843ea4666eSDouglas Anderson if (node) { 7853ea4666eSDouglas Anderson sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); 7863ea4666eSDouglas Anderson of_node_put(node); 7873ea4666eSDouglas Anderson 7883ea4666eSDouglas Anderson if (IS_ERR(sdhci_arasan->soc_ctl_base)) { 7893ea4666eSDouglas Anderson ret = PTR_ERR(sdhci_arasan->soc_ctl_base); 7903ea4666eSDouglas Anderson if (ret != -EPROBE_DEFER) 7913ea4666eSDouglas Anderson dev_err(&pdev->dev, "Can't get syscon: %d\n", 7923ea4666eSDouglas Anderson ret); 7933ea4666eSDouglas Anderson goto err_pltfm_free; 7943ea4666eSDouglas Anderson } 7953ea4666eSDouglas Anderson } 7963ea4666eSDouglas Anderson 797e3ec3a3dSSoren Brinkmann sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb"); 798e3ec3a3dSSoren Brinkmann if (IS_ERR(sdhci_arasan->clk_ahb)) { 799e3ec3a3dSSoren Brinkmann dev_err(&pdev->dev, "clk_ahb clock not found.\n"); 800278d0962SShawn Lin ret = PTR_ERR(sdhci_arasan->clk_ahb); 801278d0962SShawn Lin goto err_pltfm_free; 802e3ec3a3dSSoren Brinkmann } 803e3ec3a3dSSoren Brinkmann 804e3ec3a3dSSoren Brinkmann clk_xin = devm_clk_get(&pdev->dev, "clk_xin"); 805e3ec3a3dSSoren Brinkmann if (IS_ERR(clk_xin)) { 806e3ec3a3dSSoren Brinkmann dev_err(&pdev->dev, "clk_xin clock not found.\n"); 807278d0962SShawn Lin ret = PTR_ERR(clk_xin); 808278d0962SShawn Lin goto err_pltfm_free; 809e3ec3a3dSSoren Brinkmann } 810e3ec3a3dSSoren Brinkmann 811e3ec3a3dSSoren Brinkmann ret = clk_prepare_enable(sdhci_arasan->clk_ahb); 812e3ec3a3dSSoren Brinkmann if (ret) { 813e3ec3a3dSSoren Brinkmann dev_err(&pdev->dev, "Unable to enable AHB clock.\n"); 814278d0962SShawn Lin goto err_pltfm_free; 815e3ec3a3dSSoren Brinkmann } 816e3ec3a3dSSoren Brinkmann 817e3ec3a3dSSoren Brinkmann ret = clk_prepare_enable(clk_xin); 818e3ec3a3dSSoren Brinkmann if (ret) { 819e3ec3a3dSSoren Brinkmann dev_err(&pdev->dev, "Unable to enable SD clock.\n"); 820e3ec3a3dSSoren Brinkmann goto clk_dis_ahb; 821e3ec3a3dSSoren Brinkmann } 822e3ec3a3dSSoren Brinkmann 823e3ec3a3dSSoren Brinkmann sdhci_get_of_property(pdev); 8243794c542SZach Brown 8253794c542SZach Brown if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) 8263794c542SZach Brown sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; 8273794c542SZach Brown 8283f2c7d5dSHelmut Grohne if (of_property_read_bool(np, "xlnx,int-clock-stable-broken")) 8293f2c7d5dSHelmut Grohne sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE; 8303f2c7d5dSHelmut Grohne 831e3ec3a3dSSoren Brinkmann pltfm_host->clk = clk_xin; 832e3ec3a3dSSoren Brinkmann 833b2ca77c9SShawn Lin if (of_device_is_compatible(pdev->dev.of_node, 834b2ca77c9SShawn Lin "rockchip,rk3399-sdhci-5.1")) 835b2ca77c9SShawn Lin sdhci_arasan_update_clockmultiplier(host, 0x0); 836b2ca77c9SShawn Lin 8373ea4666eSDouglas Anderson sdhci_arasan_update_baseclkfreq(host); 8383ea4666eSDouglas Anderson 839c390f211SDouglas Anderson ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev); 840c390f211SDouglas Anderson if (ret) 841c390f211SDouglas Anderson goto clk_disable_all; 842c390f211SDouglas Anderson 84316b23787SMichal Simek ret = mmc_of_parse(host->mmc); 84416b23787SMichal Simek if (ret) { 84560208a26SMichal Simek if (ret != -EPROBE_DEFER) 846940e698cSShubhrajyoti Datta dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret); 847c390f211SDouglas Anderson goto unreg_clk; 84816b23787SMichal Simek } 84916b23787SMichal Simek 85091aa3661SShawn Lin sdhci_arasan->phy = ERR_PTR(-ENODEV); 85191aa3661SShawn Lin if (of_device_is_compatible(pdev->dev.of_node, 85291aa3661SShawn Lin "arasan,sdhci-5.1")) { 85391aa3661SShawn Lin sdhci_arasan->phy = devm_phy_get(&pdev->dev, 85491aa3661SShawn Lin "phy_arasan"); 85591aa3661SShawn Lin if (IS_ERR(sdhci_arasan->phy)) { 85691aa3661SShawn Lin ret = PTR_ERR(sdhci_arasan->phy); 85791aa3661SShawn Lin dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n"); 858c390f211SDouglas Anderson goto unreg_clk; 85991aa3661SShawn Lin } 86091aa3661SShawn Lin 86191aa3661SShawn Lin ret = phy_init(sdhci_arasan->phy); 86291aa3661SShawn Lin if (ret < 0) { 86391aa3661SShawn Lin dev_err(&pdev->dev, "phy_init err.\n"); 864c390f211SDouglas Anderson goto unreg_clk; 86591aa3661SShawn Lin } 86691aa3661SShawn Lin 867a05c8465SShawn Lin host->mmc_host_ops.hs400_enhanced_strobe = 868a05c8465SShawn Lin sdhci_arasan_hs400_enhanced_strobe; 8698a3bee9bSShawn Lin host->mmc_host_ops.start_signal_voltage_switch = 8708a3bee9bSShawn Lin sdhci_arasan_voltage_switch; 87184362d79SShawn Lin sdhci_arasan->has_cqe = true; 8727bda9482SChristoph Muellner host->mmc->caps2 |= MMC_CAP2_CQE; 8737bda9482SChristoph Muellner 8747bda9482SChristoph Muellner if (!of_property_read_bool(np, "disable-cqe-dcmd")) 8757bda9482SChristoph Muellner host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 87691aa3661SShawn Lin } 87791aa3661SShawn Lin 87884362d79SShawn Lin ret = sdhci_arasan_add_host(sdhci_arasan); 879b1df9de7SMike Looijmans if (ret) 88091aa3661SShawn Lin goto err_add_host; 881e3ec3a3dSSoren Brinkmann 882e3ec3a3dSSoren Brinkmann return 0; 883e3ec3a3dSSoren Brinkmann 88491aa3661SShawn Lin err_add_host: 88591aa3661SShawn Lin if (!IS_ERR(sdhci_arasan->phy)) 88691aa3661SShawn Lin phy_exit(sdhci_arasan->phy); 887c390f211SDouglas Anderson unreg_clk: 888c390f211SDouglas Anderson sdhci_arasan_unregister_sdclk(&pdev->dev); 889e3ec3a3dSSoren Brinkmann clk_disable_all: 890e3ec3a3dSSoren Brinkmann clk_disable_unprepare(clk_xin); 891e3ec3a3dSSoren Brinkmann clk_dis_ahb: 892e3ec3a3dSSoren Brinkmann clk_disable_unprepare(sdhci_arasan->clk_ahb); 893278d0962SShawn Lin err_pltfm_free: 894278d0962SShawn Lin sdhci_pltfm_free(pdev); 895e3ec3a3dSSoren Brinkmann return ret; 896e3ec3a3dSSoren Brinkmann } 897e3ec3a3dSSoren Brinkmann 898e3ec3a3dSSoren Brinkmann static int sdhci_arasan_remove(struct platform_device *pdev) 899e3ec3a3dSSoren Brinkmann { 9000c7fe32eSJisheng Zhang int ret; 901e3ec3a3dSSoren Brinkmann struct sdhci_host *host = platform_get_drvdata(pdev); 902e3ec3a3dSSoren Brinkmann struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 90389211418SJisheng Zhang struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 90489211418SJisheng Zhang struct clk *clk_ahb = sdhci_arasan->clk_ahb; 905e3ec3a3dSSoren Brinkmann 90691aa3661SShawn Lin if (!IS_ERR(sdhci_arasan->phy)) { 907b2db9c67SDouglas Anderson if (sdhci_arasan->is_phy_on) 90891aa3661SShawn Lin phy_power_off(sdhci_arasan->phy); 90991aa3661SShawn Lin phy_exit(sdhci_arasan->phy); 91091aa3661SShawn Lin } 91191aa3661SShawn Lin 912c390f211SDouglas Anderson sdhci_arasan_unregister_sdclk(&pdev->dev); 913c390f211SDouglas Anderson 9140c7fe32eSJisheng Zhang ret = sdhci_pltfm_unregister(pdev); 9150c7fe32eSJisheng Zhang 91689211418SJisheng Zhang clk_disable_unprepare(clk_ahb); 917e3ec3a3dSSoren Brinkmann 9180c7fe32eSJisheng Zhang return ret; 919e3ec3a3dSSoren Brinkmann } 920e3ec3a3dSSoren Brinkmann 921e3ec3a3dSSoren Brinkmann static struct platform_driver sdhci_arasan_driver = { 922e3ec3a3dSSoren Brinkmann .driver = { 923e3ec3a3dSSoren Brinkmann .name = "sdhci-arasan", 924e3ec3a3dSSoren Brinkmann .of_match_table = sdhci_arasan_of_match, 925e3ec3a3dSSoren Brinkmann .pm = &sdhci_arasan_dev_pm_ops, 926e3ec3a3dSSoren Brinkmann }, 927e3ec3a3dSSoren Brinkmann .probe = sdhci_arasan_probe, 928e3ec3a3dSSoren Brinkmann .remove = sdhci_arasan_remove, 929e3ec3a3dSSoren Brinkmann }; 930e3ec3a3dSSoren Brinkmann 931e3ec3a3dSSoren Brinkmann module_platform_driver(sdhci_arasan_driver); 932e3ec3a3dSSoren Brinkmann 933e3ec3a3dSSoren Brinkmann MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller"); 934e3ec3a3dSSoren Brinkmann MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>"); 935e3ec3a3dSSoren Brinkmann MODULE_LICENSE("GPL"); 936