12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2e3ec3a3dSSoren Brinkmann /* 3e3ec3a3dSSoren Brinkmann * Arasan Secure Digital Host Controller Interface. 4e3ec3a3dSSoren Brinkmann * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu> 5e3ec3a3dSSoren Brinkmann * Copyright (c) 2012 Wind River Systems, Inc. 6e3ec3a3dSSoren Brinkmann * Copyright (C) 2013 Pengutronix e.K. 7e3ec3a3dSSoren Brinkmann * Copyright (C) 2013 Xilinx Inc. 8e3ec3a3dSSoren Brinkmann * 9e3ec3a3dSSoren Brinkmann * Based on sdhci-of-esdhc.c 10e3ec3a3dSSoren Brinkmann * 11e3ec3a3dSSoren Brinkmann * Copyright (c) 2007 Freescale Semiconductor, Inc. 12e3ec3a3dSSoren Brinkmann * Copyright (c) 2009 MontaVista Software, Inc. 13e3ec3a3dSSoren Brinkmann * 14e3ec3a3dSSoren Brinkmann * Authors: Xiaobo Xie <X.Xie@freescale.com> 15e3ec3a3dSSoren Brinkmann * Anton Vorontsov <avorontsov@ru.mvista.com> 16e3ec3a3dSSoren Brinkmann */ 17e3ec3a3dSSoren Brinkmann 18c390f211SDouglas Anderson #include <linux/clk-provider.h> 193ea4666eSDouglas Anderson #include <linux/mfd/syscon.h> 20e3ec3a3dSSoren Brinkmann #include <linux/module.h> 21308f3f8dSSuman Tripathi #include <linux/of_device.h> 2291aa3661SShawn Lin #include <linux/phy/phy.h> 233ea4666eSDouglas Anderson #include <linux/regmap.h> 243794c542SZach Brown #include <linux/of.h> 25a5c8b2aeSManish Narani #include <linux/firmware/xlnx-zynqmp.h> 26e3ec3a3dSSoren Brinkmann 2784362d79SShawn Lin #include "cqhci.h" 2884362d79SShawn Lin #include "sdhci-pltfm.h" 29e3ec3a3dSSoren Brinkmann 3084362d79SShawn Lin #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 3184362d79SShawn Lin #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 32a05c8465SShawn Lin #define VENDOR_ENHANCED_STROBE BIT(0) 33e3ec3a3dSSoren Brinkmann 34b2db9c67SDouglas Anderson #define PHY_CLK_TOO_SLOW_HZ 400000 35b2db9c67SDouglas Anderson 36a5c8b2aeSManish Narani /* Default settings for ZynqMP Clock Phases */ 37a5c8b2aeSManish Narani #define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0} 38a5c8b2aeSManish Narani #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0} 39a5c8b2aeSManish Narani 403ea4666eSDouglas Anderson /* 413ea4666eSDouglas Anderson * On some SoCs the syscon area has a feature where the upper 16-bits of 423ea4666eSDouglas Anderson * each 32-bit register act as a write mask for the lower 16-bits. This allows 433ea4666eSDouglas Anderson * atomic updates of the register without locking. This macro is used on SoCs 443ea4666eSDouglas Anderson * that have that feature. 453ea4666eSDouglas Anderson */ 463ea4666eSDouglas Anderson #define HIWORD_UPDATE(val, mask, shift) \ 473ea4666eSDouglas Anderson ((val) << (shift) | (mask) << ((shift) + 16)) 483ea4666eSDouglas Anderson 493ea4666eSDouglas Anderson /** 503ea4666eSDouglas Anderson * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map 513ea4666eSDouglas Anderson * 523ea4666eSDouglas Anderson * @reg: Offset within the syscon of the register containing this field 533ea4666eSDouglas Anderson * @width: Number of bits for this field 543ea4666eSDouglas Anderson * @shift: Bit offset within @reg of this field (or -1 if not avail) 553ea4666eSDouglas Anderson */ 563ea4666eSDouglas Anderson struct sdhci_arasan_soc_ctl_field { 573ea4666eSDouglas Anderson u32 reg; 583ea4666eSDouglas Anderson u16 width; 593ea4666eSDouglas Anderson s16 shift; 603ea4666eSDouglas Anderson }; 613ea4666eSDouglas Anderson 623ea4666eSDouglas Anderson /** 633ea4666eSDouglas Anderson * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers 643ea4666eSDouglas Anderson * 653ea4666eSDouglas Anderson * It's up to the licensee of the Arsan IP block to make these available 663ea4666eSDouglas Anderson * somewhere if needed. Presumably these will be scattered somewhere that's 673ea4666eSDouglas Anderson * accessible via the syscon API. 683ea4666eSDouglas Anderson * 693ea4666eSDouglas Anderson * @baseclkfreq: Where to find corecfg_baseclkfreq 70b2ca77c9SShawn Lin * @clockmultiplier: Where to find corecfg_clockmultiplier 713ea4666eSDouglas Anderson * @hiword_update: If true, use HIWORD_UPDATE to access the syscon 723ea4666eSDouglas Anderson */ 733ea4666eSDouglas Anderson struct sdhci_arasan_soc_ctl_map { 743ea4666eSDouglas Anderson struct sdhci_arasan_soc_ctl_field baseclkfreq; 75b2ca77c9SShawn Lin struct sdhci_arasan_soc_ctl_field clockmultiplier; 763ea4666eSDouglas Anderson bool hiword_update; 773ea4666eSDouglas Anderson }; 783ea4666eSDouglas Anderson 79e3ec3a3dSSoren Brinkmann /** 80e1463618SManish Narani * struct sdhci_arasan_clk_data 81e1463618SManish Narani * @sdcardclk_hw: Struct for the clock we might provide to a PHY. 82e1463618SManish Narani * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. 8307a14d1dSManish Narani * @sampleclk_hw: Struct for the clock we might provide to a PHY. 8407a14d1dSManish Narani * @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw. 85f3dafc37SManish Narani * @clk_phase_in: Array of Input Clock Phase Delays for all speed modes 86f3dafc37SManish Narani * @clk_phase_out: Array of Output Clock Phase Delays for all speed modes 87f3dafc37SManish Narani * @set_clk_delays: Function pointer for setting Clock Delays 88a5c8b2aeSManish Narani * @clk_of_data: Platform specific runtime clock data storage pointer 89e1463618SManish Narani */ 90e1463618SManish Narani struct sdhci_arasan_clk_data { 91e1463618SManish Narani struct clk_hw sdcardclk_hw; 92e1463618SManish Narani struct clk *sdcardclk; 9307a14d1dSManish Narani struct clk_hw sampleclk_hw; 9407a14d1dSManish Narani struct clk *sampleclk; 95f3dafc37SManish Narani int clk_phase_in[MMC_TIMING_MMC_HS400 + 1]; 96f3dafc37SManish Narani int clk_phase_out[MMC_TIMING_MMC_HS400 + 1]; 97f3dafc37SManish Narani void (*set_clk_delays)(struct sdhci_host *host); 98a5c8b2aeSManish Narani void *clk_of_data; 99a5c8b2aeSManish Narani }; 100a5c8b2aeSManish Narani 101a5c8b2aeSManish Narani struct sdhci_arasan_zynqmp_clk_data { 102a5c8b2aeSManish Narani const struct zynqmp_eemi_ops *eemi_ops; 103e1463618SManish Narani }; 104e1463618SManish Narani 105e1463618SManish Narani /** 106e3ec3a3dSSoren Brinkmann * struct sdhci_arasan_data 107c390f211SDouglas Anderson * @host: Pointer to the main SDHCI host structure. 108e3ec3a3dSSoren Brinkmann * @clk_ahb: Pointer to the AHB clock 10991aa3661SShawn Lin * @phy: Pointer to the generic phy 110b2db9c67SDouglas Anderson * @is_phy_on: True if the PHY is on; false if not. 111e1463618SManish Narani * @clk_data: Struct for the Arasan Controller Clock Data. 1123ea4666eSDouglas Anderson * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. 1133ea4666eSDouglas Anderson * @soc_ctl_map: Map to get offsets into soc_ctl registers. 114e3ec3a3dSSoren Brinkmann */ 115e3ec3a3dSSoren Brinkmann struct sdhci_arasan_data { 116c390f211SDouglas Anderson struct sdhci_host *host; 117e3ec3a3dSSoren Brinkmann struct clk *clk_ahb; 11891aa3661SShawn Lin struct phy *phy; 119b2db9c67SDouglas Anderson bool is_phy_on; 1203ea4666eSDouglas Anderson 12184362d79SShawn Lin bool has_cqe; 122e1463618SManish Narani struct sdhci_arasan_clk_data clk_data; 123c390f211SDouglas Anderson 1243ea4666eSDouglas Anderson struct regmap *soc_ctl_base; 1253ea4666eSDouglas Anderson const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; 1263794c542SZach Brown unsigned int quirks; /* Arasan deviations from spec */ 1273794c542SZach Brown 1283794c542SZach Brown /* Controller does not have CD wired and will not function normally without */ 1293794c542SZach Brown #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0) 1303f2c7d5dSHelmut Grohne /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the 1313f2c7d5dSHelmut Grohne * internal clock even when the clock isn't stable */ 1323f2c7d5dSHelmut Grohne #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1) 133e3ec3a3dSSoren Brinkmann }; 134e3ec3a3dSSoren Brinkmann 13506b23ca0SFaiz Abbas struct sdhci_arasan_of_data { 13606b23ca0SFaiz Abbas const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; 13706b23ca0SFaiz Abbas const struct sdhci_pltfm_data *pdata; 13806b23ca0SFaiz Abbas }; 13906b23ca0SFaiz Abbas 1403ea4666eSDouglas Anderson static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = { 1413ea4666eSDouglas Anderson .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 }, 142b2ca77c9SShawn Lin .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0}, 1433ea4666eSDouglas Anderson .hiword_update = true, 1443ea4666eSDouglas Anderson }; 1453ea4666eSDouglas Anderson 1465c1a4f40SRamuthevar Vadivel Muruganx static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = { 1475c1a4f40SRamuthevar Vadivel Muruganx .baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 }, 1485c1a4f40SRamuthevar Vadivel Muruganx .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 }, 1495c1a4f40SRamuthevar Vadivel Muruganx .hiword_update = false, 1505c1a4f40SRamuthevar Vadivel Muruganx }; 1515c1a4f40SRamuthevar Vadivel Muruganx 152d1807ad6SRamuthevar Vadivel Murugan static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = { 153d1807ad6SRamuthevar Vadivel Murugan .baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 }, 154d1807ad6SRamuthevar Vadivel Murugan .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 }, 155d1807ad6SRamuthevar Vadivel Murugan .hiword_update = false, 156d1807ad6SRamuthevar Vadivel Murugan }; 157d1807ad6SRamuthevar Vadivel Murugan 1583ea4666eSDouglas Anderson /** 1593ea4666eSDouglas Anderson * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers 1603ea4666eSDouglas Anderson * 1613ea4666eSDouglas Anderson * This function allows writing to fields in sdhci_arasan_soc_ctl_map. 1623ea4666eSDouglas Anderson * Note that if a field is specified as not available (shift < 0) then 1633ea4666eSDouglas Anderson * this function will silently return an error code. It will be noisy 1643ea4666eSDouglas Anderson * and print errors for any other (unexpected) errors. 1653ea4666eSDouglas Anderson * 1663ea4666eSDouglas Anderson * @host: The sdhci_host 1673ea4666eSDouglas Anderson * @fld: The field to write to 1683ea4666eSDouglas Anderson * @val: The value to write 1693ea4666eSDouglas Anderson */ 1703ea4666eSDouglas Anderson static int sdhci_arasan_syscon_write(struct sdhci_host *host, 1713ea4666eSDouglas Anderson const struct sdhci_arasan_soc_ctl_field *fld, 1723ea4666eSDouglas Anderson u32 val) 1733ea4666eSDouglas Anderson { 1743ea4666eSDouglas Anderson struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1753ea4666eSDouglas Anderson struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 1763ea4666eSDouglas Anderson struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; 1773ea4666eSDouglas Anderson u32 reg = fld->reg; 1783ea4666eSDouglas Anderson u16 width = fld->width; 1793ea4666eSDouglas Anderson s16 shift = fld->shift; 1803ea4666eSDouglas Anderson int ret; 1813ea4666eSDouglas Anderson 1823ea4666eSDouglas Anderson /* 1833ea4666eSDouglas Anderson * Silently return errors for shift < 0 so caller doesn't have 1843ea4666eSDouglas Anderson * to check for fields which are optional. For fields that 1853ea4666eSDouglas Anderson * are required then caller needs to do something special 1863ea4666eSDouglas Anderson * anyway. 1873ea4666eSDouglas Anderson */ 1883ea4666eSDouglas Anderson if (shift < 0) 1893ea4666eSDouglas Anderson return -EINVAL; 1903ea4666eSDouglas Anderson 1913ea4666eSDouglas Anderson if (sdhci_arasan->soc_ctl_map->hiword_update) 1923ea4666eSDouglas Anderson ret = regmap_write(soc_ctl_base, reg, 1933ea4666eSDouglas Anderson HIWORD_UPDATE(val, GENMASK(width, 0), 1943ea4666eSDouglas Anderson shift)); 1953ea4666eSDouglas Anderson else 1963ea4666eSDouglas Anderson ret = regmap_update_bits(soc_ctl_base, reg, 1973ea4666eSDouglas Anderson GENMASK(shift + width, shift), 1983ea4666eSDouglas Anderson val << shift); 1993ea4666eSDouglas Anderson 2003ea4666eSDouglas Anderson /* Yell about (unexpected) regmap errors */ 2013ea4666eSDouglas Anderson if (ret) 2023ea4666eSDouglas Anderson pr_warn("%s: Regmap write fail: %d\n", 2033ea4666eSDouglas Anderson mmc_hostname(host->mmc), ret); 2043ea4666eSDouglas Anderson 2053ea4666eSDouglas Anderson return ret; 2063ea4666eSDouglas Anderson } 2073ea4666eSDouglas Anderson 208802ac39aSShawn Lin static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) 209802ac39aSShawn Lin { 210802ac39aSShawn Lin struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 211802ac39aSShawn Lin struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 212f3dafc37SManish Narani struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; 2136fc09244SDouglas Anderson bool ctrl_phy = false; 214802ac39aSShawn Lin 215b2db9c67SDouglas Anderson if (!IS_ERR(sdhci_arasan->phy)) { 216b2db9c67SDouglas Anderson if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) { 217b2db9c67SDouglas Anderson /* 218b2db9c67SDouglas Anderson * If PHY off, set clock to max speed and power PHY on. 219b2db9c67SDouglas Anderson * 220b2db9c67SDouglas Anderson * Although PHY docs apparently suggest power cycling 221b2db9c67SDouglas Anderson * when changing the clock the PHY doesn't like to be 222b2db9c67SDouglas Anderson * powered on while at low speeds like those used in ID 223b2db9c67SDouglas Anderson * mode. Even worse is powering the PHY on while the 224b2db9c67SDouglas Anderson * clock is off. 225b2db9c67SDouglas Anderson * 226b2db9c67SDouglas Anderson * To workaround the PHY limitations, the best we can 227b2db9c67SDouglas Anderson * do is to power it on at a faster speed and then slam 228b2db9c67SDouglas Anderson * through low speeds without power cycling. 229b2db9c67SDouglas Anderson */ 230b2db9c67SDouglas Anderson sdhci_set_clock(host, host->max_clk); 231b2db9c67SDouglas Anderson phy_power_on(sdhci_arasan->phy); 232b2db9c67SDouglas Anderson sdhci_arasan->is_phy_on = true; 233802ac39aSShawn Lin 234b2db9c67SDouglas Anderson /* 235b2db9c67SDouglas Anderson * We'll now fall through to the below case with 236b2db9c67SDouglas Anderson * ctrl_phy = false (so we won't turn off/on). The 237b2db9c67SDouglas Anderson * sdhci_set_clock() will set the real clock. 238b2db9c67SDouglas Anderson */ 239b2db9c67SDouglas Anderson } else if (clock > PHY_CLK_TOO_SLOW_HZ) { 240b2db9c67SDouglas Anderson /* 241b2db9c67SDouglas Anderson * At higher clock speeds the PHY is fine being power 242b2db9c67SDouglas Anderson * cycled and docs say you _should_ power cycle when 243b2db9c67SDouglas Anderson * changing clock speeds. 244b2db9c67SDouglas Anderson */ 245b2db9c67SDouglas Anderson ctrl_phy = true; 246b2db9c67SDouglas Anderson } 247b2db9c67SDouglas Anderson } 248b2db9c67SDouglas Anderson 249b2db9c67SDouglas Anderson if (ctrl_phy && sdhci_arasan->is_phy_on) { 250802ac39aSShawn Lin phy_power_off(sdhci_arasan->phy); 251b2db9c67SDouglas Anderson sdhci_arasan->is_phy_on = false; 252802ac39aSShawn Lin } 253802ac39aSShawn Lin 254f3dafc37SManish Narani /* Set the Input and Output Clock Phase Delays */ 255f3dafc37SManish Narani if (clk_data->set_clk_delays) 256f3dafc37SManish Narani clk_data->set_clk_delays(host); 257f3dafc37SManish Narani 258802ac39aSShawn Lin sdhci_set_clock(host, clock); 259802ac39aSShawn Lin 2603f2c7d5dSHelmut Grohne if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE) 2613f2c7d5dSHelmut Grohne /* 2623f2c7d5dSHelmut Grohne * Some controllers immediately report SDHCI_CLOCK_INT_STABLE 2633f2c7d5dSHelmut Grohne * after enabling the clock even though the clock is not 2643f2c7d5dSHelmut Grohne * stable. Trying to use a clock without waiting here results 2653f2c7d5dSHelmut Grohne * in EILSEQ while detecting some older/slower cards. The 2663f2c7d5dSHelmut Grohne * chosen delay is the maximum delay from sdhci_set_clock. 2673f2c7d5dSHelmut Grohne */ 2683f2c7d5dSHelmut Grohne msleep(20); 2693f2c7d5dSHelmut Grohne 2706fc09244SDouglas Anderson if (ctrl_phy) { 271802ac39aSShawn Lin phy_power_on(sdhci_arasan->phy); 272b2db9c67SDouglas Anderson sdhci_arasan->is_phy_on = true; 273802ac39aSShawn Lin } 274802ac39aSShawn Lin } 275802ac39aSShawn Lin 276a05c8465SShawn Lin static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc, 277a05c8465SShawn Lin struct mmc_ios *ios) 278a05c8465SShawn Lin { 279a05c8465SShawn Lin u32 vendor; 280a05c8465SShawn Lin struct sdhci_host *host = mmc_priv(mmc); 281a05c8465SShawn Lin 2820daf72feSJean-Francois Dagenais vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER); 283a05c8465SShawn Lin if (ios->enhanced_strobe) 284a05c8465SShawn Lin vendor |= VENDOR_ENHANCED_STROBE; 285a05c8465SShawn Lin else 286a05c8465SShawn Lin vendor &= ~VENDOR_ENHANCED_STROBE; 287a05c8465SShawn Lin 2880daf72feSJean-Francois Dagenais sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER); 289a05c8465SShawn Lin } 290a05c8465SShawn Lin 29113d62fd2SWei Yongjun static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) 2923794c542SZach Brown { 2933794c542SZach Brown u8 ctrl; 2943794c542SZach Brown struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 2953794c542SZach Brown struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 2963794c542SZach Brown 2973794c542SZach Brown sdhci_reset(host, mask); 2983794c542SZach Brown 2993794c542SZach Brown if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { 3003794c542SZach Brown ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 3013794c542SZach Brown ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 3023794c542SZach Brown sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 3033794c542SZach Brown } 3043794c542SZach Brown } 3053794c542SZach Brown 3068a3bee9bSShawn Lin static int sdhci_arasan_voltage_switch(struct mmc_host *mmc, 3078a3bee9bSShawn Lin struct mmc_ios *ios) 3088a3bee9bSShawn Lin { 3098a3bee9bSShawn Lin switch (ios->signal_voltage) { 3108a3bee9bSShawn Lin case MMC_SIGNAL_VOLTAGE_180: 3118a3bee9bSShawn Lin /* 3128a3bee9bSShawn Lin * Plese don't switch to 1V8 as arasan,5.1 doesn't 3138a3bee9bSShawn Lin * actually refer to this setting to indicate the 3148a3bee9bSShawn Lin * signal voltage and the state machine will be broken 3158a3bee9bSShawn Lin * actually if we force to enable 1V8. That's something 3168a3bee9bSShawn Lin * like broken quirk but we could work around here. 3178a3bee9bSShawn Lin */ 3188a3bee9bSShawn Lin return 0; 3198a3bee9bSShawn Lin case MMC_SIGNAL_VOLTAGE_330: 3208a3bee9bSShawn Lin case MMC_SIGNAL_VOLTAGE_120: 3218a3bee9bSShawn Lin /* We don't support 3V3 and 1V2 */ 3228a3bee9bSShawn Lin break; 3238a3bee9bSShawn Lin } 3248a3bee9bSShawn Lin 3258a3bee9bSShawn Lin return -EINVAL; 3268a3bee9bSShawn Lin } 3278a3bee9bSShawn Lin 328a81dae3aSJulia Lawall static const struct sdhci_ops sdhci_arasan_ops = { 329802ac39aSShawn Lin .set_clock = sdhci_arasan_set_clock, 330e3ec3a3dSSoren Brinkmann .get_max_clock = sdhci_pltfm_clk_get_max_clock, 3318cc35289SShawn Lin .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 3322317f56cSRussell King .set_bus_width = sdhci_set_bus_width, 3333794c542SZach Brown .reset = sdhci_arasan_reset, 33496d7b78cSRussell King .set_uhs_signaling = sdhci_set_uhs_signaling, 335c2c5252cSNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 336e3ec3a3dSSoren Brinkmann }; 337e3ec3a3dSSoren Brinkmann 338a81dae3aSJulia Lawall static const struct sdhci_pltfm_data sdhci_arasan_pdata = { 339e3ec3a3dSSoren Brinkmann .ops = &sdhci_arasan_ops, 3402d532d45SSuneel Garapati .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 3412d532d45SSuneel Garapati .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 34257aac337SPhil Edworthy SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | 34357aac337SPhil Edworthy SDHCI_QUIRK2_STOP_WITH_TC, 344e3ec3a3dSSoren Brinkmann }; 345e3ec3a3dSSoren Brinkmann 34606b23ca0SFaiz Abbas static struct sdhci_arasan_of_data sdhci_arasan_data = { 34706b23ca0SFaiz Abbas .pdata = &sdhci_arasan_pdata, 34806b23ca0SFaiz Abbas }; 34906b23ca0SFaiz Abbas 3502a2b8216SManish Narani static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = { 3512a2b8216SManish Narani .ops = &sdhci_arasan_ops, 3522a2b8216SManish Narani .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 3532a2b8216SManish Narani SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | 3542a2b8216SManish Narani SDHCI_QUIRK2_STOP_WITH_TC, 3552a2b8216SManish Narani }; 3562a2b8216SManish Narani 3572a2b8216SManish Narani static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = { 3582a2b8216SManish Narani .pdata = &sdhci_arasan_zynqmp_pdata, 3592a2b8216SManish Narani }; 3602a2b8216SManish Narani 36184362d79SShawn Lin static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask) 36284362d79SShawn Lin { 36384362d79SShawn Lin int cmd_error = 0; 36484362d79SShawn Lin int data_error = 0; 36584362d79SShawn Lin 36684362d79SShawn Lin if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 36784362d79SShawn Lin return intmask; 36884362d79SShawn Lin 36984362d79SShawn Lin cqhci_irq(host->mmc, intmask, cmd_error, data_error); 37084362d79SShawn Lin 37184362d79SShawn Lin return 0; 37284362d79SShawn Lin } 37384362d79SShawn Lin 37484362d79SShawn Lin static void sdhci_arasan_dumpregs(struct mmc_host *mmc) 37584362d79SShawn Lin { 37684362d79SShawn Lin sdhci_dumpregs(mmc_priv(mmc)); 37784362d79SShawn Lin } 37884362d79SShawn Lin 37984362d79SShawn Lin static void sdhci_arasan_cqe_enable(struct mmc_host *mmc) 38084362d79SShawn Lin { 38184362d79SShawn Lin struct sdhci_host *host = mmc_priv(mmc); 38284362d79SShawn Lin u32 reg; 38384362d79SShawn Lin 38484362d79SShawn Lin reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 38584362d79SShawn Lin while (reg & SDHCI_DATA_AVAILABLE) { 38684362d79SShawn Lin sdhci_readl(host, SDHCI_BUFFER); 38784362d79SShawn Lin reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 38884362d79SShawn Lin } 38984362d79SShawn Lin 39084362d79SShawn Lin sdhci_cqe_enable(mmc); 39184362d79SShawn Lin } 39284362d79SShawn Lin 39384362d79SShawn Lin static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = { 39484362d79SShawn Lin .enable = sdhci_arasan_cqe_enable, 39584362d79SShawn Lin .disable = sdhci_cqe_disable, 39684362d79SShawn Lin .dumpregs = sdhci_arasan_dumpregs, 39784362d79SShawn Lin }; 39884362d79SShawn Lin 39984362d79SShawn Lin static const struct sdhci_ops sdhci_arasan_cqe_ops = { 40084362d79SShawn Lin .set_clock = sdhci_arasan_set_clock, 40184362d79SShawn Lin .get_max_clock = sdhci_pltfm_clk_get_max_clock, 40284362d79SShawn Lin .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 40384362d79SShawn Lin .set_bus_width = sdhci_set_bus_width, 40484362d79SShawn Lin .reset = sdhci_arasan_reset, 40584362d79SShawn Lin .set_uhs_signaling = sdhci_set_uhs_signaling, 406c2c5252cSNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 40784362d79SShawn Lin .irq = sdhci_arasan_cqhci_irq, 40884362d79SShawn Lin }; 40984362d79SShawn Lin 41084362d79SShawn Lin static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = { 41184362d79SShawn Lin .ops = &sdhci_arasan_cqe_ops, 41284362d79SShawn Lin .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 41384362d79SShawn Lin .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 41484362d79SShawn Lin SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 41584362d79SShawn Lin }; 41684362d79SShawn Lin 41706b23ca0SFaiz Abbas static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = { 41806b23ca0SFaiz Abbas .soc_ctl_map = &rk3399_soc_ctl_map, 41906b23ca0SFaiz Abbas .pdata = &sdhci_arasan_cqe_pdata, 42006b23ca0SFaiz Abbas }; 42106b23ca0SFaiz Abbas 4225c1a4f40SRamuthevar Vadivel Muruganx static struct sdhci_arasan_of_data intel_lgm_emmc_data = { 4235c1a4f40SRamuthevar Vadivel Muruganx .soc_ctl_map = &intel_lgm_emmc_soc_ctl_map, 4245c1a4f40SRamuthevar Vadivel Muruganx .pdata = &sdhci_arasan_cqe_pdata, 4255c1a4f40SRamuthevar Vadivel Muruganx }; 4265c1a4f40SRamuthevar Vadivel Muruganx 427d1807ad6SRamuthevar Vadivel Murugan static struct sdhci_arasan_of_data intel_lgm_sdxc_data = { 428d1807ad6SRamuthevar Vadivel Murugan .soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map, 429d1807ad6SRamuthevar Vadivel Murugan .pdata = &sdhci_arasan_cqe_pdata, 430d1807ad6SRamuthevar Vadivel Murugan }; 431d1807ad6SRamuthevar Vadivel Murugan 432e3ec3a3dSSoren Brinkmann #ifdef CONFIG_PM_SLEEP 433e3ec3a3dSSoren Brinkmann /** 434e3ec3a3dSSoren Brinkmann * sdhci_arasan_suspend - Suspend method for the driver 435e3ec3a3dSSoren Brinkmann * @dev: Address of the device structure 436e3ec3a3dSSoren Brinkmann * Returns 0 on success and error value on error 437e3ec3a3dSSoren Brinkmann * 438e3ec3a3dSSoren Brinkmann * Put the device in a low power state. 439e3ec3a3dSSoren Brinkmann */ 440e3ec3a3dSSoren Brinkmann static int sdhci_arasan_suspend(struct device *dev) 441e3ec3a3dSSoren Brinkmann { 442970f2d90SWolfram Sang struct sdhci_host *host = dev_get_drvdata(dev); 443e3ec3a3dSSoren Brinkmann struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 44489211418SJisheng Zhang struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 445e3ec3a3dSSoren Brinkmann int ret; 446e3ec3a3dSSoren Brinkmann 447d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 448d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 449d38dcad4SAdrian Hunter 45084362d79SShawn Lin if (sdhci_arasan->has_cqe) { 45184362d79SShawn Lin ret = cqhci_suspend(host->mmc); 45284362d79SShawn Lin if (ret) 45384362d79SShawn Lin return ret; 45484362d79SShawn Lin } 45584362d79SShawn Lin 456e3ec3a3dSSoren Brinkmann ret = sdhci_suspend_host(host); 457e3ec3a3dSSoren Brinkmann if (ret) 458e3ec3a3dSSoren Brinkmann return ret; 459e3ec3a3dSSoren Brinkmann 460b2db9c67SDouglas Anderson if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) { 46191aa3661SShawn Lin ret = phy_power_off(sdhci_arasan->phy); 46291aa3661SShawn Lin if (ret) { 46391aa3661SShawn Lin dev_err(dev, "Cannot power off phy.\n"); 46491aa3661SShawn Lin sdhci_resume_host(host); 46591aa3661SShawn Lin return ret; 46691aa3661SShawn Lin } 467b2db9c67SDouglas Anderson sdhci_arasan->is_phy_on = false; 46891aa3661SShawn Lin } 46991aa3661SShawn Lin 470e3ec3a3dSSoren Brinkmann clk_disable(pltfm_host->clk); 471e3ec3a3dSSoren Brinkmann clk_disable(sdhci_arasan->clk_ahb); 472e3ec3a3dSSoren Brinkmann 473e3ec3a3dSSoren Brinkmann return 0; 474e3ec3a3dSSoren Brinkmann } 475e3ec3a3dSSoren Brinkmann 476e3ec3a3dSSoren Brinkmann /** 477e3ec3a3dSSoren Brinkmann * sdhci_arasan_resume - Resume method for the driver 478e3ec3a3dSSoren Brinkmann * @dev: Address of the device structure 479e3ec3a3dSSoren Brinkmann * Returns 0 on success and error value on error 480e3ec3a3dSSoren Brinkmann * 481e3ec3a3dSSoren Brinkmann * Resume operation after suspend 482e3ec3a3dSSoren Brinkmann */ 483e3ec3a3dSSoren Brinkmann static int sdhci_arasan_resume(struct device *dev) 484e3ec3a3dSSoren Brinkmann { 485970f2d90SWolfram Sang struct sdhci_host *host = dev_get_drvdata(dev); 486e3ec3a3dSSoren Brinkmann struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 48789211418SJisheng Zhang struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 488e3ec3a3dSSoren Brinkmann int ret; 489e3ec3a3dSSoren Brinkmann 490e3ec3a3dSSoren Brinkmann ret = clk_enable(sdhci_arasan->clk_ahb); 491e3ec3a3dSSoren Brinkmann if (ret) { 492e3ec3a3dSSoren Brinkmann dev_err(dev, "Cannot enable AHB clock.\n"); 493e3ec3a3dSSoren Brinkmann return ret; 494e3ec3a3dSSoren Brinkmann } 495e3ec3a3dSSoren Brinkmann 496e3ec3a3dSSoren Brinkmann ret = clk_enable(pltfm_host->clk); 497e3ec3a3dSSoren Brinkmann if (ret) { 498e3ec3a3dSSoren Brinkmann dev_err(dev, "Cannot enable SD clock.\n"); 499e3ec3a3dSSoren Brinkmann return ret; 500e3ec3a3dSSoren Brinkmann } 501e3ec3a3dSSoren Brinkmann 502b2db9c67SDouglas Anderson if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) { 50391aa3661SShawn Lin ret = phy_power_on(sdhci_arasan->phy); 50491aa3661SShawn Lin if (ret) { 50591aa3661SShawn Lin dev_err(dev, "Cannot power on phy.\n"); 50691aa3661SShawn Lin return ret; 50791aa3661SShawn Lin } 508b2db9c67SDouglas Anderson sdhci_arasan->is_phy_on = true; 50991aa3661SShawn Lin } 51091aa3661SShawn Lin 51184362d79SShawn Lin ret = sdhci_resume_host(host); 51284362d79SShawn Lin if (ret) { 51384362d79SShawn Lin dev_err(dev, "Cannot resume host.\n"); 51484362d79SShawn Lin return ret; 51584362d79SShawn Lin } 51684362d79SShawn Lin 51784362d79SShawn Lin if (sdhci_arasan->has_cqe) 51884362d79SShawn Lin return cqhci_resume(host->mmc); 51984362d79SShawn Lin 52084362d79SShawn Lin return 0; 521e3ec3a3dSSoren Brinkmann } 522e3ec3a3dSSoren Brinkmann #endif /* ! CONFIG_PM_SLEEP */ 523e3ec3a3dSSoren Brinkmann 524e3ec3a3dSSoren Brinkmann static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend, 525e3ec3a3dSSoren Brinkmann sdhci_arasan_resume); 526e3ec3a3dSSoren Brinkmann 5273ea4666eSDouglas Anderson static const struct of_device_id sdhci_arasan_of_match[] = { 5283ea4666eSDouglas Anderson /* SoC-specific compatible strings w/ soc_ctl_map */ 5293ea4666eSDouglas Anderson { 5303ea4666eSDouglas Anderson .compatible = "rockchip,rk3399-sdhci-5.1", 53106b23ca0SFaiz Abbas .data = &sdhci_arasan_rk3399_data, 5323ea4666eSDouglas Anderson }, 5335c1a4f40SRamuthevar Vadivel Muruganx { 5345c1a4f40SRamuthevar Vadivel Muruganx .compatible = "intel,lgm-sdhci-5.1-emmc", 5355c1a4f40SRamuthevar Vadivel Muruganx .data = &intel_lgm_emmc_data, 5365c1a4f40SRamuthevar Vadivel Muruganx }, 537d1807ad6SRamuthevar Vadivel Murugan { 538d1807ad6SRamuthevar Vadivel Murugan .compatible = "intel,lgm-sdhci-5.1-sdxc", 539d1807ad6SRamuthevar Vadivel Murugan .data = &intel_lgm_sdxc_data, 540d1807ad6SRamuthevar Vadivel Murugan }, 5413ea4666eSDouglas Anderson /* Generic compatible below here */ 54206b23ca0SFaiz Abbas { 54306b23ca0SFaiz Abbas .compatible = "arasan,sdhci-8.9a", 54406b23ca0SFaiz Abbas .data = &sdhci_arasan_data, 54506b23ca0SFaiz Abbas }, 54606b23ca0SFaiz Abbas { 54706b23ca0SFaiz Abbas .compatible = "arasan,sdhci-5.1", 54806b23ca0SFaiz Abbas .data = &sdhci_arasan_data, 54906b23ca0SFaiz Abbas }, 55006b23ca0SFaiz Abbas { 55106b23ca0SFaiz Abbas .compatible = "arasan,sdhci-4.9a", 55206b23ca0SFaiz Abbas .data = &sdhci_arasan_data, 55306b23ca0SFaiz Abbas }, 554a5c8b2aeSManish Narani { 555a5c8b2aeSManish Narani .compatible = "xlnx,zynqmp-8.9a", 5562a2b8216SManish Narani .data = &sdhci_arasan_zynqmp_data, 557a5c8b2aeSManish Narani }, 5583ea4666eSDouglas Anderson { /* sentinel */ } 5593ea4666eSDouglas Anderson }; 5603ea4666eSDouglas Anderson MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); 5613ea4666eSDouglas Anderson 5623ea4666eSDouglas Anderson /** 563c390f211SDouglas Anderson * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate 564c390f211SDouglas Anderson * 565c390f211SDouglas Anderson * Return the current actual rate of the SD card clock. This can be used 566c390f211SDouglas Anderson * to communicate with out PHY. 567c390f211SDouglas Anderson * 568c390f211SDouglas Anderson * @hw: Pointer to the hardware clock structure. 569c390f211SDouglas Anderson * @parent_rate The parent rate (should be rate of clk_xin). 570c390f211SDouglas Anderson * Returns the card clock rate. 571c390f211SDouglas Anderson */ 572c390f211SDouglas Anderson static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw, 573c390f211SDouglas Anderson unsigned long parent_rate) 574c390f211SDouglas Anderson 575c390f211SDouglas Anderson { 576e1463618SManish Narani struct sdhci_arasan_clk_data *clk_data = 577e1463618SManish Narani container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw); 578c390f211SDouglas Anderson struct sdhci_arasan_data *sdhci_arasan = 579e1463618SManish Narani container_of(clk_data, struct sdhci_arasan_data, clk_data); 580c390f211SDouglas Anderson struct sdhci_host *host = sdhci_arasan->host; 581c390f211SDouglas Anderson 582c390f211SDouglas Anderson return host->mmc->actual_clock; 583c390f211SDouglas Anderson } 584c390f211SDouglas Anderson 585c390f211SDouglas Anderson static const struct clk_ops arasan_sdcardclk_ops = { 586c390f211SDouglas Anderson .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, 587c390f211SDouglas Anderson }; 588c390f211SDouglas Anderson 589c390f211SDouglas Anderson /** 59007a14d1dSManish Narani * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate 59107a14d1dSManish Narani * 59207a14d1dSManish Narani * Return the current actual rate of the sampling clock. This can be used 59307a14d1dSManish Narani * to communicate with out PHY. 59407a14d1dSManish Narani * 59507a14d1dSManish Narani * @hw: Pointer to the hardware clock structure. 59607a14d1dSManish Narani * @parent_rate The parent rate (should be rate of clk_xin). 59707a14d1dSManish Narani * Returns the sample clock rate. 59807a14d1dSManish Narani */ 59907a14d1dSManish Narani static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw, 60007a14d1dSManish Narani unsigned long parent_rate) 60107a14d1dSManish Narani 60207a14d1dSManish Narani { 60307a14d1dSManish Narani struct sdhci_arasan_clk_data *clk_data = 60407a14d1dSManish Narani container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw); 60507a14d1dSManish Narani struct sdhci_arasan_data *sdhci_arasan = 60607a14d1dSManish Narani container_of(clk_data, struct sdhci_arasan_data, clk_data); 60707a14d1dSManish Narani struct sdhci_host *host = sdhci_arasan->host; 60807a14d1dSManish Narani 60907a14d1dSManish Narani return host->mmc->actual_clock; 61007a14d1dSManish Narani } 61107a14d1dSManish Narani 61207a14d1dSManish Narani static const struct clk_ops arasan_sampleclk_ops = { 61307a14d1dSManish Narani .recalc_rate = sdhci_arasan_sampleclk_recalc_rate, 61407a14d1dSManish Narani }; 61507a14d1dSManish Narani 61607a14d1dSManish Narani /** 617a5c8b2aeSManish Narani * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays 618a5c8b2aeSManish Narani * 619a5c8b2aeSManish Narani * Set the SD Output Clock Tap Delays for Output path 620a5c8b2aeSManish Narani * 621a5c8b2aeSManish Narani * @hw: Pointer to the hardware clock structure. 622a5c8b2aeSManish Narani * @degrees The clock phase shift between 0 - 359. 623a5c8b2aeSManish Narani * Return: 0 on success and error value on error 624a5c8b2aeSManish Narani */ 625a5c8b2aeSManish Narani static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees) 626a5c8b2aeSManish Narani 627a5c8b2aeSManish Narani { 628a5c8b2aeSManish Narani struct sdhci_arasan_clk_data *clk_data = 629a5c8b2aeSManish Narani container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw); 630a5c8b2aeSManish Narani struct sdhci_arasan_data *sdhci_arasan = 631a5c8b2aeSManish Narani container_of(clk_data, struct sdhci_arasan_data, clk_data); 632a5c8b2aeSManish Narani struct sdhci_host *host = sdhci_arasan->host; 633a5c8b2aeSManish Narani struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data = 634a5c8b2aeSManish Narani clk_data->clk_of_data; 635a5c8b2aeSManish Narani const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops; 636a5c8b2aeSManish Narani const char *clk_name = clk_hw_get_name(hw); 637a5c8b2aeSManish Narani u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1; 638a5c8b2aeSManish Narani u8 tap_delay, tap_max = 0; 639a5c8b2aeSManish Narani int ret; 640a5c8b2aeSManish Narani 641a5c8b2aeSManish Narani /* 642a5c8b2aeSManish Narani * This is applicable for SDHCI_SPEC_300 and above 643a5c8b2aeSManish Narani * ZynqMP does not set phase for <=25MHz clock. 644a5c8b2aeSManish Narani * If degrees is zero, no need to do anything. 645a5c8b2aeSManish Narani */ 646a5c8b2aeSManish Narani if (host->version < SDHCI_SPEC_300 || 647a5c8b2aeSManish Narani host->timing == MMC_TIMING_LEGACY || 648a5c8b2aeSManish Narani host->timing == MMC_TIMING_UHS_SDR12 || !degrees) 649a5c8b2aeSManish Narani return 0; 650a5c8b2aeSManish Narani 651a5c8b2aeSManish Narani switch (host->timing) { 652a5c8b2aeSManish Narani case MMC_TIMING_MMC_HS: 653a5c8b2aeSManish Narani case MMC_TIMING_SD_HS: 654a5c8b2aeSManish Narani case MMC_TIMING_UHS_SDR25: 655a5c8b2aeSManish Narani case MMC_TIMING_UHS_DDR50: 656a5c8b2aeSManish Narani case MMC_TIMING_MMC_DDR52: 657a5c8b2aeSManish Narani /* For 50MHz clock, 30 Taps are available */ 658a5c8b2aeSManish Narani tap_max = 30; 659a5c8b2aeSManish Narani break; 660a5c8b2aeSManish Narani case MMC_TIMING_UHS_SDR50: 661a5c8b2aeSManish Narani /* For 100MHz clock, 15 Taps are available */ 662a5c8b2aeSManish Narani tap_max = 15; 663a5c8b2aeSManish Narani break; 664a5c8b2aeSManish Narani case MMC_TIMING_UHS_SDR104: 665a5c8b2aeSManish Narani case MMC_TIMING_MMC_HS200: 666a5c8b2aeSManish Narani /* For 200MHz clock, 8 Taps are available */ 667a5c8b2aeSManish Narani tap_max = 8; 668a5c8b2aeSManish Narani default: 669a5c8b2aeSManish Narani break; 670a5c8b2aeSManish Narani } 671a5c8b2aeSManish Narani 672a5c8b2aeSManish Narani tap_delay = (degrees * tap_max) / 360; 673a5c8b2aeSManish Narani 674a5c8b2aeSManish Narani /* Set the Clock Phase */ 675a5c8b2aeSManish Narani ret = eemi_ops->ioctl(node_id, IOCTL_SET_SD_TAPDELAY, 676a5c8b2aeSManish Narani PM_TAPDELAY_OUTPUT, tap_delay, NULL); 677a5c8b2aeSManish Narani if (ret) 678a5c8b2aeSManish Narani pr_err("Error setting Output Tap Delay\n"); 679a5c8b2aeSManish Narani 680a5c8b2aeSManish Narani return ret; 681a5c8b2aeSManish Narani } 682a5c8b2aeSManish Narani 683a5c8b2aeSManish Narani static const struct clk_ops zynqmp_sdcardclk_ops = { 684a5c8b2aeSManish Narani .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, 685a5c8b2aeSManish Narani .set_phase = sdhci_zynqmp_sdcardclk_set_phase, 686a5c8b2aeSManish Narani }; 687a5c8b2aeSManish Narani 688a5c8b2aeSManish Narani /** 689a5c8b2aeSManish Narani * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays 690a5c8b2aeSManish Narani * 691a5c8b2aeSManish Narani * Set the SD Input Clock Tap Delays for Input path 692a5c8b2aeSManish Narani * 693a5c8b2aeSManish Narani * @hw: Pointer to the hardware clock structure. 694a5c8b2aeSManish Narani * @degrees The clock phase shift between 0 - 359. 695a5c8b2aeSManish Narani * Return: 0 on success and error value on error 696a5c8b2aeSManish Narani */ 697a5c8b2aeSManish Narani static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees) 698a5c8b2aeSManish Narani 699a5c8b2aeSManish Narani { 700a5c8b2aeSManish Narani struct sdhci_arasan_clk_data *clk_data = 701a5c8b2aeSManish Narani container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw); 702a5c8b2aeSManish Narani struct sdhci_arasan_data *sdhci_arasan = 703a5c8b2aeSManish Narani container_of(clk_data, struct sdhci_arasan_data, clk_data); 704a5c8b2aeSManish Narani struct sdhci_host *host = sdhci_arasan->host; 705a5c8b2aeSManish Narani struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data = 706a5c8b2aeSManish Narani clk_data->clk_of_data; 707a5c8b2aeSManish Narani const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops; 708a5c8b2aeSManish Narani const char *clk_name = clk_hw_get_name(hw); 709a5c8b2aeSManish Narani u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1; 710a5c8b2aeSManish Narani u8 tap_delay, tap_max = 0; 711a5c8b2aeSManish Narani int ret; 712a5c8b2aeSManish Narani 713a5c8b2aeSManish Narani /* 714a5c8b2aeSManish Narani * This is applicable for SDHCI_SPEC_300 and above 715a5c8b2aeSManish Narani * ZynqMP does not set phase for <=25MHz clock. 716a5c8b2aeSManish Narani * If degrees is zero, no need to do anything. 717a5c8b2aeSManish Narani */ 718a5c8b2aeSManish Narani if (host->version < SDHCI_SPEC_300 || 719a5c8b2aeSManish Narani host->timing == MMC_TIMING_LEGACY || 720a5c8b2aeSManish Narani host->timing == MMC_TIMING_UHS_SDR12 || !degrees) 721a5c8b2aeSManish Narani return 0; 722a5c8b2aeSManish Narani 723a5c8b2aeSManish Narani switch (host->timing) { 724a5c8b2aeSManish Narani case MMC_TIMING_MMC_HS: 725a5c8b2aeSManish Narani case MMC_TIMING_SD_HS: 726a5c8b2aeSManish Narani case MMC_TIMING_UHS_SDR25: 727a5c8b2aeSManish Narani case MMC_TIMING_UHS_DDR50: 728a5c8b2aeSManish Narani case MMC_TIMING_MMC_DDR52: 729a5c8b2aeSManish Narani /* For 50MHz clock, 120 Taps are available */ 730a5c8b2aeSManish Narani tap_max = 120; 731a5c8b2aeSManish Narani break; 732a5c8b2aeSManish Narani case MMC_TIMING_UHS_SDR50: 733a5c8b2aeSManish Narani /* For 100MHz clock, 60 Taps are available */ 734a5c8b2aeSManish Narani tap_max = 60; 735a5c8b2aeSManish Narani break; 736a5c8b2aeSManish Narani case MMC_TIMING_UHS_SDR104: 737a5c8b2aeSManish Narani case MMC_TIMING_MMC_HS200: 738a5c8b2aeSManish Narani /* For 200MHz clock, 30 Taps are available */ 739a5c8b2aeSManish Narani tap_max = 30; 740a5c8b2aeSManish Narani default: 741a5c8b2aeSManish Narani break; 742a5c8b2aeSManish Narani } 743a5c8b2aeSManish Narani 744a5c8b2aeSManish Narani tap_delay = (degrees * tap_max) / 360; 745a5c8b2aeSManish Narani 746a5c8b2aeSManish Narani /* Set the Clock Phase */ 747a5c8b2aeSManish Narani ret = eemi_ops->ioctl(node_id, IOCTL_SET_SD_TAPDELAY, 748a5c8b2aeSManish Narani PM_TAPDELAY_INPUT, tap_delay, NULL); 749a5c8b2aeSManish Narani if (ret) 750a5c8b2aeSManish Narani pr_err("Error setting Input Tap Delay\n"); 751a5c8b2aeSManish Narani 752a5c8b2aeSManish Narani return ret; 753a5c8b2aeSManish Narani } 754a5c8b2aeSManish Narani 755a5c8b2aeSManish Narani static const struct clk_ops zynqmp_sampleclk_ops = { 756a5c8b2aeSManish Narani .recalc_rate = sdhci_arasan_sampleclk_recalc_rate, 757a5c8b2aeSManish Narani .set_phase = sdhci_zynqmp_sampleclk_set_phase, 758a5c8b2aeSManish Narani }; 759a5c8b2aeSManish Narani 7608d2e3343SManish Narani static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid) 7618d2e3343SManish Narani { 7628d2e3343SManish Narani struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 7638d2e3343SManish Narani struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 7648d2e3343SManish Narani struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data = 7658d2e3343SManish Narani sdhci_arasan->clk_data.clk_of_data; 7668d2e3343SManish Narani const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops; 7678d2e3343SManish Narani u16 clk; 7688d2e3343SManish Narani 7698d2e3343SManish Narani clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 7708d2e3343SManish Narani clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN); 7718d2e3343SManish Narani sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 7728d2e3343SManish Narani 7738d2e3343SManish Narani /* Issue DLL Reset */ 7748d2e3343SManish Narani eemi_ops->ioctl(deviceid, IOCTL_SD_DLL_RESET, 7758d2e3343SManish Narani PM_DLL_RESET_PULSE, 0, NULL); 7768d2e3343SManish Narani 7778d2e3343SManish Narani clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 7788d2e3343SManish Narani 7798d2e3343SManish Narani sdhci_enable_clk(host, clk); 7808d2e3343SManish Narani } 7818d2e3343SManish Narani 7828d2e3343SManish Narani static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode) 7838d2e3343SManish Narani { 7848d2e3343SManish Narani struct sdhci_host *host = mmc_priv(mmc); 7858d2e3343SManish Narani struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 7868d2e3343SManish Narani struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 7878d2e3343SManish Narani struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw; 7888d2e3343SManish Narani const char *clk_name = clk_hw_get_name(hw); 7898d2e3343SManish Narani u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : 7908d2e3343SManish Narani NODE_SD_1; 7918d2e3343SManish Narani int err; 7928d2e3343SManish Narani 7938d2e3343SManish Narani arasan_zynqmp_dll_reset(host, device_id); 7948d2e3343SManish Narani 7958d2e3343SManish Narani err = sdhci_execute_tuning(mmc, opcode); 7968d2e3343SManish Narani if (err) 7978d2e3343SManish Narani return err; 7988d2e3343SManish Narani 7998d2e3343SManish Narani arasan_zynqmp_dll_reset(host, device_id); 8008d2e3343SManish Narani 8018d2e3343SManish Narani return 0; 8028d2e3343SManish Narani } 8038d2e3343SManish Narani 804a5c8b2aeSManish Narani /** 805b2ca77c9SShawn Lin * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier 806b2ca77c9SShawn Lin * 807b2ca77c9SShawn Lin * The corecfg_clockmultiplier is supposed to contain clock multiplier 808b2ca77c9SShawn Lin * value of programmable clock generator. 809b2ca77c9SShawn Lin * 810b2ca77c9SShawn Lin * NOTES: 811b2ca77c9SShawn Lin * - Many existing devices don't seem to do this and work fine. To keep 812b2ca77c9SShawn Lin * compatibility for old hardware where the device tree doesn't provide a 813b2ca77c9SShawn Lin * register map, this function is a noop if a soc_ctl_map hasn't been provided 814b2ca77c9SShawn Lin * for this platform. 815b2ca77c9SShawn Lin * - The value of corecfg_clockmultiplier should sync with that of corresponding 816b2ca77c9SShawn Lin * value reading from sdhci_capability_register. So this function is called 817b2ca77c9SShawn Lin * once at probe time and never called again. 818b2ca77c9SShawn Lin * 819b2ca77c9SShawn Lin * @host: The sdhci_host 820b2ca77c9SShawn Lin */ 821b2ca77c9SShawn Lin static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host, 822b2ca77c9SShawn Lin u32 value) 823b2ca77c9SShawn Lin { 824b2ca77c9SShawn Lin struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 825b2ca77c9SShawn Lin struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 826b2ca77c9SShawn Lin const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = 827b2ca77c9SShawn Lin sdhci_arasan->soc_ctl_map; 828b2ca77c9SShawn Lin 829b2ca77c9SShawn Lin /* Having a map is optional */ 830b2ca77c9SShawn Lin if (!soc_ctl_map) 831b2ca77c9SShawn Lin return; 832b2ca77c9SShawn Lin 833b2ca77c9SShawn Lin /* If we have a map, we expect to have a syscon */ 834b2ca77c9SShawn Lin if (!sdhci_arasan->soc_ctl_base) { 835b2ca77c9SShawn Lin pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", 836b2ca77c9SShawn Lin mmc_hostname(host->mmc)); 837b2ca77c9SShawn Lin return; 838b2ca77c9SShawn Lin } 839b2ca77c9SShawn Lin 840b2ca77c9SShawn Lin sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value); 841b2ca77c9SShawn Lin } 842b2ca77c9SShawn Lin 843b2ca77c9SShawn Lin /** 8443ea4666eSDouglas Anderson * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq 8453ea4666eSDouglas Anderson * 8463ea4666eSDouglas Anderson * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This 8473ea4666eSDouglas Anderson * function can be used to make that happen. 8483ea4666eSDouglas Anderson * 8493ea4666eSDouglas Anderson * NOTES: 8503ea4666eSDouglas Anderson * - Many existing devices don't seem to do this and work fine. To keep 8513ea4666eSDouglas Anderson * compatibility for old hardware where the device tree doesn't provide a 8523ea4666eSDouglas Anderson * register map, this function is a noop if a soc_ctl_map hasn't been provided 8533ea4666eSDouglas Anderson * for this platform. 8543ea4666eSDouglas Anderson * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider 8553ea4666eSDouglas Anderson * to achieve lower clock rates. That means that this function is called once 8563ea4666eSDouglas Anderson * at probe time and never called again. 8573ea4666eSDouglas Anderson * 8583ea4666eSDouglas Anderson * @host: The sdhci_host 8593ea4666eSDouglas Anderson */ 8603ea4666eSDouglas Anderson static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) 8613ea4666eSDouglas Anderson { 8623ea4666eSDouglas Anderson struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 8633ea4666eSDouglas Anderson struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 8643ea4666eSDouglas Anderson const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = 8653ea4666eSDouglas Anderson sdhci_arasan->soc_ctl_map; 8663ea4666eSDouglas Anderson u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000); 8673ea4666eSDouglas Anderson 8683ea4666eSDouglas Anderson /* Having a map is optional */ 8693ea4666eSDouglas Anderson if (!soc_ctl_map) 8703ea4666eSDouglas Anderson return; 8713ea4666eSDouglas Anderson 8723ea4666eSDouglas Anderson /* If we have a map, we expect to have a syscon */ 8733ea4666eSDouglas Anderson if (!sdhci_arasan->soc_ctl_base) { 8743ea4666eSDouglas Anderson pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", 8753ea4666eSDouglas Anderson mmc_hostname(host->mmc)); 8763ea4666eSDouglas Anderson return; 8773ea4666eSDouglas Anderson } 8783ea4666eSDouglas Anderson 8793ea4666eSDouglas Anderson sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); 8803ea4666eSDouglas Anderson } 8813ea4666eSDouglas Anderson 882f3dafc37SManish Narani static void sdhci_arasan_set_clk_delays(struct sdhci_host *host) 883f3dafc37SManish Narani { 884f3dafc37SManish Narani struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 885f3dafc37SManish Narani struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 886f3dafc37SManish Narani struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; 887f3dafc37SManish Narani 888f3dafc37SManish Narani clk_set_phase(clk_data->sampleclk, 889f3dafc37SManish Narani clk_data->clk_phase_in[host->timing]); 890f3dafc37SManish Narani clk_set_phase(clk_data->sdcardclk, 891f3dafc37SManish Narani clk_data->clk_phase_out[host->timing]); 892f3dafc37SManish Narani } 893f3dafc37SManish Narani 894f3dafc37SManish Narani static void arasan_dt_read_clk_phase(struct device *dev, 895f3dafc37SManish Narani struct sdhci_arasan_clk_data *clk_data, 896f3dafc37SManish Narani unsigned int timing, const char *prop) 897f3dafc37SManish Narani { 898f3dafc37SManish Narani struct device_node *np = dev->of_node; 899f3dafc37SManish Narani 900f3dafc37SManish Narani int clk_phase[2] = {0}; 901f3dafc37SManish Narani 902f3dafc37SManish Narani /* 903f3dafc37SManish Narani * Read Tap Delay values from DT, if the DT does not contain the 904f3dafc37SManish Narani * Tap Values then use the pre-defined values. 905f3dafc37SManish Narani */ 906f3dafc37SManish Narani if (of_property_read_variable_u32_array(np, prop, &clk_phase[0], 907f3dafc37SManish Narani 2, 0)) { 908f3dafc37SManish Narani dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n", 909f3dafc37SManish Narani prop, clk_data->clk_phase_in[timing], 910f3dafc37SManish Narani clk_data->clk_phase_out[timing]); 911f3dafc37SManish Narani return; 912f3dafc37SManish Narani } 913f3dafc37SManish Narani 914f3dafc37SManish Narani /* The values read are Input and Output Clock Delays in order */ 915f3dafc37SManish Narani clk_data->clk_phase_in[timing] = clk_phase[0]; 916f3dafc37SManish Narani clk_data->clk_phase_out[timing] = clk_phase[1]; 917f3dafc37SManish Narani } 918f3dafc37SManish Narani 919f3dafc37SManish Narani /** 920f3dafc37SManish Narani * arasan_dt_parse_clk_phases - Read Clock Delay values from DT 921f3dafc37SManish Narani * 922f3dafc37SManish Narani * Called at initialization to parse the values of Clock Delays. 923f3dafc37SManish Narani * 924f3dafc37SManish Narani * @dev: Pointer to our struct device. 925f3dafc37SManish Narani * @clk_data: Pointer to the Clock Data structure 926f3dafc37SManish Narani */ 927f3dafc37SManish Narani static void arasan_dt_parse_clk_phases(struct device *dev, 928f3dafc37SManish Narani struct sdhci_arasan_clk_data *clk_data) 929f3dafc37SManish Narani { 930a5c8b2aeSManish Narani int *iclk_phase, *oclk_phase; 931a5c8b2aeSManish Narani u32 mio_bank = 0; 932a5c8b2aeSManish Narani int i; 933a5c8b2aeSManish Narani 934f3dafc37SManish Narani /* 935f3dafc37SManish Narani * This has been kept as a pointer and is assigned a function here. 936f3dafc37SManish Narani * So that different controller variants can assign their own handling 937f3dafc37SManish Narani * function. 938f3dafc37SManish Narani */ 939f3dafc37SManish Narani clk_data->set_clk_delays = sdhci_arasan_set_clk_delays; 940f3dafc37SManish Narani 941a5c8b2aeSManish Narani if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) { 942a5c8b2aeSManish Narani iclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_ICLK_PHASE; 943a5c8b2aeSManish Narani oclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_OCLK_PHASE; 944a5c8b2aeSManish Narani 945a5c8b2aeSManish Narani of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank); 946a5c8b2aeSManish Narani if (mio_bank == 2) { 947a5c8b2aeSManish Narani oclk_phase[MMC_TIMING_UHS_SDR104] = 90; 948a5c8b2aeSManish Narani oclk_phase[MMC_TIMING_MMC_HS200] = 90; 949a5c8b2aeSManish Narani } 950a5c8b2aeSManish Narani 951a5c8b2aeSManish Narani for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { 952a5c8b2aeSManish Narani clk_data->clk_phase_in[i] = iclk_phase[i]; 953a5c8b2aeSManish Narani clk_data->clk_phase_out[i] = oclk_phase[i]; 954a5c8b2aeSManish Narani } 955a5c8b2aeSManish Narani } 956a5c8b2aeSManish Narani 957f3dafc37SManish Narani arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY, 958f3dafc37SManish Narani "clk-phase-legacy"); 959f3dafc37SManish Narani arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS, 960f3dafc37SManish Narani "clk-phase-mmc-hs"); 961f3dafc37SManish Narani arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS, 962f3dafc37SManish Narani "clk-phase-sd-hs"); 963f3dafc37SManish Narani arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12, 964f3dafc37SManish Narani "clk-phase-uhs-sdr12"); 965f3dafc37SManish Narani arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25, 966f3dafc37SManish Narani "clk-phase-uhs-sdr25"); 967f3dafc37SManish Narani arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50, 968f3dafc37SManish Narani "clk-phase-uhs-sdr50"); 969f3dafc37SManish Narani arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104, 970f3dafc37SManish Narani "clk-phase-uhs-sdr104"); 971f3dafc37SManish Narani arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50, 972f3dafc37SManish Narani "clk-phase-uhs-ddr50"); 973f3dafc37SManish Narani arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52, 974f3dafc37SManish Narani "clk-phase-mmc-ddr52"); 975f3dafc37SManish Narani arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200, 976f3dafc37SManish Narani "clk-phase-mmc-hs200"); 977f3dafc37SManish Narani arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400, 978f3dafc37SManish Narani "clk-phase-mmc-hs400"); 979f3dafc37SManish Narani } 980f3dafc37SManish Narani 981c390f211SDouglas Anderson /** 98207a14d1dSManish Narani * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use 983c390f211SDouglas Anderson * 984c390f211SDouglas Anderson * Some PHY devices need to know what the actual card clock is. In order for 985c390f211SDouglas Anderson * them to find out, we'll provide a clock through the common clock framework 986c390f211SDouglas Anderson * for them to query. 987c390f211SDouglas Anderson * 988c390f211SDouglas Anderson * @sdhci_arasan: Our private data structure. 989c390f211SDouglas Anderson * @clk_xin: Pointer to the functional clock 990c390f211SDouglas Anderson * @dev: Pointer to our struct device. 991c390f211SDouglas Anderson * Returns 0 on success and error value on error 992c390f211SDouglas Anderson */ 99307a14d1dSManish Narani static int 99407a14d1dSManish Narani sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan, 995c390f211SDouglas Anderson struct clk *clk_xin, 996c390f211SDouglas Anderson struct device *dev) 997c390f211SDouglas Anderson { 998e1463618SManish Narani struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; 999c390f211SDouglas Anderson struct device_node *np = dev->of_node; 1000c390f211SDouglas Anderson struct clk_init_data sdcardclk_init; 1001c390f211SDouglas Anderson const char *parent_clk_name; 1002c390f211SDouglas Anderson int ret; 1003c390f211SDouglas Anderson 1004c390f211SDouglas Anderson ret = of_property_read_string_index(np, "clock-output-names", 0, 1005c390f211SDouglas Anderson &sdcardclk_init.name); 1006c390f211SDouglas Anderson if (ret) { 1007c390f211SDouglas Anderson dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); 1008c390f211SDouglas Anderson return ret; 1009c390f211SDouglas Anderson } 1010c390f211SDouglas Anderson 1011c390f211SDouglas Anderson parent_clk_name = __clk_get_name(clk_xin); 1012c390f211SDouglas Anderson sdcardclk_init.parent_names = &parent_clk_name; 1013c390f211SDouglas Anderson sdcardclk_init.num_parents = 1; 1014c390f211SDouglas Anderson sdcardclk_init.flags = CLK_GET_RATE_NOCACHE; 1015a5c8b2aeSManish Narani if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) 1016a5c8b2aeSManish Narani sdcardclk_init.ops = &zynqmp_sdcardclk_ops; 1017a5c8b2aeSManish Narani else 1018c390f211SDouglas Anderson sdcardclk_init.ops = &arasan_sdcardclk_ops; 1019c390f211SDouglas Anderson 1020e1463618SManish Narani clk_data->sdcardclk_hw.init = &sdcardclk_init; 1021e1463618SManish Narani clk_data->sdcardclk = 1022e1463618SManish Narani devm_clk_register(dev, &clk_data->sdcardclk_hw); 1023e1463618SManish Narani clk_data->sdcardclk_hw.init = NULL; 1024c390f211SDouglas Anderson 1025c390f211SDouglas Anderson ret = of_clk_add_provider(np, of_clk_src_simple_get, 1026e1463618SManish Narani clk_data->sdcardclk); 1027c390f211SDouglas Anderson if (ret) 102807a14d1dSManish Narani dev_err(dev, "Failed to add sdcard clock provider\n"); 102907a14d1dSManish Narani 103007a14d1dSManish Narani return ret; 103107a14d1dSManish Narani } 103207a14d1dSManish Narani 103307a14d1dSManish Narani /** 103407a14d1dSManish Narani * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use 103507a14d1dSManish Narani * 103607a14d1dSManish Narani * Some PHY devices need to know what the actual card clock is. In order for 103707a14d1dSManish Narani * them to find out, we'll provide a clock through the common clock framework 103807a14d1dSManish Narani * for them to query. 103907a14d1dSManish Narani * 104007a14d1dSManish Narani * @sdhci_arasan: Our private data structure. 104107a14d1dSManish Narani * @clk_xin: Pointer to the functional clock 104207a14d1dSManish Narani * @dev: Pointer to our struct device. 104307a14d1dSManish Narani * Returns 0 on success and error value on error 104407a14d1dSManish Narani */ 104507a14d1dSManish Narani static int 104607a14d1dSManish Narani sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan, 104707a14d1dSManish Narani struct clk *clk_xin, 104807a14d1dSManish Narani struct device *dev) 104907a14d1dSManish Narani { 105007a14d1dSManish Narani struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; 105107a14d1dSManish Narani struct device_node *np = dev->of_node; 105207a14d1dSManish Narani struct clk_init_data sampleclk_init; 105307a14d1dSManish Narani const char *parent_clk_name; 105407a14d1dSManish Narani int ret; 105507a14d1dSManish Narani 105607a14d1dSManish Narani ret = of_property_read_string_index(np, "clock-output-names", 1, 105707a14d1dSManish Narani &sampleclk_init.name); 105807a14d1dSManish Narani if (ret) { 105907a14d1dSManish Narani dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); 106007a14d1dSManish Narani return ret; 106107a14d1dSManish Narani } 106207a14d1dSManish Narani 106307a14d1dSManish Narani parent_clk_name = __clk_get_name(clk_xin); 106407a14d1dSManish Narani sampleclk_init.parent_names = &parent_clk_name; 106507a14d1dSManish Narani sampleclk_init.num_parents = 1; 106607a14d1dSManish Narani sampleclk_init.flags = CLK_GET_RATE_NOCACHE; 1067a5c8b2aeSManish Narani if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) 1068a5c8b2aeSManish Narani sampleclk_init.ops = &zynqmp_sampleclk_ops; 1069a5c8b2aeSManish Narani else 107007a14d1dSManish Narani sampleclk_init.ops = &arasan_sampleclk_ops; 107107a14d1dSManish Narani 107207a14d1dSManish Narani clk_data->sampleclk_hw.init = &sampleclk_init; 107307a14d1dSManish Narani clk_data->sampleclk = 107407a14d1dSManish Narani devm_clk_register(dev, &clk_data->sampleclk_hw); 107507a14d1dSManish Narani clk_data->sampleclk_hw.init = NULL; 107607a14d1dSManish Narani 107707a14d1dSManish Narani ret = of_clk_add_provider(np, of_clk_src_simple_get, 107807a14d1dSManish Narani clk_data->sampleclk); 107907a14d1dSManish Narani if (ret) 108007a14d1dSManish Narani dev_err(dev, "Failed to add sample clock provider\n"); 1081c390f211SDouglas Anderson 1082c390f211SDouglas Anderson return ret; 1083c390f211SDouglas Anderson } 1084c390f211SDouglas Anderson 1085c390f211SDouglas Anderson /** 1086c390f211SDouglas Anderson * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk() 1087c390f211SDouglas Anderson * 1088c390f211SDouglas Anderson * Should be called any time we're exiting and sdhci_arasan_register_sdclk() 1089c390f211SDouglas Anderson * returned success. 1090c390f211SDouglas Anderson * 1091c390f211SDouglas Anderson * @dev: Pointer to our struct device. 1092c390f211SDouglas Anderson */ 1093c390f211SDouglas Anderson static void sdhci_arasan_unregister_sdclk(struct device *dev) 1094c390f211SDouglas Anderson { 1095c390f211SDouglas Anderson struct device_node *np = dev->of_node; 1096c390f211SDouglas Anderson 1097c390f211SDouglas Anderson if (!of_find_property(np, "#clock-cells", NULL)) 1098c390f211SDouglas Anderson return; 1099c390f211SDouglas Anderson 1100c390f211SDouglas Anderson of_clk_del_provider(dev->of_node); 1101c390f211SDouglas Anderson } 1102c390f211SDouglas Anderson 110307a14d1dSManish Narani /** 110407a14d1dSManish Narani * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use 110507a14d1dSManish Narani * 110607a14d1dSManish Narani * Some PHY devices need to know what the actual card clock is. In order for 110707a14d1dSManish Narani * them to find out, we'll provide a clock through the common clock framework 110807a14d1dSManish Narani * for them to query. 110907a14d1dSManish Narani * 111007a14d1dSManish Narani * Note: without seriously re-architecting SDHCI's clock code and testing on 111107a14d1dSManish Narani * all platforms, there's no way to create a totally beautiful clock here 111207a14d1dSManish Narani * with all clock ops implemented. Instead, we'll just create a clock that can 111307a14d1dSManish Narani * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock 111407a14d1dSManish Narani * framework that we're doing things behind its back. This should be sufficient 111507a14d1dSManish Narani * to create nice clean device tree bindings and later (if needed) we can try 111607a14d1dSManish Narani * re-architecting SDHCI if we see some benefit to it. 111707a14d1dSManish Narani * 111807a14d1dSManish Narani * @sdhci_arasan: Our private data structure. 111907a14d1dSManish Narani * @clk_xin: Pointer to the functional clock 112007a14d1dSManish Narani * @dev: Pointer to our struct device. 112107a14d1dSManish Narani * Returns 0 on success and error value on error 112207a14d1dSManish Narani */ 112307a14d1dSManish Narani static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, 112407a14d1dSManish Narani struct clk *clk_xin, 112507a14d1dSManish Narani struct device *dev) 112607a14d1dSManish Narani { 112707a14d1dSManish Narani struct device_node *np = dev->of_node; 112807a14d1dSManish Narani u32 num_clks = 0; 112907a14d1dSManish Narani int ret; 113007a14d1dSManish Narani 113107a14d1dSManish Narani /* Providing a clock to the PHY is optional; no error if missing */ 113207a14d1dSManish Narani if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0) 113307a14d1dSManish Narani return 0; 113407a14d1dSManish Narani 113507a14d1dSManish Narani ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev); 113607a14d1dSManish Narani if (ret) 113707a14d1dSManish Narani return ret; 113807a14d1dSManish Narani 113907a14d1dSManish Narani if (num_clks) { 114007a14d1dSManish Narani ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin, 114107a14d1dSManish Narani dev); 114207a14d1dSManish Narani if (ret) { 114307a14d1dSManish Narani sdhci_arasan_unregister_sdclk(dev); 114407a14d1dSManish Narani return ret; 114507a14d1dSManish Narani } 114607a14d1dSManish Narani } 114707a14d1dSManish Narani 114807a14d1dSManish Narani return 0; 114907a14d1dSManish Narani } 115007a14d1dSManish Narani 115184362d79SShawn Lin static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan) 115284362d79SShawn Lin { 115384362d79SShawn Lin struct sdhci_host *host = sdhci_arasan->host; 115484362d79SShawn Lin struct cqhci_host *cq_host; 115584362d79SShawn Lin bool dma64; 115684362d79SShawn Lin int ret; 115784362d79SShawn Lin 115884362d79SShawn Lin if (!sdhci_arasan->has_cqe) 115984362d79SShawn Lin return sdhci_add_host(host); 116084362d79SShawn Lin 116184362d79SShawn Lin ret = sdhci_setup_host(host); 116284362d79SShawn Lin if (ret) 116384362d79SShawn Lin return ret; 116484362d79SShawn Lin 116584362d79SShawn Lin cq_host = devm_kzalloc(host->mmc->parent, 116684362d79SShawn Lin sizeof(*cq_host), GFP_KERNEL); 116784362d79SShawn Lin if (!cq_host) { 116884362d79SShawn Lin ret = -ENOMEM; 116984362d79SShawn Lin goto cleanup; 117084362d79SShawn Lin } 117184362d79SShawn Lin 117284362d79SShawn Lin cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; 117384362d79SShawn Lin cq_host->ops = &sdhci_arasan_cqhci_ops; 117484362d79SShawn Lin 117584362d79SShawn Lin dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 117684362d79SShawn Lin if (dma64) 117784362d79SShawn Lin cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 117884362d79SShawn Lin 117984362d79SShawn Lin ret = cqhci_init(cq_host, host->mmc, dma64); 118084362d79SShawn Lin if (ret) 118184362d79SShawn Lin goto cleanup; 118284362d79SShawn Lin 118384362d79SShawn Lin ret = __sdhci_add_host(host); 118484362d79SShawn Lin if (ret) 118584362d79SShawn Lin goto cleanup; 118684362d79SShawn Lin 118784362d79SShawn Lin return 0; 118884362d79SShawn Lin 118984362d79SShawn Lin cleanup: 119084362d79SShawn Lin sdhci_cleanup_host(host); 119184362d79SShawn Lin return ret; 119284362d79SShawn Lin } 119384362d79SShawn Lin 1194e3ec3a3dSSoren Brinkmann static int sdhci_arasan_probe(struct platform_device *pdev) 1195e3ec3a3dSSoren Brinkmann { 1196e3ec3a3dSSoren Brinkmann int ret; 11973ea4666eSDouglas Anderson const struct of_device_id *match; 11983ea4666eSDouglas Anderson struct device_node *node; 1199e3ec3a3dSSoren Brinkmann struct clk *clk_xin; 1200e3ec3a3dSSoren Brinkmann struct sdhci_host *host; 1201e3ec3a3dSSoren Brinkmann struct sdhci_pltfm_host *pltfm_host; 1202e3ec3a3dSSoren Brinkmann struct sdhci_arasan_data *sdhci_arasan; 12033794c542SZach Brown struct device_node *np = pdev->dev.of_node; 120406b23ca0SFaiz Abbas const struct sdhci_arasan_of_data *data; 1205e3ec3a3dSSoren Brinkmann 120606b23ca0SFaiz Abbas match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node); 120706b23ca0SFaiz Abbas data = match->data; 120806b23ca0SFaiz Abbas host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan)); 120984362d79SShawn Lin 121089211418SJisheng Zhang if (IS_ERR(host)) 121189211418SJisheng Zhang return PTR_ERR(host); 121289211418SJisheng Zhang 121389211418SJisheng Zhang pltfm_host = sdhci_priv(host); 121489211418SJisheng Zhang sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 1215c390f211SDouglas Anderson sdhci_arasan->host = host; 1216e3ec3a3dSSoren Brinkmann 121706b23ca0SFaiz Abbas sdhci_arasan->soc_ctl_map = data->soc_ctl_map; 12183ea4666eSDouglas Anderson 12193ea4666eSDouglas Anderson node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0); 12203ea4666eSDouglas Anderson if (node) { 12213ea4666eSDouglas Anderson sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); 12223ea4666eSDouglas Anderson of_node_put(node); 12233ea4666eSDouglas Anderson 12243ea4666eSDouglas Anderson if (IS_ERR(sdhci_arasan->soc_ctl_base)) { 12253ea4666eSDouglas Anderson ret = PTR_ERR(sdhci_arasan->soc_ctl_base); 12263ea4666eSDouglas Anderson if (ret != -EPROBE_DEFER) 12273ea4666eSDouglas Anderson dev_err(&pdev->dev, "Can't get syscon: %d\n", 12283ea4666eSDouglas Anderson ret); 12293ea4666eSDouglas Anderson goto err_pltfm_free; 12303ea4666eSDouglas Anderson } 12313ea4666eSDouglas Anderson } 12323ea4666eSDouglas Anderson 1233e3ec3a3dSSoren Brinkmann sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb"); 1234e3ec3a3dSSoren Brinkmann if (IS_ERR(sdhci_arasan->clk_ahb)) { 1235e3ec3a3dSSoren Brinkmann dev_err(&pdev->dev, "clk_ahb clock not found.\n"); 1236278d0962SShawn Lin ret = PTR_ERR(sdhci_arasan->clk_ahb); 1237278d0962SShawn Lin goto err_pltfm_free; 1238e3ec3a3dSSoren Brinkmann } 1239e3ec3a3dSSoren Brinkmann 1240e3ec3a3dSSoren Brinkmann clk_xin = devm_clk_get(&pdev->dev, "clk_xin"); 1241e3ec3a3dSSoren Brinkmann if (IS_ERR(clk_xin)) { 1242e3ec3a3dSSoren Brinkmann dev_err(&pdev->dev, "clk_xin clock not found.\n"); 1243278d0962SShawn Lin ret = PTR_ERR(clk_xin); 1244278d0962SShawn Lin goto err_pltfm_free; 1245e3ec3a3dSSoren Brinkmann } 1246e3ec3a3dSSoren Brinkmann 1247e3ec3a3dSSoren Brinkmann ret = clk_prepare_enable(sdhci_arasan->clk_ahb); 1248e3ec3a3dSSoren Brinkmann if (ret) { 1249e3ec3a3dSSoren Brinkmann dev_err(&pdev->dev, "Unable to enable AHB clock.\n"); 1250278d0962SShawn Lin goto err_pltfm_free; 1251e3ec3a3dSSoren Brinkmann } 1252e3ec3a3dSSoren Brinkmann 1253e3ec3a3dSSoren Brinkmann ret = clk_prepare_enable(clk_xin); 1254e3ec3a3dSSoren Brinkmann if (ret) { 1255e3ec3a3dSSoren Brinkmann dev_err(&pdev->dev, "Unable to enable SD clock.\n"); 1256e3ec3a3dSSoren Brinkmann goto clk_dis_ahb; 1257e3ec3a3dSSoren Brinkmann } 1258e3ec3a3dSSoren Brinkmann 1259e3ec3a3dSSoren Brinkmann sdhci_get_of_property(pdev); 12603794c542SZach Brown 12613794c542SZach Brown if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) 12623794c542SZach Brown sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; 12633794c542SZach Brown 12643f2c7d5dSHelmut Grohne if (of_property_read_bool(np, "xlnx,int-clock-stable-broken")) 12653f2c7d5dSHelmut Grohne sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE; 12663f2c7d5dSHelmut Grohne 1267e3ec3a3dSSoren Brinkmann pltfm_host->clk = clk_xin; 1268e3ec3a3dSSoren Brinkmann 1269b2ca77c9SShawn Lin if (of_device_is_compatible(pdev->dev.of_node, 1270b2ca77c9SShawn Lin "rockchip,rk3399-sdhci-5.1")) 1271b2ca77c9SShawn Lin sdhci_arasan_update_clockmultiplier(host, 0x0); 1272b2ca77c9SShawn Lin 12733ea4666eSDouglas Anderson sdhci_arasan_update_baseclkfreq(host); 12743ea4666eSDouglas Anderson 1275c390f211SDouglas Anderson ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev); 1276c390f211SDouglas Anderson if (ret) 1277c390f211SDouglas Anderson goto clk_disable_all; 1278c390f211SDouglas Anderson 1279a5c8b2aeSManish Narani if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { 1280a5c8b2aeSManish Narani struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data; 1281a5c8b2aeSManish Narani const struct zynqmp_eemi_ops *eemi_ops; 1282a5c8b2aeSManish Narani 1283a5c8b2aeSManish Narani zynqmp_clk_data = devm_kzalloc(&pdev->dev, 1284a5c8b2aeSManish Narani sizeof(*zynqmp_clk_data), 1285a5c8b2aeSManish Narani GFP_KERNEL); 1286a5c8b2aeSManish Narani eemi_ops = zynqmp_pm_get_eemi_ops(); 1287a5c8b2aeSManish Narani if (IS_ERR(eemi_ops)) { 1288a5c8b2aeSManish Narani ret = PTR_ERR(eemi_ops); 1289a5c8b2aeSManish Narani goto unreg_clk; 1290a5c8b2aeSManish Narani } 1291a5c8b2aeSManish Narani 1292a5c8b2aeSManish Narani zynqmp_clk_data->eemi_ops = eemi_ops; 1293a5c8b2aeSManish Narani sdhci_arasan->clk_data.clk_of_data = zynqmp_clk_data; 12948d2e3343SManish Narani host->mmc_host_ops.execute_tuning = 12958d2e3343SManish Narani arasan_zynqmp_execute_tuning; 1296a5c8b2aeSManish Narani } 1297a5c8b2aeSManish Narani 1298f3dafc37SManish Narani arasan_dt_parse_clk_phases(&pdev->dev, &sdhci_arasan->clk_data); 1299f3dafc37SManish Narani 130016b23787SMichal Simek ret = mmc_of_parse(host->mmc); 130116b23787SMichal Simek if (ret) { 130260208a26SMichal Simek if (ret != -EPROBE_DEFER) 1303940e698cSShubhrajyoti Datta dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret); 1304c390f211SDouglas Anderson goto unreg_clk; 130516b23787SMichal Simek } 130616b23787SMichal Simek 130791aa3661SShawn Lin sdhci_arasan->phy = ERR_PTR(-ENODEV); 130891aa3661SShawn Lin if (of_device_is_compatible(pdev->dev.of_node, 130991aa3661SShawn Lin "arasan,sdhci-5.1")) { 131091aa3661SShawn Lin sdhci_arasan->phy = devm_phy_get(&pdev->dev, 131191aa3661SShawn Lin "phy_arasan"); 131291aa3661SShawn Lin if (IS_ERR(sdhci_arasan->phy)) { 131391aa3661SShawn Lin ret = PTR_ERR(sdhci_arasan->phy); 131491aa3661SShawn Lin dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n"); 1315c390f211SDouglas Anderson goto unreg_clk; 131691aa3661SShawn Lin } 131791aa3661SShawn Lin 131891aa3661SShawn Lin ret = phy_init(sdhci_arasan->phy); 131991aa3661SShawn Lin if (ret < 0) { 132091aa3661SShawn Lin dev_err(&pdev->dev, "phy_init err.\n"); 1321c390f211SDouglas Anderson goto unreg_clk; 132291aa3661SShawn Lin } 132391aa3661SShawn Lin 1324a05c8465SShawn Lin host->mmc_host_ops.hs400_enhanced_strobe = 1325a05c8465SShawn Lin sdhci_arasan_hs400_enhanced_strobe; 13268a3bee9bSShawn Lin host->mmc_host_ops.start_signal_voltage_switch = 13278a3bee9bSShawn Lin sdhci_arasan_voltage_switch; 132884362d79SShawn Lin sdhci_arasan->has_cqe = true; 13297bda9482SChristoph Muellner host->mmc->caps2 |= MMC_CAP2_CQE; 13307bda9482SChristoph Muellner 13317bda9482SChristoph Muellner if (!of_property_read_bool(np, "disable-cqe-dcmd")) 13327bda9482SChristoph Muellner host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 133391aa3661SShawn Lin } 133491aa3661SShawn Lin 133584362d79SShawn Lin ret = sdhci_arasan_add_host(sdhci_arasan); 1336b1df9de7SMike Looijmans if (ret) 133791aa3661SShawn Lin goto err_add_host; 1338e3ec3a3dSSoren Brinkmann 1339e3ec3a3dSSoren Brinkmann return 0; 1340e3ec3a3dSSoren Brinkmann 134191aa3661SShawn Lin err_add_host: 134291aa3661SShawn Lin if (!IS_ERR(sdhci_arasan->phy)) 134391aa3661SShawn Lin phy_exit(sdhci_arasan->phy); 1344c390f211SDouglas Anderson unreg_clk: 1345c390f211SDouglas Anderson sdhci_arasan_unregister_sdclk(&pdev->dev); 1346e3ec3a3dSSoren Brinkmann clk_disable_all: 1347e3ec3a3dSSoren Brinkmann clk_disable_unprepare(clk_xin); 1348e3ec3a3dSSoren Brinkmann clk_dis_ahb: 1349e3ec3a3dSSoren Brinkmann clk_disable_unprepare(sdhci_arasan->clk_ahb); 1350278d0962SShawn Lin err_pltfm_free: 1351278d0962SShawn Lin sdhci_pltfm_free(pdev); 1352e3ec3a3dSSoren Brinkmann return ret; 1353e3ec3a3dSSoren Brinkmann } 1354e3ec3a3dSSoren Brinkmann 1355e3ec3a3dSSoren Brinkmann static int sdhci_arasan_remove(struct platform_device *pdev) 1356e3ec3a3dSSoren Brinkmann { 13570c7fe32eSJisheng Zhang int ret; 1358e3ec3a3dSSoren Brinkmann struct sdhci_host *host = platform_get_drvdata(pdev); 1359e3ec3a3dSSoren Brinkmann struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 136089211418SJisheng Zhang struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 136189211418SJisheng Zhang struct clk *clk_ahb = sdhci_arasan->clk_ahb; 1362e3ec3a3dSSoren Brinkmann 136391aa3661SShawn Lin if (!IS_ERR(sdhci_arasan->phy)) { 1364b2db9c67SDouglas Anderson if (sdhci_arasan->is_phy_on) 136591aa3661SShawn Lin phy_power_off(sdhci_arasan->phy); 136691aa3661SShawn Lin phy_exit(sdhci_arasan->phy); 136791aa3661SShawn Lin } 136891aa3661SShawn Lin 1369c390f211SDouglas Anderson sdhci_arasan_unregister_sdclk(&pdev->dev); 1370c390f211SDouglas Anderson 13710c7fe32eSJisheng Zhang ret = sdhci_pltfm_unregister(pdev); 13720c7fe32eSJisheng Zhang 137389211418SJisheng Zhang clk_disable_unprepare(clk_ahb); 1374e3ec3a3dSSoren Brinkmann 13750c7fe32eSJisheng Zhang return ret; 1376e3ec3a3dSSoren Brinkmann } 1377e3ec3a3dSSoren Brinkmann 1378e3ec3a3dSSoren Brinkmann static struct platform_driver sdhci_arasan_driver = { 1379e3ec3a3dSSoren Brinkmann .driver = { 1380e3ec3a3dSSoren Brinkmann .name = "sdhci-arasan", 1381e3ec3a3dSSoren Brinkmann .of_match_table = sdhci_arasan_of_match, 1382e3ec3a3dSSoren Brinkmann .pm = &sdhci_arasan_dev_pm_ops, 1383e3ec3a3dSSoren Brinkmann }, 1384e3ec3a3dSSoren Brinkmann .probe = sdhci_arasan_probe, 1385e3ec3a3dSSoren Brinkmann .remove = sdhci_arasan_remove, 1386e3ec3a3dSSoren Brinkmann }; 1387e3ec3a3dSSoren Brinkmann 1388e3ec3a3dSSoren Brinkmann module_platform_driver(sdhci_arasan_driver); 1389e3ec3a3dSSoren Brinkmann 1390e3ec3a3dSSoren Brinkmann MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller"); 1391e3ec3a3dSSoren Brinkmann MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>"); 1392e3ec3a3dSSoren Brinkmann MODULE_LICENSE("GPL"); 1393