12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2e3ec3a3dSSoren Brinkmann /* 3e3ec3a3dSSoren Brinkmann * Arasan Secure Digital Host Controller Interface. 4e3ec3a3dSSoren Brinkmann * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu> 5e3ec3a3dSSoren Brinkmann * Copyright (c) 2012 Wind River Systems, Inc. 6e3ec3a3dSSoren Brinkmann * Copyright (C) 2013 Pengutronix e.K. 7e3ec3a3dSSoren Brinkmann * Copyright (C) 2013 Xilinx Inc. 8e3ec3a3dSSoren Brinkmann * 9e3ec3a3dSSoren Brinkmann * Based on sdhci-of-esdhc.c 10e3ec3a3dSSoren Brinkmann * 11e3ec3a3dSSoren Brinkmann * Copyright (c) 2007 Freescale Semiconductor, Inc. 12e3ec3a3dSSoren Brinkmann * Copyright (c) 2009 MontaVista Software, Inc. 13e3ec3a3dSSoren Brinkmann * 14e3ec3a3dSSoren Brinkmann * Authors: Xiaobo Xie <X.Xie@freescale.com> 15e3ec3a3dSSoren Brinkmann * Anton Vorontsov <avorontsov@ru.mvista.com> 16e3ec3a3dSSoren Brinkmann */ 17e3ec3a3dSSoren Brinkmann 18c390f211SDouglas Anderson #include <linux/clk-provider.h> 193ea4666eSDouglas Anderson #include <linux/mfd/syscon.h> 20e3ec3a3dSSoren Brinkmann #include <linux/module.h> 21308f3f8dSSuman Tripathi #include <linux/of_device.h> 2291aa3661SShawn Lin #include <linux/phy/phy.h> 233ea4666eSDouglas Anderson #include <linux/regmap.h> 243794c542SZach Brown #include <linux/of.h> 25e3ec3a3dSSoren Brinkmann 2684362d79SShawn Lin #include "cqhci.h" 2784362d79SShawn Lin #include "sdhci-pltfm.h" 28e3ec3a3dSSoren Brinkmann 2984362d79SShawn Lin #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 3084362d79SShawn Lin #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 31a05c8465SShawn Lin #define VENDOR_ENHANCED_STROBE BIT(0) 32e3ec3a3dSSoren Brinkmann 33b2db9c67SDouglas Anderson #define PHY_CLK_TOO_SLOW_HZ 400000 34b2db9c67SDouglas Anderson 353ea4666eSDouglas Anderson /* 363ea4666eSDouglas Anderson * On some SoCs the syscon area has a feature where the upper 16-bits of 373ea4666eSDouglas Anderson * each 32-bit register act as a write mask for the lower 16-bits. This allows 383ea4666eSDouglas Anderson * atomic updates of the register without locking. This macro is used on SoCs 393ea4666eSDouglas Anderson * that have that feature. 403ea4666eSDouglas Anderson */ 413ea4666eSDouglas Anderson #define HIWORD_UPDATE(val, mask, shift) \ 423ea4666eSDouglas Anderson ((val) << (shift) | (mask) << ((shift) + 16)) 433ea4666eSDouglas Anderson 443ea4666eSDouglas Anderson /** 453ea4666eSDouglas Anderson * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map 463ea4666eSDouglas Anderson * 473ea4666eSDouglas Anderson * @reg: Offset within the syscon of the register containing this field 483ea4666eSDouglas Anderson * @width: Number of bits for this field 493ea4666eSDouglas Anderson * @shift: Bit offset within @reg of this field (or -1 if not avail) 503ea4666eSDouglas Anderson */ 513ea4666eSDouglas Anderson struct sdhci_arasan_soc_ctl_field { 523ea4666eSDouglas Anderson u32 reg; 533ea4666eSDouglas Anderson u16 width; 543ea4666eSDouglas Anderson s16 shift; 553ea4666eSDouglas Anderson }; 563ea4666eSDouglas Anderson 573ea4666eSDouglas Anderson /** 583ea4666eSDouglas Anderson * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers 593ea4666eSDouglas Anderson * 603ea4666eSDouglas Anderson * It's up to the licensee of the Arsan IP block to make these available 613ea4666eSDouglas Anderson * somewhere if needed. Presumably these will be scattered somewhere that's 623ea4666eSDouglas Anderson * accessible via the syscon API. 633ea4666eSDouglas Anderson * 643ea4666eSDouglas Anderson * @baseclkfreq: Where to find corecfg_baseclkfreq 65b2ca77c9SShawn Lin * @clockmultiplier: Where to find corecfg_clockmultiplier 663ea4666eSDouglas Anderson * @hiword_update: If true, use HIWORD_UPDATE to access the syscon 673ea4666eSDouglas Anderson */ 683ea4666eSDouglas Anderson struct sdhci_arasan_soc_ctl_map { 693ea4666eSDouglas Anderson struct sdhci_arasan_soc_ctl_field baseclkfreq; 70b2ca77c9SShawn Lin struct sdhci_arasan_soc_ctl_field clockmultiplier; 713ea4666eSDouglas Anderson bool hiword_update; 723ea4666eSDouglas Anderson }; 733ea4666eSDouglas Anderson 74e3ec3a3dSSoren Brinkmann /** 75e3ec3a3dSSoren Brinkmann * struct sdhci_arasan_data 76c390f211SDouglas Anderson * @host: Pointer to the main SDHCI host structure. 77e3ec3a3dSSoren Brinkmann * @clk_ahb: Pointer to the AHB clock 7891aa3661SShawn Lin * @phy: Pointer to the generic phy 79b2db9c67SDouglas Anderson * @is_phy_on: True if the PHY is on; false if not. 80c390f211SDouglas Anderson * @sdcardclk_hw: Struct for the clock we might provide to a PHY. 81c390f211SDouglas Anderson * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. 823ea4666eSDouglas Anderson * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. 833ea4666eSDouglas Anderson * @soc_ctl_map: Map to get offsets into soc_ctl registers. 84e3ec3a3dSSoren Brinkmann */ 85e3ec3a3dSSoren Brinkmann struct sdhci_arasan_data { 86c390f211SDouglas Anderson struct sdhci_host *host; 87e3ec3a3dSSoren Brinkmann struct clk *clk_ahb; 8891aa3661SShawn Lin struct phy *phy; 89b2db9c67SDouglas Anderson bool is_phy_on; 903ea4666eSDouglas Anderson 9184362d79SShawn Lin bool has_cqe; 92c390f211SDouglas Anderson struct clk_hw sdcardclk_hw; 93c390f211SDouglas Anderson struct clk *sdcardclk; 94c390f211SDouglas Anderson 953ea4666eSDouglas Anderson struct regmap *soc_ctl_base; 963ea4666eSDouglas Anderson const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; 973794c542SZach Brown unsigned int quirks; /* Arasan deviations from spec */ 983794c542SZach Brown 993794c542SZach Brown /* Controller does not have CD wired and will not function normally without */ 1003794c542SZach Brown #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0) 1013f2c7d5dSHelmut Grohne /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the 1023f2c7d5dSHelmut Grohne * internal clock even when the clock isn't stable */ 1033f2c7d5dSHelmut Grohne #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1) 104e3ec3a3dSSoren Brinkmann }; 105e3ec3a3dSSoren Brinkmann 10606b23ca0SFaiz Abbas struct sdhci_arasan_of_data { 10706b23ca0SFaiz Abbas const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; 10806b23ca0SFaiz Abbas const struct sdhci_pltfm_data *pdata; 10906b23ca0SFaiz Abbas }; 11006b23ca0SFaiz Abbas 1113ea4666eSDouglas Anderson static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = { 1123ea4666eSDouglas Anderson .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 }, 113b2ca77c9SShawn Lin .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0}, 1143ea4666eSDouglas Anderson .hiword_update = true, 1153ea4666eSDouglas Anderson }; 1163ea4666eSDouglas Anderson 1173ea4666eSDouglas Anderson /** 1183ea4666eSDouglas Anderson * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers 1193ea4666eSDouglas Anderson * 1203ea4666eSDouglas Anderson * This function allows writing to fields in sdhci_arasan_soc_ctl_map. 1213ea4666eSDouglas Anderson * Note that if a field is specified as not available (shift < 0) then 1223ea4666eSDouglas Anderson * this function will silently return an error code. It will be noisy 1233ea4666eSDouglas Anderson * and print errors for any other (unexpected) errors. 1243ea4666eSDouglas Anderson * 1253ea4666eSDouglas Anderson * @host: The sdhci_host 1263ea4666eSDouglas Anderson * @fld: The field to write to 1273ea4666eSDouglas Anderson * @val: The value to write 1283ea4666eSDouglas Anderson */ 1293ea4666eSDouglas Anderson static int sdhci_arasan_syscon_write(struct sdhci_host *host, 1303ea4666eSDouglas Anderson const struct sdhci_arasan_soc_ctl_field *fld, 1313ea4666eSDouglas Anderson u32 val) 1323ea4666eSDouglas Anderson { 1333ea4666eSDouglas Anderson struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1343ea4666eSDouglas Anderson struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 1353ea4666eSDouglas Anderson struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; 1363ea4666eSDouglas Anderson u32 reg = fld->reg; 1373ea4666eSDouglas Anderson u16 width = fld->width; 1383ea4666eSDouglas Anderson s16 shift = fld->shift; 1393ea4666eSDouglas Anderson int ret; 1403ea4666eSDouglas Anderson 1413ea4666eSDouglas Anderson /* 1423ea4666eSDouglas Anderson * Silently return errors for shift < 0 so caller doesn't have 1433ea4666eSDouglas Anderson * to check for fields which are optional. For fields that 1443ea4666eSDouglas Anderson * are required then caller needs to do something special 1453ea4666eSDouglas Anderson * anyway. 1463ea4666eSDouglas Anderson */ 1473ea4666eSDouglas Anderson if (shift < 0) 1483ea4666eSDouglas Anderson return -EINVAL; 1493ea4666eSDouglas Anderson 1503ea4666eSDouglas Anderson if (sdhci_arasan->soc_ctl_map->hiword_update) 1513ea4666eSDouglas Anderson ret = regmap_write(soc_ctl_base, reg, 1523ea4666eSDouglas Anderson HIWORD_UPDATE(val, GENMASK(width, 0), 1533ea4666eSDouglas Anderson shift)); 1543ea4666eSDouglas Anderson else 1553ea4666eSDouglas Anderson ret = regmap_update_bits(soc_ctl_base, reg, 1563ea4666eSDouglas Anderson GENMASK(shift + width, shift), 1573ea4666eSDouglas Anderson val << shift); 1583ea4666eSDouglas Anderson 1593ea4666eSDouglas Anderson /* Yell about (unexpected) regmap errors */ 1603ea4666eSDouglas Anderson if (ret) 1613ea4666eSDouglas Anderson pr_warn("%s: Regmap write fail: %d\n", 1623ea4666eSDouglas Anderson mmc_hostname(host->mmc), ret); 1633ea4666eSDouglas Anderson 1643ea4666eSDouglas Anderson return ret; 1653ea4666eSDouglas Anderson } 1663ea4666eSDouglas Anderson 167802ac39aSShawn Lin static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) 168802ac39aSShawn Lin { 169802ac39aSShawn Lin struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 170802ac39aSShawn Lin struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 1716fc09244SDouglas Anderson bool ctrl_phy = false; 172802ac39aSShawn Lin 173b2db9c67SDouglas Anderson if (!IS_ERR(sdhci_arasan->phy)) { 174b2db9c67SDouglas Anderson if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) { 175b2db9c67SDouglas Anderson /* 176b2db9c67SDouglas Anderson * If PHY off, set clock to max speed and power PHY on. 177b2db9c67SDouglas Anderson * 178b2db9c67SDouglas Anderson * Although PHY docs apparently suggest power cycling 179b2db9c67SDouglas Anderson * when changing the clock the PHY doesn't like to be 180b2db9c67SDouglas Anderson * powered on while at low speeds like those used in ID 181b2db9c67SDouglas Anderson * mode. Even worse is powering the PHY on while the 182b2db9c67SDouglas Anderson * clock is off. 183b2db9c67SDouglas Anderson * 184b2db9c67SDouglas Anderson * To workaround the PHY limitations, the best we can 185b2db9c67SDouglas Anderson * do is to power it on at a faster speed and then slam 186b2db9c67SDouglas Anderson * through low speeds without power cycling. 187b2db9c67SDouglas Anderson */ 188b2db9c67SDouglas Anderson sdhci_set_clock(host, host->max_clk); 189b2db9c67SDouglas Anderson phy_power_on(sdhci_arasan->phy); 190b2db9c67SDouglas Anderson sdhci_arasan->is_phy_on = true; 191802ac39aSShawn Lin 192b2db9c67SDouglas Anderson /* 193b2db9c67SDouglas Anderson * We'll now fall through to the below case with 194b2db9c67SDouglas Anderson * ctrl_phy = false (so we won't turn off/on). The 195b2db9c67SDouglas Anderson * sdhci_set_clock() will set the real clock. 196b2db9c67SDouglas Anderson */ 197b2db9c67SDouglas Anderson } else if (clock > PHY_CLK_TOO_SLOW_HZ) { 198b2db9c67SDouglas Anderson /* 199b2db9c67SDouglas Anderson * At higher clock speeds the PHY is fine being power 200b2db9c67SDouglas Anderson * cycled and docs say you _should_ power cycle when 201b2db9c67SDouglas Anderson * changing clock speeds. 202b2db9c67SDouglas Anderson */ 203b2db9c67SDouglas Anderson ctrl_phy = true; 204b2db9c67SDouglas Anderson } 205b2db9c67SDouglas Anderson } 206b2db9c67SDouglas Anderson 207b2db9c67SDouglas Anderson if (ctrl_phy && sdhci_arasan->is_phy_on) { 208802ac39aSShawn Lin phy_power_off(sdhci_arasan->phy); 209b2db9c67SDouglas Anderson sdhci_arasan->is_phy_on = false; 210802ac39aSShawn Lin } 211802ac39aSShawn Lin 212802ac39aSShawn Lin sdhci_set_clock(host, clock); 213802ac39aSShawn Lin 2143f2c7d5dSHelmut Grohne if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE) 2153f2c7d5dSHelmut Grohne /* 2163f2c7d5dSHelmut Grohne * Some controllers immediately report SDHCI_CLOCK_INT_STABLE 2173f2c7d5dSHelmut Grohne * after enabling the clock even though the clock is not 2183f2c7d5dSHelmut Grohne * stable. Trying to use a clock without waiting here results 2193f2c7d5dSHelmut Grohne * in EILSEQ while detecting some older/slower cards. The 2203f2c7d5dSHelmut Grohne * chosen delay is the maximum delay from sdhci_set_clock. 2213f2c7d5dSHelmut Grohne */ 2223f2c7d5dSHelmut Grohne msleep(20); 2233f2c7d5dSHelmut Grohne 2246fc09244SDouglas Anderson if (ctrl_phy) { 225802ac39aSShawn Lin phy_power_on(sdhci_arasan->phy); 226b2db9c67SDouglas Anderson sdhci_arasan->is_phy_on = true; 227802ac39aSShawn Lin } 228802ac39aSShawn Lin } 229802ac39aSShawn Lin 230a05c8465SShawn Lin static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc, 231a05c8465SShawn Lin struct mmc_ios *ios) 232a05c8465SShawn Lin { 233a05c8465SShawn Lin u32 vendor; 234a05c8465SShawn Lin struct sdhci_host *host = mmc_priv(mmc); 235a05c8465SShawn Lin 2360daf72feSJean-Francois Dagenais vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER); 237a05c8465SShawn Lin if (ios->enhanced_strobe) 238a05c8465SShawn Lin vendor |= VENDOR_ENHANCED_STROBE; 239a05c8465SShawn Lin else 240a05c8465SShawn Lin vendor &= ~VENDOR_ENHANCED_STROBE; 241a05c8465SShawn Lin 2420daf72feSJean-Francois Dagenais sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER); 243a05c8465SShawn Lin } 244a05c8465SShawn Lin 24513d62fd2SWei Yongjun static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) 2463794c542SZach Brown { 2473794c542SZach Brown u8 ctrl; 2483794c542SZach Brown struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 2493794c542SZach Brown struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 2503794c542SZach Brown 2513794c542SZach Brown sdhci_reset(host, mask); 2523794c542SZach Brown 2533794c542SZach Brown if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { 2543794c542SZach Brown ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 2553794c542SZach Brown ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 2563794c542SZach Brown sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2573794c542SZach Brown } 2583794c542SZach Brown } 2593794c542SZach Brown 2608a3bee9bSShawn Lin static int sdhci_arasan_voltage_switch(struct mmc_host *mmc, 2618a3bee9bSShawn Lin struct mmc_ios *ios) 2628a3bee9bSShawn Lin { 2638a3bee9bSShawn Lin switch (ios->signal_voltage) { 2648a3bee9bSShawn Lin case MMC_SIGNAL_VOLTAGE_180: 2658a3bee9bSShawn Lin /* 2668a3bee9bSShawn Lin * Plese don't switch to 1V8 as arasan,5.1 doesn't 2678a3bee9bSShawn Lin * actually refer to this setting to indicate the 2688a3bee9bSShawn Lin * signal voltage and the state machine will be broken 2698a3bee9bSShawn Lin * actually if we force to enable 1V8. That's something 2708a3bee9bSShawn Lin * like broken quirk but we could work around here. 2718a3bee9bSShawn Lin */ 2728a3bee9bSShawn Lin return 0; 2738a3bee9bSShawn Lin case MMC_SIGNAL_VOLTAGE_330: 2748a3bee9bSShawn Lin case MMC_SIGNAL_VOLTAGE_120: 2758a3bee9bSShawn Lin /* We don't support 3V3 and 1V2 */ 2768a3bee9bSShawn Lin break; 2778a3bee9bSShawn Lin } 2788a3bee9bSShawn Lin 2798a3bee9bSShawn Lin return -EINVAL; 2808a3bee9bSShawn Lin } 2818a3bee9bSShawn Lin 282043f2dcaSMilan Stevanovic static void sdhci_arasan_set_power(struct sdhci_host *host, unsigned char mode, 283043f2dcaSMilan Stevanovic unsigned short vdd) 284043f2dcaSMilan Stevanovic { 285043f2dcaSMilan Stevanovic if (!IS_ERR(host->mmc->supply.vmmc)) { 286043f2dcaSMilan Stevanovic struct mmc_host *mmc = host->mmc; 287043f2dcaSMilan Stevanovic 288043f2dcaSMilan Stevanovic mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 289043f2dcaSMilan Stevanovic } 290043f2dcaSMilan Stevanovic sdhci_set_power_noreg(host, mode, vdd); 291043f2dcaSMilan Stevanovic } 292043f2dcaSMilan Stevanovic 293a81dae3aSJulia Lawall static const struct sdhci_ops sdhci_arasan_ops = { 294802ac39aSShawn Lin .set_clock = sdhci_arasan_set_clock, 295e3ec3a3dSSoren Brinkmann .get_max_clock = sdhci_pltfm_clk_get_max_clock, 2968cc35289SShawn Lin .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 2972317f56cSRussell King .set_bus_width = sdhci_set_bus_width, 2983794c542SZach Brown .reset = sdhci_arasan_reset, 29996d7b78cSRussell King .set_uhs_signaling = sdhci_set_uhs_signaling, 300043f2dcaSMilan Stevanovic .set_power = sdhci_arasan_set_power, 301e3ec3a3dSSoren Brinkmann }; 302e3ec3a3dSSoren Brinkmann 303a81dae3aSJulia Lawall static const struct sdhci_pltfm_data sdhci_arasan_pdata = { 304e3ec3a3dSSoren Brinkmann .ops = &sdhci_arasan_ops, 3052d532d45SSuneel Garapati .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 3062d532d45SSuneel Garapati .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 30757aac337SPhil Edworthy SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | 30857aac337SPhil Edworthy SDHCI_QUIRK2_STOP_WITH_TC, 309e3ec3a3dSSoren Brinkmann }; 310e3ec3a3dSSoren Brinkmann 31106b23ca0SFaiz Abbas static struct sdhci_arasan_of_data sdhci_arasan_data = { 31206b23ca0SFaiz Abbas .pdata = &sdhci_arasan_pdata, 31306b23ca0SFaiz Abbas }; 31406b23ca0SFaiz Abbas 31584362d79SShawn Lin static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask) 31684362d79SShawn Lin { 31784362d79SShawn Lin int cmd_error = 0; 31884362d79SShawn Lin int data_error = 0; 31984362d79SShawn Lin 32084362d79SShawn Lin if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 32184362d79SShawn Lin return intmask; 32284362d79SShawn Lin 32384362d79SShawn Lin cqhci_irq(host->mmc, intmask, cmd_error, data_error); 32484362d79SShawn Lin 32584362d79SShawn Lin return 0; 32684362d79SShawn Lin } 32784362d79SShawn Lin 32884362d79SShawn Lin static void sdhci_arasan_dumpregs(struct mmc_host *mmc) 32984362d79SShawn Lin { 33084362d79SShawn Lin sdhci_dumpregs(mmc_priv(mmc)); 33184362d79SShawn Lin } 33284362d79SShawn Lin 33384362d79SShawn Lin static void sdhci_arasan_cqe_enable(struct mmc_host *mmc) 33484362d79SShawn Lin { 33584362d79SShawn Lin struct sdhci_host *host = mmc_priv(mmc); 33684362d79SShawn Lin u32 reg; 33784362d79SShawn Lin 33884362d79SShawn Lin reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 33984362d79SShawn Lin while (reg & SDHCI_DATA_AVAILABLE) { 34084362d79SShawn Lin sdhci_readl(host, SDHCI_BUFFER); 34184362d79SShawn Lin reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 34284362d79SShawn Lin } 34384362d79SShawn Lin 34484362d79SShawn Lin sdhci_cqe_enable(mmc); 34584362d79SShawn Lin } 34684362d79SShawn Lin 34784362d79SShawn Lin static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = { 34884362d79SShawn Lin .enable = sdhci_arasan_cqe_enable, 34984362d79SShawn Lin .disable = sdhci_cqe_disable, 35084362d79SShawn Lin .dumpregs = sdhci_arasan_dumpregs, 35184362d79SShawn Lin }; 35284362d79SShawn Lin 35384362d79SShawn Lin static const struct sdhci_ops sdhci_arasan_cqe_ops = { 35484362d79SShawn Lin .set_clock = sdhci_arasan_set_clock, 35584362d79SShawn Lin .get_max_clock = sdhci_pltfm_clk_get_max_clock, 35684362d79SShawn Lin .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 35784362d79SShawn Lin .set_bus_width = sdhci_set_bus_width, 35884362d79SShawn Lin .reset = sdhci_arasan_reset, 35984362d79SShawn Lin .set_uhs_signaling = sdhci_set_uhs_signaling, 36084362d79SShawn Lin .set_power = sdhci_arasan_set_power, 36184362d79SShawn Lin .irq = sdhci_arasan_cqhci_irq, 36284362d79SShawn Lin }; 36384362d79SShawn Lin 36484362d79SShawn Lin static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = { 36584362d79SShawn Lin .ops = &sdhci_arasan_cqe_ops, 36684362d79SShawn Lin .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 36784362d79SShawn Lin .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 36884362d79SShawn Lin SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 36984362d79SShawn Lin }; 37084362d79SShawn Lin 37106b23ca0SFaiz Abbas static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = { 37206b23ca0SFaiz Abbas .soc_ctl_map = &rk3399_soc_ctl_map, 37306b23ca0SFaiz Abbas .pdata = &sdhci_arasan_cqe_pdata, 37406b23ca0SFaiz Abbas }; 37506b23ca0SFaiz Abbas 376e3ec3a3dSSoren Brinkmann #ifdef CONFIG_PM_SLEEP 377e3ec3a3dSSoren Brinkmann /** 378e3ec3a3dSSoren Brinkmann * sdhci_arasan_suspend - Suspend method for the driver 379e3ec3a3dSSoren Brinkmann * @dev: Address of the device structure 380e3ec3a3dSSoren Brinkmann * Returns 0 on success and error value on error 381e3ec3a3dSSoren Brinkmann * 382e3ec3a3dSSoren Brinkmann * Put the device in a low power state. 383e3ec3a3dSSoren Brinkmann */ 384e3ec3a3dSSoren Brinkmann static int sdhci_arasan_suspend(struct device *dev) 385e3ec3a3dSSoren Brinkmann { 386970f2d90SWolfram Sang struct sdhci_host *host = dev_get_drvdata(dev); 387e3ec3a3dSSoren Brinkmann struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 38889211418SJisheng Zhang struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 389e3ec3a3dSSoren Brinkmann int ret; 390e3ec3a3dSSoren Brinkmann 391d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 392d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 393d38dcad4SAdrian Hunter 39484362d79SShawn Lin if (sdhci_arasan->has_cqe) { 39584362d79SShawn Lin ret = cqhci_suspend(host->mmc); 39684362d79SShawn Lin if (ret) 39784362d79SShawn Lin return ret; 39884362d79SShawn Lin } 39984362d79SShawn Lin 400e3ec3a3dSSoren Brinkmann ret = sdhci_suspend_host(host); 401e3ec3a3dSSoren Brinkmann if (ret) 402e3ec3a3dSSoren Brinkmann return ret; 403e3ec3a3dSSoren Brinkmann 404b2db9c67SDouglas Anderson if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) { 40591aa3661SShawn Lin ret = phy_power_off(sdhci_arasan->phy); 40691aa3661SShawn Lin if (ret) { 40791aa3661SShawn Lin dev_err(dev, "Cannot power off phy.\n"); 40891aa3661SShawn Lin sdhci_resume_host(host); 40991aa3661SShawn Lin return ret; 41091aa3661SShawn Lin } 411b2db9c67SDouglas Anderson sdhci_arasan->is_phy_on = false; 41291aa3661SShawn Lin } 41391aa3661SShawn Lin 414e3ec3a3dSSoren Brinkmann clk_disable(pltfm_host->clk); 415e3ec3a3dSSoren Brinkmann clk_disable(sdhci_arasan->clk_ahb); 416e3ec3a3dSSoren Brinkmann 417e3ec3a3dSSoren Brinkmann return 0; 418e3ec3a3dSSoren Brinkmann } 419e3ec3a3dSSoren Brinkmann 420e3ec3a3dSSoren Brinkmann /** 421e3ec3a3dSSoren Brinkmann * sdhci_arasan_resume - Resume method for the driver 422e3ec3a3dSSoren Brinkmann * @dev: Address of the device structure 423e3ec3a3dSSoren Brinkmann * Returns 0 on success and error value on error 424e3ec3a3dSSoren Brinkmann * 425e3ec3a3dSSoren Brinkmann * Resume operation after suspend 426e3ec3a3dSSoren Brinkmann */ 427e3ec3a3dSSoren Brinkmann static int sdhci_arasan_resume(struct device *dev) 428e3ec3a3dSSoren Brinkmann { 429970f2d90SWolfram Sang struct sdhci_host *host = dev_get_drvdata(dev); 430e3ec3a3dSSoren Brinkmann struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 43189211418SJisheng Zhang struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 432e3ec3a3dSSoren Brinkmann int ret; 433e3ec3a3dSSoren Brinkmann 434e3ec3a3dSSoren Brinkmann ret = clk_enable(sdhci_arasan->clk_ahb); 435e3ec3a3dSSoren Brinkmann if (ret) { 436e3ec3a3dSSoren Brinkmann dev_err(dev, "Cannot enable AHB clock.\n"); 437e3ec3a3dSSoren Brinkmann return ret; 438e3ec3a3dSSoren Brinkmann } 439e3ec3a3dSSoren Brinkmann 440e3ec3a3dSSoren Brinkmann ret = clk_enable(pltfm_host->clk); 441e3ec3a3dSSoren Brinkmann if (ret) { 442e3ec3a3dSSoren Brinkmann dev_err(dev, "Cannot enable SD clock.\n"); 443e3ec3a3dSSoren Brinkmann return ret; 444e3ec3a3dSSoren Brinkmann } 445e3ec3a3dSSoren Brinkmann 446b2db9c67SDouglas Anderson if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) { 44791aa3661SShawn Lin ret = phy_power_on(sdhci_arasan->phy); 44891aa3661SShawn Lin if (ret) { 44991aa3661SShawn Lin dev_err(dev, "Cannot power on phy.\n"); 45091aa3661SShawn Lin return ret; 45191aa3661SShawn Lin } 452b2db9c67SDouglas Anderson sdhci_arasan->is_phy_on = true; 45391aa3661SShawn Lin } 45491aa3661SShawn Lin 45584362d79SShawn Lin ret = sdhci_resume_host(host); 45684362d79SShawn Lin if (ret) { 45784362d79SShawn Lin dev_err(dev, "Cannot resume host.\n"); 45884362d79SShawn Lin return ret; 45984362d79SShawn Lin } 46084362d79SShawn Lin 46184362d79SShawn Lin if (sdhci_arasan->has_cqe) 46284362d79SShawn Lin return cqhci_resume(host->mmc); 46384362d79SShawn Lin 46484362d79SShawn Lin return 0; 465e3ec3a3dSSoren Brinkmann } 466e3ec3a3dSSoren Brinkmann #endif /* ! CONFIG_PM_SLEEP */ 467e3ec3a3dSSoren Brinkmann 468e3ec3a3dSSoren Brinkmann static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend, 469e3ec3a3dSSoren Brinkmann sdhci_arasan_resume); 470e3ec3a3dSSoren Brinkmann 4713ea4666eSDouglas Anderson static const struct of_device_id sdhci_arasan_of_match[] = { 4723ea4666eSDouglas Anderson /* SoC-specific compatible strings w/ soc_ctl_map */ 4733ea4666eSDouglas Anderson { 4743ea4666eSDouglas Anderson .compatible = "rockchip,rk3399-sdhci-5.1", 47506b23ca0SFaiz Abbas .data = &sdhci_arasan_rk3399_data, 4763ea4666eSDouglas Anderson }, 4773ea4666eSDouglas Anderson /* Generic compatible below here */ 47806b23ca0SFaiz Abbas { 47906b23ca0SFaiz Abbas .compatible = "arasan,sdhci-8.9a", 48006b23ca0SFaiz Abbas .data = &sdhci_arasan_data, 48106b23ca0SFaiz Abbas }, 48206b23ca0SFaiz Abbas { 48306b23ca0SFaiz Abbas .compatible = "arasan,sdhci-5.1", 48406b23ca0SFaiz Abbas .data = &sdhci_arasan_data, 48506b23ca0SFaiz Abbas }, 48606b23ca0SFaiz Abbas { 48706b23ca0SFaiz Abbas .compatible = "arasan,sdhci-4.9a", 48806b23ca0SFaiz Abbas .data = &sdhci_arasan_data, 48906b23ca0SFaiz Abbas }, 4903ea4666eSDouglas Anderson { /* sentinel */ } 4913ea4666eSDouglas Anderson }; 4923ea4666eSDouglas Anderson MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); 4933ea4666eSDouglas Anderson 4943ea4666eSDouglas Anderson /** 495c390f211SDouglas Anderson * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate 496c390f211SDouglas Anderson * 497c390f211SDouglas Anderson * Return the current actual rate of the SD card clock. This can be used 498c390f211SDouglas Anderson * to communicate with out PHY. 499c390f211SDouglas Anderson * 500c390f211SDouglas Anderson * @hw: Pointer to the hardware clock structure. 501c390f211SDouglas Anderson * @parent_rate The parent rate (should be rate of clk_xin). 502c390f211SDouglas Anderson * Returns the card clock rate. 503c390f211SDouglas Anderson */ 504c390f211SDouglas Anderson static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw, 505c390f211SDouglas Anderson unsigned long parent_rate) 506c390f211SDouglas Anderson 507c390f211SDouglas Anderson { 508c390f211SDouglas Anderson struct sdhci_arasan_data *sdhci_arasan = 509c390f211SDouglas Anderson container_of(hw, struct sdhci_arasan_data, sdcardclk_hw); 510c390f211SDouglas Anderson struct sdhci_host *host = sdhci_arasan->host; 511c390f211SDouglas Anderson 512c390f211SDouglas Anderson return host->mmc->actual_clock; 513c390f211SDouglas Anderson } 514c390f211SDouglas Anderson 515c390f211SDouglas Anderson static const struct clk_ops arasan_sdcardclk_ops = { 516c390f211SDouglas Anderson .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, 517c390f211SDouglas Anderson }; 518c390f211SDouglas Anderson 519c390f211SDouglas Anderson /** 520b2ca77c9SShawn Lin * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier 521b2ca77c9SShawn Lin * 522b2ca77c9SShawn Lin * The corecfg_clockmultiplier is supposed to contain clock multiplier 523b2ca77c9SShawn Lin * value of programmable clock generator. 524b2ca77c9SShawn Lin * 525b2ca77c9SShawn Lin * NOTES: 526b2ca77c9SShawn Lin * - Many existing devices don't seem to do this and work fine. To keep 527b2ca77c9SShawn Lin * compatibility for old hardware where the device tree doesn't provide a 528b2ca77c9SShawn Lin * register map, this function is a noop if a soc_ctl_map hasn't been provided 529b2ca77c9SShawn Lin * for this platform. 530b2ca77c9SShawn Lin * - The value of corecfg_clockmultiplier should sync with that of corresponding 531b2ca77c9SShawn Lin * value reading from sdhci_capability_register. So this function is called 532b2ca77c9SShawn Lin * once at probe time and never called again. 533b2ca77c9SShawn Lin * 534b2ca77c9SShawn Lin * @host: The sdhci_host 535b2ca77c9SShawn Lin */ 536b2ca77c9SShawn Lin static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host, 537b2ca77c9SShawn Lin u32 value) 538b2ca77c9SShawn Lin { 539b2ca77c9SShawn Lin struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 540b2ca77c9SShawn Lin struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 541b2ca77c9SShawn Lin const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = 542b2ca77c9SShawn Lin sdhci_arasan->soc_ctl_map; 543b2ca77c9SShawn Lin 544b2ca77c9SShawn Lin /* Having a map is optional */ 545b2ca77c9SShawn Lin if (!soc_ctl_map) 546b2ca77c9SShawn Lin return; 547b2ca77c9SShawn Lin 548b2ca77c9SShawn Lin /* If we have a map, we expect to have a syscon */ 549b2ca77c9SShawn Lin if (!sdhci_arasan->soc_ctl_base) { 550b2ca77c9SShawn Lin pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", 551b2ca77c9SShawn Lin mmc_hostname(host->mmc)); 552b2ca77c9SShawn Lin return; 553b2ca77c9SShawn Lin } 554b2ca77c9SShawn Lin 555b2ca77c9SShawn Lin sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value); 556b2ca77c9SShawn Lin } 557b2ca77c9SShawn Lin 558b2ca77c9SShawn Lin /** 5593ea4666eSDouglas Anderson * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq 5603ea4666eSDouglas Anderson * 5613ea4666eSDouglas Anderson * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This 5623ea4666eSDouglas Anderson * function can be used to make that happen. 5633ea4666eSDouglas Anderson * 5643ea4666eSDouglas Anderson * NOTES: 5653ea4666eSDouglas Anderson * - Many existing devices don't seem to do this and work fine. To keep 5663ea4666eSDouglas Anderson * compatibility for old hardware where the device tree doesn't provide a 5673ea4666eSDouglas Anderson * register map, this function is a noop if a soc_ctl_map hasn't been provided 5683ea4666eSDouglas Anderson * for this platform. 5693ea4666eSDouglas Anderson * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider 5703ea4666eSDouglas Anderson * to achieve lower clock rates. That means that this function is called once 5713ea4666eSDouglas Anderson * at probe time and never called again. 5723ea4666eSDouglas Anderson * 5733ea4666eSDouglas Anderson * @host: The sdhci_host 5743ea4666eSDouglas Anderson */ 5753ea4666eSDouglas Anderson static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) 5763ea4666eSDouglas Anderson { 5773ea4666eSDouglas Anderson struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 5783ea4666eSDouglas Anderson struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 5793ea4666eSDouglas Anderson const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = 5803ea4666eSDouglas Anderson sdhci_arasan->soc_ctl_map; 5813ea4666eSDouglas Anderson u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000); 5823ea4666eSDouglas Anderson 5833ea4666eSDouglas Anderson /* Having a map is optional */ 5843ea4666eSDouglas Anderson if (!soc_ctl_map) 5853ea4666eSDouglas Anderson return; 5863ea4666eSDouglas Anderson 5873ea4666eSDouglas Anderson /* If we have a map, we expect to have a syscon */ 5883ea4666eSDouglas Anderson if (!sdhci_arasan->soc_ctl_base) { 5893ea4666eSDouglas Anderson pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", 5903ea4666eSDouglas Anderson mmc_hostname(host->mmc)); 5913ea4666eSDouglas Anderson return; 5923ea4666eSDouglas Anderson } 5933ea4666eSDouglas Anderson 5943ea4666eSDouglas Anderson sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); 5953ea4666eSDouglas Anderson } 5963ea4666eSDouglas Anderson 597c390f211SDouglas Anderson /** 598c390f211SDouglas Anderson * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use 599c390f211SDouglas Anderson * 600c390f211SDouglas Anderson * Some PHY devices need to know what the actual card clock is. In order for 601c390f211SDouglas Anderson * them to find out, we'll provide a clock through the common clock framework 602c390f211SDouglas Anderson * for them to query. 603c390f211SDouglas Anderson * 604c390f211SDouglas Anderson * Note: without seriously re-architecting SDHCI's clock code and testing on 605c390f211SDouglas Anderson * all platforms, there's no way to create a totally beautiful clock here 606c390f211SDouglas Anderson * with all clock ops implemented. Instead, we'll just create a clock that can 607c390f211SDouglas Anderson * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock 608c390f211SDouglas Anderson * framework that we're doing things behind its back. This should be sufficient 609c390f211SDouglas Anderson * to create nice clean device tree bindings and later (if needed) we can try 610c390f211SDouglas Anderson * re-architecting SDHCI if we see some benefit to it. 611c390f211SDouglas Anderson * 612c390f211SDouglas Anderson * @sdhci_arasan: Our private data structure. 613c390f211SDouglas Anderson * @clk_xin: Pointer to the functional clock 614c390f211SDouglas Anderson * @dev: Pointer to our struct device. 615c390f211SDouglas Anderson * Returns 0 on success and error value on error 616c390f211SDouglas Anderson */ 617c390f211SDouglas Anderson static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, 618c390f211SDouglas Anderson struct clk *clk_xin, 619c390f211SDouglas Anderson struct device *dev) 620c390f211SDouglas Anderson { 621c390f211SDouglas Anderson struct device_node *np = dev->of_node; 622c390f211SDouglas Anderson struct clk_init_data sdcardclk_init; 623c390f211SDouglas Anderson const char *parent_clk_name; 624c390f211SDouglas Anderson int ret; 625c390f211SDouglas Anderson 626c390f211SDouglas Anderson /* Providing a clock to the PHY is optional; no error if missing */ 627c390f211SDouglas Anderson if (!of_find_property(np, "#clock-cells", NULL)) 628c390f211SDouglas Anderson return 0; 629c390f211SDouglas Anderson 630c390f211SDouglas Anderson ret = of_property_read_string_index(np, "clock-output-names", 0, 631c390f211SDouglas Anderson &sdcardclk_init.name); 632c390f211SDouglas Anderson if (ret) { 633c390f211SDouglas Anderson dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); 634c390f211SDouglas Anderson return ret; 635c390f211SDouglas Anderson } 636c390f211SDouglas Anderson 637c390f211SDouglas Anderson parent_clk_name = __clk_get_name(clk_xin); 638c390f211SDouglas Anderson sdcardclk_init.parent_names = &parent_clk_name; 639c390f211SDouglas Anderson sdcardclk_init.num_parents = 1; 640c390f211SDouglas Anderson sdcardclk_init.flags = CLK_GET_RATE_NOCACHE; 641c390f211SDouglas Anderson sdcardclk_init.ops = &arasan_sdcardclk_ops; 642c390f211SDouglas Anderson 643c390f211SDouglas Anderson sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init; 644c390f211SDouglas Anderson sdhci_arasan->sdcardclk = 645c390f211SDouglas Anderson devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw); 646c390f211SDouglas Anderson sdhci_arasan->sdcardclk_hw.init = NULL; 647c390f211SDouglas Anderson 648c390f211SDouglas Anderson ret = of_clk_add_provider(np, of_clk_src_simple_get, 649c390f211SDouglas Anderson sdhci_arasan->sdcardclk); 650c390f211SDouglas Anderson if (ret) 651c390f211SDouglas Anderson dev_err(dev, "Failed to add clock provider\n"); 652c390f211SDouglas Anderson 653c390f211SDouglas Anderson return ret; 654c390f211SDouglas Anderson } 655c390f211SDouglas Anderson 656c390f211SDouglas Anderson /** 657c390f211SDouglas Anderson * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk() 658c390f211SDouglas Anderson * 659c390f211SDouglas Anderson * Should be called any time we're exiting and sdhci_arasan_register_sdclk() 660c390f211SDouglas Anderson * returned success. 661c390f211SDouglas Anderson * 662c390f211SDouglas Anderson * @dev: Pointer to our struct device. 663c390f211SDouglas Anderson */ 664c390f211SDouglas Anderson static void sdhci_arasan_unregister_sdclk(struct device *dev) 665c390f211SDouglas Anderson { 666c390f211SDouglas Anderson struct device_node *np = dev->of_node; 667c390f211SDouglas Anderson 668c390f211SDouglas Anderson if (!of_find_property(np, "#clock-cells", NULL)) 669c390f211SDouglas Anderson return; 670c390f211SDouglas Anderson 671c390f211SDouglas Anderson of_clk_del_provider(dev->of_node); 672c390f211SDouglas Anderson } 673c390f211SDouglas Anderson 67484362d79SShawn Lin static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan) 67584362d79SShawn Lin { 67684362d79SShawn Lin struct sdhci_host *host = sdhci_arasan->host; 67784362d79SShawn Lin struct cqhci_host *cq_host; 67884362d79SShawn Lin bool dma64; 67984362d79SShawn Lin int ret; 68084362d79SShawn Lin 68184362d79SShawn Lin if (!sdhci_arasan->has_cqe) 68284362d79SShawn Lin return sdhci_add_host(host); 68384362d79SShawn Lin 68484362d79SShawn Lin ret = sdhci_setup_host(host); 68584362d79SShawn Lin if (ret) 68684362d79SShawn Lin return ret; 68784362d79SShawn Lin 68884362d79SShawn Lin cq_host = devm_kzalloc(host->mmc->parent, 68984362d79SShawn Lin sizeof(*cq_host), GFP_KERNEL); 69084362d79SShawn Lin if (!cq_host) { 69184362d79SShawn Lin ret = -ENOMEM; 69284362d79SShawn Lin goto cleanup; 69384362d79SShawn Lin } 69484362d79SShawn Lin 69584362d79SShawn Lin cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; 69684362d79SShawn Lin cq_host->ops = &sdhci_arasan_cqhci_ops; 69784362d79SShawn Lin 69884362d79SShawn Lin dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 69984362d79SShawn Lin if (dma64) 70084362d79SShawn Lin cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 70184362d79SShawn Lin 70284362d79SShawn Lin ret = cqhci_init(cq_host, host->mmc, dma64); 70384362d79SShawn Lin if (ret) 70484362d79SShawn Lin goto cleanup; 70584362d79SShawn Lin 70684362d79SShawn Lin ret = __sdhci_add_host(host); 70784362d79SShawn Lin if (ret) 70884362d79SShawn Lin goto cleanup; 70984362d79SShawn Lin 71084362d79SShawn Lin return 0; 71184362d79SShawn Lin 71284362d79SShawn Lin cleanup: 71384362d79SShawn Lin sdhci_cleanup_host(host); 71484362d79SShawn Lin return ret; 71584362d79SShawn Lin } 71684362d79SShawn Lin 717e3ec3a3dSSoren Brinkmann static int sdhci_arasan_probe(struct platform_device *pdev) 718e3ec3a3dSSoren Brinkmann { 719e3ec3a3dSSoren Brinkmann int ret; 7203ea4666eSDouglas Anderson const struct of_device_id *match; 7213ea4666eSDouglas Anderson struct device_node *node; 722e3ec3a3dSSoren Brinkmann struct clk *clk_xin; 723e3ec3a3dSSoren Brinkmann struct sdhci_host *host; 724e3ec3a3dSSoren Brinkmann struct sdhci_pltfm_host *pltfm_host; 725e3ec3a3dSSoren Brinkmann struct sdhci_arasan_data *sdhci_arasan; 7263794c542SZach Brown struct device_node *np = pdev->dev.of_node; 72706b23ca0SFaiz Abbas const struct sdhci_arasan_of_data *data; 728e3ec3a3dSSoren Brinkmann 72906b23ca0SFaiz Abbas match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node); 73006b23ca0SFaiz Abbas data = match->data; 73106b23ca0SFaiz Abbas host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan)); 73284362d79SShawn Lin 73389211418SJisheng Zhang if (IS_ERR(host)) 73489211418SJisheng Zhang return PTR_ERR(host); 73589211418SJisheng Zhang 73689211418SJisheng Zhang pltfm_host = sdhci_priv(host); 73789211418SJisheng Zhang sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 738c390f211SDouglas Anderson sdhci_arasan->host = host; 739e3ec3a3dSSoren Brinkmann 74006b23ca0SFaiz Abbas sdhci_arasan->soc_ctl_map = data->soc_ctl_map; 7413ea4666eSDouglas Anderson 7423ea4666eSDouglas Anderson node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0); 7433ea4666eSDouglas Anderson if (node) { 7443ea4666eSDouglas Anderson sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); 7453ea4666eSDouglas Anderson of_node_put(node); 7463ea4666eSDouglas Anderson 7473ea4666eSDouglas Anderson if (IS_ERR(sdhci_arasan->soc_ctl_base)) { 7483ea4666eSDouglas Anderson ret = PTR_ERR(sdhci_arasan->soc_ctl_base); 7493ea4666eSDouglas Anderson if (ret != -EPROBE_DEFER) 7503ea4666eSDouglas Anderson dev_err(&pdev->dev, "Can't get syscon: %d\n", 7513ea4666eSDouglas Anderson ret); 7523ea4666eSDouglas Anderson goto err_pltfm_free; 7533ea4666eSDouglas Anderson } 7543ea4666eSDouglas Anderson } 7553ea4666eSDouglas Anderson 756e3ec3a3dSSoren Brinkmann sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb"); 757e3ec3a3dSSoren Brinkmann if (IS_ERR(sdhci_arasan->clk_ahb)) { 758e3ec3a3dSSoren Brinkmann dev_err(&pdev->dev, "clk_ahb clock not found.\n"); 759278d0962SShawn Lin ret = PTR_ERR(sdhci_arasan->clk_ahb); 760278d0962SShawn Lin goto err_pltfm_free; 761e3ec3a3dSSoren Brinkmann } 762e3ec3a3dSSoren Brinkmann 763e3ec3a3dSSoren Brinkmann clk_xin = devm_clk_get(&pdev->dev, "clk_xin"); 764e3ec3a3dSSoren Brinkmann if (IS_ERR(clk_xin)) { 765e3ec3a3dSSoren Brinkmann dev_err(&pdev->dev, "clk_xin clock not found.\n"); 766278d0962SShawn Lin ret = PTR_ERR(clk_xin); 767278d0962SShawn Lin goto err_pltfm_free; 768e3ec3a3dSSoren Brinkmann } 769e3ec3a3dSSoren Brinkmann 770e3ec3a3dSSoren Brinkmann ret = clk_prepare_enable(sdhci_arasan->clk_ahb); 771e3ec3a3dSSoren Brinkmann if (ret) { 772e3ec3a3dSSoren Brinkmann dev_err(&pdev->dev, "Unable to enable AHB clock.\n"); 773278d0962SShawn Lin goto err_pltfm_free; 774e3ec3a3dSSoren Brinkmann } 775e3ec3a3dSSoren Brinkmann 776e3ec3a3dSSoren Brinkmann ret = clk_prepare_enable(clk_xin); 777e3ec3a3dSSoren Brinkmann if (ret) { 778e3ec3a3dSSoren Brinkmann dev_err(&pdev->dev, "Unable to enable SD clock.\n"); 779e3ec3a3dSSoren Brinkmann goto clk_dis_ahb; 780e3ec3a3dSSoren Brinkmann } 781e3ec3a3dSSoren Brinkmann 782e3ec3a3dSSoren Brinkmann sdhci_get_of_property(pdev); 7833794c542SZach Brown 7843794c542SZach Brown if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) 7853794c542SZach Brown sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; 7863794c542SZach Brown 7873f2c7d5dSHelmut Grohne if (of_property_read_bool(np, "xlnx,int-clock-stable-broken")) 7883f2c7d5dSHelmut Grohne sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE; 7893f2c7d5dSHelmut Grohne 790e3ec3a3dSSoren Brinkmann pltfm_host->clk = clk_xin; 791e3ec3a3dSSoren Brinkmann 792b2ca77c9SShawn Lin if (of_device_is_compatible(pdev->dev.of_node, 793b2ca77c9SShawn Lin "rockchip,rk3399-sdhci-5.1")) 794b2ca77c9SShawn Lin sdhci_arasan_update_clockmultiplier(host, 0x0); 795b2ca77c9SShawn Lin 7963ea4666eSDouglas Anderson sdhci_arasan_update_baseclkfreq(host); 7973ea4666eSDouglas Anderson 798c390f211SDouglas Anderson ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev); 799c390f211SDouglas Anderson if (ret) 800c390f211SDouglas Anderson goto clk_disable_all; 801c390f211SDouglas Anderson 80216b23787SMichal Simek ret = mmc_of_parse(host->mmc); 80316b23787SMichal Simek if (ret) { 80460208a26SMichal Simek if (ret != -EPROBE_DEFER) 805940e698cSShubhrajyoti Datta dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret); 806c390f211SDouglas Anderson goto unreg_clk; 80716b23787SMichal Simek } 80816b23787SMichal Simek 80991aa3661SShawn Lin sdhci_arasan->phy = ERR_PTR(-ENODEV); 81091aa3661SShawn Lin if (of_device_is_compatible(pdev->dev.of_node, 81191aa3661SShawn Lin "arasan,sdhci-5.1")) { 81291aa3661SShawn Lin sdhci_arasan->phy = devm_phy_get(&pdev->dev, 81391aa3661SShawn Lin "phy_arasan"); 81491aa3661SShawn Lin if (IS_ERR(sdhci_arasan->phy)) { 81591aa3661SShawn Lin ret = PTR_ERR(sdhci_arasan->phy); 81691aa3661SShawn Lin dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n"); 817c390f211SDouglas Anderson goto unreg_clk; 81891aa3661SShawn Lin } 81991aa3661SShawn Lin 82091aa3661SShawn Lin ret = phy_init(sdhci_arasan->phy); 82191aa3661SShawn Lin if (ret < 0) { 82291aa3661SShawn Lin dev_err(&pdev->dev, "phy_init err.\n"); 823c390f211SDouglas Anderson goto unreg_clk; 82491aa3661SShawn Lin } 82591aa3661SShawn Lin 826a05c8465SShawn Lin host->mmc_host_ops.hs400_enhanced_strobe = 827a05c8465SShawn Lin sdhci_arasan_hs400_enhanced_strobe; 8288a3bee9bSShawn Lin host->mmc_host_ops.start_signal_voltage_switch = 8298a3bee9bSShawn Lin sdhci_arasan_voltage_switch; 83084362d79SShawn Lin sdhci_arasan->has_cqe = true; 8317bda9482SChristoph Muellner host->mmc->caps2 |= MMC_CAP2_CQE; 8327bda9482SChristoph Muellner 8337bda9482SChristoph Muellner if (!of_property_read_bool(np, "disable-cqe-dcmd")) 8347bda9482SChristoph Muellner host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 83591aa3661SShawn Lin } 83691aa3661SShawn Lin 83784362d79SShawn Lin ret = sdhci_arasan_add_host(sdhci_arasan); 838b1df9de7SMike Looijmans if (ret) 83991aa3661SShawn Lin goto err_add_host; 840e3ec3a3dSSoren Brinkmann 841e3ec3a3dSSoren Brinkmann return 0; 842e3ec3a3dSSoren Brinkmann 84391aa3661SShawn Lin err_add_host: 84491aa3661SShawn Lin if (!IS_ERR(sdhci_arasan->phy)) 84591aa3661SShawn Lin phy_exit(sdhci_arasan->phy); 846c390f211SDouglas Anderson unreg_clk: 847c390f211SDouglas Anderson sdhci_arasan_unregister_sdclk(&pdev->dev); 848e3ec3a3dSSoren Brinkmann clk_disable_all: 849e3ec3a3dSSoren Brinkmann clk_disable_unprepare(clk_xin); 850e3ec3a3dSSoren Brinkmann clk_dis_ahb: 851e3ec3a3dSSoren Brinkmann clk_disable_unprepare(sdhci_arasan->clk_ahb); 852278d0962SShawn Lin err_pltfm_free: 853278d0962SShawn Lin sdhci_pltfm_free(pdev); 854e3ec3a3dSSoren Brinkmann return ret; 855e3ec3a3dSSoren Brinkmann } 856e3ec3a3dSSoren Brinkmann 857e3ec3a3dSSoren Brinkmann static int sdhci_arasan_remove(struct platform_device *pdev) 858e3ec3a3dSSoren Brinkmann { 8590c7fe32eSJisheng Zhang int ret; 860e3ec3a3dSSoren Brinkmann struct sdhci_host *host = platform_get_drvdata(pdev); 861e3ec3a3dSSoren Brinkmann struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 86289211418SJisheng Zhang struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 86389211418SJisheng Zhang struct clk *clk_ahb = sdhci_arasan->clk_ahb; 864e3ec3a3dSSoren Brinkmann 86591aa3661SShawn Lin if (!IS_ERR(sdhci_arasan->phy)) { 866b2db9c67SDouglas Anderson if (sdhci_arasan->is_phy_on) 86791aa3661SShawn Lin phy_power_off(sdhci_arasan->phy); 86891aa3661SShawn Lin phy_exit(sdhci_arasan->phy); 86991aa3661SShawn Lin } 87091aa3661SShawn Lin 871c390f211SDouglas Anderson sdhci_arasan_unregister_sdclk(&pdev->dev); 872c390f211SDouglas Anderson 8730c7fe32eSJisheng Zhang ret = sdhci_pltfm_unregister(pdev); 8740c7fe32eSJisheng Zhang 87589211418SJisheng Zhang clk_disable_unprepare(clk_ahb); 876e3ec3a3dSSoren Brinkmann 8770c7fe32eSJisheng Zhang return ret; 878e3ec3a3dSSoren Brinkmann } 879e3ec3a3dSSoren Brinkmann 880e3ec3a3dSSoren Brinkmann static struct platform_driver sdhci_arasan_driver = { 881e3ec3a3dSSoren Brinkmann .driver = { 882e3ec3a3dSSoren Brinkmann .name = "sdhci-arasan", 883e3ec3a3dSSoren Brinkmann .of_match_table = sdhci_arasan_of_match, 884e3ec3a3dSSoren Brinkmann .pm = &sdhci_arasan_dev_pm_ops, 885e3ec3a3dSSoren Brinkmann }, 886e3ec3a3dSSoren Brinkmann .probe = sdhci_arasan_probe, 887e3ec3a3dSSoren Brinkmann .remove = sdhci_arasan_remove, 888e3ec3a3dSSoren Brinkmann }; 889e3ec3a3dSSoren Brinkmann 890e3ec3a3dSSoren Brinkmann module_platform_driver(sdhci_arasan_driver); 891e3ec3a3dSSoren Brinkmann 892e3ec3a3dSSoren Brinkmann MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller"); 893e3ec3a3dSSoren Brinkmann MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>"); 894e3ec3a3dSSoren Brinkmann MODULE_LICENSE("GPL"); 895