1 /* 2 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver 3 * 4 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 and 8 * only version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 #include <linux/delay.h> 20 #include <linux/mmc/mmc.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/slab.h> 23 24 #include "sdhci-pltfm.h" 25 26 #define CORE_MCI_VERSION 0x50 27 #define CORE_VERSION_MAJOR_SHIFT 28 28 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT) 29 #define CORE_VERSION_MINOR_MASK 0xff 30 31 #define CORE_HC_MODE 0x78 32 #define HC_MODE_EN 0x1 33 #define CORE_POWER 0x0 34 #define CORE_SW_RST BIT(7) 35 36 #define CORE_PWRCTL_STATUS 0xdc 37 #define CORE_PWRCTL_MASK 0xe0 38 #define CORE_PWRCTL_CLEAR 0xe4 39 #define CORE_PWRCTL_CTL 0xe8 40 #define CORE_PWRCTL_BUS_OFF BIT(0) 41 #define CORE_PWRCTL_BUS_ON BIT(1) 42 #define CORE_PWRCTL_IO_LOW BIT(2) 43 #define CORE_PWRCTL_IO_HIGH BIT(3) 44 #define CORE_PWRCTL_BUS_SUCCESS BIT(0) 45 #define CORE_PWRCTL_IO_SUCCESS BIT(2) 46 #define REQ_BUS_OFF BIT(0) 47 #define REQ_BUS_ON BIT(1) 48 #define REQ_IO_LOW BIT(2) 49 #define REQ_IO_HIGH BIT(3) 50 #define INT_MASK 0xf 51 #define MAX_PHASES 16 52 #define CORE_DLL_LOCK BIT(7) 53 #define CORE_DLL_EN BIT(16) 54 #define CORE_CDR_EN BIT(17) 55 #define CORE_CK_OUT_EN BIT(18) 56 #define CORE_CDR_EXT_EN BIT(19) 57 #define CORE_DLL_PDN BIT(29) 58 #define CORE_DLL_RST BIT(30) 59 #define CORE_DLL_CONFIG 0x100 60 #define CORE_DLL_STATUS 0x108 61 62 #define CORE_DLL_CONFIG_2 0x1b4 63 #define CORE_FLL_CYCLE_CNT BIT(18) 64 #define CORE_DLL_CLOCK_DISABLE BIT(21) 65 66 #define CORE_VENDOR_SPEC 0x10c 67 #define CORE_CLK_PWRSAVE BIT(1) 68 69 #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c 70 71 #define SDHCI_MSM_MIN_CLOCK 400000 72 73 #define CDR_SELEXT_SHIFT 20 74 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT) 75 #define CMUX_SHIFT_PHASE_SHIFT 24 76 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT) 77 78 #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50 79 struct sdhci_msm_host { 80 struct platform_device *pdev; 81 void __iomem *core_mem; /* MSM SDCC mapped address */ 82 int pwr_irq; /* power irq */ 83 struct clk *clk; /* main SD/MMC bus clock */ 84 struct clk *pclk; /* SDHC peripheral bus clock */ 85 struct clk *bus_clk; /* SDHC bus voter clock */ 86 struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/ 87 unsigned long clk_rate; 88 struct mmc_host *mmc; 89 bool use_14lpp_dll_reset; 90 }; 91 92 /* Platform specific tuning */ 93 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll) 94 { 95 u32 wait_cnt = 50; 96 u8 ck_out_en; 97 struct mmc_host *mmc = host->mmc; 98 99 /* Poll for CK_OUT_EN bit. max. poll time = 50us */ 100 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & 101 CORE_CK_OUT_EN); 102 103 while (ck_out_en != poll) { 104 if (--wait_cnt == 0) { 105 dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n", 106 mmc_hostname(mmc), poll); 107 return -ETIMEDOUT; 108 } 109 udelay(1); 110 111 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & 112 CORE_CK_OUT_EN); 113 } 114 115 return 0; 116 } 117 118 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase) 119 { 120 int rc; 121 static const u8 grey_coded_phase_table[] = { 122 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4, 123 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8 124 }; 125 unsigned long flags; 126 u32 config; 127 struct mmc_host *mmc = host->mmc; 128 129 spin_lock_irqsave(&host->lock, flags); 130 131 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 132 config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN); 133 config |= (CORE_CDR_EXT_EN | CORE_DLL_EN); 134 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 135 136 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */ 137 rc = msm_dll_poll_ck_out_en(host, 0); 138 if (rc) 139 goto err_out; 140 141 /* 142 * Write the selected DLL clock output phase (0 ... 15) 143 * to CDR_SELEXT bit field of DLL_CONFIG register. 144 */ 145 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 146 config &= ~CDR_SELEXT_MASK; 147 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT; 148 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 149 150 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 151 config |= CORE_CK_OUT_EN; 152 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 153 154 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */ 155 rc = msm_dll_poll_ck_out_en(host, 1); 156 if (rc) 157 goto err_out; 158 159 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 160 config |= CORE_CDR_EN; 161 config &= ~CORE_CDR_EXT_EN; 162 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 163 goto out; 164 165 err_out: 166 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n", 167 mmc_hostname(mmc), phase); 168 out: 169 spin_unlock_irqrestore(&host->lock, flags); 170 return rc; 171 } 172 173 /* 174 * Find out the greatest range of consecuitive selected 175 * DLL clock output phases that can be used as sampling 176 * setting for SD3.0 UHS-I card read operation (in SDR104 177 * timing mode) or for eMMC4.5 card read operation (in HS200 178 * timing mode). 179 * Select the 3/4 of the range and configure the DLL with the 180 * selected DLL clock output phase. 181 */ 182 183 static int msm_find_most_appropriate_phase(struct sdhci_host *host, 184 u8 *phase_table, u8 total_phases) 185 { 186 int ret; 187 u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} }; 188 u8 phases_per_row[MAX_PHASES] = { 0 }; 189 int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0; 190 int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0; 191 bool phase_0_found = false, phase_15_found = false; 192 struct mmc_host *mmc = host->mmc; 193 194 if (!total_phases || (total_phases > MAX_PHASES)) { 195 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n", 196 mmc_hostname(mmc), total_phases); 197 return -EINVAL; 198 } 199 200 for (cnt = 0; cnt < total_phases; cnt++) { 201 ranges[row_index][col_index] = phase_table[cnt]; 202 phases_per_row[row_index] += 1; 203 col_index++; 204 205 if ((cnt + 1) == total_phases) { 206 continue; 207 /* check if next phase in phase_table is consecutive or not */ 208 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) { 209 row_index++; 210 col_index = 0; 211 } 212 } 213 214 if (row_index >= MAX_PHASES) 215 return -EINVAL; 216 217 /* Check if phase-0 is present in first valid window? */ 218 if (!ranges[0][0]) { 219 phase_0_found = true; 220 phase_0_raw_index = 0; 221 /* Check if cycle exist between 2 valid windows */ 222 for (cnt = 1; cnt <= row_index; cnt++) { 223 if (phases_per_row[cnt]) { 224 for (i = 0; i < phases_per_row[cnt]; i++) { 225 if (ranges[cnt][i] == 15) { 226 phase_15_found = true; 227 phase_15_raw_index = cnt; 228 break; 229 } 230 } 231 } 232 } 233 } 234 235 /* If 2 valid windows form cycle then merge them as single window */ 236 if (phase_0_found && phase_15_found) { 237 /* number of phases in raw where phase 0 is present */ 238 u8 phases_0 = phases_per_row[phase_0_raw_index]; 239 /* number of phases in raw where phase 15 is present */ 240 u8 phases_15 = phases_per_row[phase_15_raw_index]; 241 242 if (phases_0 + phases_15 >= MAX_PHASES) 243 /* 244 * If there are more than 1 phase windows then total 245 * number of phases in both the windows should not be 246 * more than or equal to MAX_PHASES. 247 */ 248 return -EINVAL; 249 250 /* Merge 2 cyclic windows */ 251 i = phases_15; 252 for (cnt = 0; cnt < phases_0; cnt++) { 253 ranges[phase_15_raw_index][i] = 254 ranges[phase_0_raw_index][cnt]; 255 if (++i >= MAX_PHASES) 256 break; 257 } 258 259 phases_per_row[phase_0_raw_index] = 0; 260 phases_per_row[phase_15_raw_index] = phases_15 + phases_0; 261 } 262 263 for (cnt = 0; cnt <= row_index; cnt++) { 264 if (phases_per_row[cnt] > curr_max) { 265 curr_max = phases_per_row[cnt]; 266 selected_row_index = cnt; 267 } 268 } 269 270 i = (curr_max * 3) / 4; 271 if (i) 272 i--; 273 274 ret = ranges[selected_row_index][i]; 275 276 if (ret >= MAX_PHASES) { 277 ret = -EINVAL; 278 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n", 279 mmc_hostname(mmc), ret); 280 } 281 282 return ret; 283 } 284 285 static inline void msm_cm_dll_set_freq(struct sdhci_host *host) 286 { 287 u32 mclk_freq = 0, config; 288 289 /* Program the MCLK value to MCLK_FREQ bit field */ 290 if (host->clock <= 112000000) 291 mclk_freq = 0; 292 else if (host->clock <= 125000000) 293 mclk_freq = 1; 294 else if (host->clock <= 137000000) 295 mclk_freq = 2; 296 else if (host->clock <= 150000000) 297 mclk_freq = 3; 298 else if (host->clock <= 162000000) 299 mclk_freq = 4; 300 else if (host->clock <= 175000000) 301 mclk_freq = 5; 302 else if (host->clock <= 187000000) 303 mclk_freq = 6; 304 else if (host->clock <= 200000000) 305 mclk_freq = 7; 306 307 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 308 config &= ~CMUX_SHIFT_PHASE_MASK; 309 config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT; 310 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 311 } 312 313 /* Initialize the DLL (Programmable Delay Line) */ 314 static int msm_init_cm_dll(struct sdhci_host *host) 315 { 316 struct mmc_host *mmc = host->mmc; 317 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 318 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 319 int wait_cnt = 50; 320 unsigned long flags; 321 u32 config; 322 323 spin_lock_irqsave(&host->lock, flags); 324 325 /* 326 * Make sure that clock is always enabled when DLL 327 * tuning is in progress. Keeping PWRSAVE ON may 328 * turn off the clock. 329 */ 330 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); 331 config &= ~CORE_CLK_PWRSAVE; 332 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC); 333 334 if (msm_host->use_14lpp_dll_reset) { 335 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 336 config &= ~CORE_CK_OUT_EN; 337 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 338 339 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); 340 config |= CORE_DLL_CLOCK_DISABLE; 341 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2); 342 } 343 344 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 345 config |= CORE_DLL_RST; 346 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 347 348 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 349 config |= CORE_DLL_PDN; 350 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 351 msm_cm_dll_set_freq(host); 352 353 if (msm_host->use_14lpp_dll_reset && 354 !IS_ERR_OR_NULL(msm_host->xo_clk)) { 355 u32 mclk_freq = 0; 356 357 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); 358 config &= CORE_FLL_CYCLE_CNT; 359 if (config) 360 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8), 361 clk_get_rate(msm_host->xo_clk)); 362 else 363 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4), 364 clk_get_rate(msm_host->xo_clk)); 365 366 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); 367 config &= ~(0xFF << 10); 368 config |= mclk_freq << 10; 369 370 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2); 371 /* wait for 5us before enabling DLL clock */ 372 udelay(5); 373 } 374 375 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 376 config &= ~CORE_DLL_RST; 377 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 378 379 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 380 config &= ~CORE_DLL_PDN; 381 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 382 383 if (msm_host->use_14lpp_dll_reset) { 384 msm_cm_dll_set_freq(host); 385 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); 386 config &= ~CORE_DLL_CLOCK_DISABLE; 387 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2); 388 } 389 390 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 391 config |= CORE_DLL_EN; 392 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 393 394 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 395 config |= CORE_CK_OUT_EN; 396 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 397 398 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */ 399 while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) & 400 CORE_DLL_LOCK)) { 401 /* max. wait for 50us sec for LOCK bit to be set */ 402 if (--wait_cnt == 0) { 403 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n", 404 mmc_hostname(mmc)); 405 spin_unlock_irqrestore(&host->lock, flags); 406 return -ETIMEDOUT; 407 } 408 udelay(1); 409 } 410 411 spin_unlock_irqrestore(&host->lock, flags); 412 return 0; 413 } 414 415 static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode) 416 { 417 int tuning_seq_cnt = 3; 418 u8 phase, tuned_phases[16], tuned_phase_cnt = 0; 419 int rc; 420 struct mmc_host *mmc = host->mmc; 421 struct mmc_ios ios = host->mmc->ios; 422 423 /* 424 * Tuning is required for SDR104, HS200 and HS400 cards and 425 * if clock frequency is greater than 100MHz in these modes. 426 */ 427 if (host->clock <= 100 * 1000 * 1000 || 428 !((ios.timing == MMC_TIMING_MMC_HS200) || 429 (ios.timing == MMC_TIMING_UHS_SDR104))) 430 return 0; 431 432 retry: 433 /* First of all reset the tuning block */ 434 rc = msm_init_cm_dll(host); 435 if (rc) 436 return rc; 437 438 phase = 0; 439 do { 440 /* Set the phase in delay line hw block */ 441 rc = msm_config_cm_dll_phase(host, phase); 442 if (rc) 443 return rc; 444 445 rc = mmc_send_tuning(mmc, opcode, NULL); 446 if (!rc) { 447 /* Tuning is successful at this tuning point */ 448 tuned_phases[tuned_phase_cnt++] = phase; 449 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n", 450 mmc_hostname(mmc), phase); 451 } 452 } while (++phase < ARRAY_SIZE(tuned_phases)); 453 454 if (tuned_phase_cnt) { 455 rc = msm_find_most_appropriate_phase(host, tuned_phases, 456 tuned_phase_cnt); 457 if (rc < 0) 458 return rc; 459 else 460 phase = rc; 461 462 /* 463 * Finally set the selected phase in delay 464 * line hw block. 465 */ 466 rc = msm_config_cm_dll_phase(host, phase); 467 if (rc) 468 return rc; 469 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n", 470 mmc_hostname(mmc), phase); 471 } else { 472 if (--tuning_seq_cnt) 473 goto retry; 474 /* Tuning failed */ 475 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n", 476 mmc_hostname(mmc)); 477 rc = -EIO; 478 } 479 480 return rc; 481 } 482 483 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, 484 unsigned int uhs) 485 { 486 struct mmc_host *mmc = host->mmc; 487 u16 ctrl_2; 488 489 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 490 /* Select Bus Speed Mode for host */ 491 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 492 switch (uhs) { 493 case MMC_TIMING_UHS_SDR12: 494 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 495 break; 496 case MMC_TIMING_UHS_SDR25: 497 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 498 break; 499 case MMC_TIMING_UHS_SDR50: 500 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 501 break; 502 case MMC_TIMING_MMC_HS200: 503 case MMC_TIMING_UHS_SDR104: 504 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 505 break; 506 case MMC_TIMING_UHS_DDR50: 507 case MMC_TIMING_MMC_DDR52: 508 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 509 break; 510 } 511 512 /* 513 * When clock frequency is less than 100MHz, the feedback clock must be 514 * provided and DLL must not be used so that tuning can be skipped. To 515 * provide feedback clock, the mode selection can be any value less 516 * than 3'b011 in bits [2:0] of HOST CONTROL2 register. 517 */ 518 if (host->clock <= 100000000 && 519 (uhs == MMC_TIMING_MMC_HS400 || 520 uhs == MMC_TIMING_MMC_HS200 || 521 uhs == MMC_TIMING_UHS_SDR104)) 522 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 523 524 dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n", 525 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2); 526 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 527 } 528 529 static void sdhci_msm_voltage_switch(struct sdhci_host *host) 530 { 531 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 532 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 533 u32 irq_status, irq_ack = 0; 534 535 irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS); 536 irq_status &= INT_MASK; 537 538 writel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR); 539 540 if (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF)) 541 irq_ack |= CORE_PWRCTL_BUS_SUCCESS; 542 if (irq_status & (CORE_PWRCTL_IO_LOW | CORE_PWRCTL_IO_HIGH)) 543 irq_ack |= CORE_PWRCTL_IO_SUCCESS; 544 545 /* 546 * The driver has to acknowledge the interrupt, switch voltages and 547 * report back if it succeded or not to this register. The voltage 548 * switches are handled by the sdhci core, so just report success. 549 */ 550 writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL); 551 } 552 553 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) 554 { 555 struct sdhci_host *host = (struct sdhci_host *)data; 556 557 sdhci_msm_voltage_switch(host); 558 559 return IRQ_HANDLED; 560 } 561 562 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host) 563 { 564 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 565 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 566 567 return clk_round_rate(msm_host->clk, ULONG_MAX); 568 } 569 570 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) 571 { 572 return SDHCI_MSM_MIN_CLOCK; 573 } 574 575 /** 576 * __sdhci_msm_set_clock - sdhci_msm clock control. 577 * 578 * Description: 579 * MSM controller does not use internal divider and 580 * instead directly control the GCC clock as per 581 * HW recommendation. 582 **/ 583 void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) 584 { 585 u16 clk; 586 /* 587 * Keep actual_clock as zero - 588 * - since there is no divider used so no need of having actual_clock. 589 * - MSM controller uses SDCLK for data timeout calculation. If 590 * actual_clock is zero, host->clock is taken for calculation. 591 */ 592 host->mmc->actual_clock = 0; 593 594 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 595 596 if (clock == 0) 597 return; 598 599 /* 600 * MSM controller do not use clock divider. 601 * Thus read SDHCI_CLOCK_CONTROL and only enable 602 * clock with no divider value programmed. 603 */ 604 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 605 sdhci_enable_clk(host, clk); 606 } 607 608 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */ 609 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) 610 { 611 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 612 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 613 struct mmc_ios curr_ios = host->mmc->ios; 614 int rc; 615 616 if (!clock) { 617 msm_host->clk_rate = clock; 618 goto out; 619 } 620 621 spin_unlock_irq(&host->lock); 622 /* 623 * The SDHC requires internal clock frequency to be double the 624 * actual clock that will be set for DDR mode. The controller 625 * uses the faster clock(100/400MHz) for some of its parts and 626 * send the actual required clock (50/200MHz) to the card. 627 */ 628 if (curr_ios.timing == MMC_TIMING_UHS_DDR50 || 629 curr_ios.timing == MMC_TIMING_MMC_DDR52 || 630 curr_ios.timing == MMC_TIMING_MMC_HS400) 631 clock *= 2; 632 633 rc = clk_set_rate(msm_host->clk, clock); 634 if (rc) { 635 pr_err("%s: Failed to set clock at rate %u at timing %d\n", 636 mmc_hostname(host->mmc), clock, 637 curr_ios.timing); 638 goto out_lock; 639 } 640 msm_host->clk_rate = clock; 641 pr_debug("%s: Setting clock at rate %lu at timing %d\n", 642 mmc_hostname(host->mmc), clk_get_rate(msm_host->clk), 643 curr_ios.timing); 644 645 out_lock: 646 spin_lock_irq(&host->lock); 647 out: 648 __sdhci_msm_set_clock(host, clock); 649 } 650 651 static const struct of_device_id sdhci_msm_dt_match[] = { 652 { .compatible = "qcom,sdhci-msm-v4" }, 653 {}, 654 }; 655 656 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); 657 658 static const struct sdhci_ops sdhci_msm_ops = { 659 .platform_execute_tuning = sdhci_msm_execute_tuning, 660 .reset = sdhci_reset, 661 .set_clock = sdhci_msm_set_clock, 662 .get_min_clock = sdhci_msm_get_min_clock, 663 .get_max_clock = sdhci_msm_get_max_clock, 664 .set_bus_width = sdhci_set_bus_width, 665 .set_uhs_signaling = sdhci_msm_set_uhs_signaling, 666 .voltage_switch = sdhci_msm_voltage_switch, 667 }; 668 669 static const struct sdhci_pltfm_data sdhci_msm_pdata = { 670 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 671 SDHCI_QUIRK_NO_CARD_NO_RESET | 672 SDHCI_QUIRK_SINGLE_POWER_WRITE | 673 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 674 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 675 .ops = &sdhci_msm_ops, 676 }; 677 678 static int sdhci_msm_probe(struct platform_device *pdev) 679 { 680 struct sdhci_host *host; 681 struct sdhci_pltfm_host *pltfm_host; 682 struct sdhci_msm_host *msm_host; 683 struct resource *core_memres; 684 int ret; 685 u16 host_version, core_minor; 686 u32 core_version, config; 687 u8 core_major; 688 689 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host)); 690 if (IS_ERR(host)) 691 return PTR_ERR(host); 692 693 pltfm_host = sdhci_priv(host); 694 msm_host = sdhci_pltfm_priv(pltfm_host); 695 msm_host->mmc = host->mmc; 696 msm_host->pdev = pdev; 697 698 ret = mmc_of_parse(host->mmc); 699 if (ret) 700 goto pltfm_free; 701 702 sdhci_get_of_property(pdev); 703 704 /* Setup SDCC bus voter clock. */ 705 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); 706 if (!IS_ERR(msm_host->bus_clk)) { 707 /* Vote for max. clk rate for max. performance */ 708 ret = clk_set_rate(msm_host->bus_clk, INT_MAX); 709 if (ret) 710 goto pltfm_free; 711 ret = clk_prepare_enable(msm_host->bus_clk); 712 if (ret) 713 goto pltfm_free; 714 } 715 716 /* Setup main peripheral bus clock */ 717 msm_host->pclk = devm_clk_get(&pdev->dev, "iface"); 718 if (IS_ERR(msm_host->pclk)) { 719 ret = PTR_ERR(msm_host->pclk); 720 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret); 721 goto bus_clk_disable; 722 } 723 724 ret = clk_prepare_enable(msm_host->pclk); 725 if (ret) 726 goto bus_clk_disable; 727 728 /* Setup SDC MMC clock */ 729 msm_host->clk = devm_clk_get(&pdev->dev, "core"); 730 if (IS_ERR(msm_host->clk)) { 731 ret = PTR_ERR(msm_host->clk); 732 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret); 733 goto pclk_disable; 734 } 735 736 /* 737 * xo clock is needed for FLL feature of cm_dll. 738 * In case if xo clock is not mentioned in DT, warn and proceed. 739 */ 740 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo"); 741 if (IS_ERR(msm_host->xo_clk)) { 742 ret = PTR_ERR(msm_host->xo_clk); 743 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret); 744 } 745 746 /* Vote for maximum clock rate for maximum performance */ 747 ret = clk_set_rate(msm_host->clk, INT_MAX); 748 if (ret) 749 dev_warn(&pdev->dev, "core clock boost failed\n"); 750 751 ret = clk_prepare_enable(msm_host->clk); 752 if (ret) 753 goto pclk_disable; 754 755 core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1); 756 msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres); 757 758 if (IS_ERR(msm_host->core_mem)) { 759 dev_err(&pdev->dev, "Failed to remap registers\n"); 760 ret = PTR_ERR(msm_host->core_mem); 761 goto clk_disable; 762 } 763 764 config = readl_relaxed(msm_host->core_mem + CORE_POWER); 765 config |= CORE_SW_RST; 766 writel_relaxed(config, msm_host->core_mem + CORE_POWER); 767 768 /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */ 769 usleep_range(1000, 5000); 770 if (readl(msm_host->core_mem + CORE_POWER) & CORE_SW_RST) { 771 dev_err(&pdev->dev, "Stuck in reset\n"); 772 ret = -ETIMEDOUT; 773 goto clk_disable; 774 } 775 776 /* Set HC_MODE_EN bit in HC_MODE register */ 777 writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE)); 778 779 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); 780 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", 781 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >> 782 SDHCI_VENDOR_VER_SHIFT)); 783 784 core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION); 785 core_major = (core_version & CORE_VERSION_MAJOR_MASK) >> 786 CORE_VERSION_MAJOR_SHIFT; 787 core_minor = core_version & CORE_VERSION_MINOR_MASK; 788 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n", 789 core_version, core_major, core_minor); 790 791 if (core_major == 1 && core_minor >= 0x42) 792 msm_host->use_14lpp_dll_reset = true; 793 794 /* 795 * Support for some capabilities is not advertised by newer 796 * controller versions and must be explicitly enabled. 797 */ 798 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) { 799 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); 800 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; 801 writel_relaxed(config, host->ioaddr + 802 CORE_VENDOR_SPEC_CAPABILITIES0); 803 } 804 805 /* Setup IRQ for handling power/voltage tasks with PMIC */ 806 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); 807 if (msm_host->pwr_irq < 0) { 808 dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n", 809 msm_host->pwr_irq); 810 ret = msm_host->pwr_irq; 811 goto clk_disable; 812 } 813 814 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, 815 sdhci_msm_pwr_irq, IRQF_ONESHOT, 816 dev_name(&pdev->dev), host); 817 if (ret) { 818 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret); 819 goto clk_disable; 820 } 821 822 pm_runtime_get_noresume(&pdev->dev); 823 pm_runtime_set_active(&pdev->dev); 824 pm_runtime_enable(&pdev->dev); 825 pm_runtime_set_autosuspend_delay(&pdev->dev, 826 MSM_MMC_AUTOSUSPEND_DELAY_MS); 827 pm_runtime_use_autosuspend(&pdev->dev); 828 829 ret = sdhci_add_host(host); 830 if (ret) 831 goto pm_runtime_disable; 832 833 pm_runtime_mark_last_busy(&pdev->dev); 834 pm_runtime_put_autosuspend(&pdev->dev); 835 836 return 0; 837 838 pm_runtime_disable: 839 pm_runtime_disable(&pdev->dev); 840 pm_runtime_set_suspended(&pdev->dev); 841 pm_runtime_put_noidle(&pdev->dev); 842 clk_disable: 843 clk_disable_unprepare(msm_host->clk); 844 pclk_disable: 845 clk_disable_unprepare(msm_host->pclk); 846 bus_clk_disable: 847 if (!IS_ERR(msm_host->bus_clk)) 848 clk_disable_unprepare(msm_host->bus_clk); 849 pltfm_free: 850 sdhci_pltfm_free(pdev); 851 return ret; 852 } 853 854 static int sdhci_msm_remove(struct platform_device *pdev) 855 { 856 struct sdhci_host *host = platform_get_drvdata(pdev); 857 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 858 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 859 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == 860 0xffffffff); 861 862 sdhci_remove_host(host, dead); 863 864 pm_runtime_get_sync(&pdev->dev); 865 pm_runtime_disable(&pdev->dev); 866 pm_runtime_put_noidle(&pdev->dev); 867 868 clk_disable_unprepare(msm_host->clk); 869 clk_disable_unprepare(msm_host->pclk); 870 if (!IS_ERR(msm_host->bus_clk)) 871 clk_disable_unprepare(msm_host->bus_clk); 872 sdhci_pltfm_free(pdev); 873 return 0; 874 } 875 876 #ifdef CONFIG_PM 877 static int sdhci_msm_runtime_suspend(struct device *dev) 878 { 879 struct sdhci_host *host = dev_get_drvdata(dev); 880 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 881 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 882 883 clk_disable_unprepare(msm_host->clk); 884 clk_disable_unprepare(msm_host->pclk); 885 886 return 0; 887 } 888 889 static int sdhci_msm_runtime_resume(struct device *dev) 890 { 891 struct sdhci_host *host = dev_get_drvdata(dev); 892 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 893 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 894 int ret; 895 896 ret = clk_prepare_enable(msm_host->clk); 897 if (ret) { 898 dev_err(dev, "clk_enable failed for core_clk: %d\n", ret); 899 return ret; 900 } 901 ret = clk_prepare_enable(msm_host->pclk); 902 if (ret) { 903 dev_err(dev, "clk_enable failed for iface_clk: %d\n", ret); 904 clk_disable_unprepare(msm_host->clk); 905 return ret; 906 } 907 908 return 0; 909 } 910 #endif 911 912 static const struct dev_pm_ops sdhci_msm_pm_ops = { 913 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 914 pm_runtime_force_resume) 915 SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend, 916 sdhci_msm_runtime_resume, 917 NULL) 918 }; 919 920 static struct platform_driver sdhci_msm_driver = { 921 .probe = sdhci_msm_probe, 922 .remove = sdhci_msm_remove, 923 .driver = { 924 .name = "sdhci_msm", 925 .of_match_table = sdhci_msm_dt_match, 926 .pm = &sdhci_msm_pm_ops, 927 }, 928 }; 929 930 module_platform_driver(sdhci_msm_driver); 931 932 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver"); 933 MODULE_LICENSE("GPL v2"); 934