1 /* 2 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver 3 * 4 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 and 8 * only version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 #include <linux/delay.h> 20 #include <linux/mmc/mmc.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/slab.h> 23 24 #include "sdhci-pltfm.h" 25 26 #define CORE_MCI_VERSION 0x50 27 #define CORE_VERSION_MAJOR_SHIFT 28 28 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT) 29 #define CORE_VERSION_MINOR_MASK 0xff 30 31 #define CORE_HC_MODE 0x78 32 #define HC_MODE_EN 0x1 33 #define CORE_POWER 0x0 34 #define CORE_SW_RST BIT(7) 35 36 #define CORE_PWRCTL_STATUS 0xdc 37 #define CORE_PWRCTL_MASK 0xe0 38 #define CORE_PWRCTL_CLEAR 0xe4 39 #define CORE_PWRCTL_CTL 0xe8 40 #define CORE_PWRCTL_BUS_OFF BIT(0) 41 #define CORE_PWRCTL_BUS_ON BIT(1) 42 #define CORE_PWRCTL_IO_LOW BIT(2) 43 #define CORE_PWRCTL_IO_HIGH BIT(3) 44 #define CORE_PWRCTL_BUS_SUCCESS BIT(0) 45 #define CORE_PWRCTL_IO_SUCCESS BIT(2) 46 #define REQ_BUS_OFF BIT(0) 47 #define REQ_BUS_ON BIT(1) 48 #define REQ_IO_LOW BIT(2) 49 #define REQ_IO_HIGH BIT(3) 50 #define INT_MASK 0xf 51 #define MAX_PHASES 16 52 #define CORE_DLL_LOCK BIT(7) 53 #define CORE_DLL_EN BIT(16) 54 #define CORE_CDR_EN BIT(17) 55 #define CORE_CK_OUT_EN BIT(18) 56 #define CORE_CDR_EXT_EN BIT(19) 57 #define CORE_DLL_PDN BIT(29) 58 #define CORE_DLL_RST BIT(30) 59 #define CORE_DLL_CONFIG 0x100 60 #define CORE_DLL_STATUS 0x108 61 62 #define CORE_DLL_CONFIG_2 0x1b4 63 #define CORE_FLL_CYCLE_CNT BIT(18) 64 #define CORE_DLL_CLOCK_DISABLE BIT(21) 65 66 #define CORE_VENDOR_SPEC 0x10c 67 #define CORE_CLK_PWRSAVE BIT(1) 68 69 #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c 70 71 #define SDHCI_MSM_MIN_CLOCK 400000 72 73 #define CDR_SELEXT_SHIFT 20 74 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT) 75 #define CMUX_SHIFT_PHASE_SHIFT 24 76 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT) 77 78 #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50 79 struct sdhci_msm_host { 80 struct platform_device *pdev; 81 void __iomem *core_mem; /* MSM SDCC mapped address */ 82 int pwr_irq; /* power irq */ 83 struct clk *clk; /* main SD/MMC bus clock */ 84 struct clk *pclk; /* SDHC peripheral bus clock */ 85 struct clk *bus_clk; /* SDHC bus voter clock */ 86 struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/ 87 struct mmc_host *mmc; 88 bool use_14lpp_dll_reset; 89 }; 90 91 /* Platform specific tuning */ 92 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll) 93 { 94 u32 wait_cnt = 50; 95 u8 ck_out_en; 96 struct mmc_host *mmc = host->mmc; 97 98 /* Poll for CK_OUT_EN bit. max. poll time = 50us */ 99 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & 100 CORE_CK_OUT_EN); 101 102 while (ck_out_en != poll) { 103 if (--wait_cnt == 0) { 104 dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n", 105 mmc_hostname(mmc), poll); 106 return -ETIMEDOUT; 107 } 108 udelay(1); 109 110 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & 111 CORE_CK_OUT_EN); 112 } 113 114 return 0; 115 } 116 117 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase) 118 { 119 int rc; 120 static const u8 grey_coded_phase_table[] = { 121 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4, 122 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8 123 }; 124 unsigned long flags; 125 u32 config; 126 struct mmc_host *mmc = host->mmc; 127 128 spin_lock_irqsave(&host->lock, flags); 129 130 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 131 config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN); 132 config |= (CORE_CDR_EXT_EN | CORE_DLL_EN); 133 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 134 135 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */ 136 rc = msm_dll_poll_ck_out_en(host, 0); 137 if (rc) 138 goto err_out; 139 140 /* 141 * Write the selected DLL clock output phase (0 ... 15) 142 * to CDR_SELEXT bit field of DLL_CONFIG register. 143 */ 144 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 145 config &= ~CDR_SELEXT_MASK; 146 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT; 147 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 148 149 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 150 config |= CORE_CK_OUT_EN; 151 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 152 153 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */ 154 rc = msm_dll_poll_ck_out_en(host, 1); 155 if (rc) 156 goto err_out; 157 158 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 159 config |= CORE_CDR_EN; 160 config &= ~CORE_CDR_EXT_EN; 161 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 162 goto out; 163 164 err_out: 165 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n", 166 mmc_hostname(mmc), phase); 167 out: 168 spin_unlock_irqrestore(&host->lock, flags); 169 return rc; 170 } 171 172 /* 173 * Find out the greatest range of consecuitive selected 174 * DLL clock output phases that can be used as sampling 175 * setting for SD3.0 UHS-I card read operation (in SDR104 176 * timing mode) or for eMMC4.5 card read operation (in HS200 177 * timing mode). 178 * Select the 3/4 of the range and configure the DLL with the 179 * selected DLL clock output phase. 180 */ 181 182 static int msm_find_most_appropriate_phase(struct sdhci_host *host, 183 u8 *phase_table, u8 total_phases) 184 { 185 int ret; 186 u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} }; 187 u8 phases_per_row[MAX_PHASES] = { 0 }; 188 int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0; 189 int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0; 190 bool phase_0_found = false, phase_15_found = false; 191 struct mmc_host *mmc = host->mmc; 192 193 if (!total_phases || (total_phases > MAX_PHASES)) { 194 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n", 195 mmc_hostname(mmc), total_phases); 196 return -EINVAL; 197 } 198 199 for (cnt = 0; cnt < total_phases; cnt++) { 200 ranges[row_index][col_index] = phase_table[cnt]; 201 phases_per_row[row_index] += 1; 202 col_index++; 203 204 if ((cnt + 1) == total_phases) { 205 continue; 206 /* check if next phase in phase_table is consecutive or not */ 207 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) { 208 row_index++; 209 col_index = 0; 210 } 211 } 212 213 if (row_index >= MAX_PHASES) 214 return -EINVAL; 215 216 /* Check if phase-0 is present in first valid window? */ 217 if (!ranges[0][0]) { 218 phase_0_found = true; 219 phase_0_raw_index = 0; 220 /* Check if cycle exist between 2 valid windows */ 221 for (cnt = 1; cnt <= row_index; cnt++) { 222 if (phases_per_row[cnt]) { 223 for (i = 0; i < phases_per_row[cnt]; i++) { 224 if (ranges[cnt][i] == 15) { 225 phase_15_found = true; 226 phase_15_raw_index = cnt; 227 break; 228 } 229 } 230 } 231 } 232 } 233 234 /* If 2 valid windows form cycle then merge them as single window */ 235 if (phase_0_found && phase_15_found) { 236 /* number of phases in raw where phase 0 is present */ 237 u8 phases_0 = phases_per_row[phase_0_raw_index]; 238 /* number of phases in raw where phase 15 is present */ 239 u8 phases_15 = phases_per_row[phase_15_raw_index]; 240 241 if (phases_0 + phases_15 >= MAX_PHASES) 242 /* 243 * If there are more than 1 phase windows then total 244 * number of phases in both the windows should not be 245 * more than or equal to MAX_PHASES. 246 */ 247 return -EINVAL; 248 249 /* Merge 2 cyclic windows */ 250 i = phases_15; 251 for (cnt = 0; cnt < phases_0; cnt++) { 252 ranges[phase_15_raw_index][i] = 253 ranges[phase_0_raw_index][cnt]; 254 if (++i >= MAX_PHASES) 255 break; 256 } 257 258 phases_per_row[phase_0_raw_index] = 0; 259 phases_per_row[phase_15_raw_index] = phases_15 + phases_0; 260 } 261 262 for (cnt = 0; cnt <= row_index; cnt++) { 263 if (phases_per_row[cnt] > curr_max) { 264 curr_max = phases_per_row[cnt]; 265 selected_row_index = cnt; 266 } 267 } 268 269 i = (curr_max * 3) / 4; 270 if (i) 271 i--; 272 273 ret = ranges[selected_row_index][i]; 274 275 if (ret >= MAX_PHASES) { 276 ret = -EINVAL; 277 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n", 278 mmc_hostname(mmc), ret); 279 } 280 281 return ret; 282 } 283 284 static inline void msm_cm_dll_set_freq(struct sdhci_host *host) 285 { 286 u32 mclk_freq = 0, config; 287 288 /* Program the MCLK value to MCLK_FREQ bit field */ 289 if (host->clock <= 112000000) 290 mclk_freq = 0; 291 else if (host->clock <= 125000000) 292 mclk_freq = 1; 293 else if (host->clock <= 137000000) 294 mclk_freq = 2; 295 else if (host->clock <= 150000000) 296 mclk_freq = 3; 297 else if (host->clock <= 162000000) 298 mclk_freq = 4; 299 else if (host->clock <= 175000000) 300 mclk_freq = 5; 301 else if (host->clock <= 187000000) 302 mclk_freq = 6; 303 else if (host->clock <= 200000000) 304 mclk_freq = 7; 305 306 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 307 config &= ~CMUX_SHIFT_PHASE_MASK; 308 config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT; 309 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 310 } 311 312 /* Initialize the DLL (Programmable Delay Line) */ 313 static int msm_init_cm_dll(struct sdhci_host *host) 314 { 315 struct mmc_host *mmc = host->mmc; 316 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 317 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 318 int wait_cnt = 50; 319 unsigned long flags; 320 u32 config; 321 322 spin_lock_irqsave(&host->lock, flags); 323 324 /* 325 * Make sure that clock is always enabled when DLL 326 * tuning is in progress. Keeping PWRSAVE ON may 327 * turn off the clock. 328 */ 329 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); 330 config &= ~CORE_CLK_PWRSAVE; 331 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC); 332 333 if (msm_host->use_14lpp_dll_reset) { 334 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 335 config &= ~CORE_CK_OUT_EN; 336 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 337 338 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); 339 config |= CORE_DLL_CLOCK_DISABLE; 340 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2); 341 } 342 343 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 344 config |= CORE_DLL_RST; 345 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 346 347 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 348 config |= CORE_DLL_PDN; 349 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 350 msm_cm_dll_set_freq(host); 351 352 if (msm_host->use_14lpp_dll_reset && 353 !IS_ERR_OR_NULL(msm_host->xo_clk)) { 354 u32 mclk_freq = 0; 355 356 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); 357 config &= CORE_FLL_CYCLE_CNT; 358 if (config) 359 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8), 360 clk_get_rate(msm_host->xo_clk)); 361 else 362 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4), 363 clk_get_rate(msm_host->xo_clk)); 364 365 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); 366 config &= ~(0xFF << 10); 367 config |= mclk_freq << 10; 368 369 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2); 370 /* wait for 5us before enabling DLL clock */ 371 udelay(5); 372 } 373 374 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 375 config &= ~CORE_DLL_RST; 376 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 377 378 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 379 config &= ~CORE_DLL_PDN; 380 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 381 382 if (msm_host->use_14lpp_dll_reset) { 383 msm_cm_dll_set_freq(host); 384 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); 385 config &= ~CORE_DLL_CLOCK_DISABLE; 386 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2); 387 } 388 389 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 390 config |= CORE_DLL_EN; 391 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 392 393 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 394 config |= CORE_CK_OUT_EN; 395 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 396 397 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */ 398 while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) & 399 CORE_DLL_LOCK)) { 400 /* max. wait for 50us sec for LOCK bit to be set */ 401 if (--wait_cnt == 0) { 402 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n", 403 mmc_hostname(mmc)); 404 spin_unlock_irqrestore(&host->lock, flags); 405 return -ETIMEDOUT; 406 } 407 udelay(1); 408 } 409 410 spin_unlock_irqrestore(&host->lock, flags); 411 return 0; 412 } 413 414 static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode) 415 { 416 int tuning_seq_cnt = 3; 417 u8 phase, tuned_phases[16], tuned_phase_cnt = 0; 418 int rc; 419 struct mmc_host *mmc = host->mmc; 420 struct mmc_ios ios = host->mmc->ios; 421 422 /* 423 * Tuning is required for SDR104, HS200 and HS400 cards and 424 * if clock frequency is greater than 100MHz in these modes. 425 */ 426 if (host->clock <= 100 * 1000 * 1000 || 427 !((ios.timing == MMC_TIMING_MMC_HS200) || 428 (ios.timing == MMC_TIMING_UHS_SDR104))) 429 return 0; 430 431 retry: 432 /* First of all reset the tuning block */ 433 rc = msm_init_cm_dll(host); 434 if (rc) 435 return rc; 436 437 phase = 0; 438 do { 439 /* Set the phase in delay line hw block */ 440 rc = msm_config_cm_dll_phase(host, phase); 441 if (rc) 442 return rc; 443 444 rc = mmc_send_tuning(mmc, opcode, NULL); 445 if (!rc) { 446 /* Tuning is successful at this tuning point */ 447 tuned_phases[tuned_phase_cnt++] = phase; 448 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n", 449 mmc_hostname(mmc), phase); 450 } 451 } while (++phase < ARRAY_SIZE(tuned_phases)); 452 453 if (tuned_phase_cnt) { 454 rc = msm_find_most_appropriate_phase(host, tuned_phases, 455 tuned_phase_cnt); 456 if (rc < 0) 457 return rc; 458 else 459 phase = rc; 460 461 /* 462 * Finally set the selected phase in delay 463 * line hw block. 464 */ 465 rc = msm_config_cm_dll_phase(host, phase); 466 if (rc) 467 return rc; 468 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n", 469 mmc_hostname(mmc), phase); 470 } else { 471 if (--tuning_seq_cnt) 472 goto retry; 473 /* Tuning failed */ 474 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n", 475 mmc_hostname(mmc)); 476 rc = -EIO; 477 } 478 479 return rc; 480 } 481 482 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, 483 unsigned int uhs) 484 { 485 struct mmc_host *mmc = host->mmc; 486 u16 ctrl_2; 487 488 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 489 /* Select Bus Speed Mode for host */ 490 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 491 switch (uhs) { 492 case MMC_TIMING_UHS_SDR12: 493 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 494 break; 495 case MMC_TIMING_UHS_SDR25: 496 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 497 break; 498 case MMC_TIMING_UHS_SDR50: 499 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 500 break; 501 case MMC_TIMING_MMC_HS200: 502 case MMC_TIMING_UHS_SDR104: 503 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 504 break; 505 case MMC_TIMING_UHS_DDR50: 506 case MMC_TIMING_MMC_DDR52: 507 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 508 break; 509 } 510 511 /* 512 * When clock frequency is less than 100MHz, the feedback clock must be 513 * provided and DLL must not be used so that tuning can be skipped. To 514 * provide feedback clock, the mode selection can be any value less 515 * than 3'b011 in bits [2:0] of HOST CONTROL2 register. 516 */ 517 if (host->clock <= 100000000 && 518 (uhs == MMC_TIMING_MMC_HS400 || 519 uhs == MMC_TIMING_MMC_HS200 || 520 uhs == MMC_TIMING_UHS_SDR104)) 521 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 522 523 dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n", 524 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2); 525 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 526 } 527 528 static void sdhci_msm_voltage_switch(struct sdhci_host *host) 529 { 530 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 531 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 532 u32 irq_status, irq_ack = 0; 533 534 irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS); 535 irq_status &= INT_MASK; 536 537 writel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR); 538 539 if (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF)) 540 irq_ack |= CORE_PWRCTL_BUS_SUCCESS; 541 if (irq_status & (CORE_PWRCTL_IO_LOW | CORE_PWRCTL_IO_HIGH)) 542 irq_ack |= CORE_PWRCTL_IO_SUCCESS; 543 544 /* 545 * The driver has to acknowledge the interrupt, switch voltages and 546 * report back if it succeded or not to this register. The voltage 547 * switches are handled by the sdhci core, so just report success. 548 */ 549 writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL); 550 } 551 552 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) 553 { 554 struct sdhci_host *host = (struct sdhci_host *)data; 555 556 sdhci_msm_voltage_switch(host); 557 558 return IRQ_HANDLED; 559 } 560 561 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host) 562 { 563 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 564 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 565 566 return clk_round_rate(msm_host->clk, ULONG_MAX); 567 } 568 569 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) 570 { 571 return SDHCI_MSM_MIN_CLOCK; 572 } 573 574 static const struct of_device_id sdhci_msm_dt_match[] = { 575 { .compatible = "qcom,sdhci-msm-v4" }, 576 {}, 577 }; 578 579 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); 580 581 static const struct sdhci_ops sdhci_msm_ops = { 582 .platform_execute_tuning = sdhci_msm_execute_tuning, 583 .reset = sdhci_reset, 584 .set_clock = sdhci_set_clock, 585 .get_min_clock = sdhci_msm_get_min_clock, 586 .get_max_clock = sdhci_msm_get_max_clock, 587 .set_bus_width = sdhci_set_bus_width, 588 .set_uhs_signaling = sdhci_msm_set_uhs_signaling, 589 .voltage_switch = sdhci_msm_voltage_switch, 590 }; 591 592 static const struct sdhci_pltfm_data sdhci_msm_pdata = { 593 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 594 SDHCI_QUIRK_NO_CARD_NO_RESET | 595 SDHCI_QUIRK_SINGLE_POWER_WRITE | 596 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 597 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 598 .ops = &sdhci_msm_ops, 599 }; 600 601 static int sdhci_msm_probe(struct platform_device *pdev) 602 { 603 struct sdhci_host *host; 604 struct sdhci_pltfm_host *pltfm_host; 605 struct sdhci_msm_host *msm_host; 606 struct resource *core_memres; 607 int ret; 608 u16 host_version, core_minor; 609 u32 core_version, config; 610 u8 core_major; 611 612 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host)); 613 if (IS_ERR(host)) 614 return PTR_ERR(host); 615 616 pltfm_host = sdhci_priv(host); 617 msm_host = sdhci_pltfm_priv(pltfm_host); 618 msm_host->mmc = host->mmc; 619 msm_host->pdev = pdev; 620 621 ret = mmc_of_parse(host->mmc); 622 if (ret) 623 goto pltfm_free; 624 625 sdhci_get_of_property(pdev); 626 627 /* Setup SDCC bus voter clock. */ 628 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); 629 if (!IS_ERR(msm_host->bus_clk)) { 630 /* Vote for max. clk rate for max. performance */ 631 ret = clk_set_rate(msm_host->bus_clk, INT_MAX); 632 if (ret) 633 goto pltfm_free; 634 ret = clk_prepare_enable(msm_host->bus_clk); 635 if (ret) 636 goto pltfm_free; 637 } 638 639 /* Setup main peripheral bus clock */ 640 msm_host->pclk = devm_clk_get(&pdev->dev, "iface"); 641 if (IS_ERR(msm_host->pclk)) { 642 ret = PTR_ERR(msm_host->pclk); 643 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret); 644 goto bus_clk_disable; 645 } 646 647 ret = clk_prepare_enable(msm_host->pclk); 648 if (ret) 649 goto bus_clk_disable; 650 651 /* Setup SDC MMC clock */ 652 msm_host->clk = devm_clk_get(&pdev->dev, "core"); 653 if (IS_ERR(msm_host->clk)) { 654 ret = PTR_ERR(msm_host->clk); 655 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret); 656 goto pclk_disable; 657 } 658 659 /* 660 * xo clock is needed for FLL feature of cm_dll. 661 * In case if xo clock is not mentioned in DT, warn and proceed. 662 */ 663 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo"); 664 if (IS_ERR(msm_host->xo_clk)) { 665 ret = PTR_ERR(msm_host->xo_clk); 666 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret); 667 } 668 669 /* Vote for maximum clock rate for maximum performance */ 670 ret = clk_set_rate(msm_host->clk, INT_MAX); 671 if (ret) 672 dev_warn(&pdev->dev, "core clock boost failed\n"); 673 674 ret = clk_prepare_enable(msm_host->clk); 675 if (ret) 676 goto pclk_disable; 677 678 core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1); 679 msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres); 680 681 if (IS_ERR(msm_host->core_mem)) { 682 dev_err(&pdev->dev, "Failed to remap registers\n"); 683 ret = PTR_ERR(msm_host->core_mem); 684 goto clk_disable; 685 } 686 687 config = readl_relaxed(msm_host->core_mem + CORE_POWER); 688 config |= CORE_SW_RST; 689 writel_relaxed(config, msm_host->core_mem + CORE_POWER); 690 691 /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */ 692 usleep_range(1000, 5000); 693 if (readl(msm_host->core_mem + CORE_POWER) & CORE_SW_RST) { 694 dev_err(&pdev->dev, "Stuck in reset\n"); 695 ret = -ETIMEDOUT; 696 goto clk_disable; 697 } 698 699 /* Set HC_MODE_EN bit in HC_MODE register */ 700 writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE)); 701 702 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); 703 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", 704 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >> 705 SDHCI_VENDOR_VER_SHIFT)); 706 707 core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION); 708 core_major = (core_version & CORE_VERSION_MAJOR_MASK) >> 709 CORE_VERSION_MAJOR_SHIFT; 710 core_minor = core_version & CORE_VERSION_MINOR_MASK; 711 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n", 712 core_version, core_major, core_minor); 713 714 if (core_major == 1 && core_minor >= 0x42) 715 msm_host->use_14lpp_dll_reset = true; 716 717 /* 718 * Support for some capabilities is not advertised by newer 719 * controller versions and must be explicitly enabled. 720 */ 721 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) { 722 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); 723 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; 724 writel_relaxed(config, host->ioaddr + 725 CORE_VENDOR_SPEC_CAPABILITIES0); 726 } 727 728 /* Setup IRQ for handling power/voltage tasks with PMIC */ 729 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); 730 if (msm_host->pwr_irq < 0) { 731 dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n", 732 msm_host->pwr_irq); 733 ret = msm_host->pwr_irq; 734 goto clk_disable; 735 } 736 737 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, 738 sdhci_msm_pwr_irq, IRQF_ONESHOT, 739 dev_name(&pdev->dev), host); 740 if (ret) { 741 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret); 742 goto clk_disable; 743 } 744 745 pm_runtime_get_noresume(&pdev->dev); 746 pm_runtime_set_active(&pdev->dev); 747 pm_runtime_enable(&pdev->dev); 748 pm_runtime_set_autosuspend_delay(&pdev->dev, 749 MSM_MMC_AUTOSUSPEND_DELAY_MS); 750 pm_runtime_use_autosuspend(&pdev->dev); 751 752 ret = sdhci_add_host(host); 753 if (ret) 754 goto pm_runtime_disable; 755 756 pm_runtime_mark_last_busy(&pdev->dev); 757 pm_runtime_put_autosuspend(&pdev->dev); 758 759 return 0; 760 761 pm_runtime_disable: 762 pm_runtime_disable(&pdev->dev); 763 pm_runtime_set_suspended(&pdev->dev); 764 pm_runtime_put_noidle(&pdev->dev); 765 clk_disable: 766 clk_disable_unprepare(msm_host->clk); 767 pclk_disable: 768 clk_disable_unprepare(msm_host->pclk); 769 bus_clk_disable: 770 if (!IS_ERR(msm_host->bus_clk)) 771 clk_disable_unprepare(msm_host->bus_clk); 772 pltfm_free: 773 sdhci_pltfm_free(pdev); 774 return ret; 775 } 776 777 static int sdhci_msm_remove(struct platform_device *pdev) 778 { 779 struct sdhci_host *host = platform_get_drvdata(pdev); 780 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 781 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 782 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == 783 0xffffffff); 784 785 sdhci_remove_host(host, dead); 786 787 pm_runtime_get_sync(&pdev->dev); 788 pm_runtime_disable(&pdev->dev); 789 pm_runtime_put_noidle(&pdev->dev); 790 791 clk_disable_unprepare(msm_host->clk); 792 clk_disable_unprepare(msm_host->pclk); 793 if (!IS_ERR(msm_host->bus_clk)) 794 clk_disable_unprepare(msm_host->bus_clk); 795 sdhci_pltfm_free(pdev); 796 return 0; 797 } 798 799 #ifdef CONFIG_PM 800 static int sdhci_msm_runtime_suspend(struct device *dev) 801 { 802 struct sdhci_host *host = dev_get_drvdata(dev); 803 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 804 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 805 806 clk_disable_unprepare(msm_host->clk); 807 clk_disable_unprepare(msm_host->pclk); 808 809 return 0; 810 } 811 812 static int sdhci_msm_runtime_resume(struct device *dev) 813 { 814 struct sdhci_host *host = dev_get_drvdata(dev); 815 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 816 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 817 int ret; 818 819 ret = clk_prepare_enable(msm_host->clk); 820 if (ret) { 821 dev_err(dev, "clk_enable failed for core_clk: %d\n", ret); 822 return ret; 823 } 824 ret = clk_prepare_enable(msm_host->pclk); 825 if (ret) { 826 dev_err(dev, "clk_enable failed for iface_clk: %d\n", ret); 827 clk_disable_unprepare(msm_host->clk); 828 return ret; 829 } 830 831 return 0; 832 } 833 #endif 834 835 static const struct dev_pm_ops sdhci_msm_pm_ops = { 836 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 837 pm_runtime_force_resume) 838 SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend, 839 sdhci_msm_runtime_resume, 840 NULL) 841 }; 842 843 static struct platform_driver sdhci_msm_driver = { 844 .probe = sdhci_msm_probe, 845 .remove = sdhci_msm_remove, 846 .driver = { 847 .name = "sdhci_msm", 848 .of_match_table = sdhci_msm_dt_match, 849 .pm = &sdhci_msm_pm_ops, 850 }, 851 }; 852 853 module_platform_driver(sdhci_msm_driver); 854 855 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver"); 856 MODULE_LICENSE("GPL v2"); 857