1 /* 2 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver 3 * 4 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 and 8 * only version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 #include <linux/delay.h> 20 #include <linux/mmc/mmc.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/slab.h> 23 24 #include "sdhci-pltfm.h" 25 26 #define CORE_MCI_VERSION 0x50 27 #define CORE_VERSION_MAJOR_SHIFT 28 28 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT) 29 #define CORE_VERSION_MINOR_MASK 0xff 30 31 #define CORE_HC_MODE 0x78 32 #define HC_MODE_EN 0x1 33 #define CORE_POWER 0x0 34 #define CORE_SW_RST BIT(7) 35 36 #define CORE_PWRCTL_STATUS 0xdc 37 #define CORE_PWRCTL_MASK 0xe0 38 #define CORE_PWRCTL_CLEAR 0xe4 39 #define CORE_PWRCTL_CTL 0xe8 40 #define CORE_PWRCTL_BUS_OFF BIT(0) 41 #define CORE_PWRCTL_BUS_ON BIT(1) 42 #define CORE_PWRCTL_IO_LOW BIT(2) 43 #define CORE_PWRCTL_IO_HIGH BIT(3) 44 #define CORE_PWRCTL_BUS_SUCCESS BIT(0) 45 #define CORE_PWRCTL_IO_SUCCESS BIT(2) 46 #define REQ_BUS_OFF BIT(0) 47 #define REQ_BUS_ON BIT(1) 48 #define REQ_IO_LOW BIT(2) 49 #define REQ_IO_HIGH BIT(3) 50 #define INT_MASK 0xf 51 #define MAX_PHASES 16 52 #define CORE_DLL_LOCK BIT(7) 53 #define CORE_DLL_EN BIT(16) 54 #define CORE_CDR_EN BIT(17) 55 #define CORE_CK_OUT_EN BIT(18) 56 #define CORE_CDR_EXT_EN BIT(19) 57 #define CORE_DLL_PDN BIT(29) 58 #define CORE_DLL_RST BIT(30) 59 #define CORE_DLL_CONFIG 0x100 60 #define CORE_DLL_STATUS 0x108 61 62 #define CORE_VENDOR_SPEC 0x10c 63 #define CORE_CLK_PWRSAVE BIT(1) 64 65 #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c 66 67 #define CDR_SELEXT_SHIFT 20 68 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT) 69 #define CMUX_SHIFT_PHASE_SHIFT 24 70 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT) 71 72 #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50 73 struct sdhci_msm_host { 74 struct platform_device *pdev; 75 void __iomem *core_mem; /* MSM SDCC mapped address */ 76 int pwr_irq; /* power irq */ 77 struct clk *clk; /* main SD/MMC bus clock */ 78 struct clk *pclk; /* SDHC peripheral bus clock */ 79 struct clk *bus_clk; /* SDHC bus voter clock */ 80 struct mmc_host *mmc; 81 }; 82 83 /* Platform specific tuning */ 84 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll) 85 { 86 u32 wait_cnt = 50; 87 u8 ck_out_en; 88 struct mmc_host *mmc = host->mmc; 89 90 /* Poll for CK_OUT_EN bit. max. poll time = 50us */ 91 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & 92 CORE_CK_OUT_EN); 93 94 while (ck_out_en != poll) { 95 if (--wait_cnt == 0) { 96 dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n", 97 mmc_hostname(mmc), poll); 98 return -ETIMEDOUT; 99 } 100 udelay(1); 101 102 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & 103 CORE_CK_OUT_EN); 104 } 105 106 return 0; 107 } 108 109 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase) 110 { 111 int rc; 112 static const u8 grey_coded_phase_table[] = { 113 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4, 114 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8 115 }; 116 unsigned long flags; 117 u32 config; 118 struct mmc_host *mmc = host->mmc; 119 120 spin_lock_irqsave(&host->lock, flags); 121 122 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 123 config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN); 124 config |= (CORE_CDR_EXT_EN | CORE_DLL_EN); 125 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 126 127 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */ 128 rc = msm_dll_poll_ck_out_en(host, 0); 129 if (rc) 130 goto err_out; 131 132 /* 133 * Write the selected DLL clock output phase (0 ... 15) 134 * to CDR_SELEXT bit field of DLL_CONFIG register. 135 */ 136 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 137 config &= ~CDR_SELEXT_MASK; 138 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT; 139 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 140 141 /* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */ 142 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) 143 | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG); 144 145 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */ 146 rc = msm_dll_poll_ck_out_en(host, 1); 147 if (rc) 148 goto err_out; 149 150 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 151 config |= CORE_CDR_EN; 152 config &= ~CORE_CDR_EXT_EN; 153 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 154 goto out; 155 156 err_out: 157 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n", 158 mmc_hostname(mmc), phase); 159 out: 160 spin_unlock_irqrestore(&host->lock, flags); 161 return rc; 162 } 163 164 /* 165 * Find out the greatest range of consecuitive selected 166 * DLL clock output phases that can be used as sampling 167 * setting for SD3.0 UHS-I card read operation (in SDR104 168 * timing mode) or for eMMC4.5 card read operation (in HS200 169 * timing mode). 170 * Select the 3/4 of the range and configure the DLL with the 171 * selected DLL clock output phase. 172 */ 173 174 static int msm_find_most_appropriate_phase(struct sdhci_host *host, 175 u8 *phase_table, u8 total_phases) 176 { 177 int ret; 178 u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} }; 179 u8 phases_per_row[MAX_PHASES] = { 0 }; 180 int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0; 181 int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0; 182 bool phase_0_found = false, phase_15_found = false; 183 struct mmc_host *mmc = host->mmc; 184 185 if (!total_phases || (total_phases > MAX_PHASES)) { 186 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n", 187 mmc_hostname(mmc), total_phases); 188 return -EINVAL; 189 } 190 191 for (cnt = 0; cnt < total_phases; cnt++) { 192 ranges[row_index][col_index] = phase_table[cnt]; 193 phases_per_row[row_index] += 1; 194 col_index++; 195 196 if ((cnt + 1) == total_phases) { 197 continue; 198 /* check if next phase in phase_table is consecutive or not */ 199 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) { 200 row_index++; 201 col_index = 0; 202 } 203 } 204 205 if (row_index >= MAX_PHASES) 206 return -EINVAL; 207 208 /* Check if phase-0 is present in first valid window? */ 209 if (!ranges[0][0]) { 210 phase_0_found = true; 211 phase_0_raw_index = 0; 212 /* Check if cycle exist between 2 valid windows */ 213 for (cnt = 1; cnt <= row_index; cnt++) { 214 if (phases_per_row[cnt]) { 215 for (i = 0; i < phases_per_row[cnt]; i++) { 216 if (ranges[cnt][i] == 15) { 217 phase_15_found = true; 218 phase_15_raw_index = cnt; 219 break; 220 } 221 } 222 } 223 } 224 } 225 226 /* If 2 valid windows form cycle then merge them as single window */ 227 if (phase_0_found && phase_15_found) { 228 /* number of phases in raw where phase 0 is present */ 229 u8 phases_0 = phases_per_row[phase_0_raw_index]; 230 /* number of phases in raw where phase 15 is present */ 231 u8 phases_15 = phases_per_row[phase_15_raw_index]; 232 233 if (phases_0 + phases_15 >= MAX_PHASES) 234 /* 235 * If there are more than 1 phase windows then total 236 * number of phases in both the windows should not be 237 * more than or equal to MAX_PHASES. 238 */ 239 return -EINVAL; 240 241 /* Merge 2 cyclic windows */ 242 i = phases_15; 243 for (cnt = 0; cnt < phases_0; cnt++) { 244 ranges[phase_15_raw_index][i] = 245 ranges[phase_0_raw_index][cnt]; 246 if (++i >= MAX_PHASES) 247 break; 248 } 249 250 phases_per_row[phase_0_raw_index] = 0; 251 phases_per_row[phase_15_raw_index] = phases_15 + phases_0; 252 } 253 254 for (cnt = 0; cnt <= row_index; cnt++) { 255 if (phases_per_row[cnt] > curr_max) { 256 curr_max = phases_per_row[cnt]; 257 selected_row_index = cnt; 258 } 259 } 260 261 i = (curr_max * 3) / 4; 262 if (i) 263 i--; 264 265 ret = ranges[selected_row_index][i]; 266 267 if (ret >= MAX_PHASES) { 268 ret = -EINVAL; 269 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n", 270 mmc_hostname(mmc), ret); 271 } 272 273 return ret; 274 } 275 276 static inline void msm_cm_dll_set_freq(struct sdhci_host *host) 277 { 278 u32 mclk_freq = 0, config; 279 280 /* Program the MCLK value to MCLK_FREQ bit field */ 281 if (host->clock <= 112000000) 282 mclk_freq = 0; 283 else if (host->clock <= 125000000) 284 mclk_freq = 1; 285 else if (host->clock <= 137000000) 286 mclk_freq = 2; 287 else if (host->clock <= 150000000) 288 mclk_freq = 3; 289 else if (host->clock <= 162000000) 290 mclk_freq = 4; 291 else if (host->clock <= 175000000) 292 mclk_freq = 5; 293 else if (host->clock <= 187000000) 294 mclk_freq = 6; 295 else if (host->clock <= 200000000) 296 mclk_freq = 7; 297 298 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 299 config &= ~CMUX_SHIFT_PHASE_MASK; 300 config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT; 301 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 302 } 303 304 /* Initialize the DLL (Programmable Delay Line) */ 305 static int msm_init_cm_dll(struct sdhci_host *host) 306 { 307 struct mmc_host *mmc = host->mmc; 308 int wait_cnt = 50; 309 unsigned long flags; 310 311 spin_lock_irqsave(&host->lock, flags); 312 313 /* 314 * Make sure that clock is always enabled when DLL 315 * tuning is in progress. Keeping PWRSAVE ON may 316 * turn off the clock. 317 */ 318 writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) 319 & ~CORE_CLK_PWRSAVE), host->ioaddr + CORE_VENDOR_SPEC); 320 321 /* Write 1 to DLL_RST bit of DLL_CONFIG register */ 322 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) 323 | CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG); 324 325 /* Write 1 to DLL_PDN bit of DLL_CONFIG register */ 326 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) 327 | CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG); 328 msm_cm_dll_set_freq(host); 329 330 /* Write 0 to DLL_RST bit of DLL_CONFIG register */ 331 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) 332 & ~CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG); 333 334 /* Write 0 to DLL_PDN bit of DLL_CONFIG register */ 335 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) 336 & ~CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG); 337 338 /* Set DLL_EN bit to 1. */ 339 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) 340 | CORE_DLL_EN), host->ioaddr + CORE_DLL_CONFIG); 341 342 /* Set CK_OUT_EN bit to 1. */ 343 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) 344 | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG); 345 346 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */ 347 while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) & 348 CORE_DLL_LOCK)) { 349 /* max. wait for 50us sec for LOCK bit to be set */ 350 if (--wait_cnt == 0) { 351 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n", 352 mmc_hostname(mmc)); 353 spin_unlock_irqrestore(&host->lock, flags); 354 return -ETIMEDOUT; 355 } 356 udelay(1); 357 } 358 359 spin_unlock_irqrestore(&host->lock, flags); 360 return 0; 361 } 362 363 static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode) 364 { 365 int tuning_seq_cnt = 3; 366 u8 phase, tuned_phases[16], tuned_phase_cnt = 0; 367 int rc; 368 struct mmc_host *mmc = host->mmc; 369 struct mmc_ios ios = host->mmc->ios; 370 371 /* 372 * Tuning is required for SDR104, HS200 and HS400 cards and 373 * if clock frequency is greater than 100MHz in these modes. 374 */ 375 if (host->clock <= 100 * 1000 * 1000 || 376 !((ios.timing == MMC_TIMING_MMC_HS200) || 377 (ios.timing == MMC_TIMING_UHS_SDR104))) 378 return 0; 379 380 retry: 381 /* First of all reset the tuning block */ 382 rc = msm_init_cm_dll(host); 383 if (rc) 384 return rc; 385 386 phase = 0; 387 do { 388 /* Set the phase in delay line hw block */ 389 rc = msm_config_cm_dll_phase(host, phase); 390 if (rc) 391 return rc; 392 393 rc = mmc_send_tuning(mmc, opcode, NULL); 394 if (!rc) { 395 /* Tuning is successful at this tuning point */ 396 tuned_phases[tuned_phase_cnt++] = phase; 397 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n", 398 mmc_hostname(mmc), phase); 399 } 400 } while (++phase < ARRAY_SIZE(tuned_phases)); 401 402 if (tuned_phase_cnt) { 403 rc = msm_find_most_appropriate_phase(host, tuned_phases, 404 tuned_phase_cnt); 405 if (rc < 0) 406 return rc; 407 else 408 phase = rc; 409 410 /* 411 * Finally set the selected phase in delay 412 * line hw block. 413 */ 414 rc = msm_config_cm_dll_phase(host, phase); 415 if (rc) 416 return rc; 417 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n", 418 mmc_hostname(mmc), phase); 419 } else { 420 if (--tuning_seq_cnt) 421 goto retry; 422 /* Tuning failed */ 423 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n", 424 mmc_hostname(mmc)); 425 rc = -EIO; 426 } 427 428 return rc; 429 } 430 431 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, 432 unsigned int uhs) 433 { 434 struct mmc_host *mmc = host->mmc; 435 u16 ctrl_2; 436 437 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 438 /* Select Bus Speed Mode for host */ 439 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 440 switch (uhs) { 441 case MMC_TIMING_UHS_SDR12: 442 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 443 break; 444 case MMC_TIMING_UHS_SDR25: 445 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 446 break; 447 case MMC_TIMING_UHS_SDR50: 448 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 449 break; 450 case MMC_TIMING_MMC_HS200: 451 case MMC_TIMING_UHS_SDR104: 452 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 453 break; 454 case MMC_TIMING_UHS_DDR50: 455 case MMC_TIMING_MMC_DDR52: 456 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 457 break; 458 } 459 460 /* 461 * When clock frequency is less than 100MHz, the feedback clock must be 462 * provided and DLL must not be used so that tuning can be skipped. To 463 * provide feedback clock, the mode selection can be any value less 464 * than 3'b011 in bits [2:0] of HOST CONTROL2 register. 465 */ 466 if (host->clock <= 100000000 && 467 (uhs == MMC_TIMING_MMC_HS400 || 468 uhs == MMC_TIMING_MMC_HS200 || 469 uhs == MMC_TIMING_UHS_SDR104)) 470 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 471 472 dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n", 473 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2); 474 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 475 } 476 477 static void sdhci_msm_voltage_switch(struct sdhci_host *host) 478 { 479 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 480 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 481 u32 irq_status, irq_ack = 0; 482 483 irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS); 484 irq_status &= INT_MASK; 485 486 writel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR); 487 488 if (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF)) 489 irq_ack |= CORE_PWRCTL_BUS_SUCCESS; 490 if (irq_status & (CORE_PWRCTL_IO_LOW | CORE_PWRCTL_IO_HIGH)) 491 irq_ack |= CORE_PWRCTL_IO_SUCCESS; 492 493 /* 494 * The driver has to acknowledge the interrupt, switch voltages and 495 * report back if it succeded or not to this register. The voltage 496 * switches are handled by the sdhci core, so just report success. 497 */ 498 writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL); 499 } 500 501 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) 502 { 503 struct sdhci_host *host = (struct sdhci_host *)data; 504 505 sdhci_msm_voltage_switch(host); 506 507 return IRQ_HANDLED; 508 } 509 510 static const struct of_device_id sdhci_msm_dt_match[] = { 511 { .compatible = "qcom,sdhci-msm-v4" }, 512 {}, 513 }; 514 515 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); 516 517 static const struct sdhci_ops sdhci_msm_ops = { 518 .platform_execute_tuning = sdhci_msm_execute_tuning, 519 .reset = sdhci_reset, 520 .set_clock = sdhci_set_clock, 521 .set_bus_width = sdhci_set_bus_width, 522 .set_uhs_signaling = sdhci_msm_set_uhs_signaling, 523 .voltage_switch = sdhci_msm_voltage_switch, 524 }; 525 526 static const struct sdhci_pltfm_data sdhci_msm_pdata = { 527 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 528 SDHCI_QUIRK_NO_CARD_NO_RESET | 529 SDHCI_QUIRK_SINGLE_POWER_WRITE, 530 .ops = &sdhci_msm_ops, 531 }; 532 533 static int sdhci_msm_probe(struct platform_device *pdev) 534 { 535 struct sdhci_host *host; 536 struct sdhci_pltfm_host *pltfm_host; 537 struct sdhci_msm_host *msm_host; 538 struct resource *core_memres; 539 int ret; 540 u16 host_version, core_minor; 541 u32 core_version, caps; 542 u8 core_major; 543 544 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host)); 545 if (IS_ERR(host)) 546 return PTR_ERR(host); 547 548 pltfm_host = sdhci_priv(host); 549 msm_host = sdhci_pltfm_priv(pltfm_host); 550 msm_host->mmc = host->mmc; 551 msm_host->pdev = pdev; 552 553 ret = mmc_of_parse(host->mmc); 554 if (ret) 555 goto pltfm_free; 556 557 sdhci_get_of_property(pdev); 558 559 /* Setup SDCC bus voter clock. */ 560 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); 561 if (!IS_ERR(msm_host->bus_clk)) { 562 /* Vote for max. clk rate for max. performance */ 563 ret = clk_set_rate(msm_host->bus_clk, INT_MAX); 564 if (ret) 565 goto pltfm_free; 566 ret = clk_prepare_enable(msm_host->bus_clk); 567 if (ret) 568 goto pltfm_free; 569 } 570 571 /* Setup main peripheral bus clock */ 572 msm_host->pclk = devm_clk_get(&pdev->dev, "iface"); 573 if (IS_ERR(msm_host->pclk)) { 574 ret = PTR_ERR(msm_host->pclk); 575 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret); 576 goto bus_clk_disable; 577 } 578 579 ret = clk_prepare_enable(msm_host->pclk); 580 if (ret) 581 goto bus_clk_disable; 582 583 /* Setup SDC MMC clock */ 584 msm_host->clk = devm_clk_get(&pdev->dev, "core"); 585 if (IS_ERR(msm_host->clk)) { 586 ret = PTR_ERR(msm_host->clk); 587 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret); 588 goto pclk_disable; 589 } 590 591 /* Vote for maximum clock rate for maximum performance */ 592 ret = clk_set_rate(msm_host->clk, INT_MAX); 593 if (ret) 594 dev_warn(&pdev->dev, "core clock boost failed\n"); 595 596 ret = clk_prepare_enable(msm_host->clk); 597 if (ret) 598 goto pclk_disable; 599 600 core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1); 601 msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres); 602 603 if (IS_ERR(msm_host->core_mem)) { 604 dev_err(&pdev->dev, "Failed to remap registers\n"); 605 ret = PTR_ERR(msm_host->core_mem); 606 goto clk_disable; 607 } 608 609 /* Reset the core and Enable SDHC mode */ 610 writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) | 611 CORE_SW_RST, msm_host->core_mem + CORE_POWER); 612 613 /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */ 614 usleep_range(1000, 5000); 615 if (readl(msm_host->core_mem + CORE_POWER) & CORE_SW_RST) { 616 dev_err(&pdev->dev, "Stuck in reset\n"); 617 ret = -ETIMEDOUT; 618 goto clk_disable; 619 } 620 621 /* Set HC_MODE_EN bit in HC_MODE register */ 622 writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE)); 623 624 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); 625 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", 626 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >> 627 SDHCI_VENDOR_VER_SHIFT)); 628 629 core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION); 630 core_major = (core_version & CORE_VERSION_MAJOR_MASK) >> 631 CORE_VERSION_MAJOR_SHIFT; 632 core_minor = core_version & CORE_VERSION_MINOR_MASK; 633 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n", 634 core_version, core_major, core_minor); 635 636 /* 637 * Support for some capabilities is not advertised by newer 638 * controller versions and must be explicitly enabled. 639 */ 640 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) { 641 caps = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); 642 caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; 643 writel_relaxed(caps, host->ioaddr + 644 CORE_VENDOR_SPEC_CAPABILITIES0); 645 } 646 647 /* Setup IRQ for handling power/voltage tasks with PMIC */ 648 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); 649 if (msm_host->pwr_irq < 0) { 650 dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n", 651 msm_host->pwr_irq); 652 ret = msm_host->pwr_irq; 653 goto clk_disable; 654 } 655 656 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, 657 sdhci_msm_pwr_irq, IRQF_ONESHOT, 658 dev_name(&pdev->dev), host); 659 if (ret) { 660 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret); 661 goto clk_disable; 662 } 663 664 pm_runtime_get_noresume(&pdev->dev); 665 pm_runtime_set_active(&pdev->dev); 666 pm_runtime_enable(&pdev->dev); 667 pm_runtime_set_autosuspend_delay(&pdev->dev, 668 MSM_MMC_AUTOSUSPEND_DELAY_MS); 669 pm_runtime_use_autosuspend(&pdev->dev); 670 671 ret = sdhci_add_host(host); 672 if (ret) 673 goto pm_runtime_disable; 674 675 pm_runtime_mark_last_busy(&pdev->dev); 676 pm_runtime_put_autosuspend(&pdev->dev); 677 678 return 0; 679 680 pm_runtime_disable: 681 pm_runtime_disable(&pdev->dev); 682 pm_runtime_set_suspended(&pdev->dev); 683 pm_runtime_put_noidle(&pdev->dev); 684 clk_disable: 685 clk_disable_unprepare(msm_host->clk); 686 pclk_disable: 687 clk_disable_unprepare(msm_host->pclk); 688 bus_clk_disable: 689 if (!IS_ERR(msm_host->bus_clk)) 690 clk_disable_unprepare(msm_host->bus_clk); 691 pltfm_free: 692 sdhci_pltfm_free(pdev); 693 return ret; 694 } 695 696 static int sdhci_msm_remove(struct platform_device *pdev) 697 { 698 struct sdhci_host *host = platform_get_drvdata(pdev); 699 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 700 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 701 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == 702 0xffffffff); 703 704 sdhci_remove_host(host, dead); 705 706 pm_runtime_get_sync(&pdev->dev); 707 pm_runtime_disable(&pdev->dev); 708 pm_runtime_put_noidle(&pdev->dev); 709 710 clk_disable_unprepare(msm_host->clk); 711 clk_disable_unprepare(msm_host->pclk); 712 if (!IS_ERR(msm_host->bus_clk)) 713 clk_disable_unprepare(msm_host->bus_clk); 714 sdhci_pltfm_free(pdev); 715 return 0; 716 } 717 718 #ifdef CONFIG_PM 719 static int sdhci_msm_runtime_suspend(struct device *dev) 720 { 721 struct sdhci_host *host = dev_get_drvdata(dev); 722 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 723 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 724 725 clk_disable_unprepare(msm_host->clk); 726 clk_disable_unprepare(msm_host->pclk); 727 728 return 0; 729 } 730 731 static int sdhci_msm_runtime_resume(struct device *dev) 732 { 733 struct sdhci_host *host = dev_get_drvdata(dev); 734 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 735 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 736 int ret; 737 738 ret = clk_prepare_enable(msm_host->clk); 739 if (ret) { 740 dev_err(dev, "clk_enable failed for core_clk: %d\n", ret); 741 return ret; 742 } 743 ret = clk_prepare_enable(msm_host->pclk); 744 if (ret) { 745 dev_err(dev, "clk_enable failed for iface_clk: %d\n", ret); 746 clk_disable_unprepare(msm_host->clk); 747 return ret; 748 } 749 750 return 0; 751 } 752 #endif 753 754 static const struct dev_pm_ops sdhci_msm_pm_ops = { 755 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 756 pm_runtime_force_resume) 757 SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend, 758 sdhci_msm_runtime_resume, 759 NULL) 760 }; 761 762 static struct platform_driver sdhci_msm_driver = { 763 .probe = sdhci_msm_probe, 764 .remove = sdhci_msm_remove, 765 .driver = { 766 .name = "sdhci_msm", 767 .of_match_table = sdhci_msm_dt_match, 768 .pm = &sdhci_msm_pm_ops, 769 }, 770 }; 771 772 module_platform_driver(sdhci_msm_driver); 773 774 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver"); 775 MODULE_LICENSE("GPL v2"); 776