1 /* 2 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver 3 * 4 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 and 8 * only version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 #include <linux/delay.h> 20 #include <linux/mmc/mmc.h> 21 #include <linux/slab.h> 22 23 #include "sdhci-pltfm.h" 24 25 #define CORE_MCI_VERSION 0x50 26 #define CORE_VERSION_MAJOR_SHIFT 28 27 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT) 28 #define CORE_VERSION_MINOR_MASK 0xff 29 30 #define CORE_HC_MODE 0x78 31 #define HC_MODE_EN 0x1 32 #define CORE_POWER 0x0 33 #define CORE_SW_RST BIT(7) 34 35 #define CORE_PWRCTL_STATUS 0xdc 36 #define CORE_PWRCTL_MASK 0xe0 37 #define CORE_PWRCTL_CLEAR 0xe4 38 #define CORE_PWRCTL_CTL 0xe8 39 #define CORE_PWRCTL_BUS_OFF BIT(0) 40 #define CORE_PWRCTL_BUS_ON BIT(1) 41 #define CORE_PWRCTL_IO_LOW BIT(2) 42 #define CORE_PWRCTL_IO_HIGH BIT(3) 43 #define CORE_PWRCTL_BUS_SUCCESS BIT(0) 44 #define CORE_PWRCTL_IO_SUCCESS BIT(2) 45 #define REQ_BUS_OFF BIT(0) 46 #define REQ_BUS_ON BIT(1) 47 #define REQ_IO_LOW BIT(2) 48 #define REQ_IO_HIGH BIT(3) 49 #define INT_MASK 0xf 50 #define MAX_PHASES 16 51 #define CORE_DLL_LOCK BIT(7) 52 #define CORE_DLL_EN BIT(16) 53 #define CORE_CDR_EN BIT(17) 54 #define CORE_CK_OUT_EN BIT(18) 55 #define CORE_CDR_EXT_EN BIT(19) 56 #define CORE_DLL_PDN BIT(29) 57 #define CORE_DLL_RST BIT(30) 58 #define CORE_DLL_CONFIG 0x100 59 #define CORE_DLL_STATUS 0x108 60 61 #define CORE_VENDOR_SPEC 0x10c 62 #define CORE_CLK_PWRSAVE BIT(1) 63 64 #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c 65 66 #define CDR_SELEXT_SHIFT 20 67 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT) 68 #define CMUX_SHIFT_PHASE_SHIFT 24 69 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT) 70 71 struct sdhci_msm_host { 72 struct platform_device *pdev; 73 void __iomem *core_mem; /* MSM SDCC mapped address */ 74 int pwr_irq; /* power irq */ 75 struct clk *clk; /* main SD/MMC bus clock */ 76 struct clk *pclk; /* SDHC peripheral bus clock */ 77 struct clk *bus_clk; /* SDHC bus voter clock */ 78 struct mmc_host *mmc; 79 }; 80 81 /* Platform specific tuning */ 82 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll) 83 { 84 u32 wait_cnt = 50; 85 u8 ck_out_en; 86 struct mmc_host *mmc = host->mmc; 87 88 /* Poll for CK_OUT_EN bit. max. poll time = 50us */ 89 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & 90 CORE_CK_OUT_EN); 91 92 while (ck_out_en != poll) { 93 if (--wait_cnt == 0) { 94 dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n", 95 mmc_hostname(mmc), poll); 96 return -ETIMEDOUT; 97 } 98 udelay(1); 99 100 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & 101 CORE_CK_OUT_EN); 102 } 103 104 return 0; 105 } 106 107 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase) 108 { 109 int rc; 110 static const u8 grey_coded_phase_table[] = { 111 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4, 112 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8 113 }; 114 unsigned long flags; 115 u32 config; 116 struct mmc_host *mmc = host->mmc; 117 118 spin_lock_irqsave(&host->lock, flags); 119 120 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 121 config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN); 122 config |= (CORE_CDR_EXT_EN | CORE_DLL_EN); 123 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 124 125 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */ 126 rc = msm_dll_poll_ck_out_en(host, 0); 127 if (rc) 128 goto err_out; 129 130 /* 131 * Write the selected DLL clock output phase (0 ... 15) 132 * to CDR_SELEXT bit field of DLL_CONFIG register. 133 */ 134 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 135 config &= ~CDR_SELEXT_MASK; 136 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT; 137 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 138 139 /* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */ 140 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) 141 | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG); 142 143 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */ 144 rc = msm_dll_poll_ck_out_en(host, 1); 145 if (rc) 146 goto err_out; 147 148 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 149 config |= CORE_CDR_EN; 150 config &= ~CORE_CDR_EXT_EN; 151 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 152 goto out; 153 154 err_out: 155 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n", 156 mmc_hostname(mmc), phase); 157 out: 158 spin_unlock_irqrestore(&host->lock, flags); 159 return rc; 160 } 161 162 /* 163 * Find out the greatest range of consecuitive selected 164 * DLL clock output phases that can be used as sampling 165 * setting for SD3.0 UHS-I card read operation (in SDR104 166 * timing mode) or for eMMC4.5 card read operation (in HS200 167 * timing mode). 168 * Select the 3/4 of the range and configure the DLL with the 169 * selected DLL clock output phase. 170 */ 171 172 static int msm_find_most_appropriate_phase(struct sdhci_host *host, 173 u8 *phase_table, u8 total_phases) 174 { 175 int ret; 176 u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} }; 177 u8 phases_per_row[MAX_PHASES] = { 0 }; 178 int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0; 179 int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0; 180 bool phase_0_found = false, phase_15_found = false; 181 struct mmc_host *mmc = host->mmc; 182 183 if (!total_phases || (total_phases > MAX_PHASES)) { 184 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n", 185 mmc_hostname(mmc), total_phases); 186 return -EINVAL; 187 } 188 189 for (cnt = 0; cnt < total_phases; cnt++) { 190 ranges[row_index][col_index] = phase_table[cnt]; 191 phases_per_row[row_index] += 1; 192 col_index++; 193 194 if ((cnt + 1) == total_phases) { 195 continue; 196 /* check if next phase in phase_table is consecutive or not */ 197 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) { 198 row_index++; 199 col_index = 0; 200 } 201 } 202 203 if (row_index >= MAX_PHASES) 204 return -EINVAL; 205 206 /* Check if phase-0 is present in first valid window? */ 207 if (!ranges[0][0]) { 208 phase_0_found = true; 209 phase_0_raw_index = 0; 210 /* Check if cycle exist between 2 valid windows */ 211 for (cnt = 1; cnt <= row_index; cnt++) { 212 if (phases_per_row[cnt]) { 213 for (i = 0; i < phases_per_row[cnt]; i++) { 214 if (ranges[cnt][i] == 15) { 215 phase_15_found = true; 216 phase_15_raw_index = cnt; 217 break; 218 } 219 } 220 } 221 } 222 } 223 224 /* If 2 valid windows form cycle then merge them as single window */ 225 if (phase_0_found && phase_15_found) { 226 /* number of phases in raw where phase 0 is present */ 227 u8 phases_0 = phases_per_row[phase_0_raw_index]; 228 /* number of phases in raw where phase 15 is present */ 229 u8 phases_15 = phases_per_row[phase_15_raw_index]; 230 231 if (phases_0 + phases_15 >= MAX_PHASES) 232 /* 233 * If there are more than 1 phase windows then total 234 * number of phases in both the windows should not be 235 * more than or equal to MAX_PHASES. 236 */ 237 return -EINVAL; 238 239 /* Merge 2 cyclic windows */ 240 i = phases_15; 241 for (cnt = 0; cnt < phases_0; cnt++) { 242 ranges[phase_15_raw_index][i] = 243 ranges[phase_0_raw_index][cnt]; 244 if (++i >= MAX_PHASES) 245 break; 246 } 247 248 phases_per_row[phase_0_raw_index] = 0; 249 phases_per_row[phase_15_raw_index] = phases_15 + phases_0; 250 } 251 252 for (cnt = 0; cnt <= row_index; cnt++) { 253 if (phases_per_row[cnt] > curr_max) { 254 curr_max = phases_per_row[cnt]; 255 selected_row_index = cnt; 256 } 257 } 258 259 i = (curr_max * 3) / 4; 260 if (i) 261 i--; 262 263 ret = ranges[selected_row_index][i]; 264 265 if (ret >= MAX_PHASES) { 266 ret = -EINVAL; 267 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n", 268 mmc_hostname(mmc), ret); 269 } 270 271 return ret; 272 } 273 274 static inline void msm_cm_dll_set_freq(struct sdhci_host *host) 275 { 276 u32 mclk_freq = 0, config; 277 278 /* Program the MCLK value to MCLK_FREQ bit field */ 279 if (host->clock <= 112000000) 280 mclk_freq = 0; 281 else if (host->clock <= 125000000) 282 mclk_freq = 1; 283 else if (host->clock <= 137000000) 284 mclk_freq = 2; 285 else if (host->clock <= 150000000) 286 mclk_freq = 3; 287 else if (host->clock <= 162000000) 288 mclk_freq = 4; 289 else if (host->clock <= 175000000) 290 mclk_freq = 5; 291 else if (host->clock <= 187000000) 292 mclk_freq = 6; 293 else if (host->clock <= 200000000) 294 mclk_freq = 7; 295 296 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); 297 config &= ~CMUX_SHIFT_PHASE_MASK; 298 config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT; 299 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); 300 } 301 302 /* Initialize the DLL (Programmable Delay Line) */ 303 static int msm_init_cm_dll(struct sdhci_host *host) 304 { 305 struct mmc_host *mmc = host->mmc; 306 int wait_cnt = 50; 307 unsigned long flags; 308 309 spin_lock_irqsave(&host->lock, flags); 310 311 /* 312 * Make sure that clock is always enabled when DLL 313 * tuning is in progress. Keeping PWRSAVE ON may 314 * turn off the clock. 315 */ 316 writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) 317 & ~CORE_CLK_PWRSAVE), host->ioaddr + CORE_VENDOR_SPEC); 318 319 /* Write 1 to DLL_RST bit of DLL_CONFIG register */ 320 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) 321 | CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG); 322 323 /* Write 1 to DLL_PDN bit of DLL_CONFIG register */ 324 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) 325 | CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG); 326 msm_cm_dll_set_freq(host); 327 328 /* Write 0 to DLL_RST bit of DLL_CONFIG register */ 329 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) 330 & ~CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG); 331 332 /* Write 0 to DLL_PDN bit of DLL_CONFIG register */ 333 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) 334 & ~CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG); 335 336 /* Set DLL_EN bit to 1. */ 337 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) 338 | CORE_DLL_EN), host->ioaddr + CORE_DLL_CONFIG); 339 340 /* Set CK_OUT_EN bit to 1. */ 341 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) 342 | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG); 343 344 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */ 345 while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) & 346 CORE_DLL_LOCK)) { 347 /* max. wait for 50us sec for LOCK bit to be set */ 348 if (--wait_cnt == 0) { 349 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n", 350 mmc_hostname(mmc)); 351 spin_unlock_irqrestore(&host->lock, flags); 352 return -ETIMEDOUT; 353 } 354 udelay(1); 355 } 356 357 spin_unlock_irqrestore(&host->lock, flags); 358 return 0; 359 } 360 361 static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode) 362 { 363 int tuning_seq_cnt = 3; 364 u8 phase, tuned_phases[16], tuned_phase_cnt = 0; 365 int rc; 366 struct mmc_host *mmc = host->mmc; 367 struct mmc_ios ios = host->mmc->ios; 368 369 /* 370 * Tuning is required for SDR104, HS200 and HS400 cards and 371 * if clock frequency is greater than 100MHz in these modes. 372 */ 373 if (host->clock <= 100 * 1000 * 1000 || 374 !((ios.timing == MMC_TIMING_MMC_HS200) || 375 (ios.timing == MMC_TIMING_UHS_SDR104))) 376 return 0; 377 378 retry: 379 /* First of all reset the tuning block */ 380 rc = msm_init_cm_dll(host); 381 if (rc) 382 return rc; 383 384 phase = 0; 385 do { 386 /* Set the phase in delay line hw block */ 387 rc = msm_config_cm_dll_phase(host, phase); 388 if (rc) 389 return rc; 390 391 rc = mmc_send_tuning(mmc, opcode, NULL); 392 if (!rc) { 393 /* Tuning is successful at this tuning point */ 394 tuned_phases[tuned_phase_cnt++] = phase; 395 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n", 396 mmc_hostname(mmc), phase); 397 } 398 } while (++phase < ARRAY_SIZE(tuned_phases)); 399 400 if (tuned_phase_cnt) { 401 rc = msm_find_most_appropriate_phase(host, tuned_phases, 402 tuned_phase_cnt); 403 if (rc < 0) 404 return rc; 405 else 406 phase = rc; 407 408 /* 409 * Finally set the selected phase in delay 410 * line hw block. 411 */ 412 rc = msm_config_cm_dll_phase(host, phase); 413 if (rc) 414 return rc; 415 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n", 416 mmc_hostname(mmc), phase); 417 } else { 418 if (--tuning_seq_cnt) 419 goto retry; 420 /* Tuning failed */ 421 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n", 422 mmc_hostname(mmc)); 423 rc = -EIO; 424 } 425 426 return rc; 427 } 428 429 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, 430 unsigned int uhs) 431 { 432 struct mmc_host *mmc = host->mmc; 433 u16 ctrl_2; 434 435 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 436 /* Select Bus Speed Mode for host */ 437 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 438 switch (uhs) { 439 case MMC_TIMING_UHS_SDR12: 440 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 441 break; 442 case MMC_TIMING_UHS_SDR25: 443 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 444 break; 445 case MMC_TIMING_UHS_SDR50: 446 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 447 break; 448 case MMC_TIMING_MMC_HS200: 449 case MMC_TIMING_UHS_SDR104: 450 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 451 break; 452 case MMC_TIMING_UHS_DDR50: 453 case MMC_TIMING_MMC_DDR52: 454 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 455 break; 456 } 457 458 /* 459 * When clock frequency is less than 100MHz, the feedback clock must be 460 * provided and DLL must not be used so that tuning can be skipped. To 461 * provide feedback clock, the mode selection can be any value less 462 * than 3'b011 in bits [2:0] of HOST CONTROL2 register. 463 */ 464 if (host->clock <= 100000000 && 465 (uhs == MMC_TIMING_MMC_HS400 || 466 uhs == MMC_TIMING_MMC_HS200 || 467 uhs == MMC_TIMING_UHS_SDR104)) 468 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 469 470 dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n", 471 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2); 472 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 473 } 474 475 static void sdhci_msm_voltage_switch(struct sdhci_host *host) 476 { 477 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 478 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 479 u32 irq_status, irq_ack = 0; 480 481 irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS); 482 irq_status &= INT_MASK; 483 484 writel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR); 485 486 if (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF)) 487 irq_ack |= CORE_PWRCTL_BUS_SUCCESS; 488 if (irq_status & (CORE_PWRCTL_IO_LOW | CORE_PWRCTL_IO_HIGH)) 489 irq_ack |= CORE_PWRCTL_IO_SUCCESS; 490 491 /* 492 * The driver has to acknowledge the interrupt, switch voltages and 493 * report back if it succeded or not to this register. The voltage 494 * switches are handled by the sdhci core, so just report success. 495 */ 496 writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL); 497 } 498 499 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) 500 { 501 struct sdhci_host *host = (struct sdhci_host *)data; 502 503 sdhci_msm_voltage_switch(host); 504 505 return IRQ_HANDLED; 506 } 507 508 static const struct of_device_id sdhci_msm_dt_match[] = { 509 { .compatible = "qcom,sdhci-msm-v4" }, 510 {}, 511 }; 512 513 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); 514 515 static const struct sdhci_ops sdhci_msm_ops = { 516 .platform_execute_tuning = sdhci_msm_execute_tuning, 517 .reset = sdhci_reset, 518 .set_clock = sdhci_set_clock, 519 .set_bus_width = sdhci_set_bus_width, 520 .set_uhs_signaling = sdhci_msm_set_uhs_signaling, 521 .voltage_switch = sdhci_msm_voltage_switch, 522 }; 523 524 static const struct sdhci_pltfm_data sdhci_msm_pdata = { 525 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 526 SDHCI_QUIRK_NO_CARD_NO_RESET | 527 SDHCI_QUIRK_SINGLE_POWER_WRITE, 528 .ops = &sdhci_msm_ops, 529 }; 530 531 static int sdhci_msm_probe(struct platform_device *pdev) 532 { 533 struct sdhci_host *host; 534 struct sdhci_pltfm_host *pltfm_host; 535 struct sdhci_msm_host *msm_host; 536 struct resource *core_memres; 537 int ret; 538 u16 host_version, core_minor; 539 u32 core_version, caps; 540 u8 core_major; 541 542 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host)); 543 if (IS_ERR(host)) 544 return PTR_ERR(host); 545 546 pltfm_host = sdhci_priv(host); 547 msm_host = sdhci_pltfm_priv(pltfm_host); 548 msm_host->mmc = host->mmc; 549 msm_host->pdev = pdev; 550 551 ret = mmc_of_parse(host->mmc); 552 if (ret) 553 goto pltfm_free; 554 555 sdhci_get_of_property(pdev); 556 557 /* Setup SDCC bus voter clock. */ 558 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); 559 if (!IS_ERR(msm_host->bus_clk)) { 560 /* Vote for max. clk rate for max. performance */ 561 ret = clk_set_rate(msm_host->bus_clk, INT_MAX); 562 if (ret) 563 goto pltfm_free; 564 ret = clk_prepare_enable(msm_host->bus_clk); 565 if (ret) 566 goto pltfm_free; 567 } 568 569 /* Setup main peripheral bus clock */ 570 msm_host->pclk = devm_clk_get(&pdev->dev, "iface"); 571 if (IS_ERR(msm_host->pclk)) { 572 ret = PTR_ERR(msm_host->pclk); 573 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret); 574 goto bus_clk_disable; 575 } 576 577 ret = clk_prepare_enable(msm_host->pclk); 578 if (ret) 579 goto bus_clk_disable; 580 581 /* Setup SDC MMC clock */ 582 msm_host->clk = devm_clk_get(&pdev->dev, "core"); 583 if (IS_ERR(msm_host->clk)) { 584 ret = PTR_ERR(msm_host->clk); 585 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret); 586 goto pclk_disable; 587 } 588 589 /* Vote for maximum clock rate for maximum performance */ 590 ret = clk_set_rate(msm_host->clk, INT_MAX); 591 if (ret) 592 dev_warn(&pdev->dev, "core clock boost failed\n"); 593 594 ret = clk_prepare_enable(msm_host->clk); 595 if (ret) 596 goto pclk_disable; 597 598 core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1); 599 msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres); 600 601 if (IS_ERR(msm_host->core_mem)) { 602 dev_err(&pdev->dev, "Failed to remap registers\n"); 603 ret = PTR_ERR(msm_host->core_mem); 604 goto clk_disable; 605 } 606 607 /* Reset the core and Enable SDHC mode */ 608 writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) | 609 CORE_SW_RST, msm_host->core_mem + CORE_POWER); 610 611 /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */ 612 usleep_range(1000, 5000); 613 if (readl(msm_host->core_mem + CORE_POWER) & CORE_SW_RST) { 614 dev_err(&pdev->dev, "Stuck in reset\n"); 615 ret = -ETIMEDOUT; 616 goto clk_disable; 617 } 618 619 /* Set HC_MODE_EN bit in HC_MODE register */ 620 writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE)); 621 622 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); 623 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", 624 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >> 625 SDHCI_VENDOR_VER_SHIFT)); 626 627 core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION); 628 core_major = (core_version & CORE_VERSION_MAJOR_MASK) >> 629 CORE_VERSION_MAJOR_SHIFT; 630 core_minor = core_version & CORE_VERSION_MINOR_MASK; 631 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n", 632 core_version, core_major, core_minor); 633 634 /* 635 * Support for some capabilities is not advertised by newer 636 * controller versions and must be explicitly enabled. 637 */ 638 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) { 639 caps = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); 640 caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; 641 writel_relaxed(caps, host->ioaddr + 642 CORE_VENDOR_SPEC_CAPABILITIES0); 643 } 644 645 /* Setup IRQ for handling power/voltage tasks with PMIC */ 646 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); 647 if (msm_host->pwr_irq < 0) { 648 dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n", 649 msm_host->pwr_irq); 650 goto clk_disable; 651 } 652 653 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, 654 sdhci_msm_pwr_irq, IRQF_ONESHOT, 655 dev_name(&pdev->dev), host); 656 if (ret) { 657 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret); 658 goto clk_disable; 659 } 660 661 ret = sdhci_add_host(host); 662 if (ret) 663 goto clk_disable; 664 665 return 0; 666 667 clk_disable: 668 clk_disable_unprepare(msm_host->clk); 669 pclk_disable: 670 clk_disable_unprepare(msm_host->pclk); 671 bus_clk_disable: 672 if (!IS_ERR(msm_host->bus_clk)) 673 clk_disable_unprepare(msm_host->bus_clk); 674 pltfm_free: 675 sdhci_pltfm_free(pdev); 676 return ret; 677 } 678 679 static int sdhci_msm_remove(struct platform_device *pdev) 680 { 681 struct sdhci_host *host = platform_get_drvdata(pdev); 682 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 683 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 684 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == 685 0xffffffff); 686 687 sdhci_remove_host(host, dead); 688 clk_disable_unprepare(msm_host->clk); 689 clk_disable_unprepare(msm_host->pclk); 690 if (!IS_ERR(msm_host->bus_clk)) 691 clk_disable_unprepare(msm_host->bus_clk); 692 sdhci_pltfm_free(pdev); 693 return 0; 694 } 695 696 static struct platform_driver sdhci_msm_driver = { 697 .probe = sdhci_msm_probe, 698 .remove = sdhci_msm_remove, 699 .driver = { 700 .name = "sdhci_msm", 701 .of_match_table = sdhci_msm_dt_match, 702 }, 703 }; 704 705 module_platform_driver(sdhci_msm_driver); 706 707 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver"); 708 MODULE_LICENSE("GPL v2"); 709