1 /* 2 * Copyright (C) 2014 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 /* 15 * iProc SDHCI platform driver 16 */ 17 18 #include <linux/acpi.h> 19 #include <linux/delay.h> 20 #include <linux/module.h> 21 #include <linux/mmc/host.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include "sdhci-pltfm.h" 25 26 struct sdhci_iproc_data { 27 const struct sdhci_pltfm_data *pdata; 28 u32 caps; 29 u32 caps1; 30 u32 mmc_caps; 31 }; 32 33 struct sdhci_iproc_host { 34 const struct sdhci_iproc_data *data; 35 u32 shadow_cmd; 36 u32 shadow_blk; 37 bool is_cmd_shadowed; 38 bool is_blk_shadowed; 39 }; 40 41 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18) 42 43 static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg) 44 { 45 u32 val = readl(host->ioaddr + reg); 46 47 pr_debug("%s: readl [0x%02x] 0x%08x\n", 48 mmc_hostname(host->mmc), reg, val); 49 return val; 50 } 51 52 static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg) 53 { 54 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 55 struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host); 56 u32 val; 57 u16 word; 58 59 if ((reg == SDHCI_TRANSFER_MODE) && iproc_host->is_cmd_shadowed) { 60 /* Get the saved transfer mode */ 61 val = iproc_host->shadow_cmd; 62 } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) && 63 iproc_host->is_blk_shadowed) { 64 /* Get the saved block info */ 65 val = iproc_host->shadow_blk; 66 } else { 67 val = sdhci_iproc_readl(host, (reg & ~3)); 68 } 69 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff; 70 return word; 71 } 72 73 static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg) 74 { 75 u32 val = sdhci_iproc_readl(host, (reg & ~3)); 76 u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff; 77 return byte; 78 } 79 80 static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg) 81 { 82 pr_debug("%s: writel [0x%02x] 0x%08x\n", 83 mmc_hostname(host->mmc), reg, val); 84 85 writel(val, host->ioaddr + reg); 86 87 if (host->clock <= 400000) { 88 /* Round up to micro-second four SD clock delay */ 89 if (host->clock) 90 udelay((4 * 1000000 + host->clock - 1) / host->clock); 91 else 92 udelay(10); 93 } 94 } 95 96 /* 97 * The Arasan has a bugette whereby it may lose the content of successive 98 * writes to the same register that are within two SD-card clock cycles of 99 * each other (a clock domain crossing problem). The data 100 * register does not have this problem, which is just as well - otherwise we'd 101 * have to nobble the DMA engine too. 102 * 103 * This wouldn't be a problem with the code except that we can only write the 104 * controller with 32-bit writes. So two different 16-bit registers are 105 * written back to back creates the problem. 106 * 107 * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT 108 * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND. 109 * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so 110 * the work around can be further optimized. We can keep shadow values of 111 * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued. 112 * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed 113 * by the TRANSFER+COMMAND in another 32-bit write. 114 */ 115 static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg) 116 { 117 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 118 struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host); 119 u32 word_shift = REG_OFFSET_IN_BITS(reg); 120 u32 mask = 0xffff << word_shift; 121 u32 oldval, newval; 122 123 if (reg == SDHCI_COMMAND) { 124 /* Write the block now as we are issuing a command */ 125 if (iproc_host->is_blk_shadowed) { 126 sdhci_iproc_writel(host, iproc_host->shadow_blk, 127 SDHCI_BLOCK_SIZE); 128 iproc_host->is_blk_shadowed = false; 129 } 130 oldval = iproc_host->shadow_cmd; 131 iproc_host->is_cmd_shadowed = false; 132 } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) && 133 iproc_host->is_blk_shadowed) { 134 /* Block size and count are stored in shadow reg */ 135 oldval = iproc_host->shadow_blk; 136 } else { 137 /* Read reg, all other registers are not shadowed */ 138 oldval = sdhci_iproc_readl(host, (reg & ~3)); 139 } 140 newval = (oldval & ~mask) | (val << word_shift); 141 142 if (reg == SDHCI_TRANSFER_MODE) { 143 /* Save the transfer mode until the command is issued */ 144 iproc_host->shadow_cmd = newval; 145 iproc_host->is_cmd_shadowed = true; 146 } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) { 147 /* Save the block info until the command is issued */ 148 iproc_host->shadow_blk = newval; 149 iproc_host->is_blk_shadowed = true; 150 } else { 151 /* Command or other regular 32-bit write */ 152 sdhci_iproc_writel(host, newval, reg & ~3); 153 } 154 } 155 156 static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg) 157 { 158 u32 oldval = sdhci_iproc_readl(host, (reg & ~3)); 159 u32 byte_shift = REG_OFFSET_IN_BITS(reg); 160 u32 mask = 0xff << byte_shift; 161 u32 newval = (oldval & ~mask) | (val << byte_shift); 162 163 sdhci_iproc_writel(host, newval, reg & ~3); 164 } 165 166 static unsigned int sdhci_iproc_get_max_clock(struct sdhci_host *host) 167 { 168 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 169 170 if (pltfm_host->clk) 171 return sdhci_pltfm_clk_get_max_clock(host); 172 else 173 return pltfm_host->clock; 174 } 175 176 static const struct sdhci_ops sdhci_iproc_ops = { 177 .set_clock = sdhci_set_clock, 178 .get_max_clock = sdhci_iproc_get_max_clock, 179 .set_bus_width = sdhci_set_bus_width, 180 .reset = sdhci_reset, 181 .set_uhs_signaling = sdhci_set_uhs_signaling, 182 }; 183 184 static const struct sdhci_ops sdhci_iproc_32only_ops = { 185 .read_l = sdhci_iproc_readl, 186 .read_w = sdhci_iproc_readw, 187 .read_b = sdhci_iproc_readb, 188 .write_l = sdhci_iproc_writel, 189 .write_w = sdhci_iproc_writew, 190 .write_b = sdhci_iproc_writeb, 191 .set_clock = sdhci_set_clock, 192 .get_max_clock = sdhci_iproc_get_max_clock, 193 .set_bus_width = sdhci_set_bus_width, 194 .reset = sdhci_reset, 195 .set_uhs_signaling = sdhci_set_uhs_signaling, 196 }; 197 198 static const struct sdhci_pltfm_data sdhci_iproc_cygnus_pltfm_data = { 199 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 200 SDHCI_QUIRK_NO_HISPD_BIT, 201 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN | SDHCI_QUIRK2_HOST_OFF_CARD_ON, 202 .ops = &sdhci_iproc_32only_ops, 203 }; 204 205 static const struct sdhci_iproc_data iproc_cygnus_data = { 206 .pdata = &sdhci_iproc_cygnus_pltfm_data, 207 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT) 208 & SDHCI_MAX_BLOCK_MASK) | 209 SDHCI_CAN_VDD_330 | 210 SDHCI_CAN_VDD_180 | 211 SDHCI_CAN_DO_SUSPEND | 212 SDHCI_CAN_DO_HISPD | 213 SDHCI_CAN_DO_ADMA2 | 214 SDHCI_CAN_DO_SDMA, 215 .caps1 = SDHCI_DRIVER_TYPE_C | 216 SDHCI_DRIVER_TYPE_D | 217 SDHCI_SUPPORT_DDR50, 218 .mmc_caps = MMC_CAP_1_8V_DDR, 219 }; 220 221 static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = { 222 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 223 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 | 224 SDHCI_QUIRK_NO_HISPD_BIT, 225 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN, 226 .ops = &sdhci_iproc_ops, 227 }; 228 229 static const struct sdhci_iproc_data iproc_data = { 230 .pdata = &sdhci_iproc_pltfm_data, 231 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT) 232 & SDHCI_MAX_BLOCK_MASK) | 233 SDHCI_CAN_VDD_330 | 234 SDHCI_CAN_VDD_180 | 235 SDHCI_CAN_DO_SUSPEND | 236 SDHCI_CAN_DO_HISPD | 237 SDHCI_CAN_DO_ADMA2 | 238 SDHCI_CAN_DO_SDMA, 239 .caps1 = SDHCI_DRIVER_TYPE_C | 240 SDHCI_DRIVER_TYPE_D | 241 SDHCI_SUPPORT_DDR50, 242 }; 243 244 static const struct sdhci_pltfm_data sdhci_bcm2835_pltfm_data = { 245 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 246 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 247 SDHCI_QUIRK_MISSING_CAPS | 248 SDHCI_QUIRK_NO_HISPD_BIT, 249 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 250 .ops = &sdhci_iproc_32only_ops, 251 }; 252 253 static const struct sdhci_iproc_data bcm2835_data = { 254 .pdata = &sdhci_bcm2835_pltfm_data, 255 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT) 256 & SDHCI_MAX_BLOCK_MASK) | 257 SDHCI_CAN_VDD_330 | 258 SDHCI_CAN_DO_HISPD, 259 .caps1 = SDHCI_DRIVER_TYPE_A | 260 SDHCI_DRIVER_TYPE_C, 261 .mmc_caps = 0x00000000, 262 }; 263 264 static const struct of_device_id sdhci_iproc_of_match[] = { 265 { .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data }, 266 { .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_cygnus_data}, 267 { .compatible = "brcm,sdhci-iproc", .data = &iproc_data }, 268 { } 269 }; 270 MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match); 271 272 static const struct acpi_device_id sdhci_iproc_acpi_ids[] = { 273 { .id = "BRCM5871", .driver_data = (kernel_ulong_t)&iproc_cygnus_data }, 274 { .id = "BRCM5872", .driver_data = (kernel_ulong_t)&iproc_data }, 275 { /* sentinel */ } 276 }; 277 MODULE_DEVICE_TABLE(acpi, sdhci_iproc_acpi_ids); 278 279 static int sdhci_iproc_probe(struct platform_device *pdev) 280 { 281 struct device *dev = &pdev->dev; 282 const struct sdhci_iproc_data *iproc_data = NULL; 283 struct sdhci_host *host; 284 struct sdhci_iproc_host *iproc_host; 285 struct sdhci_pltfm_host *pltfm_host; 286 int ret; 287 288 iproc_data = device_get_match_data(dev); 289 if (!iproc_data) 290 return -ENODEV; 291 292 host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host)); 293 if (IS_ERR(host)) 294 return PTR_ERR(host); 295 296 pltfm_host = sdhci_priv(host); 297 iproc_host = sdhci_pltfm_priv(pltfm_host); 298 299 iproc_host->data = iproc_data; 300 301 ret = mmc_of_parse(host->mmc); 302 if (ret) 303 goto err; 304 305 sdhci_get_property(pdev); 306 307 host->mmc->caps |= iproc_host->data->mmc_caps; 308 309 if (dev->of_node) { 310 pltfm_host->clk = devm_clk_get(dev, NULL); 311 if (IS_ERR(pltfm_host->clk)) { 312 ret = PTR_ERR(pltfm_host->clk); 313 goto err; 314 } 315 ret = clk_prepare_enable(pltfm_host->clk); 316 if (ret) { 317 dev_err(dev, "failed to enable host clk\n"); 318 goto err; 319 } 320 } 321 322 if (iproc_host->data->pdata->quirks & SDHCI_QUIRK_MISSING_CAPS) { 323 host->caps = iproc_host->data->caps; 324 host->caps1 = iproc_host->data->caps1; 325 } 326 327 ret = sdhci_add_host(host); 328 if (ret) 329 goto err_clk; 330 331 return 0; 332 333 err_clk: 334 if (dev->of_node) 335 clk_disable_unprepare(pltfm_host->clk); 336 err: 337 sdhci_pltfm_free(pdev); 338 return ret; 339 } 340 341 static struct platform_driver sdhci_iproc_driver = { 342 .driver = { 343 .name = "sdhci-iproc", 344 .of_match_table = sdhci_iproc_of_match, 345 .acpi_match_table = ACPI_PTR(sdhci_iproc_acpi_ids), 346 .pm = &sdhci_pltfm_pmops, 347 }, 348 .probe = sdhci_iproc_probe, 349 .remove = sdhci_pltfm_unregister, 350 }; 351 module_platform_driver(sdhci_iproc_driver); 352 353 MODULE_AUTHOR("Broadcom"); 354 MODULE_DESCRIPTION("IPROC SDHCI driver"); 355 MODULE_LICENSE("GPL v2"); 356