1 /* 2 * Copyright (C) 2014 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 /* 15 * iProc SDHCI platform driver 16 */ 17 18 #include <linux/delay.h> 19 #include <linux/module.h> 20 #include <linux/mmc/host.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include "sdhci-pltfm.h" 24 25 struct sdhci_iproc_data { 26 const struct sdhci_pltfm_data *pdata; 27 u32 caps; 28 u32 caps1; 29 u32 mmc_caps; 30 }; 31 32 struct sdhci_iproc_host { 33 const struct sdhci_iproc_data *data; 34 u32 shadow_cmd; 35 u32 shadow_blk; 36 }; 37 38 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18) 39 40 static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg) 41 { 42 u32 val = readl(host->ioaddr + reg); 43 44 pr_debug("%s: readl [0x%02x] 0x%08x\n", 45 mmc_hostname(host->mmc), reg, val); 46 return val; 47 } 48 49 static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg) 50 { 51 u32 val = sdhci_iproc_readl(host, (reg & ~3)); 52 u16 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff; 53 return word; 54 } 55 56 static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg) 57 { 58 u32 val = sdhci_iproc_readl(host, (reg & ~3)); 59 u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff; 60 return byte; 61 } 62 63 static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg) 64 { 65 pr_debug("%s: writel [0x%02x] 0x%08x\n", 66 mmc_hostname(host->mmc), reg, val); 67 68 writel(val, host->ioaddr + reg); 69 70 if (host->clock <= 400000) { 71 /* Round up to micro-second four SD clock delay */ 72 if (host->clock) 73 udelay((4 * 1000000 + host->clock - 1) / host->clock); 74 else 75 udelay(10); 76 } 77 } 78 79 /* 80 * The Arasan has a bugette whereby it may lose the content of successive 81 * writes to the same register that are within two SD-card clock cycles of 82 * each other (a clock domain crossing problem). The data 83 * register does not have this problem, which is just as well - otherwise we'd 84 * have to nobble the DMA engine too. 85 * 86 * This wouldn't be a problem with the code except that we can only write the 87 * controller with 32-bit writes. So two different 16-bit registers are 88 * written back to back creates the problem. 89 * 90 * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT 91 * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND. 92 * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so 93 * the work around can be further optimized. We can keep shadow values of 94 * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued. 95 * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed 96 * by the TRANSFER+COMMAND in another 32-bit write. 97 */ 98 static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg) 99 { 100 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 101 struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host); 102 u32 word_shift = REG_OFFSET_IN_BITS(reg); 103 u32 mask = 0xffff << word_shift; 104 u32 oldval, newval; 105 106 if (reg == SDHCI_COMMAND) { 107 /* Write the block now as we are issuing a command */ 108 if (iproc_host->shadow_blk != 0) { 109 sdhci_iproc_writel(host, iproc_host->shadow_blk, 110 SDHCI_BLOCK_SIZE); 111 iproc_host->shadow_blk = 0; 112 } 113 oldval = iproc_host->shadow_cmd; 114 } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) { 115 /* Block size and count are stored in shadow reg */ 116 oldval = iproc_host->shadow_blk; 117 } else { 118 /* Read reg, all other registers are not shadowed */ 119 oldval = sdhci_iproc_readl(host, (reg & ~3)); 120 } 121 newval = (oldval & ~mask) | (val << word_shift); 122 123 if (reg == SDHCI_TRANSFER_MODE) { 124 /* Save the transfer mode until the command is issued */ 125 iproc_host->shadow_cmd = newval; 126 } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) { 127 /* Save the block info until the command is issued */ 128 iproc_host->shadow_blk = newval; 129 } else { 130 /* Command or other regular 32-bit write */ 131 sdhci_iproc_writel(host, newval, reg & ~3); 132 } 133 } 134 135 static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg) 136 { 137 u32 oldval = sdhci_iproc_readl(host, (reg & ~3)); 138 u32 byte_shift = REG_OFFSET_IN_BITS(reg); 139 u32 mask = 0xff << byte_shift; 140 u32 newval = (oldval & ~mask) | (val << byte_shift); 141 142 sdhci_iproc_writel(host, newval, reg & ~3); 143 } 144 145 static const struct sdhci_ops sdhci_iproc_ops = { 146 .read_l = sdhci_iproc_readl, 147 .read_w = sdhci_iproc_readw, 148 .read_b = sdhci_iproc_readb, 149 .write_l = sdhci_iproc_writel, 150 .write_w = sdhci_iproc_writew, 151 .write_b = sdhci_iproc_writeb, 152 .set_clock = sdhci_set_clock, 153 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 154 .set_bus_width = sdhci_set_bus_width, 155 .reset = sdhci_reset, 156 .set_uhs_signaling = sdhci_set_uhs_signaling, 157 }; 158 159 static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = { 160 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 161 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN, 162 .ops = &sdhci_iproc_ops, 163 }; 164 165 static const struct sdhci_iproc_data iproc_data = { 166 .pdata = &sdhci_iproc_pltfm_data, 167 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT) 168 & SDHCI_MAX_BLOCK_MASK) | 169 SDHCI_CAN_VDD_330 | 170 SDHCI_CAN_VDD_180 | 171 SDHCI_CAN_DO_SUSPEND | 172 SDHCI_CAN_DO_HISPD | 173 SDHCI_CAN_DO_ADMA2 | 174 SDHCI_CAN_DO_SDMA, 175 .caps1 = SDHCI_DRIVER_TYPE_C | 176 SDHCI_DRIVER_TYPE_D | 177 SDHCI_SUPPORT_DDR50, 178 .mmc_caps = MMC_CAP_1_8V_DDR, 179 }; 180 181 static const struct sdhci_pltfm_data sdhci_bcm2835_pltfm_data = { 182 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 183 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 184 SDHCI_QUIRK_MISSING_CAPS, 185 .ops = &sdhci_iproc_ops, 186 }; 187 188 static const struct sdhci_iproc_data bcm2835_data = { 189 .pdata = &sdhci_bcm2835_pltfm_data, 190 .caps = SDHCI_CAN_VDD_330, 191 .caps1 = 0x00000000, 192 .mmc_caps = 0x00000000, 193 }; 194 195 static const struct of_device_id sdhci_iproc_of_match[] = { 196 { .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data }, 197 { .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_data }, 198 { } 199 }; 200 MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match); 201 202 static int sdhci_iproc_probe(struct platform_device *pdev) 203 { 204 const struct of_device_id *match; 205 const struct sdhci_iproc_data *iproc_data; 206 struct sdhci_host *host; 207 struct sdhci_iproc_host *iproc_host; 208 struct sdhci_pltfm_host *pltfm_host; 209 int ret; 210 211 match = of_match_device(sdhci_iproc_of_match, &pdev->dev); 212 if (!match) 213 return -EINVAL; 214 iproc_data = match->data; 215 216 host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host)); 217 if (IS_ERR(host)) 218 return PTR_ERR(host); 219 220 pltfm_host = sdhci_priv(host); 221 iproc_host = sdhci_pltfm_priv(pltfm_host); 222 223 iproc_host->data = iproc_data; 224 225 mmc_of_parse(host->mmc); 226 sdhci_get_of_property(pdev); 227 228 host->mmc->caps |= iproc_host->data->mmc_caps; 229 230 pltfm_host->clk = devm_clk_get(&pdev->dev, NULL); 231 if (IS_ERR(pltfm_host->clk)) { 232 ret = PTR_ERR(pltfm_host->clk); 233 goto err; 234 } 235 ret = clk_prepare_enable(pltfm_host->clk); 236 if (ret) { 237 dev_err(&pdev->dev, "failed to enable host clk\n"); 238 goto err; 239 } 240 241 if (iproc_host->data->pdata->quirks & SDHCI_QUIRK_MISSING_CAPS) { 242 host->caps = iproc_host->data->caps; 243 host->caps1 = iproc_host->data->caps1; 244 } 245 246 ret = sdhci_add_host(host); 247 if (ret) 248 goto err_clk; 249 250 return 0; 251 252 err_clk: 253 clk_disable_unprepare(pltfm_host->clk); 254 err: 255 sdhci_pltfm_free(pdev); 256 return ret; 257 } 258 259 static struct platform_driver sdhci_iproc_driver = { 260 .driver = { 261 .name = "sdhci-iproc", 262 .of_match_table = sdhci_iproc_of_match, 263 .pm = &sdhci_pltfm_pmops, 264 }, 265 .probe = sdhci_iproc_probe, 266 .remove = sdhci_pltfm_unregister, 267 }; 268 module_platform_driver(sdhci_iproc_driver); 269 270 MODULE_AUTHOR("Broadcom"); 271 MODULE_DESCRIPTION("IPROC SDHCI driver"); 272 MODULE_LICENSE("GPL v2"); 273