1 /* 2 * Freescale eSDHC i.MX controller driver for the platform bus. 3 * 4 * derived from the OF-version. 5 * 6 * Copyright (c) 2010 Pengutronix e.K. 7 * Author: Wolfram Sang <w.sang@pengutronix.de> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License. 12 */ 13 14 #include <linux/io.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/clk.h> 18 #include <linux/gpio.h> 19 #include <linux/module.h> 20 #include <linux/slab.h> 21 #include <linux/mmc/host.h> 22 #include <linux/mmc/mmc.h> 23 #include <linux/mmc/sdio.h> 24 #include <linux/mmc/slot-gpio.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/of_gpio.h> 28 #include <linux/pinctrl/consumer.h> 29 #include <linux/platform_data/mmc-esdhc-imx.h> 30 #include "sdhci-pltfm.h" 31 #include "sdhci-esdhc.h" 32 33 #define ESDHC_CTRL_D3CD 0x08 34 /* VENDOR SPEC register */ 35 #define ESDHC_VENDOR_SPEC 0xc0 36 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 37 #define ESDHC_WTMK_LVL 0x44 38 #define ESDHC_MIX_CTRL 0x48 39 #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 40 /* Bits 3 and 6 are not SDHCI standard definitions */ 41 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 42 43 /* 44 * Our interpretation of the SDHCI_HOST_CONTROL register 45 */ 46 #define ESDHC_CTRL_4BITBUS (0x1 << 1) 47 #define ESDHC_CTRL_8BITBUS (0x2 << 1) 48 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 49 50 /* 51 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: 52 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 53 * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 54 * Define this macro DMA error INT for fsl eSDHC 55 */ 56 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 57 58 /* 59 * The CMDTYPE of the CMD register (offset 0xE) should be set to 60 * "11" when the STOP CMD12 is issued on imx53 to abort one 61 * open ended multi-blk IO. Otherwise the TC INT wouldn't 62 * be generated. 63 * In exact block transfer, the controller doesn't complete the 64 * operations automatically as required at the end of the 65 * transfer and remains on hold if the abort command is not sent. 66 * As a result, the TC flag is not asserted and SW received timeout 67 * exeception. Bit1 of Vendor Spec registor is used to fix it. 68 */ 69 #define ESDHC_FLAG_MULTIBLK_NO_INT (1 << 1) 70 71 enum imx_esdhc_type { 72 IMX25_ESDHC, 73 IMX35_ESDHC, 74 IMX51_ESDHC, 75 IMX53_ESDHC, 76 IMX6Q_USDHC, 77 }; 78 79 struct pltfm_imx_data { 80 int flags; 81 u32 scratchpad; 82 enum imx_esdhc_type devtype; 83 struct pinctrl *pinctrl; 84 struct esdhc_platform_data boarddata; 85 struct clk *clk_ipg; 86 struct clk *clk_ahb; 87 struct clk *clk_per; 88 }; 89 90 static struct platform_device_id imx_esdhc_devtype[] = { 91 { 92 .name = "sdhci-esdhc-imx25", 93 .driver_data = IMX25_ESDHC, 94 }, { 95 .name = "sdhci-esdhc-imx35", 96 .driver_data = IMX35_ESDHC, 97 }, { 98 .name = "sdhci-esdhc-imx51", 99 .driver_data = IMX51_ESDHC, 100 }, { 101 .name = "sdhci-esdhc-imx53", 102 .driver_data = IMX53_ESDHC, 103 }, { 104 .name = "sdhci-usdhc-imx6q", 105 .driver_data = IMX6Q_USDHC, 106 }, { 107 /* sentinel */ 108 } 109 }; 110 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 111 112 static const struct of_device_id imx_esdhc_dt_ids[] = { 113 { .compatible = "fsl,imx25-esdhc", .data = &imx_esdhc_devtype[IMX25_ESDHC], }, 114 { .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], }, 115 { .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], }, 116 { .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], }, 117 { .compatible = "fsl,imx6q-usdhc", .data = &imx_esdhc_devtype[IMX6Q_USDHC], }, 118 { /* sentinel */ } 119 }; 120 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 121 122 static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 123 { 124 return data->devtype == IMX25_ESDHC; 125 } 126 127 static inline int is_imx35_esdhc(struct pltfm_imx_data *data) 128 { 129 return data->devtype == IMX35_ESDHC; 130 } 131 132 static inline int is_imx51_esdhc(struct pltfm_imx_data *data) 133 { 134 return data->devtype == IMX51_ESDHC; 135 } 136 137 static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 138 { 139 return data->devtype == IMX53_ESDHC; 140 } 141 142 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 143 { 144 return data->devtype == IMX6Q_USDHC; 145 } 146 147 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 148 { 149 void __iomem *base = host->ioaddr + (reg & ~0x3); 150 u32 shift = (reg & 0x3) * 8; 151 152 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 153 } 154 155 static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 156 { 157 u32 val = readl(host->ioaddr + reg); 158 159 if (unlikely(reg == SDHCI_CAPABILITIES)) { 160 /* In FSL esdhc IC module, only bit20 is used to indicate the 161 * ADMA2 capability of esdhc, but this bit is messed up on 162 * some SOCs (e.g. on MX25, MX35 this bit is set, but they 163 * don't actually support ADMA2). So set the BROKEN_ADMA 164 * uirk on MX25/35 platforms. 165 */ 166 167 if (val & SDHCI_CAN_DO_ADMA1) { 168 val &= ~SDHCI_CAN_DO_ADMA1; 169 val |= SDHCI_CAN_DO_ADMA2; 170 } 171 } 172 173 if (unlikely(reg == SDHCI_INT_STATUS)) { 174 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 175 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 176 val |= SDHCI_INT_ADMA_ERROR; 177 } 178 } 179 180 return val; 181 } 182 183 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 184 { 185 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 186 struct pltfm_imx_data *imx_data = pltfm_host->priv; 187 u32 data; 188 189 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 190 if (val & SDHCI_INT_CARD_INT) { 191 /* 192 * Clear and then set D3CD bit to avoid missing the 193 * card interrupt. This is a eSDHC controller problem 194 * so we need to apply the following workaround: clear 195 * and set D3CD bit will make eSDHC re-sample the card 196 * interrupt. In case a card interrupt was lost, 197 * re-sample it by the following steps. 198 */ 199 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 200 data &= ~ESDHC_CTRL_D3CD; 201 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 202 data |= ESDHC_CTRL_D3CD; 203 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 204 } 205 } 206 207 if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 208 && (reg == SDHCI_INT_STATUS) 209 && (val & SDHCI_INT_DATA_END))) { 210 u32 v; 211 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 212 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 213 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 214 } 215 216 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 217 if (val & SDHCI_INT_ADMA_ERROR) { 218 val &= ~SDHCI_INT_ADMA_ERROR; 219 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 220 } 221 } 222 223 writel(val, host->ioaddr + reg); 224 } 225 226 static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 227 { 228 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 229 struct pltfm_imx_data *imx_data = pltfm_host->priv; 230 231 if (unlikely(reg == SDHCI_HOST_VERSION)) { 232 reg ^= 2; 233 if (is_imx6q_usdhc(imx_data)) { 234 /* 235 * The usdhc register returns a wrong host version. 236 * Correct it here. 237 */ 238 return SDHCI_SPEC_300; 239 } 240 } 241 242 return readw(host->ioaddr + reg); 243 } 244 245 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 246 { 247 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 248 struct pltfm_imx_data *imx_data = pltfm_host->priv; 249 250 switch (reg) { 251 case SDHCI_TRANSFER_MODE: 252 if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 253 && (host->cmd->opcode == SD_IO_RW_EXTENDED) 254 && (host->cmd->data->blocks > 1) 255 && (host->cmd->data->flags & MMC_DATA_READ)) { 256 u32 v; 257 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 258 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 259 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 260 } 261 262 if (is_imx6q_usdhc(imx_data)) { 263 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 264 /* Swap AC23 bit */ 265 if (val & SDHCI_TRNS_AUTO_CMD23) { 266 val &= ~SDHCI_TRNS_AUTO_CMD23; 267 val |= ESDHC_MIX_CTRL_AC23EN; 268 } 269 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 270 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 271 } else { 272 /* 273 * Postpone this write, we must do it together with a 274 * command write that is down below. 275 */ 276 imx_data->scratchpad = val; 277 } 278 return; 279 case SDHCI_COMMAND: 280 if ((host->cmd->opcode == MMC_STOP_TRANSMISSION || 281 host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 282 (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 283 val |= SDHCI_CMD_ABORTCMD; 284 285 if (is_imx6q_usdhc(imx_data)) 286 writel(val << 16, 287 host->ioaddr + SDHCI_TRANSFER_MODE); 288 else 289 writel(val << 16 | imx_data->scratchpad, 290 host->ioaddr + SDHCI_TRANSFER_MODE); 291 return; 292 case SDHCI_BLOCK_SIZE: 293 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 294 break; 295 } 296 esdhc_clrset_le(host, 0xffff, val, reg); 297 } 298 299 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 300 { 301 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 302 struct pltfm_imx_data *imx_data = pltfm_host->priv; 303 u32 new_val; 304 u32 mask; 305 306 switch (reg) { 307 case SDHCI_POWER_CONTROL: 308 /* 309 * FSL put some DMA bits here 310 * If your board has a regulator, code should be here 311 */ 312 return; 313 case SDHCI_HOST_CONTROL: 314 /* FSL messed up here, so we need to manually compose it. */ 315 new_val = val & SDHCI_CTRL_LED; 316 /* ensure the endianness */ 317 new_val |= ESDHC_HOST_CONTROL_LE; 318 /* bits 8&9 are reserved on mx25 */ 319 if (!is_imx25_esdhc(imx_data)) { 320 /* DMA mode bits are shifted */ 321 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 322 } 323 324 /* 325 * Do not touch buswidth bits here. This is done in 326 * esdhc_pltfm_bus_width. 327 */ 328 mask = 0xffff & ~ESDHC_CTRL_BUSWIDTH_MASK; 329 330 esdhc_clrset_le(host, mask, new_val, reg); 331 return; 332 } 333 esdhc_clrset_le(host, 0xff, val, reg); 334 335 /* 336 * The esdhc has a design violation to SDHC spec which tells 337 * that software reset should not affect card detection circuit. 338 * But esdhc clears its SYSCTL register bits [0..2] during the 339 * software reset. This will stop those clocks that card detection 340 * circuit relies on. To work around it, we turn the clocks on back 341 * to keep card detection circuit functional. 342 */ 343 if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { 344 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 345 /* 346 * The reset on usdhc fails to clear MIX_CTRL register. 347 * Do it manually here. 348 */ 349 if (is_imx6q_usdhc(imx_data)) 350 writel(0, host->ioaddr + ESDHC_MIX_CTRL); 351 } 352 } 353 354 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 355 { 356 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 357 358 return clk_get_rate(pltfm_host->clk) / 256 / 16; 359 } 360 361 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 362 { 363 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 364 struct pltfm_imx_data *imx_data = pltfm_host->priv; 365 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 366 367 switch (boarddata->wp_type) { 368 case ESDHC_WP_GPIO: 369 return mmc_gpio_get_ro(host->mmc); 370 case ESDHC_WP_CONTROLLER: 371 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 372 SDHCI_WRITE_PROTECT); 373 case ESDHC_WP_NONE: 374 break; 375 } 376 377 return -ENOSYS; 378 } 379 380 static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width) 381 { 382 u32 ctrl; 383 384 switch (width) { 385 case MMC_BUS_WIDTH_8: 386 ctrl = ESDHC_CTRL_8BITBUS; 387 break; 388 case MMC_BUS_WIDTH_4: 389 ctrl = ESDHC_CTRL_4BITBUS; 390 break; 391 default: 392 ctrl = 0; 393 break; 394 } 395 396 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 397 SDHCI_HOST_CONTROL); 398 399 return 0; 400 } 401 402 static const struct sdhci_ops sdhci_esdhc_ops = { 403 .read_l = esdhc_readl_le, 404 .read_w = esdhc_readw_le, 405 .write_l = esdhc_writel_le, 406 .write_w = esdhc_writew_le, 407 .write_b = esdhc_writeb_le, 408 .set_clock = esdhc_set_clock, 409 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 410 .get_min_clock = esdhc_pltfm_get_min_clock, 411 .get_ro = esdhc_pltfm_get_ro, 412 .platform_bus_width = esdhc_pltfm_bus_width, 413 }; 414 415 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 416 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 417 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 418 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 419 | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 420 .ops = &sdhci_esdhc_ops, 421 }; 422 423 #ifdef CONFIG_OF 424 static int 425 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 426 struct esdhc_platform_data *boarddata) 427 { 428 struct device_node *np = pdev->dev.of_node; 429 430 if (!np) 431 return -ENODEV; 432 433 if (of_get_property(np, "non-removable", NULL)) 434 boarddata->cd_type = ESDHC_CD_PERMANENT; 435 436 if (of_get_property(np, "fsl,cd-controller", NULL)) 437 boarddata->cd_type = ESDHC_CD_CONTROLLER; 438 439 if (of_get_property(np, "fsl,wp-controller", NULL)) 440 boarddata->wp_type = ESDHC_WP_CONTROLLER; 441 442 boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 443 if (gpio_is_valid(boarddata->cd_gpio)) 444 boarddata->cd_type = ESDHC_CD_GPIO; 445 446 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 447 if (gpio_is_valid(boarddata->wp_gpio)) 448 boarddata->wp_type = ESDHC_WP_GPIO; 449 450 of_property_read_u32(np, "bus-width", &boarddata->max_bus_width); 451 452 return 0; 453 } 454 #else 455 static inline int 456 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 457 struct esdhc_platform_data *boarddata) 458 { 459 return -ENODEV; 460 } 461 #endif 462 463 static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 464 { 465 const struct of_device_id *of_id = 466 of_match_device(imx_esdhc_dt_ids, &pdev->dev); 467 struct sdhci_pltfm_host *pltfm_host; 468 struct sdhci_host *host; 469 struct esdhc_platform_data *boarddata; 470 int err; 471 struct pltfm_imx_data *imx_data; 472 473 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata); 474 if (IS_ERR(host)) 475 return PTR_ERR(host); 476 477 pltfm_host = sdhci_priv(host); 478 479 imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); 480 if (!imx_data) { 481 err = -ENOMEM; 482 goto free_sdhci; 483 } 484 485 if (of_id) 486 pdev->id_entry = of_id->data; 487 imx_data->devtype = pdev->id_entry->driver_data; 488 pltfm_host->priv = imx_data; 489 490 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 491 if (IS_ERR(imx_data->clk_ipg)) { 492 err = PTR_ERR(imx_data->clk_ipg); 493 goto free_sdhci; 494 } 495 496 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 497 if (IS_ERR(imx_data->clk_ahb)) { 498 err = PTR_ERR(imx_data->clk_ahb); 499 goto free_sdhci; 500 } 501 502 imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 503 if (IS_ERR(imx_data->clk_per)) { 504 err = PTR_ERR(imx_data->clk_per); 505 goto free_sdhci; 506 } 507 508 pltfm_host->clk = imx_data->clk_per; 509 510 clk_prepare_enable(imx_data->clk_per); 511 clk_prepare_enable(imx_data->clk_ipg); 512 clk_prepare_enable(imx_data->clk_ahb); 513 514 imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 515 if (IS_ERR(imx_data->pinctrl)) { 516 err = PTR_ERR(imx_data->pinctrl); 517 goto disable_clk; 518 } 519 520 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 521 522 if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data)) 523 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ 524 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK 525 | SDHCI_QUIRK_BROKEN_ADMA; 526 527 if (is_imx53_esdhc(imx_data)) 528 imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT; 529 530 /* 531 * The imx6q ROM code will change the default watermark level setting 532 * to something insane. Change it back here. 533 */ 534 if (is_imx6q_usdhc(imx_data)) 535 writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); 536 537 boarddata = &imx_data->boarddata; 538 if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) { 539 if (!host->mmc->parent->platform_data) { 540 dev_err(mmc_dev(host->mmc), "no board data!\n"); 541 err = -EINVAL; 542 goto disable_clk; 543 } 544 imx_data->boarddata = *((struct esdhc_platform_data *) 545 host->mmc->parent->platform_data); 546 } 547 548 /* write_protect */ 549 if (boarddata->wp_type == ESDHC_WP_GPIO) { 550 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); 551 if (err) { 552 dev_err(mmc_dev(host->mmc), 553 "failed to request write-protect gpio!\n"); 554 goto disable_clk; 555 } 556 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 557 } 558 559 /* card_detect */ 560 switch (boarddata->cd_type) { 561 case ESDHC_CD_GPIO: 562 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio); 563 if (err) { 564 dev_err(mmc_dev(host->mmc), 565 "failed to request card-detect gpio!\n"); 566 goto disable_clk; 567 } 568 /* fall through */ 569 570 case ESDHC_CD_CONTROLLER: 571 /* we have a working card_detect back */ 572 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 573 break; 574 575 case ESDHC_CD_PERMANENT: 576 host->mmc->caps = MMC_CAP_NONREMOVABLE; 577 break; 578 579 case ESDHC_CD_NONE: 580 break; 581 } 582 583 switch (boarddata->max_bus_width) { 584 case 8: 585 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 586 break; 587 case 4: 588 host->mmc->caps |= MMC_CAP_4_BIT_DATA; 589 break; 590 case 1: 591 default: 592 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 593 break; 594 } 595 596 err = sdhci_add_host(host); 597 if (err) 598 goto disable_clk; 599 600 return 0; 601 602 disable_clk: 603 clk_disable_unprepare(imx_data->clk_per); 604 clk_disable_unprepare(imx_data->clk_ipg); 605 clk_disable_unprepare(imx_data->clk_ahb); 606 free_sdhci: 607 sdhci_pltfm_free(pdev); 608 return err; 609 } 610 611 static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 612 { 613 struct sdhci_host *host = platform_get_drvdata(pdev); 614 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 615 struct pltfm_imx_data *imx_data = pltfm_host->priv; 616 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 617 618 sdhci_remove_host(host, dead); 619 620 clk_disable_unprepare(imx_data->clk_per); 621 clk_disable_unprepare(imx_data->clk_ipg); 622 clk_disable_unprepare(imx_data->clk_ahb); 623 624 sdhci_pltfm_free(pdev); 625 626 return 0; 627 } 628 629 static struct platform_driver sdhci_esdhc_imx_driver = { 630 .driver = { 631 .name = "sdhci-esdhc-imx", 632 .owner = THIS_MODULE, 633 .of_match_table = imx_esdhc_dt_ids, 634 .pm = SDHCI_PLTFM_PMOPS, 635 }, 636 .id_table = imx_esdhc_devtype, 637 .probe = sdhci_esdhc_imx_probe, 638 .remove = sdhci_esdhc_imx_remove, 639 }; 640 641 module_platform_driver(sdhci_esdhc_imx_driver); 642 643 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 644 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); 645 MODULE_LICENSE("GPL v2"); 646