1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Freescale eSDHC i.MX controller driver for the platform bus. 4 * 5 * derived from the OF-version. 6 * 7 * Copyright (c) 2010 Pengutronix e.K. 8 * Author: Wolfram Sang <kernel@pengutronix.de> 9 */ 10 11 #include <linux/io.h> 12 #include <linux/delay.h> 13 #include <linux/err.h> 14 #include <linux/clk.h> 15 #include <linux/module.h> 16 #include <linux/slab.h> 17 #include <linux/mmc/host.h> 18 #include <linux/mmc/mmc.h> 19 #include <linux/mmc/sdio.h> 20 #include <linux/mmc/slot-gpio.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/platform_data/mmc-esdhc-imx.h> 25 #include <linux/pm_runtime.h> 26 #include "sdhci-pltfm.h" 27 #include "sdhci-esdhc.h" 28 29 #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f 30 #define ESDHC_CTRL_D3CD 0x08 31 #define ESDHC_BURST_LEN_EN_INCR (1 << 27) 32 /* VENDOR SPEC register */ 33 #define ESDHC_VENDOR_SPEC 0xc0 34 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 35 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 36 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 37 #define ESDHC_WTMK_LVL 0x44 38 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 39 #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF 40 #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0 41 #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000 42 #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16 43 #define ESDHC_WTMK_LVL_WML_VAL_DEF 64 44 #define ESDHC_WTMK_LVL_WML_VAL_MAX 128 45 #define ESDHC_MIX_CTRL 0x48 46 #define ESDHC_MIX_CTRL_DDREN (1 << 3) 47 #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 48 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 49 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 50 #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) 51 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 52 #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 53 /* Bits 3 and 6 are not SDHCI standard definitions */ 54 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 55 /* Tuning bits */ 56 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 57 58 /* dll control register */ 59 #define ESDHC_DLL_CTRL 0x60 60 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 61 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 62 63 /* tune control register */ 64 #define ESDHC_TUNE_CTRL_STATUS 0x68 65 #define ESDHC_TUNE_CTRL_STEP 1 66 #define ESDHC_TUNE_CTRL_MIN 0 67 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 68 69 /* strobe dll register */ 70 #define ESDHC_STROBE_DLL_CTRL 0x70 71 #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) 72 #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) 73 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 74 75 #define ESDHC_STROBE_DLL_STATUS 0x74 76 #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) 77 #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 78 79 #define ESDHC_TUNING_CTRL 0xcc 80 #define ESDHC_STD_TUNING_EN (1 << 24) 81 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 82 #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 83 #define ESDHC_TUNING_START_TAP_MASK 0xff 84 #define ESDHC_TUNING_STEP_MASK 0x00070000 85 #define ESDHC_TUNING_STEP_SHIFT 16 86 87 /* pinctrl state */ 88 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 89 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 90 91 /* 92 * Our interpretation of the SDHCI_HOST_CONTROL register 93 */ 94 #define ESDHC_CTRL_4BITBUS (0x1 << 1) 95 #define ESDHC_CTRL_8BITBUS (0x2 << 1) 96 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 97 98 /* 99 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC: 100 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 101 * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 102 * Define this macro DMA error INT for fsl eSDHC 103 */ 104 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 105 106 /* 107 * The CMDTYPE of the CMD register (offset 0xE) should be set to 108 * "11" when the STOP CMD12 is issued on imx53 to abort one 109 * open ended multi-blk IO. Otherwise the TC INT wouldn't 110 * be generated. 111 * In exact block transfer, the controller doesn't complete the 112 * operations automatically as required at the end of the 113 * transfer and remains on hold if the abort command is not sent. 114 * As a result, the TC flag is not asserted and SW received timeout 115 * exception. Bit1 of Vendor Spec register is used to fix it. 116 */ 117 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 118 /* 119 * The flag tells that the ESDHC controller is an USDHC block that is 120 * integrated on the i.MX6 series. 121 */ 122 #define ESDHC_FLAG_USDHC BIT(3) 123 /* The IP supports manual tuning process */ 124 #define ESDHC_FLAG_MAN_TUNING BIT(4) 125 /* The IP supports standard tuning process */ 126 #define ESDHC_FLAG_STD_TUNING BIT(5) 127 /* The IP has SDHCI_CAPABILITIES_1 register */ 128 #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 129 /* 130 * The IP has erratum ERR004536 131 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 132 * when reading data from the card 133 * This flag is also set for i.MX25 and i.MX35 in order to get 134 * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits). 135 */ 136 #define ESDHC_FLAG_ERR004536 BIT(7) 137 /* The IP supports HS200 mode */ 138 #define ESDHC_FLAG_HS200 BIT(8) 139 /* The IP supports HS400 mode */ 140 #define ESDHC_FLAG_HS400 BIT(9) 141 142 /* A clock frequency higher than this rate requires strobe dll control */ 143 #define ESDHC_STROBE_DLL_CLK_FREQ 100000000 144 145 struct esdhc_soc_data { 146 u32 flags; 147 }; 148 149 static struct esdhc_soc_data esdhc_imx25_data = { 150 .flags = ESDHC_FLAG_ERR004536, 151 }; 152 153 static struct esdhc_soc_data esdhc_imx35_data = { 154 .flags = ESDHC_FLAG_ERR004536, 155 }; 156 157 static struct esdhc_soc_data esdhc_imx51_data = { 158 .flags = 0, 159 }; 160 161 static struct esdhc_soc_data esdhc_imx53_data = { 162 .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 163 }; 164 165 static struct esdhc_soc_data usdhc_imx6q_data = { 166 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, 167 }; 168 169 static struct esdhc_soc_data usdhc_imx6sl_data = { 170 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 171 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 172 | ESDHC_FLAG_HS200, 173 }; 174 175 static struct esdhc_soc_data usdhc_imx6sx_data = { 176 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 177 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, 178 }; 179 180 static struct esdhc_soc_data usdhc_imx7d_data = { 181 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 182 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 183 | ESDHC_FLAG_HS400, 184 }; 185 186 struct pltfm_imx_data { 187 u32 scratchpad; 188 struct pinctrl *pinctrl; 189 struct pinctrl_state *pins_default; 190 struct pinctrl_state *pins_100mhz; 191 struct pinctrl_state *pins_200mhz; 192 const struct esdhc_soc_data *socdata; 193 struct esdhc_platform_data boarddata; 194 struct clk *clk_ipg; 195 struct clk *clk_ahb; 196 struct clk *clk_per; 197 unsigned int actual_clock; 198 enum { 199 NO_CMD_PENDING, /* no multiblock command pending */ 200 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 201 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 202 } multiblock_status; 203 u32 is_ddr; 204 }; 205 206 static const struct platform_device_id imx_esdhc_devtype[] = { 207 { 208 .name = "sdhci-esdhc-imx25", 209 .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 210 }, { 211 .name = "sdhci-esdhc-imx35", 212 .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 213 }, { 214 .name = "sdhci-esdhc-imx51", 215 .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 216 }, { 217 /* sentinel */ 218 } 219 }; 220 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 221 222 static const struct of_device_id imx_esdhc_dt_ids[] = { 223 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 224 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 225 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 226 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 227 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 228 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 229 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 230 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, 231 { /* sentinel */ } 232 }; 233 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 234 235 static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 236 { 237 return data->socdata == &esdhc_imx25_data; 238 } 239 240 static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 241 { 242 return data->socdata == &esdhc_imx53_data; 243 } 244 245 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 246 { 247 return data->socdata == &usdhc_imx6q_data; 248 } 249 250 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 251 { 252 return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 253 } 254 255 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 256 { 257 void __iomem *base = host->ioaddr + (reg & ~0x3); 258 u32 shift = (reg & 0x3) * 8; 259 260 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 261 } 262 263 static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 264 { 265 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 266 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 267 u32 val = readl(host->ioaddr + reg); 268 269 if (unlikely(reg == SDHCI_PRESENT_STATE)) { 270 u32 fsl_prss = val; 271 /* save the least 20 bits */ 272 val = fsl_prss & 0x000FFFFF; 273 /* move dat[0-3] bits */ 274 val |= (fsl_prss & 0x0F000000) >> 4; 275 /* move cmd line bit */ 276 val |= (fsl_prss & 0x00800000) << 1; 277 } 278 279 if (unlikely(reg == SDHCI_CAPABILITIES)) { 280 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 281 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 282 val &= 0xffff0000; 283 284 /* In FSL esdhc IC module, only bit20 is used to indicate the 285 * ADMA2 capability of esdhc, but this bit is messed up on 286 * some SOCs (e.g. on MX25, MX35 this bit is set, but they 287 * don't actually support ADMA2). So set the BROKEN_ADMA 288 * quirk on MX25/35 platforms. 289 */ 290 291 if (val & SDHCI_CAN_DO_ADMA1) { 292 val &= ~SDHCI_CAN_DO_ADMA1; 293 val |= SDHCI_CAN_DO_ADMA2; 294 } 295 } 296 297 if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 298 if (esdhc_is_usdhc(imx_data)) { 299 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 300 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 301 else 302 /* imx6q/dl does not have cap_1 register, fake one */ 303 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 304 | SDHCI_SUPPORT_SDR50 305 | SDHCI_USE_SDR50_TUNING 306 | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT); 307 308 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 309 val |= SDHCI_SUPPORT_HS400; 310 311 /* 312 * Do not advertise faster UHS modes if there are no 313 * pinctrl states for 100MHz/200MHz. 314 */ 315 if (IS_ERR_OR_NULL(imx_data->pins_100mhz) || 316 IS_ERR_OR_NULL(imx_data->pins_200mhz)) 317 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50 318 | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400); 319 } 320 } 321 322 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 323 val = 0; 324 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 325 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 326 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 327 } 328 329 if (unlikely(reg == SDHCI_INT_STATUS)) { 330 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 331 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 332 val |= SDHCI_INT_ADMA_ERROR; 333 } 334 335 /* 336 * mask off the interrupt we get in response to the manually 337 * sent CMD12 338 */ 339 if ((imx_data->multiblock_status == WAIT_FOR_INT) && 340 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 341 val &= ~SDHCI_INT_RESPONSE; 342 writel(SDHCI_INT_RESPONSE, host->ioaddr + 343 SDHCI_INT_STATUS); 344 imx_data->multiblock_status = NO_CMD_PENDING; 345 } 346 } 347 348 return val; 349 } 350 351 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 352 { 353 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 354 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 355 u32 data; 356 357 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || 358 reg == SDHCI_INT_STATUS)) { 359 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 360 /* 361 * Clear and then set D3CD bit to avoid missing the 362 * card interrupt. This is an eSDHC controller problem 363 * so we need to apply the following workaround: clear 364 * and set D3CD bit will make eSDHC re-sample the card 365 * interrupt. In case a card interrupt was lost, 366 * re-sample it by the following steps. 367 */ 368 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 369 data &= ~ESDHC_CTRL_D3CD; 370 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 371 data |= ESDHC_CTRL_D3CD; 372 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 373 } 374 375 if (val & SDHCI_INT_ADMA_ERROR) { 376 val &= ~SDHCI_INT_ADMA_ERROR; 377 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 378 } 379 } 380 381 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 382 && (reg == SDHCI_INT_STATUS) 383 && (val & SDHCI_INT_DATA_END))) { 384 u32 v; 385 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 386 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 387 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 388 389 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 390 { 391 /* send a manual CMD12 with RESPTYP=none */ 392 data = MMC_STOP_TRANSMISSION << 24 | 393 SDHCI_CMD_ABORTCMD << 16; 394 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 395 imx_data->multiblock_status = WAIT_FOR_INT; 396 } 397 } 398 399 writel(val, host->ioaddr + reg); 400 } 401 402 static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 403 { 404 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 405 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 406 u16 ret = 0; 407 u32 val; 408 409 if (unlikely(reg == SDHCI_HOST_VERSION)) { 410 reg ^= 2; 411 if (esdhc_is_usdhc(imx_data)) { 412 /* 413 * The usdhc register returns a wrong host version. 414 * Correct it here. 415 */ 416 return SDHCI_SPEC_300; 417 } 418 } 419 420 if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 421 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 422 if (val & ESDHC_VENDOR_SPEC_VSELECT) 423 ret |= SDHCI_CTRL_VDD_180; 424 425 if (esdhc_is_usdhc(imx_data)) { 426 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 427 val = readl(host->ioaddr + ESDHC_MIX_CTRL); 428 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 429 /* the std tuning bits is in ACMD12_ERR for imx6sl */ 430 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 431 } 432 433 if (val & ESDHC_MIX_CTRL_EXE_TUNE) 434 ret |= SDHCI_CTRL_EXEC_TUNING; 435 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 436 ret |= SDHCI_CTRL_TUNED_CLK; 437 438 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 439 440 return ret; 441 } 442 443 if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 444 if (esdhc_is_usdhc(imx_data)) { 445 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 446 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 447 /* Swap AC23 bit */ 448 if (m & ESDHC_MIX_CTRL_AC23EN) { 449 ret &= ~ESDHC_MIX_CTRL_AC23EN; 450 ret |= SDHCI_TRNS_AUTO_CMD23; 451 } 452 } else { 453 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 454 } 455 456 return ret; 457 } 458 459 return readw(host->ioaddr + reg); 460 } 461 462 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 463 { 464 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 465 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 466 u32 new_val = 0; 467 468 switch (reg) { 469 case SDHCI_CLOCK_CONTROL: 470 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 471 if (val & SDHCI_CLOCK_CARD_EN) 472 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 473 else 474 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 475 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 476 return; 477 case SDHCI_HOST_CONTROL2: 478 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 479 if (val & SDHCI_CTRL_VDD_180) 480 new_val |= ESDHC_VENDOR_SPEC_VSELECT; 481 else 482 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 483 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 484 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 485 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 486 if (val & SDHCI_CTRL_TUNED_CLK) { 487 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 488 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 489 } else { 490 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 491 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 492 } 493 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 494 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 495 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 496 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 497 if (val & SDHCI_CTRL_TUNED_CLK) { 498 v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 499 } else { 500 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 501 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 502 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 503 } 504 505 if (val & SDHCI_CTRL_EXEC_TUNING) { 506 v |= ESDHC_MIX_CTRL_EXE_TUNE; 507 m |= ESDHC_MIX_CTRL_FBCLK_SEL; 508 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 509 } else { 510 v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 511 } 512 513 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 514 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 515 } 516 return; 517 case SDHCI_TRANSFER_MODE: 518 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 519 && (host->cmd->opcode == SD_IO_RW_EXTENDED) 520 && (host->cmd->data->blocks > 1) 521 && (host->cmd->data->flags & MMC_DATA_READ)) { 522 u32 v; 523 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 524 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 525 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 526 } 527 528 if (esdhc_is_usdhc(imx_data)) { 529 u32 wml; 530 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 531 /* Swap AC23 bit */ 532 if (val & SDHCI_TRNS_AUTO_CMD23) { 533 val &= ~SDHCI_TRNS_AUTO_CMD23; 534 val |= ESDHC_MIX_CTRL_AC23EN; 535 } 536 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 537 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 538 539 /* Set watermark levels for PIO access to maximum value 540 * (128 words) to accommodate full 512 bytes buffer. 541 * For DMA access restore the levels to default value. 542 */ 543 m = readl(host->ioaddr + ESDHC_WTMK_LVL); 544 if (val & SDHCI_TRNS_DMA) 545 wml = ESDHC_WTMK_LVL_WML_VAL_DEF; 546 else 547 wml = ESDHC_WTMK_LVL_WML_VAL_MAX; 548 m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK | 549 ESDHC_WTMK_LVL_WR_WML_MASK); 550 m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) | 551 (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT); 552 writel(m, host->ioaddr + ESDHC_WTMK_LVL); 553 } else { 554 /* 555 * Postpone this write, we must do it together with a 556 * command write that is down below. 557 */ 558 imx_data->scratchpad = val; 559 } 560 return; 561 case SDHCI_COMMAND: 562 if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 563 val |= SDHCI_CMD_ABORTCMD; 564 565 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 566 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 567 imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 568 569 if (esdhc_is_usdhc(imx_data)) 570 writel(val << 16, 571 host->ioaddr + SDHCI_TRANSFER_MODE); 572 else 573 writel(val << 16 | imx_data->scratchpad, 574 host->ioaddr + SDHCI_TRANSFER_MODE); 575 return; 576 case SDHCI_BLOCK_SIZE: 577 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 578 break; 579 } 580 esdhc_clrset_le(host, 0xffff, val, reg); 581 } 582 583 static u8 esdhc_readb_le(struct sdhci_host *host, int reg) 584 { 585 u8 ret; 586 u32 val; 587 588 switch (reg) { 589 case SDHCI_HOST_CONTROL: 590 val = readl(host->ioaddr + reg); 591 592 ret = val & SDHCI_CTRL_LED; 593 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; 594 ret |= (val & ESDHC_CTRL_4BITBUS); 595 ret |= (val & ESDHC_CTRL_8BITBUS) << 3; 596 return ret; 597 } 598 599 return readb(host->ioaddr + reg); 600 } 601 602 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 603 { 604 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 605 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 606 u32 new_val = 0; 607 u32 mask; 608 609 switch (reg) { 610 case SDHCI_POWER_CONTROL: 611 /* 612 * FSL put some DMA bits here 613 * If your board has a regulator, code should be here 614 */ 615 return; 616 case SDHCI_HOST_CONTROL: 617 /* FSL messed up here, so we need to manually compose it. */ 618 new_val = val & SDHCI_CTRL_LED; 619 /* ensure the endianness */ 620 new_val |= ESDHC_HOST_CONTROL_LE; 621 /* bits 8&9 are reserved on mx25 */ 622 if (!is_imx25_esdhc(imx_data)) { 623 /* DMA mode bits are shifted */ 624 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 625 } 626 627 /* 628 * Do not touch buswidth bits here. This is done in 629 * esdhc_pltfm_bus_width. 630 * Do not touch the D3CD bit either which is used for the 631 * SDIO interrupt erratum workaround. 632 */ 633 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 634 635 esdhc_clrset_le(host, mask, new_val, reg); 636 return; 637 case SDHCI_SOFTWARE_RESET: 638 if (val & SDHCI_RESET_DATA) 639 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); 640 break; 641 } 642 esdhc_clrset_le(host, 0xff, val, reg); 643 644 if (reg == SDHCI_SOFTWARE_RESET) { 645 if (val & SDHCI_RESET_ALL) { 646 /* 647 * The esdhc has a design violation to SDHC spec which 648 * tells that software reset should not affect card 649 * detection circuit. But esdhc clears its SYSCTL 650 * register bits [0..2] during the software reset. This 651 * will stop those clocks that card detection circuit 652 * relies on. To work around it, we turn the clocks on 653 * back to keep card detection circuit functional. 654 */ 655 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 656 /* 657 * The reset on usdhc fails to clear MIX_CTRL register. 658 * Do it manually here. 659 */ 660 if (esdhc_is_usdhc(imx_data)) { 661 /* 662 * the tuning bits should be kept during reset 663 */ 664 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 665 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 666 host->ioaddr + ESDHC_MIX_CTRL); 667 imx_data->is_ddr = 0; 668 } 669 } else if (val & SDHCI_RESET_DATA) { 670 /* 671 * The eSDHC DAT line software reset clears at least the 672 * data transfer width on i.MX25, so make sure that the 673 * Host Control register is unaffected. 674 */ 675 esdhc_clrset_le(host, 0xff, new_val, 676 SDHCI_HOST_CONTROL); 677 } 678 } 679 } 680 681 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 682 { 683 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 684 685 return pltfm_host->clock; 686 } 687 688 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 689 { 690 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 691 692 return pltfm_host->clock / 256 / 16; 693 } 694 695 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 696 unsigned int clock) 697 { 698 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 699 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 700 unsigned int host_clock = pltfm_host->clock; 701 int ddr_pre_div = imx_data->is_ddr ? 2 : 1; 702 int pre_div = 1; 703 int div = 1; 704 u32 temp, val; 705 706 if (esdhc_is_usdhc(imx_data)) { 707 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 708 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 709 host->ioaddr + ESDHC_VENDOR_SPEC); 710 } 711 712 if (clock == 0) { 713 host->mmc->actual_clock = 0; 714 return; 715 } 716 717 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ 718 if (is_imx53_esdhc(imx_data)) { 719 /* 720 * According to the i.MX53 reference manual, if DLLCTRL[10] can 721 * be set, then the controller is eSDHCv3, else it is eSDHCv2. 722 */ 723 val = readl(host->ioaddr + ESDHC_DLL_CTRL); 724 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); 725 temp = readl(host->ioaddr + ESDHC_DLL_CTRL); 726 writel(val, host->ioaddr + ESDHC_DLL_CTRL); 727 if (temp & BIT(10)) 728 pre_div = 2; 729 } 730 731 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 732 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 733 | ESDHC_CLOCK_MASK); 734 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 735 736 while (host_clock / (16 * pre_div * ddr_pre_div) > clock && 737 pre_div < 256) 738 pre_div *= 2; 739 740 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16) 741 div++; 742 743 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); 744 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 745 clock, host->mmc->actual_clock); 746 747 pre_div >>= 1; 748 div--; 749 750 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 751 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 752 | (div << ESDHC_DIVIDER_SHIFT) 753 | (pre_div << ESDHC_PREDIV_SHIFT)); 754 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 755 756 if (esdhc_is_usdhc(imx_data)) { 757 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 758 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 759 host->ioaddr + ESDHC_VENDOR_SPEC); 760 } 761 762 mdelay(1); 763 } 764 765 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 766 { 767 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 768 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 769 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 770 771 switch (boarddata->wp_type) { 772 case ESDHC_WP_GPIO: 773 return mmc_gpio_get_ro(host->mmc); 774 case ESDHC_WP_CONTROLLER: 775 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 776 SDHCI_WRITE_PROTECT); 777 case ESDHC_WP_NONE: 778 break; 779 } 780 781 return -ENOSYS; 782 } 783 784 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 785 { 786 u32 ctrl; 787 788 switch (width) { 789 case MMC_BUS_WIDTH_8: 790 ctrl = ESDHC_CTRL_8BITBUS; 791 break; 792 case MMC_BUS_WIDTH_4: 793 ctrl = ESDHC_CTRL_4BITBUS; 794 break; 795 default: 796 ctrl = 0; 797 break; 798 } 799 800 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 801 SDHCI_HOST_CONTROL); 802 } 803 804 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 805 { 806 u32 reg; 807 808 /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 809 mdelay(1); 810 811 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 812 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 813 ESDHC_MIX_CTRL_FBCLK_SEL; 814 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 815 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 816 dev_dbg(mmc_dev(host->mmc), 817 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 818 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 819 } 820 821 static void esdhc_post_tuning(struct sdhci_host *host) 822 { 823 u32 reg; 824 825 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 826 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 827 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 828 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 829 } 830 831 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 832 { 833 int min, max, avg, ret; 834 835 /* find the mininum delay first which can pass tuning */ 836 min = ESDHC_TUNE_CTRL_MIN; 837 while (min < ESDHC_TUNE_CTRL_MAX) { 838 esdhc_prepare_tuning(host, min); 839 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 840 break; 841 min += ESDHC_TUNE_CTRL_STEP; 842 } 843 844 /* find the maxinum delay which can not pass tuning */ 845 max = min + ESDHC_TUNE_CTRL_STEP; 846 while (max < ESDHC_TUNE_CTRL_MAX) { 847 esdhc_prepare_tuning(host, max); 848 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 849 max -= ESDHC_TUNE_CTRL_STEP; 850 break; 851 } 852 max += ESDHC_TUNE_CTRL_STEP; 853 } 854 855 /* use average delay to get the best timing */ 856 avg = (min + max) / 2; 857 esdhc_prepare_tuning(host, avg); 858 ret = mmc_send_tuning(host->mmc, opcode, NULL); 859 esdhc_post_tuning(host); 860 861 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 862 ret ? "failed" : "passed", avg, ret); 863 864 return ret; 865 } 866 867 static int esdhc_change_pinstate(struct sdhci_host *host, 868 unsigned int uhs) 869 { 870 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 871 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 872 struct pinctrl_state *pinctrl; 873 874 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 875 876 if (IS_ERR(imx_data->pinctrl) || 877 IS_ERR(imx_data->pins_default) || 878 IS_ERR(imx_data->pins_100mhz) || 879 IS_ERR(imx_data->pins_200mhz)) 880 return -EINVAL; 881 882 switch (uhs) { 883 case MMC_TIMING_UHS_SDR50: 884 case MMC_TIMING_UHS_DDR50: 885 pinctrl = imx_data->pins_100mhz; 886 break; 887 case MMC_TIMING_UHS_SDR104: 888 case MMC_TIMING_MMC_HS200: 889 case MMC_TIMING_MMC_HS400: 890 pinctrl = imx_data->pins_200mhz; 891 break; 892 default: 893 /* back to default state for other legacy timing */ 894 pinctrl = imx_data->pins_default; 895 } 896 897 return pinctrl_select_state(imx_data->pinctrl, pinctrl); 898 } 899 900 /* 901 * For HS400 eMMC, there is a data_strobe line. This signal is generated 902 * by the device and used for data output and CRC status response output 903 * in HS400 mode. The frequency of this signal follows the frequency of 904 * CLK generated by host. The host receives the data which is aligned to the 905 * edge of data_strobe line. Due to the time delay between CLK line and 906 * data_strobe line, if the delay time is larger than one clock cycle, 907 * then CLK and data_strobe line will be misaligned, read error shows up. 908 * So when the CLK is higher than 100MHz, each clock cycle is short enough, 909 * host should configure the delay target. 910 */ 911 static void esdhc_set_strobe_dll(struct sdhci_host *host) 912 { 913 u32 v; 914 915 if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) { 916 /* disable clock before enabling strobe dll */ 917 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & 918 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 919 host->ioaddr + ESDHC_VENDOR_SPEC); 920 921 /* force a reset on strobe dll */ 922 writel(ESDHC_STROBE_DLL_CTRL_RESET, 923 host->ioaddr + ESDHC_STROBE_DLL_CTRL); 924 /* 925 * enable strobe dll ctrl and adjust the delay target 926 * for the uSDHC loopback read clock 927 */ 928 v = ESDHC_STROBE_DLL_CTRL_ENABLE | 929 (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 930 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 931 /* wait 1us to make sure strobe dll status register stable */ 932 udelay(1); 933 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS); 934 if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK)) 935 dev_warn(mmc_dev(host->mmc), 936 "warning! HS400 strobe DLL status REF not lock!\n"); 937 if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK)) 938 dev_warn(mmc_dev(host->mmc), 939 "warning! HS400 strobe DLL status SLV not lock!\n"); 940 } 941 } 942 943 static void esdhc_reset_tuning(struct sdhci_host *host) 944 { 945 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 946 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 947 u32 ctrl; 948 949 /* Reset the tuning circuit */ 950 if (esdhc_is_usdhc(imx_data)) { 951 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 952 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); 953 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 954 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 955 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 956 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 957 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 958 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 959 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 960 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 961 } 962 } 963 } 964 965 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 966 { 967 u32 m; 968 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 969 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 970 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 971 972 /* disable ddr mode and disable HS400 mode */ 973 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 974 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); 975 imx_data->is_ddr = 0; 976 977 switch (timing) { 978 case MMC_TIMING_UHS_SDR12: 979 case MMC_TIMING_UHS_SDR25: 980 case MMC_TIMING_UHS_SDR50: 981 case MMC_TIMING_UHS_SDR104: 982 case MMC_TIMING_MMC_HS200: 983 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 984 break; 985 case MMC_TIMING_UHS_DDR50: 986 case MMC_TIMING_MMC_DDR52: 987 m |= ESDHC_MIX_CTRL_DDREN; 988 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 989 imx_data->is_ddr = 1; 990 if (boarddata->delay_line) { 991 u32 v; 992 v = boarddata->delay_line << 993 ESDHC_DLL_OVERRIDE_VAL_SHIFT | 994 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 995 if (is_imx53_esdhc(imx_data)) 996 v <<= 1; 997 writel(v, host->ioaddr + ESDHC_DLL_CTRL); 998 } 999 break; 1000 case MMC_TIMING_MMC_HS400: 1001 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 1002 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1003 imx_data->is_ddr = 1; 1004 /* update clock after enable DDR for strobe DLL lock */ 1005 host->ops->set_clock(host, host->clock); 1006 esdhc_set_strobe_dll(host); 1007 break; 1008 case MMC_TIMING_LEGACY: 1009 default: 1010 esdhc_reset_tuning(host); 1011 break; 1012 } 1013 1014 esdhc_change_pinstate(host, timing); 1015 } 1016 1017 static void esdhc_reset(struct sdhci_host *host, u8 mask) 1018 { 1019 sdhci_reset(host, mask); 1020 1021 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1022 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1023 } 1024 1025 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 1026 { 1027 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1028 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1029 1030 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */ 1031 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27; 1032 } 1033 1034 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 1035 { 1036 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1037 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1038 1039 /* use maximum timeout counter */ 1040 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, 1041 esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 1042 SDHCI_TIMEOUT_CONTROL); 1043 } 1044 1045 static struct sdhci_ops sdhci_esdhc_ops = { 1046 .read_l = esdhc_readl_le, 1047 .read_w = esdhc_readw_le, 1048 .read_b = esdhc_readb_le, 1049 .write_l = esdhc_writel_le, 1050 .write_w = esdhc_writew_le, 1051 .write_b = esdhc_writeb_le, 1052 .set_clock = esdhc_pltfm_set_clock, 1053 .get_max_clock = esdhc_pltfm_get_max_clock, 1054 .get_min_clock = esdhc_pltfm_get_min_clock, 1055 .get_max_timeout_count = esdhc_get_max_timeout_count, 1056 .get_ro = esdhc_pltfm_get_ro, 1057 .set_timeout = esdhc_set_timeout, 1058 .set_bus_width = esdhc_pltfm_set_bus_width, 1059 .set_uhs_signaling = esdhc_set_uhs_signaling, 1060 .reset = esdhc_reset, 1061 }; 1062 1063 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 1064 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 1065 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 1066 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 1067 | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 1068 .ops = &sdhci_esdhc_ops, 1069 }; 1070 1071 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) 1072 { 1073 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1074 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1075 int tmp; 1076 1077 if (esdhc_is_usdhc(imx_data)) { 1078 /* 1079 * The imx6q ROM code will change the default watermark 1080 * level setting to something insane. Change it back here. 1081 */ 1082 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); 1083 1084 /* 1085 * ROM code will change the bit burst_length_enable setting 1086 * to zero if this usdhc is chosen to boot system. Change 1087 * it back here, otherwise it will impact the performance a 1088 * lot. This bit is used to enable/disable the burst length 1089 * for the external AHB2AXI bridge. It's useful especially 1090 * for INCR transfer because without burst length indicator, 1091 * the AHB2AXI bridge does not know the burst length in 1092 * advance. And without burst length indicator, AHB INCR 1093 * transfer can only be converted to singles on the AXI side. 1094 */ 1095 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) 1096 | ESDHC_BURST_LEN_EN_INCR, 1097 host->ioaddr + SDHCI_HOST_CONTROL); 1098 /* 1099 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 1100 * TO1.1, it's harmless for MX6SL 1101 */ 1102 writel(readl(host->ioaddr + 0x6c) | BIT(7), 1103 host->ioaddr + 0x6c); 1104 1105 /* disable DLL_CTRL delay line settings */ 1106 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); 1107 1108 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1109 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1110 tmp |= ESDHC_STD_TUNING_EN | 1111 ESDHC_TUNING_START_TAP_DEFAULT; 1112 if (imx_data->boarddata.tuning_start_tap) { 1113 tmp &= ~ESDHC_TUNING_START_TAP_MASK; 1114 tmp |= imx_data->boarddata.tuning_start_tap; 1115 } 1116 1117 if (imx_data->boarddata.tuning_step) { 1118 tmp &= ~ESDHC_TUNING_STEP_MASK; 1119 tmp |= imx_data->boarddata.tuning_step 1120 << ESDHC_TUNING_STEP_SHIFT; 1121 } 1122 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1123 } 1124 } 1125 } 1126 1127 #ifdef CONFIG_OF 1128 static int 1129 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 1130 struct sdhci_host *host, 1131 struct pltfm_imx_data *imx_data) 1132 { 1133 struct device_node *np = pdev->dev.of_node; 1134 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1135 int ret; 1136 1137 if (of_get_property(np, "fsl,wp-controller", NULL)) 1138 boarddata->wp_type = ESDHC_WP_CONTROLLER; 1139 1140 /* 1141 * If we have this property, then activate WP check. 1142 * Retrieveing and requesting the actual WP GPIO will happen 1143 * in the call to mmc_of_parse(). 1144 */ 1145 if (of_property_read_bool(np, "wp-gpios")) 1146 boarddata->wp_type = ESDHC_WP_GPIO; 1147 1148 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 1149 of_property_read_u32(np, "fsl,tuning-start-tap", 1150 &boarddata->tuning_start_tap); 1151 1152 if (of_find_property(np, "no-1-8-v", NULL)) 1153 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1154 1155 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 1156 boarddata->delay_line = 0; 1157 1158 mmc_of_parse_voltage(np, &host->ocr_mask); 1159 1160 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pins_default)) { 1161 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 1162 ESDHC_PINCTRL_STATE_100MHZ); 1163 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 1164 ESDHC_PINCTRL_STATE_200MHZ); 1165 } 1166 1167 /* call to generic mmc_of_parse to support additional capabilities */ 1168 ret = mmc_of_parse(host->mmc); 1169 if (ret) 1170 return ret; 1171 1172 if (mmc_gpio_get_cd(host->mmc) >= 0) 1173 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1174 1175 return 0; 1176 } 1177 #else 1178 static inline int 1179 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 1180 struct sdhci_host *host, 1181 struct pltfm_imx_data *imx_data) 1182 { 1183 return -ENODEV; 1184 } 1185 #endif 1186 1187 static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev, 1188 struct sdhci_host *host, 1189 struct pltfm_imx_data *imx_data) 1190 { 1191 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1192 int err; 1193 1194 if (!host->mmc->parent->platform_data) { 1195 dev_err(mmc_dev(host->mmc), "no board data!\n"); 1196 return -EINVAL; 1197 } 1198 1199 imx_data->boarddata = *((struct esdhc_platform_data *) 1200 host->mmc->parent->platform_data); 1201 /* write_protect */ 1202 if (boarddata->wp_type == ESDHC_WP_GPIO) { 1203 err = mmc_gpiod_request_ro(host->mmc, "wp", 0, false, 0, NULL); 1204 if (err) { 1205 dev_err(mmc_dev(host->mmc), 1206 "failed to request write-protect gpio!\n"); 1207 return err; 1208 } 1209 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 1210 } 1211 1212 /* card_detect */ 1213 switch (boarddata->cd_type) { 1214 case ESDHC_CD_GPIO: 1215 err = mmc_gpiod_request_cd(host->mmc, "cd", 0, false, 0, NULL); 1216 if (err) { 1217 dev_err(mmc_dev(host->mmc), 1218 "failed to request card-detect gpio!\n"); 1219 return err; 1220 } 1221 /* fall through */ 1222 1223 case ESDHC_CD_CONTROLLER: 1224 /* we have a working card_detect back */ 1225 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1226 break; 1227 1228 case ESDHC_CD_PERMANENT: 1229 host->mmc->caps |= MMC_CAP_NONREMOVABLE; 1230 break; 1231 1232 case ESDHC_CD_NONE: 1233 break; 1234 } 1235 1236 switch (boarddata->max_bus_width) { 1237 case 8: 1238 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 1239 break; 1240 case 4: 1241 host->mmc->caps |= MMC_CAP_4_BIT_DATA; 1242 break; 1243 case 1: 1244 default: 1245 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 1246 break; 1247 } 1248 1249 return 0; 1250 } 1251 1252 static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 1253 { 1254 const struct of_device_id *of_id = 1255 of_match_device(imx_esdhc_dt_ids, &pdev->dev); 1256 struct sdhci_pltfm_host *pltfm_host; 1257 struct sdhci_host *host; 1258 int err; 1259 struct pltfm_imx_data *imx_data; 1260 1261 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 1262 sizeof(*imx_data)); 1263 if (IS_ERR(host)) 1264 return PTR_ERR(host); 1265 1266 pltfm_host = sdhci_priv(host); 1267 1268 imx_data = sdhci_pltfm_priv(pltfm_host); 1269 1270 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 1271 pdev->id_entry->driver_data; 1272 1273 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1274 if (IS_ERR(imx_data->clk_ipg)) { 1275 err = PTR_ERR(imx_data->clk_ipg); 1276 goto free_sdhci; 1277 } 1278 1279 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1280 if (IS_ERR(imx_data->clk_ahb)) { 1281 err = PTR_ERR(imx_data->clk_ahb); 1282 goto free_sdhci; 1283 } 1284 1285 imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 1286 if (IS_ERR(imx_data->clk_per)) { 1287 err = PTR_ERR(imx_data->clk_per); 1288 goto free_sdhci; 1289 } 1290 1291 pltfm_host->clk = imx_data->clk_per; 1292 pltfm_host->clock = clk_get_rate(pltfm_host->clk); 1293 err = clk_prepare_enable(imx_data->clk_per); 1294 if (err) 1295 goto free_sdhci; 1296 err = clk_prepare_enable(imx_data->clk_ipg); 1297 if (err) 1298 goto disable_per_clk; 1299 err = clk_prepare_enable(imx_data->clk_ahb); 1300 if (err) 1301 goto disable_ipg_clk; 1302 1303 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1304 if (IS_ERR(imx_data->pinctrl)) { 1305 err = PTR_ERR(imx_data->pinctrl); 1306 goto disable_ahb_clk; 1307 } 1308 1309 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, 1310 PINCTRL_STATE_DEFAULT); 1311 if (IS_ERR(imx_data->pins_default)) 1312 dev_warn(mmc_dev(host->mmc), "could not get default state\n"); 1313 1314 if (esdhc_is_usdhc(imx_data)) { 1315 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 1316 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; 1317 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 1318 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 1319 1320 /* clear tuning bits in case ROM has set it already */ 1321 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); 1322 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1323 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1324 } 1325 1326 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 1327 sdhci_esdhc_ops.platform_execute_tuning = 1328 esdhc_executing_tuning; 1329 1330 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 1331 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1332 1333 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 1334 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; 1335 1336 if (of_id) 1337 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 1338 else 1339 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data); 1340 if (err) 1341 goto disable_ahb_clk; 1342 1343 sdhci_esdhc_imx_hwinit(host); 1344 1345 err = sdhci_add_host(host); 1346 if (err) 1347 goto disable_ahb_clk; 1348 1349 pm_runtime_set_active(&pdev->dev); 1350 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1351 pm_runtime_use_autosuspend(&pdev->dev); 1352 pm_suspend_ignore_children(&pdev->dev, 1); 1353 pm_runtime_enable(&pdev->dev); 1354 1355 return 0; 1356 1357 disable_ahb_clk: 1358 clk_disable_unprepare(imx_data->clk_ahb); 1359 disable_ipg_clk: 1360 clk_disable_unprepare(imx_data->clk_ipg); 1361 disable_per_clk: 1362 clk_disable_unprepare(imx_data->clk_per); 1363 free_sdhci: 1364 sdhci_pltfm_free(pdev); 1365 return err; 1366 } 1367 1368 static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 1369 { 1370 struct sdhci_host *host = platform_get_drvdata(pdev); 1371 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1372 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1373 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 1374 1375 pm_runtime_get_sync(&pdev->dev); 1376 pm_runtime_disable(&pdev->dev); 1377 pm_runtime_put_noidle(&pdev->dev); 1378 1379 sdhci_remove_host(host, dead); 1380 1381 clk_disable_unprepare(imx_data->clk_per); 1382 clk_disable_unprepare(imx_data->clk_ipg); 1383 clk_disable_unprepare(imx_data->clk_ahb); 1384 1385 sdhci_pltfm_free(pdev); 1386 1387 return 0; 1388 } 1389 1390 #ifdef CONFIG_PM_SLEEP 1391 static int sdhci_esdhc_suspend(struct device *dev) 1392 { 1393 struct sdhci_host *host = dev_get_drvdata(dev); 1394 1395 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1396 mmc_retune_needed(host->mmc); 1397 1398 return sdhci_suspend_host(host); 1399 } 1400 1401 static int sdhci_esdhc_resume(struct device *dev) 1402 { 1403 struct sdhci_host *host = dev_get_drvdata(dev); 1404 1405 /* re-initialize hw state in case it's lost in low power mode */ 1406 sdhci_esdhc_imx_hwinit(host); 1407 1408 return sdhci_resume_host(host); 1409 } 1410 #endif 1411 1412 #ifdef CONFIG_PM 1413 static int sdhci_esdhc_runtime_suspend(struct device *dev) 1414 { 1415 struct sdhci_host *host = dev_get_drvdata(dev); 1416 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1417 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1418 int ret; 1419 1420 ret = sdhci_runtime_suspend_host(host); 1421 if (ret) 1422 return ret; 1423 1424 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1425 mmc_retune_needed(host->mmc); 1426 1427 if (!sdhci_sdio_irq_enabled(host)) { 1428 imx_data->actual_clock = host->mmc->actual_clock; 1429 esdhc_pltfm_set_clock(host, 0); 1430 clk_disable_unprepare(imx_data->clk_per); 1431 clk_disable_unprepare(imx_data->clk_ipg); 1432 } 1433 clk_disable_unprepare(imx_data->clk_ahb); 1434 1435 return ret; 1436 } 1437 1438 static int sdhci_esdhc_runtime_resume(struct device *dev) 1439 { 1440 struct sdhci_host *host = dev_get_drvdata(dev); 1441 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1442 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1443 int err; 1444 1445 err = clk_prepare_enable(imx_data->clk_ahb); 1446 if (err) 1447 return err; 1448 1449 if (!sdhci_sdio_irq_enabled(host)) { 1450 err = clk_prepare_enable(imx_data->clk_per); 1451 if (err) 1452 goto disable_ahb_clk; 1453 err = clk_prepare_enable(imx_data->clk_ipg); 1454 if (err) 1455 goto disable_per_clk; 1456 esdhc_pltfm_set_clock(host, imx_data->actual_clock); 1457 } 1458 1459 err = sdhci_runtime_resume_host(host); 1460 if (err) 1461 goto disable_ipg_clk; 1462 1463 return 0; 1464 1465 disable_ipg_clk: 1466 if (!sdhci_sdio_irq_enabled(host)) 1467 clk_disable_unprepare(imx_data->clk_ipg); 1468 disable_per_clk: 1469 if (!sdhci_sdio_irq_enabled(host)) 1470 clk_disable_unprepare(imx_data->clk_per); 1471 disable_ahb_clk: 1472 clk_disable_unprepare(imx_data->clk_ahb); 1473 return err; 1474 } 1475 #endif 1476 1477 static const struct dev_pm_ops sdhci_esdhc_pmops = { 1478 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) 1479 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 1480 sdhci_esdhc_runtime_resume, NULL) 1481 }; 1482 1483 static struct platform_driver sdhci_esdhc_imx_driver = { 1484 .driver = { 1485 .name = "sdhci-esdhc-imx", 1486 .of_match_table = imx_esdhc_dt_ids, 1487 .pm = &sdhci_esdhc_pmops, 1488 }, 1489 .id_table = imx_esdhc_devtype, 1490 .probe = sdhci_esdhc_imx_probe, 1491 .remove = sdhci_esdhc_imx_remove, 1492 }; 1493 1494 module_platform_driver(sdhci_esdhc_imx_driver); 1495 1496 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1497 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 1498 MODULE_LICENSE("GPL v2"); 1499