1 /* 2 * Freescale eSDHC i.MX controller driver for the platform bus. 3 * 4 * derived from the OF-version. 5 * 6 * Copyright (c) 2010 Pengutronix e.K. 7 * Author: Wolfram Sang <kernel@pengutronix.de> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License. 12 */ 13 14 #include <linux/io.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/clk.h> 18 #include <linux/gpio.h> 19 #include <linux/module.h> 20 #include <linux/slab.h> 21 #include <linux/mmc/host.h> 22 #include <linux/mmc/mmc.h> 23 #include <linux/mmc/sdio.h> 24 #include <linux/mmc/slot-gpio.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/of_gpio.h> 28 #include <linux/pinctrl/consumer.h> 29 #include <linux/platform_data/mmc-esdhc-imx.h> 30 #include <linux/pm_runtime.h> 31 #include "sdhci-pltfm.h" 32 #include "sdhci-esdhc.h" 33 34 #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f 35 #define ESDHC_CTRL_D3CD 0x08 36 #define ESDHC_BURST_LEN_EN_INCR (1 << 27) 37 /* VENDOR SPEC register */ 38 #define ESDHC_VENDOR_SPEC 0xc0 39 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 40 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 41 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 42 #define ESDHC_WTMK_LVL 0x44 43 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 44 #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF 45 #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0 46 #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000 47 #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16 48 #define ESDHC_WTMK_LVL_WML_VAL_DEF 64 49 #define ESDHC_WTMK_LVL_WML_VAL_MAX 128 50 #define ESDHC_MIX_CTRL 0x48 51 #define ESDHC_MIX_CTRL_DDREN (1 << 3) 52 #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 53 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 54 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 55 #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) 56 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 57 #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 58 /* Bits 3 and 6 are not SDHCI standard definitions */ 59 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 60 /* Tuning bits */ 61 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 62 63 /* dll control register */ 64 #define ESDHC_DLL_CTRL 0x60 65 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 66 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 67 68 /* tune control register */ 69 #define ESDHC_TUNE_CTRL_STATUS 0x68 70 #define ESDHC_TUNE_CTRL_STEP 1 71 #define ESDHC_TUNE_CTRL_MIN 0 72 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 73 74 /* strobe dll register */ 75 #define ESDHC_STROBE_DLL_CTRL 0x70 76 #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) 77 #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) 78 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 79 80 #define ESDHC_STROBE_DLL_STATUS 0x74 81 #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) 82 #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 83 84 #define ESDHC_TUNING_CTRL 0xcc 85 #define ESDHC_STD_TUNING_EN (1 << 24) 86 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 87 #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 88 #define ESDHC_TUNING_START_TAP_MASK 0xff 89 #define ESDHC_TUNING_STEP_MASK 0x00070000 90 #define ESDHC_TUNING_STEP_SHIFT 16 91 92 /* pinctrl state */ 93 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 94 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 95 96 /* 97 * Our interpretation of the SDHCI_HOST_CONTROL register 98 */ 99 #define ESDHC_CTRL_4BITBUS (0x1 << 1) 100 #define ESDHC_CTRL_8BITBUS (0x2 << 1) 101 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 102 103 /* 104 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC: 105 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 106 * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 107 * Define this macro DMA error INT for fsl eSDHC 108 */ 109 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 110 111 /* 112 * The CMDTYPE of the CMD register (offset 0xE) should be set to 113 * "11" when the STOP CMD12 is issued on imx53 to abort one 114 * open ended multi-blk IO. Otherwise the TC INT wouldn't 115 * be generated. 116 * In exact block transfer, the controller doesn't complete the 117 * operations automatically as required at the end of the 118 * transfer and remains on hold if the abort command is not sent. 119 * As a result, the TC flag is not asserted and SW received timeout 120 * exception. Bit1 of Vendor Spec register is used to fix it. 121 */ 122 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 123 /* 124 * The flag tells that the ESDHC controller is an USDHC block that is 125 * integrated on the i.MX6 series. 126 */ 127 #define ESDHC_FLAG_USDHC BIT(3) 128 /* The IP supports manual tuning process */ 129 #define ESDHC_FLAG_MAN_TUNING BIT(4) 130 /* The IP supports standard tuning process */ 131 #define ESDHC_FLAG_STD_TUNING BIT(5) 132 /* The IP has SDHCI_CAPABILITIES_1 register */ 133 #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 134 /* 135 * The IP has erratum ERR004536 136 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 137 * when reading data from the card 138 * This flag is also set for i.MX25 and i.MX35 in order to get 139 * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits). 140 */ 141 #define ESDHC_FLAG_ERR004536 BIT(7) 142 /* The IP supports HS200 mode */ 143 #define ESDHC_FLAG_HS200 BIT(8) 144 /* The IP supports HS400 mode */ 145 #define ESDHC_FLAG_HS400 BIT(9) 146 147 /* A clock frequency higher than this rate requires strobe dll control */ 148 #define ESDHC_STROBE_DLL_CLK_FREQ 100000000 149 150 struct esdhc_soc_data { 151 u32 flags; 152 }; 153 154 static struct esdhc_soc_data esdhc_imx25_data = { 155 .flags = ESDHC_FLAG_ERR004536, 156 }; 157 158 static struct esdhc_soc_data esdhc_imx35_data = { 159 .flags = ESDHC_FLAG_ERR004536, 160 }; 161 162 static struct esdhc_soc_data esdhc_imx51_data = { 163 .flags = 0, 164 }; 165 166 static struct esdhc_soc_data esdhc_imx53_data = { 167 .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 168 }; 169 170 static struct esdhc_soc_data usdhc_imx6q_data = { 171 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, 172 }; 173 174 static struct esdhc_soc_data usdhc_imx6sl_data = { 175 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 176 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 177 | ESDHC_FLAG_HS200, 178 }; 179 180 static struct esdhc_soc_data usdhc_imx6sx_data = { 181 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 182 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, 183 }; 184 185 static struct esdhc_soc_data usdhc_imx7d_data = { 186 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 187 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 188 | ESDHC_FLAG_HS400, 189 }; 190 191 struct pltfm_imx_data { 192 u32 scratchpad; 193 struct pinctrl *pinctrl; 194 struct pinctrl_state *pins_default; 195 struct pinctrl_state *pins_100mhz; 196 struct pinctrl_state *pins_200mhz; 197 const struct esdhc_soc_data *socdata; 198 struct esdhc_platform_data boarddata; 199 struct clk *clk_ipg; 200 struct clk *clk_ahb; 201 struct clk *clk_per; 202 unsigned int actual_clock; 203 enum { 204 NO_CMD_PENDING, /* no multiblock command pending */ 205 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 206 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 207 } multiblock_status; 208 u32 is_ddr; 209 }; 210 211 static const struct platform_device_id imx_esdhc_devtype[] = { 212 { 213 .name = "sdhci-esdhc-imx25", 214 .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 215 }, { 216 .name = "sdhci-esdhc-imx35", 217 .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 218 }, { 219 .name = "sdhci-esdhc-imx51", 220 .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 221 }, { 222 /* sentinel */ 223 } 224 }; 225 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 226 227 static const struct of_device_id imx_esdhc_dt_ids[] = { 228 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 229 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 230 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 231 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 232 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 233 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 234 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 235 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, 236 { /* sentinel */ } 237 }; 238 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 239 240 static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 241 { 242 return data->socdata == &esdhc_imx25_data; 243 } 244 245 static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 246 { 247 return data->socdata == &esdhc_imx53_data; 248 } 249 250 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 251 { 252 return data->socdata == &usdhc_imx6q_data; 253 } 254 255 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 256 { 257 return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 258 } 259 260 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 261 { 262 void __iomem *base = host->ioaddr + (reg & ~0x3); 263 u32 shift = (reg & 0x3) * 8; 264 265 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 266 } 267 268 static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 269 { 270 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 271 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 272 u32 val = readl(host->ioaddr + reg); 273 274 if (unlikely(reg == SDHCI_PRESENT_STATE)) { 275 u32 fsl_prss = val; 276 /* save the least 20 bits */ 277 val = fsl_prss & 0x000FFFFF; 278 /* move dat[0-3] bits */ 279 val |= (fsl_prss & 0x0F000000) >> 4; 280 /* move cmd line bit */ 281 val |= (fsl_prss & 0x00800000) << 1; 282 } 283 284 if (unlikely(reg == SDHCI_CAPABILITIES)) { 285 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 286 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 287 val &= 0xffff0000; 288 289 /* In FSL esdhc IC module, only bit20 is used to indicate the 290 * ADMA2 capability of esdhc, but this bit is messed up on 291 * some SOCs (e.g. on MX25, MX35 this bit is set, but they 292 * don't actually support ADMA2). So set the BROKEN_ADMA 293 * quirk on MX25/35 platforms. 294 */ 295 296 if (val & SDHCI_CAN_DO_ADMA1) { 297 val &= ~SDHCI_CAN_DO_ADMA1; 298 val |= SDHCI_CAN_DO_ADMA2; 299 } 300 } 301 302 if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 303 if (esdhc_is_usdhc(imx_data)) { 304 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 305 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 306 else 307 /* imx6q/dl does not have cap_1 register, fake one */ 308 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 309 | SDHCI_SUPPORT_SDR50 310 | SDHCI_USE_SDR50_TUNING 311 | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT); 312 313 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 314 val |= SDHCI_SUPPORT_HS400; 315 } 316 } 317 318 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 319 val = 0; 320 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 321 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 322 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 323 } 324 325 if (unlikely(reg == SDHCI_INT_STATUS)) { 326 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 327 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 328 val |= SDHCI_INT_ADMA_ERROR; 329 } 330 331 /* 332 * mask off the interrupt we get in response to the manually 333 * sent CMD12 334 */ 335 if ((imx_data->multiblock_status == WAIT_FOR_INT) && 336 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 337 val &= ~SDHCI_INT_RESPONSE; 338 writel(SDHCI_INT_RESPONSE, host->ioaddr + 339 SDHCI_INT_STATUS); 340 imx_data->multiblock_status = NO_CMD_PENDING; 341 } 342 } 343 344 return val; 345 } 346 347 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 348 { 349 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 350 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 351 u32 data; 352 353 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || 354 reg == SDHCI_INT_STATUS)) { 355 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 356 /* 357 * Clear and then set D3CD bit to avoid missing the 358 * card interrupt. This is an eSDHC controller problem 359 * so we need to apply the following workaround: clear 360 * and set D3CD bit will make eSDHC re-sample the card 361 * interrupt. In case a card interrupt was lost, 362 * re-sample it by the following steps. 363 */ 364 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 365 data &= ~ESDHC_CTRL_D3CD; 366 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 367 data |= ESDHC_CTRL_D3CD; 368 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 369 } 370 371 if (val & SDHCI_INT_ADMA_ERROR) { 372 val &= ~SDHCI_INT_ADMA_ERROR; 373 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 374 } 375 } 376 377 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 378 && (reg == SDHCI_INT_STATUS) 379 && (val & SDHCI_INT_DATA_END))) { 380 u32 v; 381 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 382 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 383 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 384 385 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 386 { 387 /* send a manual CMD12 with RESPTYP=none */ 388 data = MMC_STOP_TRANSMISSION << 24 | 389 SDHCI_CMD_ABORTCMD << 16; 390 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 391 imx_data->multiblock_status = WAIT_FOR_INT; 392 } 393 } 394 395 writel(val, host->ioaddr + reg); 396 } 397 398 static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 399 { 400 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 401 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 402 u16 ret = 0; 403 u32 val; 404 405 if (unlikely(reg == SDHCI_HOST_VERSION)) { 406 reg ^= 2; 407 if (esdhc_is_usdhc(imx_data)) { 408 /* 409 * The usdhc register returns a wrong host version. 410 * Correct it here. 411 */ 412 return SDHCI_SPEC_300; 413 } 414 } 415 416 if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 417 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 418 if (val & ESDHC_VENDOR_SPEC_VSELECT) 419 ret |= SDHCI_CTRL_VDD_180; 420 421 if (esdhc_is_usdhc(imx_data)) { 422 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 423 val = readl(host->ioaddr + ESDHC_MIX_CTRL); 424 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 425 /* the std tuning bits is in ACMD12_ERR for imx6sl */ 426 val = readl(host->ioaddr + SDHCI_ACMD12_ERR); 427 } 428 429 if (val & ESDHC_MIX_CTRL_EXE_TUNE) 430 ret |= SDHCI_CTRL_EXEC_TUNING; 431 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 432 ret |= SDHCI_CTRL_TUNED_CLK; 433 434 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 435 436 return ret; 437 } 438 439 if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 440 if (esdhc_is_usdhc(imx_data)) { 441 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 442 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 443 /* Swap AC23 bit */ 444 if (m & ESDHC_MIX_CTRL_AC23EN) { 445 ret &= ~ESDHC_MIX_CTRL_AC23EN; 446 ret |= SDHCI_TRNS_AUTO_CMD23; 447 } 448 } else { 449 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 450 } 451 452 return ret; 453 } 454 455 return readw(host->ioaddr + reg); 456 } 457 458 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 459 { 460 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 461 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 462 u32 new_val = 0; 463 464 switch (reg) { 465 case SDHCI_CLOCK_CONTROL: 466 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 467 if (val & SDHCI_CLOCK_CARD_EN) 468 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 469 else 470 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 471 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 472 return; 473 case SDHCI_HOST_CONTROL2: 474 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 475 if (val & SDHCI_CTRL_VDD_180) 476 new_val |= ESDHC_VENDOR_SPEC_VSELECT; 477 else 478 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 479 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 480 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 481 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 482 if (val & SDHCI_CTRL_TUNED_CLK) { 483 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 484 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 485 } else { 486 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 487 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 488 } 489 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 490 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 491 u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); 492 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 493 if (val & SDHCI_CTRL_TUNED_CLK) { 494 v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 495 } else { 496 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 497 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 498 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 499 } 500 501 if (val & SDHCI_CTRL_EXEC_TUNING) { 502 v |= ESDHC_MIX_CTRL_EXE_TUNE; 503 m |= ESDHC_MIX_CTRL_FBCLK_SEL; 504 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 505 } else { 506 v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 507 } 508 509 writel(v, host->ioaddr + SDHCI_ACMD12_ERR); 510 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 511 } 512 return; 513 case SDHCI_TRANSFER_MODE: 514 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 515 && (host->cmd->opcode == SD_IO_RW_EXTENDED) 516 && (host->cmd->data->blocks > 1) 517 && (host->cmd->data->flags & MMC_DATA_READ)) { 518 u32 v; 519 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 520 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 521 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 522 } 523 524 if (esdhc_is_usdhc(imx_data)) { 525 u32 wml; 526 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 527 /* Swap AC23 bit */ 528 if (val & SDHCI_TRNS_AUTO_CMD23) { 529 val &= ~SDHCI_TRNS_AUTO_CMD23; 530 val |= ESDHC_MIX_CTRL_AC23EN; 531 } 532 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 533 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 534 535 /* Set watermark levels for PIO access to maximum value 536 * (128 words) to accommodate full 512 bytes buffer. 537 * For DMA access restore the levels to default value. 538 */ 539 m = readl(host->ioaddr + ESDHC_WTMK_LVL); 540 if (val & SDHCI_TRNS_DMA) 541 wml = ESDHC_WTMK_LVL_WML_VAL_DEF; 542 else 543 wml = ESDHC_WTMK_LVL_WML_VAL_MAX; 544 m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK | 545 ESDHC_WTMK_LVL_WR_WML_MASK); 546 m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) | 547 (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT); 548 writel(m, host->ioaddr + ESDHC_WTMK_LVL); 549 } else { 550 /* 551 * Postpone this write, we must do it together with a 552 * command write that is down below. 553 */ 554 imx_data->scratchpad = val; 555 } 556 return; 557 case SDHCI_COMMAND: 558 if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 559 val |= SDHCI_CMD_ABORTCMD; 560 561 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 562 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 563 imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 564 565 if (esdhc_is_usdhc(imx_data)) 566 writel(val << 16, 567 host->ioaddr + SDHCI_TRANSFER_MODE); 568 else 569 writel(val << 16 | imx_data->scratchpad, 570 host->ioaddr + SDHCI_TRANSFER_MODE); 571 return; 572 case SDHCI_BLOCK_SIZE: 573 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 574 break; 575 } 576 esdhc_clrset_le(host, 0xffff, val, reg); 577 } 578 579 static u8 esdhc_readb_le(struct sdhci_host *host, int reg) 580 { 581 u8 ret; 582 u32 val; 583 584 switch (reg) { 585 case SDHCI_HOST_CONTROL: 586 val = readl(host->ioaddr + reg); 587 588 ret = val & SDHCI_CTRL_LED; 589 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; 590 ret |= (val & ESDHC_CTRL_4BITBUS); 591 ret |= (val & ESDHC_CTRL_8BITBUS) << 3; 592 return ret; 593 } 594 595 return readb(host->ioaddr + reg); 596 } 597 598 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 599 { 600 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 601 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 602 u32 new_val = 0; 603 u32 mask; 604 605 switch (reg) { 606 case SDHCI_POWER_CONTROL: 607 /* 608 * FSL put some DMA bits here 609 * If your board has a regulator, code should be here 610 */ 611 return; 612 case SDHCI_HOST_CONTROL: 613 /* FSL messed up here, so we need to manually compose it. */ 614 new_val = val & SDHCI_CTRL_LED; 615 /* ensure the endianness */ 616 new_val |= ESDHC_HOST_CONTROL_LE; 617 /* bits 8&9 are reserved on mx25 */ 618 if (!is_imx25_esdhc(imx_data)) { 619 /* DMA mode bits are shifted */ 620 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 621 } 622 623 /* 624 * Do not touch buswidth bits here. This is done in 625 * esdhc_pltfm_bus_width. 626 * Do not touch the D3CD bit either which is used for the 627 * SDIO interrupt erratum workaround. 628 */ 629 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 630 631 esdhc_clrset_le(host, mask, new_val, reg); 632 return; 633 case SDHCI_SOFTWARE_RESET: 634 if (val & SDHCI_RESET_DATA) 635 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); 636 break; 637 } 638 esdhc_clrset_le(host, 0xff, val, reg); 639 640 if (reg == SDHCI_SOFTWARE_RESET) { 641 if (val & SDHCI_RESET_ALL) { 642 /* 643 * The esdhc has a design violation to SDHC spec which 644 * tells that software reset should not affect card 645 * detection circuit. But esdhc clears its SYSCTL 646 * register bits [0..2] during the software reset. This 647 * will stop those clocks that card detection circuit 648 * relies on. To work around it, we turn the clocks on 649 * back to keep card detection circuit functional. 650 */ 651 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 652 /* 653 * The reset on usdhc fails to clear MIX_CTRL register. 654 * Do it manually here. 655 */ 656 if (esdhc_is_usdhc(imx_data)) { 657 /* 658 * the tuning bits should be kept during reset 659 */ 660 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 661 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 662 host->ioaddr + ESDHC_MIX_CTRL); 663 imx_data->is_ddr = 0; 664 } 665 } else if (val & SDHCI_RESET_DATA) { 666 /* 667 * The eSDHC DAT line software reset clears at least the 668 * data transfer width on i.MX25, so make sure that the 669 * Host Control register is unaffected. 670 */ 671 esdhc_clrset_le(host, 0xff, new_val, 672 SDHCI_HOST_CONTROL); 673 } 674 } 675 } 676 677 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 678 { 679 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 680 681 return pltfm_host->clock; 682 } 683 684 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 685 { 686 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 687 688 return pltfm_host->clock / 256 / 16; 689 } 690 691 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 692 unsigned int clock) 693 { 694 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 695 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 696 unsigned int host_clock = pltfm_host->clock; 697 int ddr_pre_div = imx_data->is_ddr ? 2 : 1; 698 int pre_div = 1; 699 int div = 1; 700 u32 temp, val; 701 702 if (clock == 0) { 703 host->mmc->actual_clock = 0; 704 705 if (esdhc_is_usdhc(imx_data)) { 706 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 707 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 708 host->ioaddr + ESDHC_VENDOR_SPEC); 709 } 710 return; 711 } 712 713 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ 714 if (is_imx53_esdhc(imx_data)) { 715 /* 716 * According to the i.MX53 reference manual, if DLLCTRL[10] can 717 * be set, then the controller is eSDHCv3, else it is eSDHCv2. 718 */ 719 val = readl(host->ioaddr + ESDHC_DLL_CTRL); 720 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); 721 temp = readl(host->ioaddr + ESDHC_DLL_CTRL); 722 writel(val, host->ioaddr + ESDHC_DLL_CTRL); 723 if (temp & BIT(10)) 724 pre_div = 2; 725 } 726 727 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 728 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 729 | ESDHC_CLOCK_MASK); 730 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 731 732 while (host_clock / (16 * pre_div * ddr_pre_div) > clock && 733 pre_div < 256) 734 pre_div *= 2; 735 736 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16) 737 div++; 738 739 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); 740 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 741 clock, host->mmc->actual_clock); 742 743 pre_div >>= 1; 744 div--; 745 746 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 747 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 748 | (div << ESDHC_DIVIDER_SHIFT) 749 | (pre_div << ESDHC_PREDIV_SHIFT)); 750 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 751 752 if (esdhc_is_usdhc(imx_data)) { 753 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 754 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 755 host->ioaddr + ESDHC_VENDOR_SPEC); 756 } 757 758 mdelay(1); 759 } 760 761 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 762 { 763 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 764 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 765 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 766 767 switch (boarddata->wp_type) { 768 case ESDHC_WP_GPIO: 769 return mmc_gpio_get_ro(host->mmc); 770 case ESDHC_WP_CONTROLLER: 771 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 772 SDHCI_WRITE_PROTECT); 773 case ESDHC_WP_NONE: 774 break; 775 } 776 777 return -ENOSYS; 778 } 779 780 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 781 { 782 u32 ctrl; 783 784 switch (width) { 785 case MMC_BUS_WIDTH_8: 786 ctrl = ESDHC_CTRL_8BITBUS; 787 break; 788 case MMC_BUS_WIDTH_4: 789 ctrl = ESDHC_CTRL_4BITBUS; 790 break; 791 default: 792 ctrl = 0; 793 break; 794 } 795 796 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 797 SDHCI_HOST_CONTROL); 798 } 799 800 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 801 { 802 u32 reg; 803 804 /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 805 mdelay(1); 806 807 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 808 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 809 ESDHC_MIX_CTRL_FBCLK_SEL; 810 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 811 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 812 dev_dbg(mmc_dev(host->mmc), 813 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 814 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 815 } 816 817 static void esdhc_post_tuning(struct sdhci_host *host) 818 { 819 u32 reg; 820 821 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 822 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 823 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 824 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 825 } 826 827 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 828 { 829 int min, max, avg, ret; 830 831 /* find the mininum delay first which can pass tuning */ 832 min = ESDHC_TUNE_CTRL_MIN; 833 while (min < ESDHC_TUNE_CTRL_MAX) { 834 esdhc_prepare_tuning(host, min); 835 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 836 break; 837 min += ESDHC_TUNE_CTRL_STEP; 838 } 839 840 /* find the maxinum delay which can not pass tuning */ 841 max = min + ESDHC_TUNE_CTRL_STEP; 842 while (max < ESDHC_TUNE_CTRL_MAX) { 843 esdhc_prepare_tuning(host, max); 844 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 845 max -= ESDHC_TUNE_CTRL_STEP; 846 break; 847 } 848 max += ESDHC_TUNE_CTRL_STEP; 849 } 850 851 /* use average delay to get the best timing */ 852 avg = (min + max) / 2; 853 esdhc_prepare_tuning(host, avg); 854 ret = mmc_send_tuning(host->mmc, opcode, NULL); 855 esdhc_post_tuning(host); 856 857 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 858 ret ? "failed" : "passed", avg, ret); 859 860 return ret; 861 } 862 863 static int esdhc_change_pinstate(struct sdhci_host *host, 864 unsigned int uhs) 865 { 866 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 867 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 868 struct pinctrl_state *pinctrl; 869 870 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 871 872 if (IS_ERR(imx_data->pinctrl) || 873 IS_ERR(imx_data->pins_default) || 874 IS_ERR(imx_data->pins_100mhz) || 875 IS_ERR(imx_data->pins_200mhz)) 876 return -EINVAL; 877 878 switch (uhs) { 879 case MMC_TIMING_UHS_SDR50: 880 case MMC_TIMING_UHS_DDR50: 881 pinctrl = imx_data->pins_100mhz; 882 break; 883 case MMC_TIMING_UHS_SDR104: 884 case MMC_TIMING_MMC_HS200: 885 case MMC_TIMING_MMC_HS400: 886 pinctrl = imx_data->pins_200mhz; 887 break; 888 default: 889 /* back to default state for other legacy timing */ 890 pinctrl = imx_data->pins_default; 891 } 892 893 return pinctrl_select_state(imx_data->pinctrl, pinctrl); 894 } 895 896 /* 897 * For HS400 eMMC, there is a data_strobe line. This signal is generated 898 * by the device and used for data output and CRC status response output 899 * in HS400 mode. The frequency of this signal follows the frequency of 900 * CLK generated by host. The host receives the data which is aligned to the 901 * edge of data_strobe line. Due to the time delay between CLK line and 902 * data_strobe line, if the delay time is larger than one clock cycle, 903 * then CLK and data_strobe line will be misaligned, read error shows up. 904 * So when the CLK is higher than 100MHz, each clock cycle is short enough, 905 * host should configure the delay target. 906 */ 907 static void esdhc_set_strobe_dll(struct sdhci_host *host) 908 { 909 u32 v; 910 911 if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) { 912 /* disable clock before enabling strobe dll */ 913 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & 914 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 915 host->ioaddr + ESDHC_VENDOR_SPEC); 916 917 /* force a reset on strobe dll */ 918 writel(ESDHC_STROBE_DLL_CTRL_RESET, 919 host->ioaddr + ESDHC_STROBE_DLL_CTRL); 920 /* 921 * enable strobe dll ctrl and adjust the delay target 922 * for the uSDHC loopback read clock 923 */ 924 v = ESDHC_STROBE_DLL_CTRL_ENABLE | 925 (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 926 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 927 /* wait 1us to make sure strobe dll status register stable */ 928 udelay(1); 929 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS); 930 if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK)) 931 dev_warn(mmc_dev(host->mmc), 932 "warning! HS400 strobe DLL status REF not lock!\n"); 933 if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK)) 934 dev_warn(mmc_dev(host->mmc), 935 "warning! HS400 strobe DLL status SLV not lock!\n"); 936 } 937 } 938 939 static void esdhc_reset_tuning(struct sdhci_host *host) 940 { 941 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 942 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 943 u32 ctrl; 944 945 /* Reset the tuning circuit */ 946 if (esdhc_is_usdhc(imx_data)) { 947 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 948 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); 949 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 950 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 951 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 952 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 953 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 954 ctrl = readl(host->ioaddr + SDHCI_ACMD12_ERR); 955 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 956 writel(ctrl, host->ioaddr + SDHCI_ACMD12_ERR); 957 } 958 } 959 } 960 961 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 962 { 963 u32 m; 964 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 965 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 966 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 967 968 /* disable ddr mode and disable HS400 mode */ 969 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 970 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); 971 imx_data->is_ddr = 0; 972 973 switch (timing) { 974 case MMC_TIMING_UHS_SDR12: 975 case MMC_TIMING_UHS_SDR25: 976 case MMC_TIMING_UHS_SDR50: 977 case MMC_TIMING_UHS_SDR104: 978 case MMC_TIMING_MMC_HS200: 979 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 980 break; 981 case MMC_TIMING_UHS_DDR50: 982 case MMC_TIMING_MMC_DDR52: 983 m |= ESDHC_MIX_CTRL_DDREN; 984 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 985 imx_data->is_ddr = 1; 986 if (boarddata->delay_line) { 987 u32 v; 988 v = boarddata->delay_line << 989 ESDHC_DLL_OVERRIDE_VAL_SHIFT | 990 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 991 if (is_imx53_esdhc(imx_data)) 992 v <<= 1; 993 writel(v, host->ioaddr + ESDHC_DLL_CTRL); 994 } 995 break; 996 case MMC_TIMING_MMC_HS400: 997 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 998 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 999 imx_data->is_ddr = 1; 1000 /* update clock after enable DDR for strobe DLL lock */ 1001 host->ops->set_clock(host, host->clock); 1002 esdhc_set_strobe_dll(host); 1003 break; 1004 case MMC_TIMING_LEGACY: 1005 default: 1006 esdhc_reset_tuning(host); 1007 break; 1008 } 1009 1010 esdhc_change_pinstate(host, timing); 1011 } 1012 1013 static void esdhc_reset(struct sdhci_host *host, u8 mask) 1014 { 1015 sdhci_reset(host, mask); 1016 1017 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1018 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1019 } 1020 1021 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 1022 { 1023 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1024 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1025 1026 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */ 1027 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27; 1028 } 1029 1030 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 1031 { 1032 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1033 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1034 1035 /* use maximum timeout counter */ 1036 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, 1037 esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 1038 SDHCI_TIMEOUT_CONTROL); 1039 } 1040 1041 static struct sdhci_ops sdhci_esdhc_ops = { 1042 .read_l = esdhc_readl_le, 1043 .read_w = esdhc_readw_le, 1044 .read_b = esdhc_readb_le, 1045 .write_l = esdhc_writel_le, 1046 .write_w = esdhc_writew_le, 1047 .write_b = esdhc_writeb_le, 1048 .set_clock = esdhc_pltfm_set_clock, 1049 .get_max_clock = esdhc_pltfm_get_max_clock, 1050 .get_min_clock = esdhc_pltfm_get_min_clock, 1051 .get_max_timeout_count = esdhc_get_max_timeout_count, 1052 .get_ro = esdhc_pltfm_get_ro, 1053 .set_timeout = esdhc_set_timeout, 1054 .set_bus_width = esdhc_pltfm_set_bus_width, 1055 .set_uhs_signaling = esdhc_set_uhs_signaling, 1056 .reset = esdhc_reset, 1057 }; 1058 1059 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 1060 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 1061 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 1062 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 1063 | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 1064 .ops = &sdhci_esdhc_ops, 1065 }; 1066 1067 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) 1068 { 1069 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1070 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1071 int tmp; 1072 1073 if (esdhc_is_usdhc(imx_data)) { 1074 /* 1075 * The imx6q ROM code will change the default watermark 1076 * level setting to something insane. Change it back here. 1077 */ 1078 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); 1079 1080 /* 1081 * ROM code will change the bit burst_length_enable setting 1082 * to zero if this usdhc is chosen to boot system. Change 1083 * it back here, otherwise it will impact the performance a 1084 * lot. This bit is used to enable/disable the burst length 1085 * for the external AHB2AXI bridge. It's useful especially 1086 * for INCR transfer because without burst length indicator, 1087 * the AHB2AXI bridge does not know the burst length in 1088 * advance. And without burst length indicator, AHB INCR 1089 * transfer can only be converted to singles on the AXI side. 1090 */ 1091 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) 1092 | ESDHC_BURST_LEN_EN_INCR, 1093 host->ioaddr + SDHCI_HOST_CONTROL); 1094 /* 1095 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 1096 * TO1.1, it's harmless for MX6SL 1097 */ 1098 writel(readl(host->ioaddr + 0x6c) | BIT(7), 1099 host->ioaddr + 0x6c); 1100 1101 /* disable DLL_CTRL delay line settings */ 1102 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); 1103 1104 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1105 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1106 tmp |= ESDHC_STD_TUNING_EN | 1107 ESDHC_TUNING_START_TAP_DEFAULT; 1108 if (imx_data->boarddata.tuning_start_tap) { 1109 tmp &= ~ESDHC_TUNING_START_TAP_MASK; 1110 tmp |= imx_data->boarddata.tuning_start_tap; 1111 } 1112 1113 if (imx_data->boarddata.tuning_step) { 1114 tmp &= ~ESDHC_TUNING_STEP_MASK; 1115 tmp |= imx_data->boarddata.tuning_step 1116 << ESDHC_TUNING_STEP_SHIFT; 1117 } 1118 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1119 } 1120 } 1121 } 1122 1123 #ifdef CONFIG_OF 1124 static int 1125 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 1126 struct sdhci_host *host, 1127 struct pltfm_imx_data *imx_data) 1128 { 1129 struct device_node *np = pdev->dev.of_node; 1130 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1131 int ret; 1132 1133 if (of_get_property(np, "fsl,wp-controller", NULL)) 1134 boarddata->wp_type = ESDHC_WP_CONTROLLER; 1135 1136 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 1137 if (gpio_is_valid(boarddata->wp_gpio)) 1138 boarddata->wp_type = ESDHC_WP_GPIO; 1139 1140 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 1141 of_property_read_u32(np, "fsl,tuning-start-tap", 1142 &boarddata->tuning_start_tap); 1143 1144 if (of_find_property(np, "no-1-8-v", NULL)) 1145 boarddata->support_vsel = false; 1146 else 1147 boarddata->support_vsel = true; 1148 1149 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 1150 boarddata->delay_line = 0; 1151 1152 mmc_of_parse_voltage(np, &host->ocr_mask); 1153 1154 /* sdr50 and sdr104 need work on 1.8v signal voltage */ 1155 if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) && 1156 !IS_ERR(imx_data->pins_default)) { 1157 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 1158 ESDHC_PINCTRL_STATE_100MHZ); 1159 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 1160 ESDHC_PINCTRL_STATE_200MHZ); 1161 if (IS_ERR(imx_data->pins_100mhz) || 1162 IS_ERR(imx_data->pins_200mhz)) { 1163 dev_warn(mmc_dev(host->mmc), 1164 "could not get ultra high speed state, work on normal mode\n"); 1165 /* 1166 * fall back to not supporting uhs by specifying no 1167 * 1.8v quirk 1168 */ 1169 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1170 } 1171 } else { 1172 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1173 } 1174 1175 /* call to generic mmc_of_parse to support additional capabilities */ 1176 ret = mmc_of_parse(host->mmc); 1177 if (ret) 1178 return ret; 1179 1180 if (mmc_gpio_get_cd(host->mmc) >= 0) 1181 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1182 1183 return 0; 1184 } 1185 #else 1186 static inline int 1187 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 1188 struct sdhci_host *host, 1189 struct pltfm_imx_data *imx_data) 1190 { 1191 return -ENODEV; 1192 } 1193 #endif 1194 1195 static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev, 1196 struct sdhci_host *host, 1197 struct pltfm_imx_data *imx_data) 1198 { 1199 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1200 int err; 1201 1202 if (!host->mmc->parent->platform_data) { 1203 dev_err(mmc_dev(host->mmc), "no board data!\n"); 1204 return -EINVAL; 1205 } 1206 1207 imx_data->boarddata = *((struct esdhc_platform_data *) 1208 host->mmc->parent->platform_data); 1209 /* write_protect */ 1210 if (boarddata->wp_type == ESDHC_WP_GPIO) { 1211 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); 1212 if (err) { 1213 dev_err(mmc_dev(host->mmc), 1214 "failed to request write-protect gpio!\n"); 1215 return err; 1216 } 1217 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 1218 } 1219 1220 /* card_detect */ 1221 switch (boarddata->cd_type) { 1222 case ESDHC_CD_GPIO: 1223 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); 1224 if (err) { 1225 dev_err(mmc_dev(host->mmc), 1226 "failed to request card-detect gpio!\n"); 1227 return err; 1228 } 1229 /* fall through */ 1230 1231 case ESDHC_CD_CONTROLLER: 1232 /* we have a working card_detect back */ 1233 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1234 break; 1235 1236 case ESDHC_CD_PERMANENT: 1237 host->mmc->caps |= MMC_CAP_NONREMOVABLE; 1238 break; 1239 1240 case ESDHC_CD_NONE: 1241 break; 1242 } 1243 1244 switch (boarddata->max_bus_width) { 1245 case 8: 1246 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 1247 break; 1248 case 4: 1249 host->mmc->caps |= MMC_CAP_4_BIT_DATA; 1250 break; 1251 case 1: 1252 default: 1253 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 1254 break; 1255 } 1256 1257 return 0; 1258 } 1259 1260 static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 1261 { 1262 const struct of_device_id *of_id = 1263 of_match_device(imx_esdhc_dt_ids, &pdev->dev); 1264 struct sdhci_pltfm_host *pltfm_host; 1265 struct sdhci_host *host; 1266 int err; 1267 struct pltfm_imx_data *imx_data; 1268 1269 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 1270 sizeof(*imx_data)); 1271 if (IS_ERR(host)) 1272 return PTR_ERR(host); 1273 1274 pltfm_host = sdhci_priv(host); 1275 1276 imx_data = sdhci_pltfm_priv(pltfm_host); 1277 1278 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 1279 pdev->id_entry->driver_data; 1280 1281 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1282 if (IS_ERR(imx_data->clk_ipg)) { 1283 err = PTR_ERR(imx_data->clk_ipg); 1284 goto free_sdhci; 1285 } 1286 1287 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1288 if (IS_ERR(imx_data->clk_ahb)) { 1289 err = PTR_ERR(imx_data->clk_ahb); 1290 goto free_sdhci; 1291 } 1292 1293 imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 1294 if (IS_ERR(imx_data->clk_per)) { 1295 err = PTR_ERR(imx_data->clk_per); 1296 goto free_sdhci; 1297 } 1298 1299 pltfm_host->clk = imx_data->clk_per; 1300 pltfm_host->clock = clk_get_rate(pltfm_host->clk); 1301 err = clk_prepare_enable(imx_data->clk_per); 1302 if (err) 1303 goto free_sdhci; 1304 err = clk_prepare_enable(imx_data->clk_ipg); 1305 if (err) 1306 goto disable_per_clk; 1307 err = clk_prepare_enable(imx_data->clk_ahb); 1308 if (err) 1309 goto disable_ipg_clk; 1310 1311 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1312 if (IS_ERR(imx_data->pinctrl)) { 1313 err = PTR_ERR(imx_data->pinctrl); 1314 goto disable_ahb_clk; 1315 } 1316 1317 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, 1318 PINCTRL_STATE_DEFAULT); 1319 if (IS_ERR(imx_data->pins_default)) 1320 dev_warn(mmc_dev(host->mmc), "could not get default state\n"); 1321 1322 if (esdhc_is_usdhc(imx_data)) { 1323 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 1324 host->mmc->caps |= MMC_CAP_1_8V_DDR; 1325 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 1326 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 1327 1328 /* clear tuning bits in case ROM has set it already */ 1329 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); 1330 writel(0x0, host->ioaddr + SDHCI_ACMD12_ERR); 1331 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1332 } 1333 1334 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 1335 sdhci_esdhc_ops.platform_execute_tuning = 1336 esdhc_executing_tuning; 1337 1338 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 1339 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1340 1341 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 1342 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; 1343 1344 if (of_id) 1345 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 1346 else 1347 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data); 1348 if (err) 1349 goto disable_ahb_clk; 1350 1351 sdhci_esdhc_imx_hwinit(host); 1352 1353 err = sdhci_add_host(host); 1354 if (err) 1355 goto disable_ahb_clk; 1356 1357 pm_runtime_set_active(&pdev->dev); 1358 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1359 pm_runtime_use_autosuspend(&pdev->dev); 1360 pm_suspend_ignore_children(&pdev->dev, 1); 1361 pm_runtime_enable(&pdev->dev); 1362 1363 return 0; 1364 1365 disable_ahb_clk: 1366 clk_disable_unprepare(imx_data->clk_ahb); 1367 disable_ipg_clk: 1368 clk_disable_unprepare(imx_data->clk_ipg); 1369 disable_per_clk: 1370 clk_disable_unprepare(imx_data->clk_per); 1371 free_sdhci: 1372 sdhci_pltfm_free(pdev); 1373 return err; 1374 } 1375 1376 static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 1377 { 1378 struct sdhci_host *host = platform_get_drvdata(pdev); 1379 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1380 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1381 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 1382 1383 pm_runtime_get_sync(&pdev->dev); 1384 pm_runtime_disable(&pdev->dev); 1385 pm_runtime_put_noidle(&pdev->dev); 1386 1387 sdhci_remove_host(host, dead); 1388 1389 clk_disable_unprepare(imx_data->clk_per); 1390 clk_disable_unprepare(imx_data->clk_ipg); 1391 clk_disable_unprepare(imx_data->clk_ahb); 1392 1393 sdhci_pltfm_free(pdev); 1394 1395 return 0; 1396 } 1397 1398 #ifdef CONFIG_PM_SLEEP 1399 static int sdhci_esdhc_suspend(struct device *dev) 1400 { 1401 struct sdhci_host *host = dev_get_drvdata(dev); 1402 1403 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1404 mmc_retune_needed(host->mmc); 1405 1406 return sdhci_suspend_host(host); 1407 } 1408 1409 static int sdhci_esdhc_resume(struct device *dev) 1410 { 1411 struct sdhci_host *host = dev_get_drvdata(dev); 1412 1413 /* re-initialize hw state in case it's lost in low power mode */ 1414 sdhci_esdhc_imx_hwinit(host); 1415 1416 return sdhci_resume_host(host); 1417 } 1418 #endif 1419 1420 #ifdef CONFIG_PM 1421 static int sdhci_esdhc_runtime_suspend(struct device *dev) 1422 { 1423 struct sdhci_host *host = dev_get_drvdata(dev); 1424 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1425 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1426 int ret; 1427 1428 ret = sdhci_runtime_suspend_host(host); 1429 if (ret) 1430 return ret; 1431 1432 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1433 mmc_retune_needed(host->mmc); 1434 1435 if (!sdhci_sdio_irq_enabled(host)) { 1436 imx_data->actual_clock = host->mmc->actual_clock; 1437 esdhc_pltfm_set_clock(host, 0); 1438 clk_disable_unprepare(imx_data->clk_per); 1439 clk_disable_unprepare(imx_data->clk_ipg); 1440 } 1441 clk_disable_unprepare(imx_data->clk_ahb); 1442 1443 return ret; 1444 } 1445 1446 static int sdhci_esdhc_runtime_resume(struct device *dev) 1447 { 1448 struct sdhci_host *host = dev_get_drvdata(dev); 1449 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1450 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1451 int err; 1452 1453 err = clk_prepare_enable(imx_data->clk_ahb); 1454 if (err) 1455 return err; 1456 1457 if (!sdhci_sdio_irq_enabled(host)) { 1458 err = clk_prepare_enable(imx_data->clk_per); 1459 if (err) 1460 goto disable_ahb_clk; 1461 err = clk_prepare_enable(imx_data->clk_ipg); 1462 if (err) 1463 goto disable_per_clk; 1464 esdhc_pltfm_set_clock(host, imx_data->actual_clock); 1465 } 1466 1467 err = sdhci_runtime_resume_host(host); 1468 if (err) 1469 goto disable_ipg_clk; 1470 1471 return 0; 1472 1473 disable_ipg_clk: 1474 if (!sdhci_sdio_irq_enabled(host)) 1475 clk_disable_unprepare(imx_data->clk_ipg); 1476 disable_per_clk: 1477 if (!sdhci_sdio_irq_enabled(host)) 1478 clk_disable_unprepare(imx_data->clk_per); 1479 disable_ahb_clk: 1480 clk_disable_unprepare(imx_data->clk_ahb); 1481 return err; 1482 } 1483 #endif 1484 1485 static const struct dev_pm_ops sdhci_esdhc_pmops = { 1486 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) 1487 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 1488 sdhci_esdhc_runtime_resume, NULL) 1489 }; 1490 1491 static struct platform_driver sdhci_esdhc_imx_driver = { 1492 .driver = { 1493 .name = "sdhci-esdhc-imx", 1494 .of_match_table = imx_esdhc_dt_ids, 1495 .pm = &sdhci_esdhc_pmops, 1496 }, 1497 .id_table = imx_esdhc_devtype, 1498 .probe = sdhci_esdhc_imx_probe, 1499 .remove = sdhci_esdhc_imx_remove, 1500 }; 1501 1502 module_platform_driver(sdhci_esdhc_imx_driver); 1503 1504 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1505 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 1506 MODULE_LICENSE("GPL v2"); 1507