1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Freescale eSDHC i.MX controller driver for the platform bus.
4  *
5  * derived from the OF-version.
6  *
7  * Copyright (c) 2010 Pengutronix e.K.
8  *   Author: Wolfram Sang <kernel@pengutronix.de>
9  */
10 
11 #include <linux/bitfield.h>
12 #include <linux/io.h>
13 #include <linux/iopoll.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
17 #include <linux/module.h>
18 #include <linux/slab.h>
19 #include <linux/pm_qos.h>
20 #include <linux/mmc/host.h>
21 #include <linux/mmc/mmc.h>
22 #include <linux/mmc/sdio.h>
23 #include <linux/mmc/slot-gpio.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/pm_runtime.h>
28 #include "sdhci-pltfm.h"
29 #include "sdhci-esdhc.h"
30 #include "cqhci.h"
31 
32 #define ESDHC_SYS_CTRL_DTOCV_MASK	0x0f
33 #define	ESDHC_CTRL_D3CD			0x08
34 #define ESDHC_BURST_LEN_EN_INCR		(1 << 27)
35 /* VENDOR SPEC register */
36 #define ESDHC_VENDOR_SPEC		0xc0
37 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK	(1 << 1)
38 #define  ESDHC_VENDOR_SPEC_VSELECT	(1 << 1)
39 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON	(1 << 8)
40 #define ESDHC_DEBUG_SEL_AND_STATUS_REG		0xc2
41 #define ESDHC_DEBUG_SEL_REG			0xc3
42 #define ESDHC_DEBUG_SEL_MASK			0xf
43 #define ESDHC_DEBUG_SEL_CMD_STATE		1
44 #define ESDHC_DEBUG_SEL_DATA_STATE		2
45 #define ESDHC_DEBUG_SEL_TRANS_STATE		3
46 #define ESDHC_DEBUG_SEL_DMA_STATE		4
47 #define ESDHC_DEBUG_SEL_ADMA_STATE		5
48 #define ESDHC_DEBUG_SEL_FIFO_STATE		6
49 #define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE	7
50 #define ESDHC_WTMK_LVL			0x44
51 #define  ESDHC_WTMK_DEFAULT_VAL		0x10401040
52 #define  ESDHC_WTMK_LVL_RD_WML_MASK	0x000000FF
53 #define  ESDHC_WTMK_LVL_RD_WML_SHIFT	0
54 #define  ESDHC_WTMK_LVL_WR_WML_MASK	0x00FF0000
55 #define  ESDHC_WTMK_LVL_WR_WML_SHIFT	16
56 #define  ESDHC_WTMK_LVL_WML_VAL_DEF	64
57 #define  ESDHC_WTMK_LVL_WML_VAL_MAX	128
58 #define ESDHC_MIX_CTRL			0x48
59 #define  ESDHC_MIX_CTRL_DDREN		(1 << 3)
60 #define  ESDHC_MIX_CTRL_AC23EN		(1 << 7)
61 #define  ESDHC_MIX_CTRL_EXE_TUNE	(1 << 22)
62 #define  ESDHC_MIX_CTRL_SMPCLK_SEL	(1 << 23)
63 #define  ESDHC_MIX_CTRL_AUTO_TUNE_EN	(1 << 24)
64 #define  ESDHC_MIX_CTRL_FBCLK_SEL	(1 << 25)
65 #define  ESDHC_MIX_CTRL_HS400_EN	(1 << 26)
66 #define  ESDHC_MIX_CTRL_HS400_ES_EN	(1 << 27)
67 /* Bits 3 and 6 are not SDHCI standard definitions */
68 #define  ESDHC_MIX_CTRL_SDHCI_MASK	0xb7
69 /* Tuning bits */
70 #define  ESDHC_MIX_CTRL_TUNING_MASK	0x03c00000
71 
72 /* dll control register */
73 #define ESDHC_DLL_CTRL			0x60
74 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT	9
75 #define ESDHC_DLL_OVERRIDE_EN_SHIFT	8
76 
77 /* tune control register */
78 #define ESDHC_TUNE_CTRL_STATUS		0x68
79 #define  ESDHC_TUNE_CTRL_STEP		1
80 #define  ESDHC_TUNE_CTRL_MIN		0
81 #define  ESDHC_TUNE_CTRL_MAX		((1 << 7) - 1)
82 
83 /* strobe dll register */
84 #define ESDHC_STROBE_DLL_CTRL		0x70
85 #define ESDHC_STROBE_DLL_CTRL_ENABLE	(1 << 0)
86 #define ESDHC_STROBE_DLL_CTRL_RESET	(1 << 1)
87 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT	0x7
88 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT	3
89 #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT	(4 << 20)
90 
91 #define ESDHC_STROBE_DLL_STATUS		0x74
92 #define ESDHC_STROBE_DLL_STS_REF_LOCK	(1 << 1)
93 #define ESDHC_STROBE_DLL_STS_SLV_LOCK	0x1
94 
95 #define ESDHC_VEND_SPEC2		0xc8
96 #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ	(1 << 8)
97 #define ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN	(1 << 4)
98 #define ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN	(0 << 4)
99 #define ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN	(2 << 4)
100 #define ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN	(1 << 6)
101 #define ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK	(7 << 4)
102 
103 #define ESDHC_TUNING_CTRL		0xcc
104 #define ESDHC_STD_TUNING_EN		(1 << 24)
105 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
106 #define ESDHC_TUNING_START_TAP_DEFAULT	0x1
107 #define ESDHC_TUNING_START_TAP_MASK	0x7f
108 #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE	(1 << 7)
109 #define ESDHC_TUNING_STEP_MASK		0x00070000
110 #define ESDHC_TUNING_STEP_SHIFT		16
111 
112 /* pinctrl state */
113 #define ESDHC_PINCTRL_STATE_100MHZ	"state_100mhz"
114 #define ESDHC_PINCTRL_STATE_200MHZ	"state_200mhz"
115 
116 /*
117  * Our interpretation of the SDHCI_HOST_CONTROL register
118  */
119 #define ESDHC_CTRL_4BITBUS		(0x1 << 1)
120 #define ESDHC_CTRL_8BITBUS		(0x2 << 1)
121 #define ESDHC_CTRL_BUSWIDTH_MASK	(0x3 << 1)
122 #define USDHC_GET_BUSWIDTH(c) (c & ESDHC_CTRL_BUSWIDTH_MASK)
123 
124 /*
125  * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
126  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
127  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
128  * Define this macro DMA error INT for fsl eSDHC
129  */
130 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR	(1 << 28)
131 
132 /* the address offset of CQHCI */
133 #define ESDHC_CQHCI_ADDR_OFFSET		0x100
134 
135 /*
136  * The CMDTYPE of the CMD register (offset 0xE) should be set to
137  * "11" when the STOP CMD12 is issued on imx53 to abort one
138  * open ended multi-blk IO. Otherwise the TC INT wouldn't
139  * be generated.
140  * In exact block transfer, the controller doesn't complete the
141  * operations automatically as required at the end of the
142  * transfer and remains on hold if the abort command is not sent.
143  * As a result, the TC flag is not asserted and SW received timeout
144  * exception. Bit1 of Vendor Spec register is used to fix it.
145  */
146 #define ESDHC_FLAG_MULTIBLK_NO_INT	BIT(1)
147 /*
148  * The flag tells that the ESDHC controller is an USDHC block that is
149  * integrated on the i.MX6 series.
150  */
151 #define ESDHC_FLAG_USDHC		BIT(3)
152 /* The IP supports manual tuning process */
153 #define ESDHC_FLAG_MAN_TUNING		BIT(4)
154 /* The IP supports standard tuning process */
155 #define ESDHC_FLAG_STD_TUNING		BIT(5)
156 /* The IP has SDHCI_CAPABILITIES_1 register */
157 #define ESDHC_FLAG_HAVE_CAP1		BIT(6)
158 /*
159  * The IP has erratum ERR004536
160  * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
161  * when reading data from the card
162  * This flag is also set for i.MX25 and i.MX35 in order to get
163  * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
164  */
165 #define ESDHC_FLAG_ERR004536		BIT(7)
166 /* The IP supports HS200 mode */
167 #define ESDHC_FLAG_HS200		BIT(8)
168 /* The IP supports HS400 mode */
169 #define ESDHC_FLAG_HS400		BIT(9)
170 /*
171  * The IP has errata ERR010450
172  * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
173  * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
174  */
175 #define ESDHC_FLAG_ERR010450		BIT(10)
176 /* The IP supports HS400ES mode */
177 #define ESDHC_FLAG_HS400_ES		BIT(11)
178 /* The IP has Host Controller Interface for Command Queuing */
179 #define ESDHC_FLAG_CQHCI		BIT(12)
180 /* need request pmqos during low power */
181 #define ESDHC_FLAG_PMQOS		BIT(13)
182 /* The IP state got lost in low power mode */
183 #define ESDHC_FLAG_STATE_LOST_IN_LPMODE		BIT(14)
184 /* The IP lost clock rate in PM_RUNTIME */
185 #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME	BIT(15)
186 /*
187  * The IP do not support the ACMD23 feature completely when use ADMA mode.
188  * In ADMA mode, it only use the 16 bit block count of the register 0x4
189  * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will
190  * ignore the upper 16 bit of the CMD23's argument. This will block the reliable
191  * write operation in RPMB, because RPMB reliable write need to set the bit31
192  * of the CMD23's argument.
193  * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA
194  * do not has this limitation. so when these SoC use ADMA mode, it need to
195  * disable the ACMD23 feature.
196  */
197 #define ESDHC_FLAG_BROKEN_AUTO_CMD23	BIT(16)
198 
199 /* ERR004536 is not applicable for the IP  */
200 #define ESDHC_FLAG_SKIP_ERR004536	BIT(17)
201 
202 enum wp_types {
203 	ESDHC_WP_NONE,		/* no WP, neither controller nor gpio */
204 	ESDHC_WP_CONTROLLER,	/* mmc controller internal WP */
205 	ESDHC_WP_GPIO,		/* external gpio pin for WP */
206 };
207 
208 enum cd_types {
209 	ESDHC_CD_NONE,		/* no CD, neither controller nor gpio */
210 	ESDHC_CD_CONTROLLER,	/* mmc controller internal CD */
211 	ESDHC_CD_GPIO,		/* external gpio pin for CD */
212 	ESDHC_CD_PERMANENT,	/* no CD, card permanently wired to host */
213 };
214 
215 /*
216  * struct esdhc_platform_data - platform data for esdhc on i.MX
217  *
218  * ESDHC_WP(CD)_CONTROLLER type is not available on i.MX25/35.
219  *
220  * @wp_type:	type of write_protect method (see wp_types enum above)
221  * @cd_type:	type of card_detect method (see cd_types enum above)
222  */
223 
224 struct esdhc_platform_data {
225 	enum wp_types wp_type;
226 	enum cd_types cd_type;
227 	int max_bus_width;
228 	unsigned int delay_line;
229 	unsigned int tuning_step;       /* The delay cell steps in tuning procedure */
230 	unsigned int tuning_start_tap;	/* The start delay cell point in tuning procedure */
231 	unsigned int strobe_dll_delay_target;	/* The delay cell for strobe pad (read clock) */
232 };
233 
234 struct esdhc_soc_data {
235 	u32 flags;
236 };
237 
238 static const struct esdhc_soc_data esdhc_imx25_data = {
239 	.flags = ESDHC_FLAG_ERR004536,
240 };
241 
242 static const struct esdhc_soc_data esdhc_imx35_data = {
243 	.flags = ESDHC_FLAG_ERR004536,
244 };
245 
246 static const struct esdhc_soc_data esdhc_imx51_data = {
247 	.flags = 0,
248 };
249 
250 static const struct esdhc_soc_data esdhc_imx53_data = {
251 	.flags = ESDHC_FLAG_MULTIBLK_NO_INT,
252 };
253 
254 static const struct esdhc_soc_data usdhc_imx6q_data = {
255 	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
256 			| ESDHC_FLAG_BROKEN_AUTO_CMD23,
257 };
258 
259 static const struct esdhc_soc_data usdhc_imx6sl_data = {
260 	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
261 			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
262 			| ESDHC_FLAG_HS200
263 			| ESDHC_FLAG_BROKEN_AUTO_CMD23,
264 };
265 
266 static const struct esdhc_soc_data usdhc_imx6sll_data = {
267 	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
268 			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
269 			| ESDHC_FLAG_HS400
270 			| ESDHC_FLAG_STATE_LOST_IN_LPMODE,
271 };
272 
273 static const struct esdhc_soc_data usdhc_imx6sx_data = {
274 	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
275 			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
276 			| ESDHC_FLAG_STATE_LOST_IN_LPMODE
277 			| ESDHC_FLAG_BROKEN_AUTO_CMD23,
278 };
279 
280 static const struct esdhc_soc_data usdhc_imx6ull_data = {
281 	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
282 			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
283 			| ESDHC_FLAG_ERR010450
284 			| ESDHC_FLAG_STATE_LOST_IN_LPMODE,
285 };
286 
287 static const struct esdhc_soc_data usdhc_imx7d_data = {
288 	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
289 			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
290 			| ESDHC_FLAG_HS400
291 			| ESDHC_FLAG_STATE_LOST_IN_LPMODE
292 			| ESDHC_FLAG_BROKEN_AUTO_CMD23,
293 };
294 
295 static struct esdhc_soc_data usdhc_s32g2_data = {
296 	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
297 			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
298 			| ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
299 			| ESDHC_FLAG_SKIP_ERR004536,
300 };
301 
302 static struct esdhc_soc_data usdhc_imx7ulp_data = {
303 	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
304 			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
305 			| ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400
306 			| ESDHC_FLAG_STATE_LOST_IN_LPMODE,
307 };
308 
309 static struct esdhc_soc_data usdhc_imx8qxp_data = {
310 	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
311 			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
312 			| ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
313 			| ESDHC_FLAG_CQHCI
314 			| ESDHC_FLAG_STATE_LOST_IN_LPMODE
315 			| ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME,
316 };
317 
318 static struct esdhc_soc_data usdhc_imx8mm_data = {
319 	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
320 			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
321 			| ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
322 			| ESDHC_FLAG_CQHCI
323 			| ESDHC_FLAG_STATE_LOST_IN_LPMODE,
324 };
325 
326 struct pltfm_imx_data {
327 	u32 scratchpad;
328 	struct pinctrl *pinctrl;
329 	struct pinctrl_state *pins_100mhz;
330 	struct pinctrl_state *pins_200mhz;
331 	const struct esdhc_soc_data *socdata;
332 	struct esdhc_platform_data boarddata;
333 	struct clk *clk_ipg;
334 	struct clk *clk_ahb;
335 	struct clk *clk_per;
336 	unsigned int actual_clock;
337 	enum {
338 		NO_CMD_PENDING,      /* no multiblock command pending */
339 		MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
340 		WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
341 	} multiblock_status;
342 	u32 is_ddr;
343 	struct pm_qos_request pm_qos_req;
344 };
345 
346 static const struct of_device_id imx_esdhc_dt_ids[] = {
347 	{ .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
348 	{ .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
349 	{ .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
350 	{ .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
351 	{ .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
352 	{ .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
353 	{ .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
354 	{ .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
355 	{ .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
356 	{ .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
357 	{ .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
358 	{ .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
359 	{ .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
360 	{ .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, },
361 	{ /* sentinel */ }
362 };
363 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
364 
365 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
366 {
367 	return data->socdata == &esdhc_imx25_data;
368 }
369 
370 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
371 {
372 	return data->socdata == &esdhc_imx53_data;
373 }
374 
375 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
376 {
377 	return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
378 }
379 
380 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
381 {
382 	void __iomem *base = host->ioaddr + (reg & ~0x3);
383 	u32 shift = (reg & 0x3) * 8;
384 
385 	writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
386 }
387 
388 #define DRIVER_NAME "sdhci-esdhc-imx"
389 #define ESDHC_IMX_DUMP(f, x...) \
390 	pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
391 static void esdhc_dump_debug_regs(struct sdhci_host *host)
392 {
393 	int i;
394 	char *debug_status[7] = {
395 				 "cmd debug status",
396 				 "data debug status",
397 				 "trans debug status",
398 				 "dma debug status",
399 				 "adma debug status",
400 				 "fifo debug status",
401 				 "async fifo debug status"
402 	};
403 
404 	ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n");
405 	for (i = 0; i < 7; i++) {
406 		esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK,
407 			ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG);
408 		ESDHC_IMX_DUMP("%s:  0x%04x\n", debug_status[i],
409 			readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG));
410 	}
411 
412 	esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG);
413 
414 }
415 
416 static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host)
417 {
418 	u32 present_state;
419 	int ret;
420 
421 	ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state,
422 				(present_state & ESDHC_CLOCK_GATE_OFF), 2, 100);
423 	if (ret == -ETIMEDOUT)
424 		dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__);
425 }
426 
427 /* Enable the auto tuning circuit to check the CMD line and BUS line */
428 static inline void usdhc_auto_tuning_mode_sel(struct sdhci_host *host)
429 {
430 	u32 buswidth, auto_tune_buswidth;
431 
432 	buswidth = USDHC_GET_BUSWIDTH(readl(host->ioaddr + SDHCI_HOST_CONTROL));
433 
434 	switch (buswidth) {
435 	case ESDHC_CTRL_8BITBUS:
436 		auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN;
437 		break;
438 	case ESDHC_CTRL_4BITBUS:
439 		auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN;
440 		break;
441 	default:	/* 1BITBUS */
442 		auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN;
443 		break;
444 	}
445 
446 	esdhc_clrset_le(host, ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK,
447 			auto_tune_buswidth | ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN,
448 			ESDHC_VEND_SPEC2);
449 }
450 
451 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
452 {
453 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
454 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
455 	u32 val = readl(host->ioaddr + reg);
456 
457 	if (unlikely(reg == SDHCI_PRESENT_STATE)) {
458 		u32 fsl_prss = val;
459 		/* save the least 20 bits */
460 		val = fsl_prss & 0x000FFFFF;
461 		/* move dat[0-3] bits */
462 		val |= (fsl_prss & 0x0F000000) >> 4;
463 		/* move cmd line bit */
464 		val |= (fsl_prss & 0x00800000) << 1;
465 	}
466 
467 	if (unlikely(reg == SDHCI_CAPABILITIES)) {
468 		/* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
469 		if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
470 			val &= 0xffff0000;
471 
472 		/* In FSL esdhc IC module, only bit20 is used to indicate the
473 		 * ADMA2 capability of esdhc, but this bit is messed up on
474 		 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
475 		 * don't actually support ADMA2). So set the BROKEN_ADMA
476 		 * quirk on MX25/35 platforms.
477 		 */
478 
479 		if (val & SDHCI_CAN_DO_ADMA1) {
480 			val &= ~SDHCI_CAN_DO_ADMA1;
481 			val |= SDHCI_CAN_DO_ADMA2;
482 		}
483 	}
484 
485 	if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
486 		if (esdhc_is_usdhc(imx_data)) {
487 			if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
488 				val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
489 			else
490 				/* imx6q/dl does not have cap_1 register, fake one */
491 				val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
492 					| SDHCI_SUPPORT_SDR50
493 					| SDHCI_USE_SDR50_TUNING
494 					| FIELD_PREP(SDHCI_RETUNING_MODE_MASK,
495 						     SDHCI_TUNING_MODE_3);
496 
497 			/*
498 			 * Do not advertise faster UHS modes if there are no
499 			 * pinctrl states for 100MHz/200MHz.
500 			 */
501 			if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
502 				val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
503 			if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
504 				val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
505 		}
506 	}
507 
508 	if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
509 		val = 0;
510 		val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF);
511 		val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF);
512 		val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF);
513 	}
514 
515 	if (unlikely(reg == SDHCI_INT_STATUS)) {
516 		if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
517 			val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
518 			val |= SDHCI_INT_ADMA_ERROR;
519 		}
520 
521 		/*
522 		 * mask off the interrupt we get in response to the manually
523 		 * sent CMD12
524 		 */
525 		if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
526 		    ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
527 			val &= ~SDHCI_INT_RESPONSE;
528 			writel(SDHCI_INT_RESPONSE, host->ioaddr +
529 						   SDHCI_INT_STATUS);
530 			imx_data->multiblock_status = NO_CMD_PENDING;
531 		}
532 	}
533 
534 	return val;
535 }
536 
537 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
538 {
539 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
540 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
541 	u32 data;
542 
543 	if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
544 			reg == SDHCI_INT_STATUS)) {
545 		if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
546 			/*
547 			 * Clear and then set D3CD bit to avoid missing the
548 			 * card interrupt. This is an eSDHC controller problem
549 			 * so we need to apply the following workaround: clear
550 			 * and set D3CD bit will make eSDHC re-sample the card
551 			 * interrupt. In case a card interrupt was lost,
552 			 * re-sample it by the following steps.
553 			 */
554 			data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
555 			data &= ~ESDHC_CTRL_D3CD;
556 			writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
557 			data |= ESDHC_CTRL_D3CD;
558 			writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
559 		}
560 
561 		if (val & SDHCI_INT_ADMA_ERROR) {
562 			val &= ~SDHCI_INT_ADMA_ERROR;
563 			val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
564 		}
565 	}
566 
567 	if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
568 				&& (reg == SDHCI_INT_STATUS)
569 				&& (val & SDHCI_INT_DATA_END))) {
570 			u32 v;
571 			v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
572 			v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
573 			writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
574 
575 			if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
576 			{
577 				/* send a manual CMD12 with RESPTYP=none */
578 				data = MMC_STOP_TRANSMISSION << 24 |
579 				       SDHCI_CMD_ABORTCMD << 16;
580 				writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
581 				imx_data->multiblock_status = WAIT_FOR_INT;
582 			}
583 	}
584 
585 	writel(val, host->ioaddr + reg);
586 }
587 
588 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
589 {
590 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
591 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
592 	u16 ret = 0;
593 	u32 val;
594 
595 	if (unlikely(reg == SDHCI_HOST_VERSION)) {
596 		reg ^= 2;
597 		if (esdhc_is_usdhc(imx_data)) {
598 			/*
599 			 * The usdhc register returns a wrong host version.
600 			 * Correct it here.
601 			 */
602 			return SDHCI_SPEC_300;
603 		}
604 	}
605 
606 	if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
607 		val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
608 		if (val & ESDHC_VENDOR_SPEC_VSELECT)
609 			ret |= SDHCI_CTRL_VDD_180;
610 
611 		if (esdhc_is_usdhc(imx_data)) {
612 			if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
613 				val = readl(host->ioaddr + ESDHC_MIX_CTRL);
614 			else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
615 				/* the std tuning bits is in ACMD12_ERR for imx6sl */
616 				val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
617 		}
618 
619 		if (val & ESDHC_MIX_CTRL_EXE_TUNE)
620 			ret |= SDHCI_CTRL_EXEC_TUNING;
621 		if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
622 			ret |= SDHCI_CTRL_TUNED_CLK;
623 
624 		ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
625 
626 		return ret;
627 	}
628 
629 	if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
630 		if (esdhc_is_usdhc(imx_data)) {
631 			u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
632 			ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
633 			/* Swap AC23 bit */
634 			if (m & ESDHC_MIX_CTRL_AC23EN) {
635 				ret &= ~ESDHC_MIX_CTRL_AC23EN;
636 				ret |= SDHCI_TRNS_AUTO_CMD23;
637 			}
638 		} else {
639 			ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
640 		}
641 
642 		return ret;
643 	}
644 
645 	return readw(host->ioaddr + reg);
646 }
647 
648 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
649 {
650 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
651 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
652 	u32 new_val = 0;
653 
654 	switch (reg) {
655 	case SDHCI_CLOCK_CONTROL:
656 		new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
657 		if (val & SDHCI_CLOCK_CARD_EN)
658 			new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
659 		else
660 			new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
661 		writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
662 		if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON))
663 			esdhc_wait_for_card_clock_gate_off(host);
664 		return;
665 	case SDHCI_HOST_CONTROL2:
666 		new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
667 		if (val & SDHCI_CTRL_VDD_180)
668 			new_val |= ESDHC_VENDOR_SPEC_VSELECT;
669 		else
670 			new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
671 		writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
672 		if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
673 			u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
674 			u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
675 			if (val & SDHCI_CTRL_TUNED_CLK) {
676 				v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
677 			} else {
678 				v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
679 				m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
680 				m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
681 			}
682 
683 			if (val & SDHCI_CTRL_EXEC_TUNING) {
684 				v |= ESDHC_MIX_CTRL_EXE_TUNE;
685 				m |= ESDHC_MIX_CTRL_FBCLK_SEL;
686 				m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
687 				usdhc_auto_tuning_mode_sel(host);
688 			} else {
689 				v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
690 			}
691 
692 			writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
693 			writel(m, host->ioaddr + ESDHC_MIX_CTRL);
694 		}
695 		return;
696 	case SDHCI_TRANSFER_MODE:
697 		if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
698 				&& (host->cmd->opcode == SD_IO_RW_EXTENDED)
699 				&& (host->cmd->data->blocks > 1)
700 				&& (host->cmd->data->flags & MMC_DATA_READ)) {
701 			u32 v;
702 			v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
703 			v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
704 			writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
705 		}
706 
707 		if (esdhc_is_usdhc(imx_data)) {
708 			u32 wml;
709 			u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
710 			/* Swap AC23 bit */
711 			if (val & SDHCI_TRNS_AUTO_CMD23) {
712 				val &= ~SDHCI_TRNS_AUTO_CMD23;
713 				val |= ESDHC_MIX_CTRL_AC23EN;
714 			}
715 			m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
716 			writel(m, host->ioaddr + ESDHC_MIX_CTRL);
717 
718 			/* Set watermark levels for PIO access to maximum value
719 			 * (128 words) to accommodate full 512 bytes buffer.
720 			 * For DMA access restore the levels to default value.
721 			 */
722 			m = readl(host->ioaddr + ESDHC_WTMK_LVL);
723 			if (val & SDHCI_TRNS_DMA) {
724 				wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
725 			} else {
726 				u8 ctrl;
727 				wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
728 
729 				/*
730 				 * Since already disable DMA mode, so also need
731 				 * to clear the DMASEL. Otherwise, for standard
732 				 * tuning, when send tuning command, usdhc will
733 				 * still prefetch the ADMA script from wrong
734 				 * DMA address, then we will see IOMMU report
735 				 * some error which show lack of TLB mapping.
736 				 */
737 				ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
738 				ctrl &= ~SDHCI_CTRL_DMA_MASK;
739 				sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
740 			}
741 			m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
742 			       ESDHC_WTMK_LVL_WR_WML_MASK);
743 			m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
744 			     (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
745 			writel(m, host->ioaddr + ESDHC_WTMK_LVL);
746 		} else {
747 			/*
748 			 * Postpone this write, we must do it together with a
749 			 * command write that is down below.
750 			 */
751 			imx_data->scratchpad = val;
752 		}
753 		return;
754 	case SDHCI_COMMAND:
755 		if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
756 			val |= SDHCI_CMD_ABORTCMD;
757 
758 		if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
759 		    (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
760 			imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
761 
762 		if (esdhc_is_usdhc(imx_data))
763 			writel(val << 16,
764 			       host->ioaddr + SDHCI_TRANSFER_MODE);
765 		else
766 			writel(val << 16 | imx_data->scratchpad,
767 			       host->ioaddr + SDHCI_TRANSFER_MODE);
768 		return;
769 	case SDHCI_BLOCK_SIZE:
770 		val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
771 		break;
772 	}
773 	esdhc_clrset_le(host, 0xffff, val, reg);
774 }
775 
776 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
777 {
778 	u8 ret;
779 	u32 val;
780 
781 	switch (reg) {
782 	case SDHCI_HOST_CONTROL:
783 		val = readl(host->ioaddr + reg);
784 
785 		ret = val & SDHCI_CTRL_LED;
786 		ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
787 		ret |= (val & ESDHC_CTRL_4BITBUS);
788 		ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
789 		return ret;
790 	}
791 
792 	return readb(host->ioaddr + reg);
793 }
794 
795 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
796 {
797 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
798 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
799 	u32 new_val = 0;
800 	u32 mask;
801 
802 	switch (reg) {
803 	case SDHCI_POWER_CONTROL:
804 		/*
805 		 * FSL put some DMA bits here
806 		 * If your board has a regulator, code should be here
807 		 */
808 		return;
809 	case SDHCI_HOST_CONTROL:
810 		/* FSL messed up here, so we need to manually compose it. */
811 		new_val = val & SDHCI_CTRL_LED;
812 		/* ensure the endianness */
813 		new_val |= ESDHC_HOST_CONTROL_LE;
814 		/* bits 8&9 are reserved on mx25 */
815 		if (!is_imx25_esdhc(imx_data)) {
816 			/* DMA mode bits are shifted */
817 			new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
818 		}
819 
820 		/*
821 		 * Do not touch buswidth bits here. This is done in
822 		 * esdhc_pltfm_bus_width.
823 		 * Do not touch the D3CD bit either which is used for the
824 		 * SDIO interrupt erratum workaround.
825 		 */
826 		mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
827 
828 		esdhc_clrset_le(host, mask, new_val, reg);
829 		return;
830 	case SDHCI_SOFTWARE_RESET:
831 		if (val & SDHCI_RESET_DATA)
832 			new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
833 		break;
834 	}
835 	esdhc_clrset_le(host, 0xff, val, reg);
836 
837 	if (reg == SDHCI_SOFTWARE_RESET) {
838 		if (val & SDHCI_RESET_ALL) {
839 			/*
840 			 * The esdhc has a design violation to SDHC spec which
841 			 * tells that software reset should not affect card
842 			 * detection circuit. But esdhc clears its SYSCTL
843 			 * register bits [0..2] during the software reset. This
844 			 * will stop those clocks that card detection circuit
845 			 * relies on. To work around it, we turn the clocks on
846 			 * back to keep card detection circuit functional.
847 			 */
848 			esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
849 			/*
850 			 * The reset on usdhc fails to clear MIX_CTRL register.
851 			 * Do it manually here.
852 			 */
853 			if (esdhc_is_usdhc(imx_data)) {
854 				/*
855 				 * the tuning bits should be kept during reset
856 				 */
857 				new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
858 				writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
859 						host->ioaddr + ESDHC_MIX_CTRL);
860 				imx_data->is_ddr = 0;
861 			}
862 		} else if (val & SDHCI_RESET_DATA) {
863 			/*
864 			 * The eSDHC DAT line software reset clears at least the
865 			 * data transfer width on i.MX25, so make sure that the
866 			 * Host Control register is unaffected.
867 			 */
868 			esdhc_clrset_le(host, 0xff, new_val,
869 					SDHCI_HOST_CONTROL);
870 		}
871 	}
872 }
873 
874 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
875 {
876 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
877 
878 	return pltfm_host->clock;
879 }
880 
881 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
882 {
883 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
884 
885 	return pltfm_host->clock / 256 / 16;
886 }
887 
888 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
889 					 unsigned int clock)
890 {
891 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
892 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
893 	unsigned int host_clock = pltfm_host->clock;
894 	int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
895 	int pre_div = 1;
896 	int div = 1;
897 	int ret;
898 	u32 temp, val;
899 
900 	if (esdhc_is_usdhc(imx_data)) {
901 		val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
902 		writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
903 			host->ioaddr + ESDHC_VENDOR_SPEC);
904 		esdhc_wait_for_card_clock_gate_off(host);
905 	}
906 
907 	if (clock == 0) {
908 		host->mmc->actual_clock = 0;
909 		return;
910 	}
911 
912 	/* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
913 	if (is_imx53_esdhc(imx_data)) {
914 		/*
915 		 * According to the i.MX53 reference manual, if DLLCTRL[10] can
916 		 * be set, then the controller is eSDHCv3, else it is eSDHCv2.
917 		 */
918 		val = readl(host->ioaddr + ESDHC_DLL_CTRL);
919 		writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
920 		temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
921 		writel(val, host->ioaddr + ESDHC_DLL_CTRL);
922 		if (temp & BIT(10))
923 			pre_div = 2;
924 	}
925 
926 	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
927 	temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
928 		| ESDHC_CLOCK_MASK);
929 	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
930 
931 	if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
932 		unsigned int max_clock;
933 
934 		max_clock = imx_data->is_ddr ? 45000000 : 150000000;
935 
936 		clock = min(clock, max_clock);
937 	}
938 
939 	while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
940 			pre_div < 256)
941 		pre_div *= 2;
942 
943 	while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
944 		div++;
945 
946 	host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
947 	dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
948 		clock, host->mmc->actual_clock);
949 
950 	pre_div >>= 1;
951 	div--;
952 
953 	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
954 	temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
955 		| (div << ESDHC_DIVIDER_SHIFT)
956 		| (pre_div << ESDHC_PREDIV_SHIFT));
957 	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
958 
959 	/* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */
960 	ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp,
961 				(temp & ESDHC_CLOCK_STABLE), 2, 100);
962 	if (ret == -ETIMEDOUT)
963 		dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n");
964 
965 	if (esdhc_is_usdhc(imx_data)) {
966 		val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
967 		writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
968 			host->ioaddr + ESDHC_VENDOR_SPEC);
969 	}
970 
971 }
972 
973 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
974 {
975 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
976 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
977 	struct esdhc_platform_data *boarddata = &imx_data->boarddata;
978 
979 	switch (boarddata->wp_type) {
980 	case ESDHC_WP_GPIO:
981 		return mmc_gpio_get_ro(host->mmc);
982 	case ESDHC_WP_CONTROLLER:
983 		return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
984 			       SDHCI_WRITE_PROTECT);
985 	case ESDHC_WP_NONE:
986 		break;
987 	}
988 
989 	return -ENOSYS;
990 }
991 
992 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
993 {
994 	u32 ctrl;
995 
996 	switch (width) {
997 	case MMC_BUS_WIDTH_8:
998 		ctrl = ESDHC_CTRL_8BITBUS;
999 		break;
1000 	case MMC_BUS_WIDTH_4:
1001 		ctrl = ESDHC_CTRL_4BITBUS;
1002 		break;
1003 	default:
1004 		ctrl = 0;
1005 		break;
1006 	}
1007 
1008 	esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
1009 			SDHCI_HOST_CONTROL);
1010 }
1011 
1012 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1013 {
1014 	struct sdhci_host *host = mmc_priv(mmc);
1015 
1016 	/*
1017 	 * i.MX uSDHC internally already uses a fixed optimized timing for
1018 	 * DDR50, normally does not require tuning for DDR50 mode.
1019 	 */
1020 	if (host->timing == MMC_TIMING_UHS_DDR50)
1021 		return 0;
1022 
1023 	return sdhci_execute_tuning(mmc, opcode);
1024 }
1025 
1026 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
1027 {
1028 	u32 reg;
1029 	u8 sw_rst;
1030 	int ret;
1031 
1032 	/* FIXME: delay a bit for card to be ready for next tuning due to errors */
1033 	mdelay(1);
1034 
1035 	/* IC suggest to reset USDHC before every tuning command */
1036 	esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
1037 	ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst,
1038 				!(sw_rst & SDHCI_RESET_ALL), 10, 100);
1039 	if (ret == -ETIMEDOUT)
1040 		dev_warn(mmc_dev(host->mmc),
1041 		"warning! RESET_ALL never complete before sending tuning command\n");
1042 
1043 	reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1044 	reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
1045 			ESDHC_MIX_CTRL_FBCLK_SEL;
1046 	writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1047 	writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1048 	dev_dbg(mmc_dev(host->mmc),
1049 		"tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
1050 			val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
1051 }
1052 
1053 static void esdhc_post_tuning(struct sdhci_host *host)
1054 {
1055 	u32 reg;
1056 
1057 	usdhc_auto_tuning_mode_sel(host);
1058 
1059 	reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1060 	reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1061 	reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
1062 	writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1063 }
1064 
1065 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
1066 {
1067 	int min, max, avg, ret;
1068 
1069 	/* find the mininum delay first which can pass tuning */
1070 	min = ESDHC_TUNE_CTRL_MIN;
1071 	while (min < ESDHC_TUNE_CTRL_MAX) {
1072 		esdhc_prepare_tuning(host, min);
1073 		if (!mmc_send_tuning(host->mmc, opcode, NULL))
1074 			break;
1075 		min += ESDHC_TUNE_CTRL_STEP;
1076 	}
1077 
1078 	/* find the maxinum delay which can not pass tuning */
1079 	max = min + ESDHC_TUNE_CTRL_STEP;
1080 	while (max < ESDHC_TUNE_CTRL_MAX) {
1081 		esdhc_prepare_tuning(host, max);
1082 		if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1083 			max -= ESDHC_TUNE_CTRL_STEP;
1084 			break;
1085 		}
1086 		max += ESDHC_TUNE_CTRL_STEP;
1087 	}
1088 
1089 	/* use average delay to get the best timing */
1090 	avg = (min + max) / 2;
1091 	esdhc_prepare_tuning(host, avg);
1092 	ret = mmc_send_tuning(host->mmc, opcode, NULL);
1093 	esdhc_post_tuning(host);
1094 
1095 	dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
1096 		ret ? "failed" : "passed", avg, ret);
1097 
1098 	return ret;
1099 }
1100 
1101 static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
1102 {
1103 	struct sdhci_host *host = mmc_priv(mmc);
1104 	u32 m;
1105 
1106 	m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1107 	if (ios->enhanced_strobe)
1108 		m |= ESDHC_MIX_CTRL_HS400_ES_EN;
1109 	else
1110 		m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
1111 	writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1112 }
1113 
1114 static int esdhc_change_pinstate(struct sdhci_host *host,
1115 						unsigned int uhs)
1116 {
1117 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1118 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1119 	struct pinctrl_state *pinctrl;
1120 
1121 	dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
1122 
1123 	if (IS_ERR(imx_data->pinctrl) ||
1124 		IS_ERR(imx_data->pins_100mhz) ||
1125 		IS_ERR(imx_data->pins_200mhz))
1126 		return -EINVAL;
1127 
1128 	switch (uhs) {
1129 	case MMC_TIMING_UHS_SDR50:
1130 	case MMC_TIMING_UHS_DDR50:
1131 		pinctrl = imx_data->pins_100mhz;
1132 		break;
1133 	case MMC_TIMING_UHS_SDR104:
1134 	case MMC_TIMING_MMC_HS200:
1135 	case MMC_TIMING_MMC_HS400:
1136 		pinctrl = imx_data->pins_200mhz;
1137 		break;
1138 	default:
1139 		/* back to default state for other legacy timing */
1140 		return pinctrl_select_default_state(mmc_dev(host->mmc));
1141 	}
1142 
1143 	return pinctrl_select_state(imx_data->pinctrl, pinctrl);
1144 }
1145 
1146 /*
1147  * For HS400 eMMC, there is a data_strobe line. This signal is generated
1148  * by the device and used for data output and CRC status response output
1149  * in HS400 mode. The frequency of this signal follows the frequency of
1150  * CLK generated by host. The host receives the data which is aligned to the
1151  * edge of data_strobe line. Due to the time delay between CLK line and
1152  * data_strobe line, if the delay time is larger than one clock cycle,
1153  * then CLK and data_strobe line will be misaligned, read error shows up.
1154  */
1155 static void esdhc_set_strobe_dll(struct sdhci_host *host)
1156 {
1157 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1158 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1159 	u32 strobe_delay;
1160 	u32 v;
1161 	int ret;
1162 
1163 	/* disable clock before enabling strobe dll */
1164 	writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
1165 		~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
1166 		host->ioaddr + ESDHC_VENDOR_SPEC);
1167 	esdhc_wait_for_card_clock_gate_off(host);
1168 
1169 	/* force a reset on strobe dll */
1170 	writel(ESDHC_STROBE_DLL_CTRL_RESET,
1171 		host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1172 	/* clear the reset bit on strobe dll before any setting */
1173 	writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1174 
1175 	/*
1176 	 * enable strobe dll ctrl and adjust the delay target
1177 	 * for the uSDHC loopback read clock
1178 	 */
1179 	if (imx_data->boarddata.strobe_dll_delay_target)
1180 		strobe_delay = imx_data->boarddata.strobe_dll_delay_target;
1181 	else
1182 		strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT;
1183 	v = ESDHC_STROBE_DLL_CTRL_ENABLE |
1184 		ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
1185 		(strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
1186 	writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1187 
1188 	/* wait max 50us to get the REF/SLV lock */
1189 	ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
1190 		((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50);
1191 	if (ret == -ETIMEDOUT)
1192 		dev_warn(mmc_dev(host->mmc),
1193 		"warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v);
1194 }
1195 
1196 static void esdhc_reset_tuning(struct sdhci_host *host)
1197 {
1198 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1199 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1200 	u32 ctrl;
1201 	int ret;
1202 
1203 	/* Reset the tuning circuit */
1204 	if (esdhc_is_usdhc(imx_data)) {
1205 		if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1206 			ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
1207 			ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1208 			ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
1209 			writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1210 			writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1211 		} else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1212 			ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1213 			ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1214 			ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1215 			writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1216 			/* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */
1217 			ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS,
1218 				ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50);
1219 			if (ret == -ETIMEDOUT)
1220 				dev_warn(mmc_dev(host->mmc),
1221 				 "Warning! clear execute tuning bit failed\n");
1222 			/*
1223 			 * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the
1224 			 * usdhc IP internal logic flag execute_tuning_with_clr_buf, which
1225 			 * will finally make sure the normal data transfer logic correct.
1226 			 */
1227 			ctrl = readl(host->ioaddr + SDHCI_INT_STATUS);
1228 			ctrl |= SDHCI_INT_DATA_AVAIL;
1229 			writel(ctrl, host->ioaddr + SDHCI_INT_STATUS);
1230 		}
1231 	}
1232 }
1233 
1234 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1235 {
1236 	u32 m;
1237 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1238 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1239 	struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1240 
1241 	/* disable ddr mode and disable HS400 mode */
1242 	m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1243 	m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
1244 	imx_data->is_ddr = 0;
1245 
1246 	switch (timing) {
1247 	case MMC_TIMING_UHS_SDR12:
1248 	case MMC_TIMING_UHS_SDR25:
1249 	case MMC_TIMING_UHS_SDR50:
1250 	case MMC_TIMING_UHS_SDR104:
1251 	case MMC_TIMING_MMC_HS:
1252 	case MMC_TIMING_MMC_HS200:
1253 		writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1254 		break;
1255 	case MMC_TIMING_UHS_DDR50:
1256 	case MMC_TIMING_MMC_DDR52:
1257 		m |= ESDHC_MIX_CTRL_DDREN;
1258 		writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1259 		imx_data->is_ddr = 1;
1260 		if (boarddata->delay_line) {
1261 			u32 v;
1262 			v = boarddata->delay_line <<
1263 				ESDHC_DLL_OVERRIDE_VAL_SHIFT |
1264 				(1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
1265 			if (is_imx53_esdhc(imx_data))
1266 				v <<= 1;
1267 			writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1268 		}
1269 		break;
1270 	case MMC_TIMING_MMC_HS400:
1271 		m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1272 		writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1273 		imx_data->is_ddr = 1;
1274 		/* update clock after enable DDR for strobe DLL lock */
1275 		host->ops->set_clock(host, host->clock);
1276 		esdhc_set_strobe_dll(host);
1277 		break;
1278 	case MMC_TIMING_LEGACY:
1279 	default:
1280 		esdhc_reset_tuning(host);
1281 		break;
1282 	}
1283 
1284 	esdhc_change_pinstate(host, timing);
1285 }
1286 
1287 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1288 {
1289 	sdhci_reset(host, mask);
1290 
1291 	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1292 	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1293 }
1294 
1295 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1296 {
1297 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1298 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1299 
1300 	/* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1301 	return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1302 }
1303 
1304 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1305 {
1306 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1307 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1308 
1309 	/* use maximum timeout counter */
1310 	esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1311 			esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1312 			SDHCI_TIMEOUT_CONTROL);
1313 }
1314 
1315 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
1316 {
1317 	int cmd_error = 0;
1318 	int data_error = 0;
1319 
1320 	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1321 		return intmask;
1322 
1323 	cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1324 
1325 	return 0;
1326 }
1327 
1328 static struct sdhci_ops sdhci_esdhc_ops = {
1329 	.read_l = esdhc_readl_le,
1330 	.read_w = esdhc_readw_le,
1331 	.read_b = esdhc_readb_le,
1332 	.write_l = esdhc_writel_le,
1333 	.write_w = esdhc_writew_le,
1334 	.write_b = esdhc_writeb_le,
1335 	.set_clock = esdhc_pltfm_set_clock,
1336 	.get_max_clock = esdhc_pltfm_get_max_clock,
1337 	.get_min_clock = esdhc_pltfm_get_min_clock,
1338 	.get_max_timeout_count = esdhc_get_max_timeout_count,
1339 	.get_ro = esdhc_pltfm_get_ro,
1340 	.set_timeout = esdhc_set_timeout,
1341 	.set_bus_width = esdhc_pltfm_set_bus_width,
1342 	.set_uhs_signaling = esdhc_set_uhs_signaling,
1343 	.reset = esdhc_reset,
1344 	.irq = esdhc_cqhci_irq,
1345 	.dump_vendor_regs = esdhc_dump_debug_regs,
1346 };
1347 
1348 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1349 	.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1350 			| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1351 			| SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1352 			| SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1353 	.ops = &sdhci_esdhc_ops,
1354 };
1355 
1356 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1357 {
1358 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1359 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1360 	struct cqhci_host *cq_host = host->mmc->cqe_private;
1361 	int tmp;
1362 
1363 	if (esdhc_is_usdhc(imx_data)) {
1364 		/*
1365 		 * The imx6q ROM code will change the default watermark
1366 		 * level setting to something insane.  Change it back here.
1367 		 */
1368 		writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1369 
1370 		/*
1371 		 * ROM code will change the bit burst_length_enable setting
1372 		 * to zero if this usdhc is chosen to boot system. Change
1373 		 * it back here, otherwise it will impact the performance a
1374 		 * lot. This bit is used to enable/disable the burst length
1375 		 * for the external AHB2AXI bridge. It's useful especially
1376 		 * for INCR transfer because without burst length indicator,
1377 		 * the AHB2AXI bridge does not know the burst length in
1378 		 * advance. And without burst length indicator, AHB INCR
1379 		 * transfer can only be converted to singles on the AXI side.
1380 		 */
1381 		writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1382 			| ESDHC_BURST_LEN_EN_INCR,
1383 			host->ioaddr + SDHCI_HOST_CONTROL);
1384 
1385 		/*
1386 		 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1387 		 * TO1.1, it's harmless for MX6SL
1388 		 */
1389 		if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_ERR004536)) {
1390 			writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1391 				host->ioaddr + 0x6c);
1392 		}
1393 
1394 		/* disable DLL_CTRL delay line settings */
1395 		writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1396 
1397 		/*
1398 		 * For the case of command with busy, if set the bit
1399 		 * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a
1400 		 * transfer complete interrupt when busy is deasserted.
1401 		 * When CQHCI use DCMD to send a CMD need R1b respons,
1402 		 * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ,
1403 		 * otherwise DCMD will always meet timeout waiting for
1404 		 * hardware interrupt issue.
1405 		 */
1406 		if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1407 			tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
1408 			tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
1409 			writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
1410 
1411 			host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1412 		}
1413 
1414 		if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1415 			tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1416 			tmp |= ESDHC_STD_TUNING_EN |
1417 				ESDHC_TUNING_START_TAP_DEFAULT;
1418 			if (imx_data->boarddata.tuning_start_tap) {
1419 				tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1420 				tmp |= imx_data->boarddata.tuning_start_tap;
1421 			}
1422 
1423 			if (imx_data->boarddata.tuning_step) {
1424 				tmp &= ~ESDHC_TUNING_STEP_MASK;
1425 				tmp |= imx_data->boarddata.tuning_step
1426 					<< ESDHC_TUNING_STEP_SHIFT;
1427 			}
1428 
1429 			/* Disable the CMD CRC check for tuning, if not, need to
1430 			 * add some delay after every tuning command, because
1431 			 * hardware standard tuning logic will directly go to next
1432 			 * step once it detect the CMD CRC error, will not wait for
1433 			 * the card side to finally send out the tuning data, trigger
1434 			 * the buffer read ready interrupt immediately. If usdhc send
1435 			 * the next tuning command some eMMC card will stuck, can't
1436 			 * response, block the tuning procedure or the first command
1437 			 * after the whole tuning procedure always can't get any response.
1438 			 */
1439 			tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
1440 			writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1441 		} else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1442 			/*
1443 			 * ESDHC_STD_TUNING_EN may be configed in bootloader
1444 			 * or ROM code, so clear this bit here to make sure
1445 			 * the manual tuning can work.
1446 			 */
1447 			tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1448 			tmp &= ~ESDHC_STD_TUNING_EN;
1449 			writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1450 		}
1451 
1452 		/*
1453 		 * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card
1454 		 * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let the
1455 		 * the 1st linux configure power/clock for the 2nd Linux.
1456 		 *
1457 		 * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux
1458 		 * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump.
1459 		 * After we clear the pending interrupt and halt CQCTL, issue gone.
1460 		 */
1461 		if (cq_host) {
1462 			tmp = cqhci_readl(cq_host, CQHCI_IS);
1463 			cqhci_writel(cq_host, tmp, CQHCI_IS);
1464 			cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
1465 		}
1466 	}
1467 }
1468 
1469 static void esdhc_cqe_enable(struct mmc_host *mmc)
1470 {
1471 	struct sdhci_host *host = mmc_priv(mmc);
1472 	struct cqhci_host *cq_host = mmc->cqe_private;
1473 	u32 reg;
1474 	u16 mode;
1475 	int count = 10;
1476 
1477 	/*
1478 	 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
1479 	 * the case after tuning, so ensure the buffer is drained.
1480 	 */
1481 	reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1482 	while (reg & SDHCI_DATA_AVAILABLE) {
1483 		sdhci_readl(host, SDHCI_BUFFER);
1484 		reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1485 		if (count-- == 0) {
1486 			dev_warn(mmc_dev(host->mmc),
1487 				"CQE may get stuck because the Buffer Read Enable bit is set\n");
1488 			break;
1489 		}
1490 		mdelay(1);
1491 	}
1492 
1493 	/*
1494 	 * Runtime resume will reset the entire host controller, which
1495 	 * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL.
1496 	 * Here set DMAEN and BCEN when enable CMDQ.
1497 	 */
1498 	mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1499 	if (host->flags & SDHCI_REQ_USE_DMA)
1500 		mode |= SDHCI_TRNS_DMA;
1501 	if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1502 		mode |= SDHCI_TRNS_BLK_CNT_EN;
1503 	sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1504 
1505 	/*
1506 	 * Though Runtime resume reset the entire host controller,
1507 	 * but do not impact the CQHCI side, need to clear the
1508 	 * HALT bit, avoid CQHCI stuck in the first request when
1509 	 * system resume back.
1510 	 */
1511 	cqhci_writel(cq_host, 0, CQHCI_CTL);
1512 	if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT)
1513 		dev_err(mmc_dev(host->mmc),
1514 			"failed to exit halt state when enable CQE\n");
1515 
1516 
1517 	sdhci_cqe_enable(mmc);
1518 }
1519 
1520 static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
1521 {
1522 	sdhci_dumpregs(mmc_priv(mmc));
1523 }
1524 
1525 static const struct cqhci_host_ops esdhc_cqhci_ops = {
1526 	.enable		= esdhc_cqe_enable,
1527 	.disable	= sdhci_cqe_disable,
1528 	.dumpregs	= esdhc_sdhci_dumpregs,
1529 };
1530 
1531 static int
1532 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1533 			 struct sdhci_host *host,
1534 			 struct pltfm_imx_data *imx_data)
1535 {
1536 	struct device_node *np = pdev->dev.of_node;
1537 	struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1538 	int ret;
1539 
1540 	if (of_get_property(np, "fsl,wp-controller", NULL))
1541 		boarddata->wp_type = ESDHC_WP_CONTROLLER;
1542 
1543 	/*
1544 	 * If we have this property, then activate WP check.
1545 	 * Retrieveing and requesting the actual WP GPIO will happen
1546 	 * in the call to mmc_of_parse().
1547 	 */
1548 	if (of_property_read_bool(np, "wp-gpios"))
1549 		boarddata->wp_type = ESDHC_WP_GPIO;
1550 
1551 	of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1552 	of_property_read_u32(np, "fsl,tuning-start-tap",
1553 			     &boarddata->tuning_start_tap);
1554 
1555 	of_property_read_u32(np, "fsl,strobe-dll-delay-target",
1556 				&boarddata->strobe_dll_delay_target);
1557 	if (of_find_property(np, "no-1-8-v", NULL))
1558 		host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1559 
1560 	if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1561 		boarddata->delay_line = 0;
1562 
1563 	mmc_of_parse_voltage(host->mmc, &host->ocr_mask);
1564 
1565 	if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) {
1566 		imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1567 						ESDHC_PINCTRL_STATE_100MHZ);
1568 		imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1569 						ESDHC_PINCTRL_STATE_200MHZ);
1570 	}
1571 
1572 	/* call to generic mmc_of_parse to support additional capabilities */
1573 	ret = mmc_of_parse(host->mmc);
1574 	if (ret)
1575 		return ret;
1576 
1577 	if (mmc_gpio_get_cd(host->mmc) >= 0)
1578 		host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1579 
1580 	return 0;
1581 }
1582 
1583 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1584 {
1585 	struct sdhci_pltfm_host *pltfm_host;
1586 	struct sdhci_host *host;
1587 	struct cqhci_host *cq_host;
1588 	int err;
1589 	struct pltfm_imx_data *imx_data;
1590 
1591 	host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1592 				sizeof(*imx_data));
1593 	if (IS_ERR(host))
1594 		return PTR_ERR(host);
1595 
1596 	pltfm_host = sdhci_priv(host);
1597 
1598 	imx_data = sdhci_pltfm_priv(pltfm_host);
1599 
1600 	imx_data->socdata = device_get_match_data(&pdev->dev);
1601 
1602 	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1603 		cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1604 
1605 	imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1606 	if (IS_ERR(imx_data->clk_ipg)) {
1607 		err = PTR_ERR(imx_data->clk_ipg);
1608 		goto free_sdhci;
1609 	}
1610 
1611 	imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1612 	if (IS_ERR(imx_data->clk_ahb)) {
1613 		err = PTR_ERR(imx_data->clk_ahb);
1614 		goto free_sdhci;
1615 	}
1616 
1617 	imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1618 	if (IS_ERR(imx_data->clk_per)) {
1619 		err = PTR_ERR(imx_data->clk_per);
1620 		goto free_sdhci;
1621 	}
1622 
1623 	pltfm_host->clk = imx_data->clk_per;
1624 	pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1625 	err = clk_prepare_enable(imx_data->clk_per);
1626 	if (err)
1627 		goto free_sdhci;
1628 	err = clk_prepare_enable(imx_data->clk_ipg);
1629 	if (err)
1630 		goto disable_per_clk;
1631 	err = clk_prepare_enable(imx_data->clk_ahb);
1632 	if (err)
1633 		goto disable_ipg_clk;
1634 
1635 	imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1636 	if (IS_ERR(imx_data->pinctrl))
1637 		dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n");
1638 
1639 	if (esdhc_is_usdhc(imx_data)) {
1640 		host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1641 		host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1642 
1643 		/* GPIO CD can be set as a wakeup source */
1644 		host->mmc->caps |= MMC_CAP_CD_WAKE;
1645 
1646 		if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1647 			host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1648 
1649 		/* clear tuning bits in case ROM has set it already */
1650 		writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1651 		writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1652 		writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1653 
1654 		/*
1655 		 * Link usdhc specific mmc_host_ops execute_tuning function,
1656 		 * to replace the standard one in sdhci_ops.
1657 		 */
1658 		host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
1659 	}
1660 
1661 	if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1662 		sdhci_esdhc_ops.platform_execute_tuning =
1663 					esdhc_executing_tuning;
1664 
1665 	if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1666 		host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1667 
1668 	if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1669 		host->mmc->caps2 |= MMC_CAP2_HS400;
1670 
1671 	if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
1672 		host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
1673 
1674 	if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
1675 		host->mmc->caps2 |= MMC_CAP2_HS400_ES;
1676 		host->mmc_host_ops.hs400_enhanced_strobe =
1677 					esdhc_hs400_enhanced_strobe;
1678 	}
1679 
1680 	if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1681 		host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1682 		cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1683 		if (!cq_host) {
1684 			err = -ENOMEM;
1685 			goto disable_ahb_clk;
1686 		}
1687 
1688 		cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
1689 		cq_host->ops = &esdhc_cqhci_ops;
1690 
1691 		err = cqhci_init(cq_host, host->mmc, false);
1692 		if (err)
1693 			goto disable_ahb_clk;
1694 	}
1695 
1696 	err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1697 	if (err)
1698 		goto disable_ahb_clk;
1699 
1700 	sdhci_esdhc_imx_hwinit(host);
1701 
1702 	err = sdhci_add_host(host);
1703 	if (err)
1704 		goto disable_ahb_clk;
1705 
1706 	/*
1707 	 * Setup the wakeup capability here, let user to decide
1708 	 * whether need to enable this wakeup through sysfs interface.
1709 	 */
1710 	if ((host->mmc->pm_caps & MMC_PM_KEEP_POWER) &&
1711 			(host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ))
1712 		device_set_wakeup_capable(&pdev->dev, true);
1713 
1714 	pm_runtime_set_active(&pdev->dev);
1715 	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1716 	pm_runtime_use_autosuspend(&pdev->dev);
1717 	pm_suspend_ignore_children(&pdev->dev, 1);
1718 	pm_runtime_enable(&pdev->dev);
1719 
1720 	return 0;
1721 
1722 disable_ahb_clk:
1723 	clk_disable_unprepare(imx_data->clk_ahb);
1724 disable_ipg_clk:
1725 	clk_disable_unprepare(imx_data->clk_ipg);
1726 disable_per_clk:
1727 	clk_disable_unprepare(imx_data->clk_per);
1728 free_sdhci:
1729 	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1730 		cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1731 	sdhci_pltfm_free(pdev);
1732 	return err;
1733 }
1734 
1735 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1736 {
1737 	struct sdhci_host *host = platform_get_drvdata(pdev);
1738 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1739 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1740 	int dead;
1741 
1742 	pm_runtime_get_sync(&pdev->dev);
1743 	dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1744 	pm_runtime_disable(&pdev->dev);
1745 	pm_runtime_put_noidle(&pdev->dev);
1746 
1747 	sdhci_remove_host(host, dead);
1748 
1749 	clk_disable_unprepare(imx_data->clk_per);
1750 	clk_disable_unprepare(imx_data->clk_ipg);
1751 	clk_disable_unprepare(imx_data->clk_ahb);
1752 
1753 	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1754 		cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1755 
1756 	sdhci_pltfm_free(pdev);
1757 
1758 	return 0;
1759 }
1760 
1761 #ifdef CONFIG_PM_SLEEP
1762 static int sdhci_esdhc_suspend(struct device *dev)
1763 {
1764 	struct sdhci_host *host = dev_get_drvdata(dev);
1765 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1766 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1767 	int ret;
1768 
1769 	if (host->mmc->caps2 & MMC_CAP2_CQE) {
1770 		ret = cqhci_suspend(host->mmc);
1771 		if (ret)
1772 			return ret;
1773 	}
1774 
1775 	if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) &&
1776 		(host->tuning_mode != SDHCI_TUNING_MODE_1)) {
1777 		mmc_retune_timer_stop(host->mmc);
1778 		mmc_retune_needed(host->mmc);
1779 	}
1780 
1781 	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1782 		mmc_retune_needed(host->mmc);
1783 
1784 	ret = sdhci_suspend_host(host);
1785 	if (ret)
1786 		return ret;
1787 
1788 	ret = pinctrl_pm_select_sleep_state(dev);
1789 	if (ret)
1790 		return ret;
1791 
1792 	ret = mmc_gpio_set_cd_wake(host->mmc, true);
1793 
1794 	return ret;
1795 }
1796 
1797 static int sdhci_esdhc_resume(struct device *dev)
1798 {
1799 	struct sdhci_host *host = dev_get_drvdata(dev);
1800 	int ret;
1801 
1802 	ret = pinctrl_pm_select_default_state(dev);
1803 	if (ret)
1804 		return ret;
1805 
1806 	/* re-initialize hw state in case it's lost in low power mode */
1807 	sdhci_esdhc_imx_hwinit(host);
1808 
1809 	ret = sdhci_resume_host(host);
1810 	if (ret)
1811 		return ret;
1812 
1813 	if (host->mmc->caps2 & MMC_CAP2_CQE)
1814 		ret = cqhci_resume(host->mmc);
1815 
1816 	if (!ret)
1817 		ret = mmc_gpio_set_cd_wake(host->mmc, false);
1818 
1819 	return ret;
1820 }
1821 #endif
1822 
1823 #ifdef CONFIG_PM
1824 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1825 {
1826 	struct sdhci_host *host = dev_get_drvdata(dev);
1827 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1828 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1829 	int ret;
1830 
1831 	if (host->mmc->caps2 & MMC_CAP2_CQE) {
1832 		ret = cqhci_suspend(host->mmc);
1833 		if (ret)
1834 			return ret;
1835 	}
1836 
1837 	ret = sdhci_runtime_suspend_host(host);
1838 	if (ret)
1839 		return ret;
1840 
1841 	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1842 		mmc_retune_needed(host->mmc);
1843 
1844 	imx_data->actual_clock = host->mmc->actual_clock;
1845 	esdhc_pltfm_set_clock(host, 0);
1846 	clk_disable_unprepare(imx_data->clk_per);
1847 	clk_disable_unprepare(imx_data->clk_ipg);
1848 	clk_disable_unprepare(imx_data->clk_ahb);
1849 
1850 	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1851 		cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1852 
1853 	return ret;
1854 }
1855 
1856 static int sdhci_esdhc_runtime_resume(struct device *dev)
1857 {
1858 	struct sdhci_host *host = dev_get_drvdata(dev);
1859 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1860 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1861 	int err;
1862 
1863 	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1864 		cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1865 
1866 	if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME)
1867 		clk_set_rate(imx_data->clk_per, pltfm_host->clock);
1868 
1869 	err = clk_prepare_enable(imx_data->clk_ahb);
1870 	if (err)
1871 		goto remove_pm_qos_request;
1872 
1873 	err = clk_prepare_enable(imx_data->clk_per);
1874 	if (err)
1875 		goto disable_ahb_clk;
1876 
1877 	err = clk_prepare_enable(imx_data->clk_ipg);
1878 	if (err)
1879 		goto disable_per_clk;
1880 
1881 	esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1882 
1883 	err = sdhci_runtime_resume_host(host, 0);
1884 	if (err)
1885 		goto disable_ipg_clk;
1886 
1887 	if (host->mmc->caps2 & MMC_CAP2_CQE)
1888 		err = cqhci_resume(host->mmc);
1889 
1890 	return err;
1891 
1892 disable_ipg_clk:
1893 	clk_disable_unprepare(imx_data->clk_ipg);
1894 disable_per_clk:
1895 	clk_disable_unprepare(imx_data->clk_per);
1896 disable_ahb_clk:
1897 	clk_disable_unprepare(imx_data->clk_ahb);
1898 remove_pm_qos_request:
1899 	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1900 		cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1901 	return err;
1902 }
1903 #endif
1904 
1905 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1906 	SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1907 	SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1908 				sdhci_esdhc_runtime_resume, NULL)
1909 };
1910 
1911 static struct platform_driver sdhci_esdhc_imx_driver = {
1912 	.driver		= {
1913 		.name	= "sdhci-esdhc-imx",
1914 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
1915 		.of_match_table = imx_esdhc_dt_ids,
1916 		.pm	= &sdhci_esdhc_pmops,
1917 	},
1918 	.probe		= sdhci_esdhc_imx_probe,
1919 	.remove		= sdhci_esdhc_imx_remove,
1920 };
1921 
1922 module_platform_driver(sdhci_esdhc_imx_driver);
1923 
1924 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1925 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1926 MODULE_LICENSE("GPL v2");
1927