1 /* 2 * Freescale eSDHC i.MX controller driver for the platform bus. 3 * 4 * derived from the OF-version. 5 * 6 * Copyright (c) 2010 Pengutronix e.K. 7 * Author: Wolfram Sang <kernel@pengutronix.de> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License. 12 */ 13 14 #include <linux/io.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/clk.h> 18 #include <linux/gpio.h> 19 #include <linux/module.h> 20 #include <linux/slab.h> 21 #include <linux/mmc/host.h> 22 #include <linux/mmc/mmc.h> 23 #include <linux/mmc/sdio.h> 24 #include <linux/mmc/slot-gpio.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/of_gpio.h> 28 #include <linux/pinctrl/consumer.h> 29 #include <linux/platform_data/mmc-esdhc-imx.h> 30 #include <linux/pm_runtime.h> 31 #include "sdhci-pltfm.h" 32 #include "sdhci-esdhc.h" 33 34 #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f 35 #define ESDHC_CTRL_D3CD 0x08 36 #define ESDHC_BURST_LEN_EN_INCR (1 << 27) 37 /* VENDOR SPEC register */ 38 #define ESDHC_VENDOR_SPEC 0xc0 39 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 40 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 41 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 42 #define ESDHC_WTMK_LVL 0x44 43 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 44 #define ESDHC_MIX_CTRL 0x48 45 #define ESDHC_MIX_CTRL_DDREN (1 << 3) 46 #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 47 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 48 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 49 #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) 50 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 51 #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 52 /* Bits 3 and 6 are not SDHCI standard definitions */ 53 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 54 /* Tuning bits */ 55 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 56 57 /* dll control register */ 58 #define ESDHC_DLL_CTRL 0x60 59 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 60 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 61 62 /* tune control register */ 63 #define ESDHC_TUNE_CTRL_STATUS 0x68 64 #define ESDHC_TUNE_CTRL_STEP 1 65 #define ESDHC_TUNE_CTRL_MIN 0 66 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 67 68 /* strobe dll register */ 69 #define ESDHC_STROBE_DLL_CTRL 0x70 70 #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) 71 #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) 72 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 73 74 #define ESDHC_STROBE_DLL_STATUS 0x74 75 #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) 76 #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 77 78 #define ESDHC_TUNING_CTRL 0xcc 79 #define ESDHC_STD_TUNING_EN (1 << 24) 80 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 81 #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 82 #define ESDHC_TUNING_START_TAP_MASK 0xff 83 #define ESDHC_TUNING_STEP_MASK 0x00070000 84 #define ESDHC_TUNING_STEP_SHIFT 16 85 86 /* pinctrl state */ 87 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 88 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 89 90 /* 91 * Our interpretation of the SDHCI_HOST_CONTROL register 92 */ 93 #define ESDHC_CTRL_4BITBUS (0x1 << 1) 94 #define ESDHC_CTRL_8BITBUS (0x2 << 1) 95 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 96 97 /* 98 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC: 99 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 100 * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 101 * Define this macro DMA error INT for fsl eSDHC 102 */ 103 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 104 105 /* 106 * The CMDTYPE of the CMD register (offset 0xE) should be set to 107 * "11" when the STOP CMD12 is issued on imx53 to abort one 108 * open ended multi-blk IO. Otherwise the TC INT wouldn't 109 * be generated. 110 * In exact block transfer, the controller doesn't complete the 111 * operations automatically as required at the end of the 112 * transfer and remains on hold if the abort command is not sent. 113 * As a result, the TC flag is not asserted and SW received timeout 114 * exception. Bit1 of Vendor Spec register is used to fix it. 115 */ 116 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 117 /* 118 * The flag tells that the ESDHC controller is an USDHC block that is 119 * integrated on the i.MX6 series. 120 */ 121 #define ESDHC_FLAG_USDHC BIT(3) 122 /* The IP supports manual tuning process */ 123 #define ESDHC_FLAG_MAN_TUNING BIT(4) 124 /* The IP supports standard tuning process */ 125 #define ESDHC_FLAG_STD_TUNING BIT(5) 126 /* The IP has SDHCI_CAPABILITIES_1 register */ 127 #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 128 /* 129 * The IP has erratum ERR004536 130 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 131 * when reading data from the card 132 * This flag is also set for i.MX25 and i.MX35 in order to get 133 * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits). 134 */ 135 #define ESDHC_FLAG_ERR004536 BIT(7) 136 /* The IP supports HS200 mode */ 137 #define ESDHC_FLAG_HS200 BIT(8) 138 /* The IP supports HS400 mode */ 139 #define ESDHC_FLAG_HS400 BIT(9) 140 141 /* A clock frequency higher than this rate requires strobe dll control */ 142 #define ESDHC_STROBE_DLL_CLK_FREQ 100000000 143 144 struct esdhc_soc_data { 145 u32 flags; 146 }; 147 148 static struct esdhc_soc_data esdhc_imx25_data = { 149 .flags = ESDHC_FLAG_ERR004536, 150 }; 151 152 static struct esdhc_soc_data esdhc_imx35_data = { 153 .flags = ESDHC_FLAG_ERR004536, 154 }; 155 156 static struct esdhc_soc_data esdhc_imx51_data = { 157 .flags = 0, 158 }; 159 160 static struct esdhc_soc_data esdhc_imx53_data = { 161 .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 162 }; 163 164 static struct esdhc_soc_data usdhc_imx6q_data = { 165 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, 166 }; 167 168 static struct esdhc_soc_data usdhc_imx6sl_data = { 169 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 170 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 171 | ESDHC_FLAG_HS200, 172 }; 173 174 static struct esdhc_soc_data usdhc_imx6sx_data = { 175 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 176 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, 177 }; 178 179 static struct esdhc_soc_data usdhc_imx7d_data = { 180 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 181 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 182 | ESDHC_FLAG_HS400, 183 }; 184 185 struct pltfm_imx_data { 186 u32 scratchpad; 187 struct pinctrl *pinctrl; 188 struct pinctrl_state *pins_default; 189 struct pinctrl_state *pins_100mhz; 190 struct pinctrl_state *pins_200mhz; 191 const struct esdhc_soc_data *socdata; 192 struct esdhc_platform_data boarddata; 193 struct clk *clk_ipg; 194 struct clk *clk_ahb; 195 struct clk *clk_per; 196 enum { 197 NO_CMD_PENDING, /* no multiblock command pending */ 198 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 199 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 200 } multiblock_status; 201 u32 is_ddr; 202 }; 203 204 static const struct platform_device_id imx_esdhc_devtype[] = { 205 { 206 .name = "sdhci-esdhc-imx25", 207 .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 208 }, { 209 .name = "sdhci-esdhc-imx35", 210 .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 211 }, { 212 .name = "sdhci-esdhc-imx51", 213 .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 214 }, { 215 /* sentinel */ 216 } 217 }; 218 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 219 220 static const struct of_device_id imx_esdhc_dt_ids[] = { 221 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 222 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 223 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 224 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 225 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 226 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 227 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 228 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, 229 { /* sentinel */ } 230 }; 231 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 232 233 static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 234 { 235 return data->socdata == &esdhc_imx25_data; 236 } 237 238 static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 239 { 240 return data->socdata == &esdhc_imx53_data; 241 } 242 243 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 244 { 245 return data->socdata == &usdhc_imx6q_data; 246 } 247 248 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 249 { 250 return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 251 } 252 253 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 254 { 255 void __iomem *base = host->ioaddr + (reg & ~0x3); 256 u32 shift = (reg & 0x3) * 8; 257 258 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 259 } 260 261 static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 262 { 263 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 264 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 265 u32 val = readl(host->ioaddr + reg); 266 267 if (unlikely(reg == SDHCI_PRESENT_STATE)) { 268 u32 fsl_prss = val; 269 /* save the least 20 bits */ 270 val = fsl_prss & 0x000FFFFF; 271 /* move dat[0-3] bits */ 272 val |= (fsl_prss & 0x0F000000) >> 4; 273 /* move cmd line bit */ 274 val |= (fsl_prss & 0x00800000) << 1; 275 } 276 277 if (unlikely(reg == SDHCI_CAPABILITIES)) { 278 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 279 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 280 val &= 0xffff0000; 281 282 /* In FSL esdhc IC module, only bit20 is used to indicate the 283 * ADMA2 capability of esdhc, but this bit is messed up on 284 * some SOCs (e.g. on MX25, MX35 this bit is set, but they 285 * don't actually support ADMA2). So set the BROKEN_ADMA 286 * quirk on MX25/35 platforms. 287 */ 288 289 if (val & SDHCI_CAN_DO_ADMA1) { 290 val &= ~SDHCI_CAN_DO_ADMA1; 291 val |= SDHCI_CAN_DO_ADMA2; 292 } 293 } 294 295 if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 296 if (esdhc_is_usdhc(imx_data)) { 297 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 298 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 299 else 300 /* imx6q/dl does not have cap_1 register, fake one */ 301 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 302 | SDHCI_SUPPORT_SDR50 303 | SDHCI_USE_SDR50_TUNING 304 | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT); 305 306 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 307 val |= SDHCI_SUPPORT_HS400; 308 } 309 } 310 311 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 312 val = 0; 313 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 314 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 315 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 316 } 317 318 if (unlikely(reg == SDHCI_INT_STATUS)) { 319 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 320 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 321 val |= SDHCI_INT_ADMA_ERROR; 322 } 323 324 /* 325 * mask off the interrupt we get in response to the manually 326 * sent CMD12 327 */ 328 if ((imx_data->multiblock_status == WAIT_FOR_INT) && 329 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 330 val &= ~SDHCI_INT_RESPONSE; 331 writel(SDHCI_INT_RESPONSE, host->ioaddr + 332 SDHCI_INT_STATUS); 333 imx_data->multiblock_status = NO_CMD_PENDING; 334 } 335 } 336 337 return val; 338 } 339 340 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 341 { 342 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 343 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 344 u32 data; 345 346 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || 347 reg == SDHCI_INT_STATUS)) { 348 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 349 /* 350 * Clear and then set D3CD bit to avoid missing the 351 * card interrupt. This is an eSDHC controller problem 352 * so we need to apply the following workaround: clear 353 * and set D3CD bit will make eSDHC re-sample the card 354 * interrupt. In case a card interrupt was lost, 355 * re-sample it by the following steps. 356 */ 357 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 358 data &= ~ESDHC_CTRL_D3CD; 359 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 360 data |= ESDHC_CTRL_D3CD; 361 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 362 } 363 364 if (val & SDHCI_INT_ADMA_ERROR) { 365 val &= ~SDHCI_INT_ADMA_ERROR; 366 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 367 } 368 } 369 370 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 371 && (reg == SDHCI_INT_STATUS) 372 && (val & SDHCI_INT_DATA_END))) { 373 u32 v; 374 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 375 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 376 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 377 378 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 379 { 380 /* send a manual CMD12 with RESPTYP=none */ 381 data = MMC_STOP_TRANSMISSION << 24 | 382 SDHCI_CMD_ABORTCMD << 16; 383 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 384 imx_data->multiblock_status = WAIT_FOR_INT; 385 } 386 } 387 388 writel(val, host->ioaddr + reg); 389 } 390 391 static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 392 { 393 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 394 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 395 u16 ret = 0; 396 u32 val; 397 398 if (unlikely(reg == SDHCI_HOST_VERSION)) { 399 reg ^= 2; 400 if (esdhc_is_usdhc(imx_data)) { 401 /* 402 * The usdhc register returns a wrong host version. 403 * Correct it here. 404 */ 405 return SDHCI_SPEC_300; 406 } 407 } 408 409 if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 410 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 411 if (val & ESDHC_VENDOR_SPEC_VSELECT) 412 ret |= SDHCI_CTRL_VDD_180; 413 414 if (esdhc_is_usdhc(imx_data)) { 415 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 416 val = readl(host->ioaddr + ESDHC_MIX_CTRL); 417 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 418 /* the std tuning bits is in ACMD12_ERR for imx6sl */ 419 val = readl(host->ioaddr + SDHCI_ACMD12_ERR); 420 } 421 422 if (val & ESDHC_MIX_CTRL_EXE_TUNE) 423 ret |= SDHCI_CTRL_EXEC_TUNING; 424 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 425 ret |= SDHCI_CTRL_TUNED_CLK; 426 427 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 428 429 return ret; 430 } 431 432 if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 433 if (esdhc_is_usdhc(imx_data)) { 434 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 435 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 436 /* Swap AC23 bit */ 437 if (m & ESDHC_MIX_CTRL_AC23EN) { 438 ret &= ~ESDHC_MIX_CTRL_AC23EN; 439 ret |= SDHCI_TRNS_AUTO_CMD23; 440 } 441 } else { 442 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 443 } 444 445 return ret; 446 } 447 448 return readw(host->ioaddr + reg); 449 } 450 451 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 452 { 453 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 454 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 455 u32 new_val = 0; 456 457 switch (reg) { 458 case SDHCI_CLOCK_CONTROL: 459 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 460 if (val & SDHCI_CLOCK_CARD_EN) 461 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 462 else 463 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 464 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 465 return; 466 case SDHCI_HOST_CONTROL2: 467 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 468 if (val & SDHCI_CTRL_VDD_180) 469 new_val |= ESDHC_VENDOR_SPEC_VSELECT; 470 else 471 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 472 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 473 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 474 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 475 if (val & SDHCI_CTRL_TUNED_CLK) { 476 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 477 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 478 } else { 479 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 480 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 481 } 482 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 483 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 484 u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); 485 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 486 if (val & SDHCI_CTRL_TUNED_CLK) { 487 v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 488 } else { 489 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 490 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 491 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 492 } 493 494 if (val & SDHCI_CTRL_EXEC_TUNING) { 495 v |= ESDHC_MIX_CTRL_EXE_TUNE; 496 m |= ESDHC_MIX_CTRL_FBCLK_SEL; 497 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 498 } else { 499 v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 500 } 501 502 writel(v, host->ioaddr + SDHCI_ACMD12_ERR); 503 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 504 } 505 return; 506 case SDHCI_TRANSFER_MODE: 507 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 508 && (host->cmd->opcode == SD_IO_RW_EXTENDED) 509 && (host->cmd->data->blocks > 1) 510 && (host->cmd->data->flags & MMC_DATA_READ)) { 511 u32 v; 512 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 513 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 514 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 515 } 516 517 if (esdhc_is_usdhc(imx_data)) { 518 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 519 /* Swap AC23 bit */ 520 if (val & SDHCI_TRNS_AUTO_CMD23) { 521 val &= ~SDHCI_TRNS_AUTO_CMD23; 522 val |= ESDHC_MIX_CTRL_AC23EN; 523 } 524 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 525 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 526 } else { 527 /* 528 * Postpone this write, we must do it together with a 529 * command write that is down below. 530 */ 531 imx_data->scratchpad = val; 532 } 533 return; 534 case SDHCI_COMMAND: 535 if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 536 val |= SDHCI_CMD_ABORTCMD; 537 538 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 539 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 540 imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 541 542 if (esdhc_is_usdhc(imx_data)) 543 writel(val << 16, 544 host->ioaddr + SDHCI_TRANSFER_MODE); 545 else 546 writel(val << 16 | imx_data->scratchpad, 547 host->ioaddr + SDHCI_TRANSFER_MODE); 548 return; 549 case SDHCI_BLOCK_SIZE: 550 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 551 break; 552 } 553 esdhc_clrset_le(host, 0xffff, val, reg); 554 } 555 556 static u8 esdhc_readb_le(struct sdhci_host *host, int reg) 557 { 558 u8 ret; 559 u32 val; 560 561 switch (reg) { 562 case SDHCI_HOST_CONTROL: 563 val = readl(host->ioaddr + reg); 564 565 ret = val & SDHCI_CTRL_LED; 566 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; 567 ret |= (val & ESDHC_CTRL_4BITBUS); 568 ret |= (val & ESDHC_CTRL_8BITBUS) << 3; 569 return ret; 570 } 571 572 return readb(host->ioaddr + reg); 573 } 574 575 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 576 { 577 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 578 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 579 u32 new_val = 0; 580 u32 mask; 581 582 switch (reg) { 583 case SDHCI_POWER_CONTROL: 584 /* 585 * FSL put some DMA bits here 586 * If your board has a regulator, code should be here 587 */ 588 return; 589 case SDHCI_HOST_CONTROL: 590 /* FSL messed up here, so we need to manually compose it. */ 591 new_val = val & SDHCI_CTRL_LED; 592 /* ensure the endianness */ 593 new_val |= ESDHC_HOST_CONTROL_LE; 594 /* bits 8&9 are reserved on mx25 */ 595 if (!is_imx25_esdhc(imx_data)) { 596 /* DMA mode bits are shifted */ 597 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 598 } 599 600 /* 601 * Do not touch buswidth bits here. This is done in 602 * esdhc_pltfm_bus_width. 603 * Do not touch the D3CD bit either which is used for the 604 * SDIO interrupt erratum workaround. 605 */ 606 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 607 608 esdhc_clrset_le(host, mask, new_val, reg); 609 return; 610 case SDHCI_SOFTWARE_RESET: 611 if (val & SDHCI_RESET_DATA) 612 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); 613 break; 614 } 615 esdhc_clrset_le(host, 0xff, val, reg); 616 617 if (reg == SDHCI_SOFTWARE_RESET) { 618 if (val & SDHCI_RESET_ALL) { 619 /* 620 * The esdhc has a design violation to SDHC spec which 621 * tells that software reset should not affect card 622 * detection circuit. But esdhc clears its SYSCTL 623 * register bits [0..2] during the software reset. This 624 * will stop those clocks that card detection circuit 625 * relies on. To work around it, we turn the clocks on 626 * back to keep card detection circuit functional. 627 */ 628 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 629 /* 630 * The reset on usdhc fails to clear MIX_CTRL register. 631 * Do it manually here. 632 */ 633 if (esdhc_is_usdhc(imx_data)) { 634 /* 635 * the tuning bits should be kept during reset 636 */ 637 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 638 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 639 host->ioaddr + ESDHC_MIX_CTRL); 640 imx_data->is_ddr = 0; 641 } 642 } else if (val & SDHCI_RESET_DATA) { 643 /* 644 * The eSDHC DAT line software reset clears at least the 645 * data transfer width on i.MX25, so make sure that the 646 * Host Control register is unaffected. 647 */ 648 esdhc_clrset_le(host, 0xff, new_val, 649 SDHCI_HOST_CONTROL); 650 } 651 } 652 } 653 654 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 655 { 656 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 657 658 return pltfm_host->clock; 659 } 660 661 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 662 { 663 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 664 665 return pltfm_host->clock / 256 / 16; 666 } 667 668 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 669 unsigned int clock) 670 { 671 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 672 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 673 unsigned int host_clock = pltfm_host->clock; 674 int ddr_pre_div = imx_data->is_ddr ? 2 : 1; 675 int pre_div = 1; 676 int div = 1; 677 u32 temp, val; 678 679 if (clock == 0) { 680 host->mmc->actual_clock = 0; 681 682 if (esdhc_is_usdhc(imx_data)) { 683 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 684 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 685 host->ioaddr + ESDHC_VENDOR_SPEC); 686 } 687 return; 688 } 689 690 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 691 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 692 | ESDHC_CLOCK_MASK); 693 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 694 695 while (host_clock / (16 * pre_div * ddr_pre_div) > clock && 696 pre_div < 256) 697 pre_div *= 2; 698 699 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16) 700 div++; 701 702 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); 703 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 704 clock, host->mmc->actual_clock); 705 706 pre_div >>= 1; 707 div--; 708 709 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 710 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 711 | (div << ESDHC_DIVIDER_SHIFT) 712 | (pre_div << ESDHC_PREDIV_SHIFT)); 713 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 714 715 if (esdhc_is_usdhc(imx_data)) { 716 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 717 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 718 host->ioaddr + ESDHC_VENDOR_SPEC); 719 } 720 721 mdelay(1); 722 } 723 724 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 725 { 726 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 727 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 728 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 729 730 switch (boarddata->wp_type) { 731 case ESDHC_WP_GPIO: 732 return mmc_gpio_get_ro(host->mmc); 733 case ESDHC_WP_CONTROLLER: 734 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 735 SDHCI_WRITE_PROTECT); 736 case ESDHC_WP_NONE: 737 break; 738 } 739 740 return -ENOSYS; 741 } 742 743 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 744 { 745 u32 ctrl; 746 747 switch (width) { 748 case MMC_BUS_WIDTH_8: 749 ctrl = ESDHC_CTRL_8BITBUS; 750 break; 751 case MMC_BUS_WIDTH_4: 752 ctrl = ESDHC_CTRL_4BITBUS; 753 break; 754 default: 755 ctrl = 0; 756 break; 757 } 758 759 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 760 SDHCI_HOST_CONTROL); 761 } 762 763 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 764 { 765 u32 reg; 766 767 /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 768 mdelay(1); 769 770 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 771 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 772 ESDHC_MIX_CTRL_FBCLK_SEL; 773 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 774 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 775 dev_dbg(mmc_dev(host->mmc), 776 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 777 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 778 } 779 780 static void esdhc_post_tuning(struct sdhci_host *host) 781 { 782 u32 reg; 783 784 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 785 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 786 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 787 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 788 } 789 790 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 791 { 792 int min, max, avg, ret; 793 794 /* find the mininum delay first which can pass tuning */ 795 min = ESDHC_TUNE_CTRL_MIN; 796 while (min < ESDHC_TUNE_CTRL_MAX) { 797 esdhc_prepare_tuning(host, min); 798 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 799 break; 800 min += ESDHC_TUNE_CTRL_STEP; 801 } 802 803 /* find the maxinum delay which can not pass tuning */ 804 max = min + ESDHC_TUNE_CTRL_STEP; 805 while (max < ESDHC_TUNE_CTRL_MAX) { 806 esdhc_prepare_tuning(host, max); 807 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 808 max -= ESDHC_TUNE_CTRL_STEP; 809 break; 810 } 811 max += ESDHC_TUNE_CTRL_STEP; 812 } 813 814 /* use average delay to get the best timing */ 815 avg = (min + max) / 2; 816 esdhc_prepare_tuning(host, avg); 817 ret = mmc_send_tuning(host->mmc, opcode, NULL); 818 esdhc_post_tuning(host); 819 820 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 821 ret ? "failed" : "passed", avg, ret); 822 823 return ret; 824 } 825 826 static int esdhc_change_pinstate(struct sdhci_host *host, 827 unsigned int uhs) 828 { 829 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 830 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 831 struct pinctrl_state *pinctrl; 832 833 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 834 835 if (IS_ERR(imx_data->pinctrl) || 836 IS_ERR(imx_data->pins_default) || 837 IS_ERR(imx_data->pins_100mhz) || 838 IS_ERR(imx_data->pins_200mhz)) 839 return -EINVAL; 840 841 switch (uhs) { 842 case MMC_TIMING_UHS_SDR50: 843 case MMC_TIMING_UHS_DDR50: 844 pinctrl = imx_data->pins_100mhz; 845 break; 846 case MMC_TIMING_UHS_SDR104: 847 case MMC_TIMING_MMC_HS200: 848 case MMC_TIMING_MMC_HS400: 849 pinctrl = imx_data->pins_200mhz; 850 break; 851 default: 852 /* back to default state for other legacy timing */ 853 pinctrl = imx_data->pins_default; 854 } 855 856 return pinctrl_select_state(imx_data->pinctrl, pinctrl); 857 } 858 859 /* 860 * For HS400 eMMC, there is a data_strobe line. This signal is generated 861 * by the device and used for data output and CRC status response output 862 * in HS400 mode. The frequency of this signal follows the frequency of 863 * CLK generated by host. The host receives the data which is aligned to the 864 * edge of data_strobe line. Due to the time delay between CLK line and 865 * data_strobe line, if the delay time is larger than one clock cycle, 866 * then CLK and data_strobe line will be misaligned, read error shows up. 867 * So when the CLK is higher than 100MHz, each clock cycle is short enough, 868 * host should configure the delay target. 869 */ 870 static void esdhc_set_strobe_dll(struct sdhci_host *host) 871 { 872 u32 v; 873 874 if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) { 875 /* disable clock before enabling strobe dll */ 876 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & 877 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 878 host->ioaddr + ESDHC_VENDOR_SPEC); 879 880 /* force a reset on strobe dll */ 881 writel(ESDHC_STROBE_DLL_CTRL_RESET, 882 host->ioaddr + ESDHC_STROBE_DLL_CTRL); 883 /* 884 * enable strobe dll ctrl and adjust the delay target 885 * for the uSDHC loopback read clock 886 */ 887 v = ESDHC_STROBE_DLL_CTRL_ENABLE | 888 (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 889 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 890 /* wait 1us to make sure strobe dll status register stable */ 891 udelay(1); 892 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS); 893 if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK)) 894 dev_warn(mmc_dev(host->mmc), 895 "warning! HS400 strobe DLL status REF not lock!\n"); 896 if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK)) 897 dev_warn(mmc_dev(host->mmc), 898 "warning! HS400 strobe DLL status SLV not lock!\n"); 899 } 900 } 901 902 static void esdhc_reset_tuning(struct sdhci_host *host) 903 { 904 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 905 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 906 u32 ctrl; 907 908 /* Reset the tuning circuit */ 909 if (esdhc_is_usdhc(imx_data)) { 910 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 911 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); 912 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 913 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 914 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 915 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 916 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 917 ctrl = readl(host->ioaddr + SDHCI_ACMD12_ERR); 918 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 919 writel(ctrl, host->ioaddr + SDHCI_ACMD12_ERR); 920 } 921 } 922 } 923 924 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 925 { 926 u32 m; 927 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 928 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 929 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 930 931 /* disable ddr mode and disable HS400 mode */ 932 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 933 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); 934 imx_data->is_ddr = 0; 935 936 switch (timing) { 937 case MMC_TIMING_UHS_SDR12: 938 case MMC_TIMING_UHS_SDR25: 939 case MMC_TIMING_UHS_SDR50: 940 case MMC_TIMING_UHS_SDR104: 941 case MMC_TIMING_MMC_HS200: 942 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 943 break; 944 case MMC_TIMING_UHS_DDR50: 945 case MMC_TIMING_MMC_DDR52: 946 m |= ESDHC_MIX_CTRL_DDREN; 947 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 948 imx_data->is_ddr = 1; 949 if (boarddata->delay_line) { 950 u32 v; 951 v = boarddata->delay_line << 952 ESDHC_DLL_OVERRIDE_VAL_SHIFT | 953 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 954 if (is_imx53_esdhc(imx_data)) 955 v <<= 1; 956 writel(v, host->ioaddr + ESDHC_DLL_CTRL); 957 } 958 break; 959 case MMC_TIMING_MMC_HS400: 960 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 961 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 962 imx_data->is_ddr = 1; 963 /* update clock after enable DDR for strobe DLL lock */ 964 host->ops->set_clock(host, host->clock); 965 esdhc_set_strobe_dll(host); 966 break; 967 case MMC_TIMING_LEGACY: 968 default: 969 esdhc_reset_tuning(host); 970 break; 971 } 972 973 esdhc_change_pinstate(host, timing); 974 } 975 976 static void esdhc_reset(struct sdhci_host *host, u8 mask) 977 { 978 sdhci_reset(host, mask); 979 980 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 981 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 982 } 983 984 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 985 { 986 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 987 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 988 989 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */ 990 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27; 991 } 992 993 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 994 { 995 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 996 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 997 998 /* use maximum timeout counter */ 999 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, 1000 esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 1001 SDHCI_TIMEOUT_CONTROL); 1002 } 1003 1004 static struct sdhci_ops sdhci_esdhc_ops = { 1005 .read_l = esdhc_readl_le, 1006 .read_w = esdhc_readw_le, 1007 .read_b = esdhc_readb_le, 1008 .write_l = esdhc_writel_le, 1009 .write_w = esdhc_writew_le, 1010 .write_b = esdhc_writeb_le, 1011 .set_clock = esdhc_pltfm_set_clock, 1012 .get_max_clock = esdhc_pltfm_get_max_clock, 1013 .get_min_clock = esdhc_pltfm_get_min_clock, 1014 .get_max_timeout_count = esdhc_get_max_timeout_count, 1015 .get_ro = esdhc_pltfm_get_ro, 1016 .set_timeout = esdhc_set_timeout, 1017 .set_bus_width = esdhc_pltfm_set_bus_width, 1018 .set_uhs_signaling = esdhc_set_uhs_signaling, 1019 .reset = esdhc_reset, 1020 }; 1021 1022 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 1023 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 1024 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 1025 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 1026 | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 1027 .ops = &sdhci_esdhc_ops, 1028 }; 1029 1030 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) 1031 { 1032 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1033 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1034 int tmp; 1035 1036 if (esdhc_is_usdhc(imx_data)) { 1037 /* 1038 * The imx6q ROM code will change the default watermark 1039 * level setting to something insane. Change it back here. 1040 */ 1041 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); 1042 1043 /* 1044 * ROM code will change the bit burst_length_enable setting 1045 * to zero if this usdhc is chosen to boot system. Change 1046 * it back here, otherwise it will impact the performance a 1047 * lot. This bit is used to enable/disable the burst length 1048 * for the external AHB2AXI bridge. It's useful especially 1049 * for INCR transfer because without burst length indicator, 1050 * the AHB2AXI bridge does not know the burst length in 1051 * advance. And without burst length indicator, AHB INCR 1052 * transfer can only be converted to singles on the AXI side. 1053 */ 1054 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) 1055 | ESDHC_BURST_LEN_EN_INCR, 1056 host->ioaddr + SDHCI_HOST_CONTROL); 1057 /* 1058 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 1059 * TO1.1, it's harmless for MX6SL 1060 */ 1061 writel(readl(host->ioaddr + 0x6c) | BIT(7), 1062 host->ioaddr + 0x6c); 1063 1064 /* disable DLL_CTRL delay line settings */ 1065 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); 1066 1067 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1068 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1069 tmp |= ESDHC_STD_TUNING_EN | 1070 ESDHC_TUNING_START_TAP_DEFAULT; 1071 if (imx_data->boarddata.tuning_start_tap) { 1072 tmp &= ~ESDHC_TUNING_START_TAP_MASK; 1073 tmp |= imx_data->boarddata.tuning_start_tap; 1074 } 1075 1076 if (imx_data->boarddata.tuning_step) { 1077 tmp &= ~ESDHC_TUNING_STEP_MASK; 1078 tmp |= imx_data->boarddata.tuning_step 1079 << ESDHC_TUNING_STEP_SHIFT; 1080 } 1081 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1082 } 1083 } 1084 } 1085 1086 #ifdef CONFIG_OF 1087 static int 1088 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 1089 struct sdhci_host *host, 1090 struct pltfm_imx_data *imx_data) 1091 { 1092 struct device_node *np = pdev->dev.of_node; 1093 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1094 int ret; 1095 1096 if (of_get_property(np, "fsl,wp-controller", NULL)) 1097 boarddata->wp_type = ESDHC_WP_CONTROLLER; 1098 1099 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 1100 if (gpio_is_valid(boarddata->wp_gpio)) 1101 boarddata->wp_type = ESDHC_WP_GPIO; 1102 1103 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 1104 of_property_read_u32(np, "fsl,tuning-start-tap", 1105 &boarddata->tuning_start_tap); 1106 1107 if (of_find_property(np, "no-1-8-v", NULL)) 1108 boarddata->support_vsel = false; 1109 else 1110 boarddata->support_vsel = true; 1111 1112 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 1113 boarddata->delay_line = 0; 1114 1115 mmc_of_parse_voltage(np, &host->ocr_mask); 1116 1117 /* sdr50 and sdr104 need work on 1.8v signal voltage */ 1118 if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) && 1119 !IS_ERR(imx_data->pins_default)) { 1120 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 1121 ESDHC_PINCTRL_STATE_100MHZ); 1122 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 1123 ESDHC_PINCTRL_STATE_200MHZ); 1124 if (IS_ERR(imx_data->pins_100mhz) || 1125 IS_ERR(imx_data->pins_200mhz)) { 1126 dev_warn(mmc_dev(host->mmc), 1127 "could not get ultra high speed state, work on normal mode\n"); 1128 /* 1129 * fall back to not supporting uhs by specifying no 1130 * 1.8v quirk 1131 */ 1132 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1133 } 1134 } else { 1135 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1136 } 1137 1138 /* call to generic mmc_of_parse to support additional capabilities */ 1139 ret = mmc_of_parse(host->mmc); 1140 if (ret) 1141 return ret; 1142 1143 if (mmc_gpio_get_cd(host->mmc) >= 0) 1144 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1145 1146 return 0; 1147 } 1148 #else 1149 static inline int 1150 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 1151 struct sdhci_host *host, 1152 struct pltfm_imx_data *imx_data) 1153 { 1154 return -ENODEV; 1155 } 1156 #endif 1157 1158 static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev, 1159 struct sdhci_host *host, 1160 struct pltfm_imx_data *imx_data) 1161 { 1162 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1163 int err; 1164 1165 if (!host->mmc->parent->platform_data) { 1166 dev_err(mmc_dev(host->mmc), "no board data!\n"); 1167 return -EINVAL; 1168 } 1169 1170 imx_data->boarddata = *((struct esdhc_platform_data *) 1171 host->mmc->parent->platform_data); 1172 /* write_protect */ 1173 if (boarddata->wp_type == ESDHC_WP_GPIO) { 1174 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); 1175 if (err) { 1176 dev_err(mmc_dev(host->mmc), 1177 "failed to request write-protect gpio!\n"); 1178 return err; 1179 } 1180 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 1181 } 1182 1183 /* card_detect */ 1184 switch (boarddata->cd_type) { 1185 case ESDHC_CD_GPIO: 1186 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); 1187 if (err) { 1188 dev_err(mmc_dev(host->mmc), 1189 "failed to request card-detect gpio!\n"); 1190 return err; 1191 } 1192 /* fall through */ 1193 1194 case ESDHC_CD_CONTROLLER: 1195 /* we have a working card_detect back */ 1196 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1197 break; 1198 1199 case ESDHC_CD_PERMANENT: 1200 host->mmc->caps |= MMC_CAP_NONREMOVABLE; 1201 break; 1202 1203 case ESDHC_CD_NONE: 1204 break; 1205 } 1206 1207 switch (boarddata->max_bus_width) { 1208 case 8: 1209 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 1210 break; 1211 case 4: 1212 host->mmc->caps |= MMC_CAP_4_BIT_DATA; 1213 break; 1214 case 1: 1215 default: 1216 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 1217 break; 1218 } 1219 1220 return 0; 1221 } 1222 1223 static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 1224 { 1225 const struct of_device_id *of_id = 1226 of_match_device(imx_esdhc_dt_ids, &pdev->dev); 1227 struct sdhci_pltfm_host *pltfm_host; 1228 struct sdhci_host *host; 1229 int err; 1230 struct pltfm_imx_data *imx_data; 1231 1232 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 1233 sizeof(*imx_data)); 1234 if (IS_ERR(host)) 1235 return PTR_ERR(host); 1236 1237 pltfm_host = sdhci_priv(host); 1238 1239 imx_data = sdhci_pltfm_priv(pltfm_host); 1240 1241 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 1242 pdev->id_entry->driver_data; 1243 1244 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1245 if (IS_ERR(imx_data->clk_ipg)) { 1246 err = PTR_ERR(imx_data->clk_ipg); 1247 goto free_sdhci; 1248 } 1249 1250 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1251 if (IS_ERR(imx_data->clk_ahb)) { 1252 err = PTR_ERR(imx_data->clk_ahb); 1253 goto free_sdhci; 1254 } 1255 1256 imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 1257 if (IS_ERR(imx_data->clk_per)) { 1258 err = PTR_ERR(imx_data->clk_per); 1259 goto free_sdhci; 1260 } 1261 1262 pltfm_host->clk = imx_data->clk_per; 1263 pltfm_host->clock = clk_get_rate(pltfm_host->clk); 1264 err = clk_prepare_enable(imx_data->clk_per); 1265 if (err) 1266 goto free_sdhci; 1267 err = clk_prepare_enable(imx_data->clk_ipg); 1268 if (err) 1269 goto disable_per_clk; 1270 err = clk_prepare_enable(imx_data->clk_ahb); 1271 if (err) 1272 goto disable_ipg_clk; 1273 1274 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1275 if (IS_ERR(imx_data->pinctrl)) { 1276 err = PTR_ERR(imx_data->pinctrl); 1277 goto disable_ahb_clk; 1278 } 1279 1280 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, 1281 PINCTRL_STATE_DEFAULT); 1282 if (IS_ERR(imx_data->pins_default)) 1283 dev_warn(mmc_dev(host->mmc), "could not get default state\n"); 1284 1285 if (esdhc_is_usdhc(imx_data)) { 1286 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 1287 host->mmc->caps |= MMC_CAP_1_8V_DDR; 1288 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 1289 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 1290 1291 /* clear tuning bits in case ROM has set it already */ 1292 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); 1293 writel(0x0, host->ioaddr + SDHCI_ACMD12_ERR); 1294 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1295 } 1296 1297 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 1298 sdhci_esdhc_ops.platform_execute_tuning = 1299 esdhc_executing_tuning; 1300 1301 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 1302 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1303 1304 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 1305 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; 1306 1307 if (of_id) 1308 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 1309 else 1310 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data); 1311 if (err) 1312 goto disable_ahb_clk; 1313 1314 sdhci_esdhc_imx_hwinit(host); 1315 1316 err = sdhci_add_host(host); 1317 if (err) 1318 goto disable_ahb_clk; 1319 1320 pm_runtime_set_active(&pdev->dev); 1321 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1322 pm_runtime_use_autosuspend(&pdev->dev); 1323 pm_suspend_ignore_children(&pdev->dev, 1); 1324 pm_runtime_enable(&pdev->dev); 1325 1326 return 0; 1327 1328 disable_ahb_clk: 1329 clk_disable_unprepare(imx_data->clk_ahb); 1330 disable_ipg_clk: 1331 clk_disable_unprepare(imx_data->clk_ipg); 1332 disable_per_clk: 1333 clk_disable_unprepare(imx_data->clk_per); 1334 free_sdhci: 1335 sdhci_pltfm_free(pdev); 1336 return err; 1337 } 1338 1339 static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 1340 { 1341 struct sdhci_host *host = platform_get_drvdata(pdev); 1342 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1343 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1344 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 1345 1346 pm_runtime_get_sync(&pdev->dev); 1347 pm_runtime_disable(&pdev->dev); 1348 pm_runtime_put_noidle(&pdev->dev); 1349 1350 sdhci_remove_host(host, dead); 1351 1352 clk_disable_unprepare(imx_data->clk_per); 1353 clk_disable_unprepare(imx_data->clk_ipg); 1354 clk_disable_unprepare(imx_data->clk_ahb); 1355 1356 sdhci_pltfm_free(pdev); 1357 1358 return 0; 1359 } 1360 1361 #ifdef CONFIG_PM_SLEEP 1362 static int sdhci_esdhc_suspend(struct device *dev) 1363 { 1364 struct sdhci_host *host = dev_get_drvdata(dev); 1365 1366 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1367 mmc_retune_needed(host->mmc); 1368 1369 return sdhci_suspend_host(host); 1370 } 1371 1372 static int sdhci_esdhc_resume(struct device *dev) 1373 { 1374 struct sdhci_host *host = dev_get_drvdata(dev); 1375 1376 /* re-initialize hw state in case it's lost in low power mode */ 1377 sdhci_esdhc_imx_hwinit(host); 1378 1379 return sdhci_resume_host(host); 1380 } 1381 #endif 1382 1383 #ifdef CONFIG_PM 1384 static int sdhci_esdhc_runtime_suspend(struct device *dev) 1385 { 1386 struct sdhci_host *host = dev_get_drvdata(dev); 1387 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1388 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1389 int ret; 1390 1391 ret = sdhci_runtime_suspend_host(host); 1392 1393 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1394 mmc_retune_needed(host->mmc); 1395 1396 if (!sdhci_sdio_irq_enabled(host)) { 1397 clk_disable_unprepare(imx_data->clk_per); 1398 clk_disable_unprepare(imx_data->clk_ipg); 1399 } 1400 clk_disable_unprepare(imx_data->clk_ahb); 1401 1402 return ret; 1403 } 1404 1405 static int sdhci_esdhc_runtime_resume(struct device *dev) 1406 { 1407 struct sdhci_host *host = dev_get_drvdata(dev); 1408 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1409 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1410 int err; 1411 1412 if (!sdhci_sdio_irq_enabled(host)) { 1413 err = clk_prepare_enable(imx_data->clk_per); 1414 if (err) 1415 return err; 1416 err = clk_prepare_enable(imx_data->clk_ipg); 1417 if (err) 1418 goto disable_per_clk; 1419 } 1420 err = clk_prepare_enable(imx_data->clk_ahb); 1421 if (err) 1422 goto disable_ipg_clk; 1423 err = sdhci_runtime_resume_host(host); 1424 if (err) 1425 goto disable_ahb_clk; 1426 1427 return 0; 1428 1429 disable_ahb_clk: 1430 clk_disable_unprepare(imx_data->clk_ahb); 1431 disable_ipg_clk: 1432 if (!sdhci_sdio_irq_enabled(host)) 1433 clk_disable_unprepare(imx_data->clk_ipg); 1434 disable_per_clk: 1435 if (!sdhci_sdio_irq_enabled(host)) 1436 clk_disable_unprepare(imx_data->clk_per); 1437 return err; 1438 } 1439 #endif 1440 1441 static const struct dev_pm_ops sdhci_esdhc_pmops = { 1442 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) 1443 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 1444 sdhci_esdhc_runtime_resume, NULL) 1445 }; 1446 1447 static struct platform_driver sdhci_esdhc_imx_driver = { 1448 .driver = { 1449 .name = "sdhci-esdhc-imx", 1450 .of_match_table = imx_esdhc_dt_ids, 1451 .pm = &sdhci_esdhc_pmops, 1452 }, 1453 .id_table = imx_esdhc_devtype, 1454 .probe = sdhci_esdhc_imx_probe, 1455 .remove = sdhci_esdhc_imx_remove, 1456 }; 1457 1458 module_platform_driver(sdhci_esdhc_imx_driver); 1459 1460 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1461 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 1462 MODULE_LICENSE("GPL v2"); 1463