1 /* 2 * Freescale eSDHC i.MX controller driver for the platform bus. 3 * 4 * derived from the OF-version. 5 * 6 * Copyright (c) 2010 Pengutronix e.K. 7 * Author: Wolfram Sang <w.sang@pengutronix.de> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License. 12 */ 13 14 #include <linux/io.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/clk.h> 18 #include <linux/gpio.h> 19 #include <linux/module.h> 20 #include <linux/slab.h> 21 #include <linux/mmc/host.h> 22 #include <linux/mmc/mmc.h> 23 #include <linux/mmc/sdio.h> 24 #include <linux/mmc/slot-gpio.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/of_gpio.h> 28 #include <linux/pinctrl/consumer.h> 29 #include <linux/platform_data/mmc-esdhc-imx.h> 30 #include <linux/pm_runtime.h> 31 #include "sdhci-pltfm.h" 32 #include "sdhci-esdhc.h" 33 34 #define ESDHC_CTRL_D3CD 0x08 35 /* VENDOR SPEC register */ 36 #define ESDHC_VENDOR_SPEC 0xc0 37 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 38 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 39 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 40 #define ESDHC_WTMK_LVL 0x44 41 #define ESDHC_MIX_CTRL 0x48 42 #define ESDHC_MIX_CTRL_DDREN (1 << 3) 43 #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 44 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 45 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 46 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 47 /* Bits 3 and 6 are not SDHCI standard definitions */ 48 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 49 /* Tuning bits */ 50 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 51 52 /* dll control register */ 53 #define ESDHC_DLL_CTRL 0x60 54 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 55 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 56 57 /* tune control register */ 58 #define ESDHC_TUNE_CTRL_STATUS 0x68 59 #define ESDHC_TUNE_CTRL_STEP 1 60 #define ESDHC_TUNE_CTRL_MIN 0 61 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 62 63 #define ESDHC_TUNING_CTRL 0xcc 64 #define ESDHC_STD_TUNING_EN (1 << 24) 65 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 66 #define ESDHC_TUNING_START_TAP 0x1 67 68 /* pinctrl state */ 69 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 70 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 71 72 /* 73 * Our interpretation of the SDHCI_HOST_CONTROL register 74 */ 75 #define ESDHC_CTRL_4BITBUS (0x1 << 1) 76 #define ESDHC_CTRL_8BITBUS (0x2 << 1) 77 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 78 79 /* 80 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: 81 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 82 * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 83 * Define this macro DMA error INT for fsl eSDHC 84 */ 85 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 86 87 /* 88 * The CMDTYPE of the CMD register (offset 0xE) should be set to 89 * "11" when the STOP CMD12 is issued on imx53 to abort one 90 * open ended multi-blk IO. Otherwise the TC INT wouldn't 91 * be generated. 92 * In exact block transfer, the controller doesn't complete the 93 * operations automatically as required at the end of the 94 * transfer and remains on hold if the abort command is not sent. 95 * As a result, the TC flag is not asserted and SW received timeout 96 * exeception. Bit1 of Vendor Spec registor is used to fix it. 97 */ 98 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 99 /* 100 * The flag enables the workaround for ESDHC errata ENGcm07207 which 101 * affects i.MX25 and i.MX35. 102 */ 103 #define ESDHC_FLAG_ENGCM07207 BIT(2) 104 /* 105 * The flag tells that the ESDHC controller is an USDHC block that is 106 * integrated on the i.MX6 series. 107 */ 108 #define ESDHC_FLAG_USDHC BIT(3) 109 /* The IP supports manual tuning process */ 110 #define ESDHC_FLAG_MAN_TUNING BIT(4) 111 /* The IP supports standard tuning process */ 112 #define ESDHC_FLAG_STD_TUNING BIT(5) 113 /* The IP has SDHCI_CAPABILITIES_1 register */ 114 #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 115 116 struct esdhc_soc_data { 117 u32 flags; 118 }; 119 120 static struct esdhc_soc_data esdhc_imx25_data = { 121 .flags = ESDHC_FLAG_ENGCM07207, 122 }; 123 124 static struct esdhc_soc_data esdhc_imx35_data = { 125 .flags = ESDHC_FLAG_ENGCM07207, 126 }; 127 128 static struct esdhc_soc_data esdhc_imx51_data = { 129 .flags = 0, 130 }; 131 132 static struct esdhc_soc_data esdhc_imx53_data = { 133 .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 134 }; 135 136 static struct esdhc_soc_data usdhc_imx6q_data = { 137 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, 138 }; 139 140 static struct esdhc_soc_data usdhc_imx6sl_data = { 141 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 142 | ESDHC_FLAG_HAVE_CAP1, 143 }; 144 145 struct pltfm_imx_data { 146 u32 scratchpad; 147 struct pinctrl *pinctrl; 148 struct pinctrl_state *pins_default; 149 struct pinctrl_state *pins_100mhz; 150 struct pinctrl_state *pins_200mhz; 151 const struct esdhc_soc_data *socdata; 152 struct esdhc_platform_data boarddata; 153 struct clk *clk_ipg; 154 struct clk *clk_ahb; 155 struct clk *clk_per; 156 enum { 157 NO_CMD_PENDING, /* no multiblock command pending*/ 158 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 159 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 160 } multiblock_status; 161 u32 is_ddr; 162 }; 163 164 static struct platform_device_id imx_esdhc_devtype[] = { 165 { 166 .name = "sdhci-esdhc-imx25", 167 .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 168 }, { 169 .name = "sdhci-esdhc-imx35", 170 .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 171 }, { 172 .name = "sdhci-esdhc-imx51", 173 .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 174 }, { 175 /* sentinel */ 176 } 177 }; 178 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 179 180 static const struct of_device_id imx_esdhc_dt_ids[] = { 181 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 182 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 183 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 184 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 185 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 186 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 187 { /* sentinel */ } 188 }; 189 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 190 191 static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 192 { 193 return data->socdata == &esdhc_imx25_data; 194 } 195 196 static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 197 { 198 return data->socdata == &esdhc_imx53_data; 199 } 200 201 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 202 { 203 return data->socdata == &usdhc_imx6q_data; 204 } 205 206 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 207 { 208 return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 209 } 210 211 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 212 { 213 void __iomem *base = host->ioaddr + (reg & ~0x3); 214 u32 shift = (reg & 0x3) * 8; 215 216 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 217 } 218 219 static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 220 { 221 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 222 struct pltfm_imx_data *imx_data = pltfm_host->priv; 223 u32 val = readl(host->ioaddr + reg); 224 225 if (unlikely(reg == SDHCI_PRESENT_STATE)) { 226 u32 fsl_prss = val; 227 /* save the least 20 bits */ 228 val = fsl_prss & 0x000FFFFF; 229 /* move dat[0-3] bits */ 230 val |= (fsl_prss & 0x0F000000) >> 4; 231 /* move cmd line bit */ 232 val |= (fsl_prss & 0x00800000) << 1; 233 } 234 235 if (unlikely(reg == SDHCI_CAPABILITIES)) { 236 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 237 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 238 val &= 0xffff0000; 239 240 /* In FSL esdhc IC module, only bit20 is used to indicate the 241 * ADMA2 capability of esdhc, but this bit is messed up on 242 * some SOCs (e.g. on MX25, MX35 this bit is set, but they 243 * don't actually support ADMA2). So set the BROKEN_ADMA 244 * uirk on MX25/35 platforms. 245 */ 246 247 if (val & SDHCI_CAN_DO_ADMA1) { 248 val &= ~SDHCI_CAN_DO_ADMA1; 249 val |= SDHCI_CAN_DO_ADMA2; 250 } 251 } 252 253 if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 254 if (esdhc_is_usdhc(imx_data)) { 255 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 256 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 257 else 258 /* imx6q/dl does not have cap_1 register, fake one */ 259 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 260 | SDHCI_SUPPORT_SDR50 261 | SDHCI_USE_SDR50_TUNING; 262 } 263 } 264 265 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 266 val = 0; 267 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 268 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 269 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 270 } 271 272 if (unlikely(reg == SDHCI_INT_STATUS)) { 273 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 274 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 275 val |= SDHCI_INT_ADMA_ERROR; 276 } 277 278 /* 279 * mask off the interrupt we get in response to the manually 280 * sent CMD12 281 */ 282 if ((imx_data->multiblock_status == WAIT_FOR_INT) && 283 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 284 val &= ~SDHCI_INT_RESPONSE; 285 writel(SDHCI_INT_RESPONSE, host->ioaddr + 286 SDHCI_INT_STATUS); 287 imx_data->multiblock_status = NO_CMD_PENDING; 288 } 289 } 290 291 return val; 292 } 293 294 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 295 { 296 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 297 struct pltfm_imx_data *imx_data = pltfm_host->priv; 298 u32 data; 299 300 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 301 if (val & SDHCI_INT_CARD_INT) { 302 /* 303 * Clear and then set D3CD bit to avoid missing the 304 * card interrupt. This is a eSDHC controller problem 305 * so we need to apply the following workaround: clear 306 * and set D3CD bit will make eSDHC re-sample the card 307 * interrupt. In case a card interrupt was lost, 308 * re-sample it by the following steps. 309 */ 310 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 311 data &= ~ESDHC_CTRL_D3CD; 312 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 313 data |= ESDHC_CTRL_D3CD; 314 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 315 } 316 } 317 318 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 319 && (reg == SDHCI_INT_STATUS) 320 && (val & SDHCI_INT_DATA_END))) { 321 u32 v; 322 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 323 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 324 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 325 326 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 327 { 328 /* send a manual CMD12 with RESPTYP=none */ 329 data = MMC_STOP_TRANSMISSION << 24 | 330 SDHCI_CMD_ABORTCMD << 16; 331 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 332 imx_data->multiblock_status = WAIT_FOR_INT; 333 } 334 } 335 336 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 337 if (val & SDHCI_INT_ADMA_ERROR) { 338 val &= ~SDHCI_INT_ADMA_ERROR; 339 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 340 } 341 } 342 343 writel(val, host->ioaddr + reg); 344 } 345 346 static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 347 { 348 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 349 struct pltfm_imx_data *imx_data = pltfm_host->priv; 350 u16 ret = 0; 351 u32 val; 352 353 if (unlikely(reg == SDHCI_HOST_VERSION)) { 354 reg ^= 2; 355 if (esdhc_is_usdhc(imx_data)) { 356 /* 357 * The usdhc register returns a wrong host version. 358 * Correct it here. 359 */ 360 return SDHCI_SPEC_300; 361 } 362 } 363 364 if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 365 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 366 if (val & ESDHC_VENDOR_SPEC_VSELECT) 367 ret |= SDHCI_CTRL_VDD_180; 368 369 if (esdhc_is_usdhc(imx_data)) { 370 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 371 val = readl(host->ioaddr + ESDHC_MIX_CTRL); 372 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 373 /* the std tuning bits is in ACMD12_ERR for imx6sl */ 374 val = readl(host->ioaddr + SDHCI_ACMD12_ERR); 375 } 376 377 if (val & ESDHC_MIX_CTRL_EXE_TUNE) 378 ret |= SDHCI_CTRL_EXEC_TUNING; 379 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 380 ret |= SDHCI_CTRL_TUNED_CLK; 381 382 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 383 384 return ret; 385 } 386 387 if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 388 if (esdhc_is_usdhc(imx_data)) { 389 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 390 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 391 /* Swap AC23 bit */ 392 if (m & ESDHC_MIX_CTRL_AC23EN) { 393 ret &= ~ESDHC_MIX_CTRL_AC23EN; 394 ret |= SDHCI_TRNS_AUTO_CMD23; 395 } 396 } else { 397 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 398 } 399 400 return ret; 401 } 402 403 return readw(host->ioaddr + reg); 404 } 405 406 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 407 { 408 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 409 struct pltfm_imx_data *imx_data = pltfm_host->priv; 410 u32 new_val = 0; 411 412 switch (reg) { 413 case SDHCI_CLOCK_CONTROL: 414 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 415 if (val & SDHCI_CLOCK_CARD_EN) 416 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 417 else 418 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 419 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 420 return; 421 case SDHCI_HOST_CONTROL2: 422 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 423 if (val & SDHCI_CTRL_VDD_180) 424 new_val |= ESDHC_VENDOR_SPEC_VSELECT; 425 else 426 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 427 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 428 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 429 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 430 if (val & SDHCI_CTRL_TUNED_CLK) 431 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 432 else 433 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 434 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 435 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 436 u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); 437 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 438 if (val & SDHCI_CTRL_TUNED_CLK) { 439 v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 440 } else { 441 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 442 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 443 } 444 445 if (val & SDHCI_CTRL_EXEC_TUNING) { 446 v |= ESDHC_MIX_CTRL_EXE_TUNE; 447 m |= ESDHC_MIX_CTRL_FBCLK_SEL; 448 } else { 449 v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 450 } 451 452 writel(v, host->ioaddr + SDHCI_ACMD12_ERR); 453 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 454 } 455 return; 456 case SDHCI_TRANSFER_MODE: 457 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 458 && (host->cmd->opcode == SD_IO_RW_EXTENDED) 459 && (host->cmd->data->blocks > 1) 460 && (host->cmd->data->flags & MMC_DATA_READ)) { 461 u32 v; 462 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 463 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 464 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 465 } 466 467 if (esdhc_is_usdhc(imx_data)) { 468 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 469 /* Swap AC23 bit */ 470 if (val & SDHCI_TRNS_AUTO_CMD23) { 471 val &= ~SDHCI_TRNS_AUTO_CMD23; 472 val |= ESDHC_MIX_CTRL_AC23EN; 473 } 474 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 475 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 476 } else { 477 /* 478 * Postpone this write, we must do it together with a 479 * command write that is down below. 480 */ 481 imx_data->scratchpad = val; 482 } 483 return; 484 case SDHCI_COMMAND: 485 if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 486 val |= SDHCI_CMD_ABORTCMD; 487 488 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 489 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 490 imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 491 492 if (esdhc_is_usdhc(imx_data)) 493 writel(val << 16, 494 host->ioaddr + SDHCI_TRANSFER_MODE); 495 else 496 writel(val << 16 | imx_data->scratchpad, 497 host->ioaddr + SDHCI_TRANSFER_MODE); 498 return; 499 case SDHCI_BLOCK_SIZE: 500 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 501 break; 502 } 503 esdhc_clrset_le(host, 0xffff, val, reg); 504 } 505 506 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 507 { 508 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 509 struct pltfm_imx_data *imx_data = pltfm_host->priv; 510 u32 new_val; 511 u32 mask; 512 513 switch (reg) { 514 case SDHCI_POWER_CONTROL: 515 /* 516 * FSL put some DMA bits here 517 * If your board has a regulator, code should be here 518 */ 519 return; 520 case SDHCI_HOST_CONTROL: 521 /* FSL messed up here, so we need to manually compose it. */ 522 new_val = val & SDHCI_CTRL_LED; 523 /* ensure the endianness */ 524 new_val |= ESDHC_HOST_CONTROL_LE; 525 /* bits 8&9 are reserved on mx25 */ 526 if (!is_imx25_esdhc(imx_data)) { 527 /* DMA mode bits are shifted */ 528 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 529 } 530 531 /* 532 * Do not touch buswidth bits here. This is done in 533 * esdhc_pltfm_bus_width. 534 * Do not touch the D3CD bit either which is used for the 535 * SDIO interrupt errata workaround. 536 */ 537 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 538 539 esdhc_clrset_le(host, mask, new_val, reg); 540 return; 541 } 542 esdhc_clrset_le(host, 0xff, val, reg); 543 544 /* 545 * The esdhc has a design violation to SDHC spec which tells 546 * that software reset should not affect card detection circuit. 547 * But esdhc clears its SYSCTL register bits [0..2] during the 548 * software reset. This will stop those clocks that card detection 549 * circuit relies on. To work around it, we turn the clocks on back 550 * to keep card detection circuit functional. 551 */ 552 if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { 553 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 554 /* 555 * The reset on usdhc fails to clear MIX_CTRL register. 556 * Do it manually here. 557 */ 558 if (esdhc_is_usdhc(imx_data)) { 559 /* the tuning bits should be kept during reset */ 560 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 561 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 562 host->ioaddr + ESDHC_MIX_CTRL); 563 imx_data->is_ddr = 0; 564 } 565 } 566 } 567 568 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 569 { 570 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 571 struct pltfm_imx_data *imx_data = pltfm_host->priv; 572 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 573 574 if (boarddata->f_max && (boarddata->f_max < pltfm_host->clock)) 575 return boarddata->f_max; 576 else 577 return pltfm_host->clock; 578 } 579 580 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 581 { 582 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 583 584 return pltfm_host->clock / 256 / 16; 585 } 586 587 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 588 unsigned int clock) 589 { 590 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 591 struct pltfm_imx_data *imx_data = pltfm_host->priv; 592 unsigned int host_clock = pltfm_host->clock; 593 int pre_div = 2; 594 int div = 1; 595 u32 temp, val; 596 597 if (clock == 0) { 598 host->mmc->actual_clock = 0; 599 600 if (esdhc_is_usdhc(imx_data)) { 601 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 602 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 603 host->ioaddr + ESDHC_VENDOR_SPEC); 604 } 605 return; 606 } 607 608 if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) 609 pre_div = 1; 610 611 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 612 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 613 | ESDHC_CLOCK_MASK); 614 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 615 616 while (host_clock / pre_div / 16 > clock && pre_div < 256) 617 pre_div *= 2; 618 619 while (host_clock / pre_div / div > clock && div < 16) 620 div++; 621 622 host->mmc->actual_clock = host_clock / pre_div / div; 623 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 624 clock, host->mmc->actual_clock); 625 626 if (imx_data->is_ddr) 627 pre_div >>= 2; 628 else 629 pre_div >>= 1; 630 div--; 631 632 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 633 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 634 | (div << ESDHC_DIVIDER_SHIFT) 635 | (pre_div << ESDHC_PREDIV_SHIFT)); 636 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 637 638 if (esdhc_is_usdhc(imx_data)) { 639 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 640 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 641 host->ioaddr + ESDHC_VENDOR_SPEC); 642 } 643 644 mdelay(1); 645 } 646 647 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 648 { 649 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 650 struct pltfm_imx_data *imx_data = pltfm_host->priv; 651 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 652 653 switch (boarddata->wp_type) { 654 case ESDHC_WP_GPIO: 655 return mmc_gpio_get_ro(host->mmc); 656 case ESDHC_WP_CONTROLLER: 657 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 658 SDHCI_WRITE_PROTECT); 659 case ESDHC_WP_NONE: 660 break; 661 } 662 663 return -ENOSYS; 664 } 665 666 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 667 { 668 u32 ctrl; 669 670 switch (width) { 671 case MMC_BUS_WIDTH_8: 672 ctrl = ESDHC_CTRL_8BITBUS; 673 break; 674 case MMC_BUS_WIDTH_4: 675 ctrl = ESDHC_CTRL_4BITBUS; 676 break; 677 default: 678 ctrl = 0; 679 break; 680 } 681 682 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 683 SDHCI_HOST_CONTROL); 684 } 685 686 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 687 { 688 u32 reg; 689 690 /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 691 mdelay(1); 692 693 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 694 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 695 ESDHC_MIX_CTRL_FBCLK_SEL; 696 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 697 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 698 dev_dbg(mmc_dev(host->mmc), 699 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 700 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 701 } 702 703 static void esdhc_post_tuning(struct sdhci_host *host) 704 { 705 u32 reg; 706 707 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 708 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 709 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 710 } 711 712 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 713 { 714 int min, max, avg, ret; 715 716 /* find the mininum delay first which can pass tuning */ 717 min = ESDHC_TUNE_CTRL_MIN; 718 while (min < ESDHC_TUNE_CTRL_MAX) { 719 esdhc_prepare_tuning(host, min); 720 if (!mmc_send_tuning(host->mmc)) 721 break; 722 min += ESDHC_TUNE_CTRL_STEP; 723 } 724 725 /* find the maxinum delay which can not pass tuning */ 726 max = min + ESDHC_TUNE_CTRL_STEP; 727 while (max < ESDHC_TUNE_CTRL_MAX) { 728 esdhc_prepare_tuning(host, max); 729 if (mmc_send_tuning(host->mmc)) { 730 max -= ESDHC_TUNE_CTRL_STEP; 731 break; 732 } 733 max += ESDHC_TUNE_CTRL_STEP; 734 } 735 736 /* use average delay to get the best timing */ 737 avg = (min + max) / 2; 738 esdhc_prepare_tuning(host, avg); 739 ret = mmc_send_tuning(host->mmc); 740 esdhc_post_tuning(host); 741 742 dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", 743 ret ? "failed" : "passed", avg, ret); 744 745 return ret; 746 } 747 748 static int esdhc_change_pinstate(struct sdhci_host *host, 749 unsigned int uhs) 750 { 751 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 752 struct pltfm_imx_data *imx_data = pltfm_host->priv; 753 struct pinctrl_state *pinctrl; 754 755 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 756 757 if (IS_ERR(imx_data->pinctrl) || 758 IS_ERR(imx_data->pins_default) || 759 IS_ERR(imx_data->pins_100mhz) || 760 IS_ERR(imx_data->pins_200mhz)) 761 return -EINVAL; 762 763 switch (uhs) { 764 case MMC_TIMING_UHS_SDR50: 765 pinctrl = imx_data->pins_100mhz; 766 break; 767 case MMC_TIMING_UHS_SDR104: 768 case MMC_TIMING_MMC_HS200: 769 pinctrl = imx_data->pins_200mhz; 770 break; 771 default: 772 /* back to default state for other legacy timing */ 773 pinctrl = imx_data->pins_default; 774 } 775 776 return pinctrl_select_state(imx_data->pinctrl, pinctrl); 777 } 778 779 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 780 { 781 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 782 struct pltfm_imx_data *imx_data = pltfm_host->priv; 783 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 784 785 switch (timing) { 786 case MMC_TIMING_UHS_SDR12: 787 case MMC_TIMING_UHS_SDR25: 788 case MMC_TIMING_UHS_SDR50: 789 case MMC_TIMING_UHS_SDR104: 790 case MMC_TIMING_MMC_HS200: 791 break; 792 case MMC_TIMING_UHS_DDR50: 793 case MMC_TIMING_MMC_DDR52: 794 writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | 795 ESDHC_MIX_CTRL_DDREN, 796 host->ioaddr + ESDHC_MIX_CTRL); 797 imx_data->is_ddr = 1; 798 if (boarddata->delay_line) { 799 u32 v; 800 v = boarddata->delay_line << 801 ESDHC_DLL_OVERRIDE_VAL_SHIFT | 802 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 803 if (is_imx53_esdhc(imx_data)) 804 v <<= 1; 805 writel(v, host->ioaddr + ESDHC_DLL_CTRL); 806 } 807 break; 808 } 809 810 esdhc_change_pinstate(host, timing); 811 } 812 813 static void esdhc_reset(struct sdhci_host *host, u8 mask) 814 { 815 sdhci_reset(host, mask); 816 817 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 818 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 819 } 820 821 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 822 { 823 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 824 struct pltfm_imx_data *imx_data = pltfm_host->priv; 825 826 return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27; 827 } 828 829 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 830 { 831 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 832 struct pltfm_imx_data *imx_data = pltfm_host->priv; 833 834 /* use maximum timeout counter */ 835 sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 836 SDHCI_TIMEOUT_CONTROL); 837 } 838 839 static struct sdhci_ops sdhci_esdhc_ops = { 840 .read_l = esdhc_readl_le, 841 .read_w = esdhc_readw_le, 842 .write_l = esdhc_writel_le, 843 .write_w = esdhc_writew_le, 844 .write_b = esdhc_writeb_le, 845 .set_clock = esdhc_pltfm_set_clock, 846 .get_max_clock = esdhc_pltfm_get_max_clock, 847 .get_min_clock = esdhc_pltfm_get_min_clock, 848 .get_max_timeout_count = esdhc_get_max_timeout_count, 849 .get_ro = esdhc_pltfm_get_ro, 850 .set_timeout = esdhc_set_timeout, 851 .set_bus_width = esdhc_pltfm_set_bus_width, 852 .set_uhs_signaling = esdhc_set_uhs_signaling, 853 .reset = esdhc_reset, 854 }; 855 856 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 857 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 858 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 859 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 860 | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 861 .ops = &sdhci_esdhc_ops, 862 }; 863 864 #ifdef CONFIG_OF 865 static int 866 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 867 struct esdhc_platform_data *boarddata) 868 { 869 struct device_node *np = pdev->dev.of_node; 870 871 if (!np) 872 return -ENODEV; 873 874 if (of_get_property(np, "non-removable", NULL)) 875 boarddata->cd_type = ESDHC_CD_PERMANENT; 876 877 if (of_get_property(np, "fsl,cd-controller", NULL)) 878 boarddata->cd_type = ESDHC_CD_CONTROLLER; 879 880 if (of_get_property(np, "fsl,wp-controller", NULL)) 881 boarddata->wp_type = ESDHC_WP_CONTROLLER; 882 883 boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 884 if (gpio_is_valid(boarddata->cd_gpio)) 885 boarddata->cd_type = ESDHC_CD_GPIO; 886 887 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 888 if (gpio_is_valid(boarddata->wp_gpio)) 889 boarddata->wp_type = ESDHC_WP_GPIO; 890 891 of_property_read_u32(np, "bus-width", &boarddata->max_bus_width); 892 893 of_property_read_u32(np, "max-frequency", &boarddata->f_max); 894 895 if (of_find_property(np, "no-1-8-v", NULL)) 896 boarddata->support_vsel = false; 897 else 898 boarddata->support_vsel = true; 899 900 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 901 boarddata->delay_line = 0; 902 903 return 0; 904 } 905 #else 906 static inline int 907 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 908 struct esdhc_platform_data *boarddata) 909 { 910 return -ENODEV; 911 } 912 #endif 913 914 static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 915 { 916 const struct of_device_id *of_id = 917 of_match_device(imx_esdhc_dt_ids, &pdev->dev); 918 struct sdhci_pltfm_host *pltfm_host; 919 struct sdhci_host *host; 920 struct esdhc_platform_data *boarddata; 921 int err; 922 struct pltfm_imx_data *imx_data; 923 924 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0); 925 if (IS_ERR(host)) 926 return PTR_ERR(host); 927 928 pltfm_host = sdhci_priv(host); 929 930 imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); 931 if (!imx_data) { 932 err = -ENOMEM; 933 goto free_sdhci; 934 } 935 936 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 937 pdev->id_entry->driver_data; 938 pltfm_host->priv = imx_data; 939 940 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 941 if (IS_ERR(imx_data->clk_ipg)) { 942 err = PTR_ERR(imx_data->clk_ipg); 943 goto free_sdhci; 944 } 945 946 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 947 if (IS_ERR(imx_data->clk_ahb)) { 948 err = PTR_ERR(imx_data->clk_ahb); 949 goto free_sdhci; 950 } 951 952 imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 953 if (IS_ERR(imx_data->clk_per)) { 954 err = PTR_ERR(imx_data->clk_per); 955 goto free_sdhci; 956 } 957 958 pltfm_host->clk = imx_data->clk_per; 959 pltfm_host->clock = clk_get_rate(pltfm_host->clk); 960 clk_prepare_enable(imx_data->clk_per); 961 clk_prepare_enable(imx_data->clk_ipg); 962 clk_prepare_enable(imx_data->clk_ahb); 963 964 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 965 if (IS_ERR(imx_data->pinctrl)) { 966 err = PTR_ERR(imx_data->pinctrl); 967 goto disable_clk; 968 } 969 970 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, 971 PINCTRL_STATE_DEFAULT); 972 if (IS_ERR(imx_data->pins_default)) 973 dev_warn(mmc_dev(host->mmc), "could not get default state\n"); 974 975 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 976 977 if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) 978 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ 979 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK 980 | SDHCI_QUIRK_BROKEN_ADMA; 981 982 /* 983 * The imx6q ROM code will change the default watermark level setting 984 * to something insane. Change it back here. 985 */ 986 if (esdhc_is_usdhc(imx_data)) { 987 writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); 988 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 989 host->mmc->caps |= MMC_CAP_1_8V_DDR; 990 } 991 992 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 993 sdhci_esdhc_ops.platform_execute_tuning = 994 esdhc_executing_tuning; 995 996 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 997 writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) | 998 ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP, 999 host->ioaddr + ESDHC_TUNING_CTRL); 1000 1001 boarddata = &imx_data->boarddata; 1002 if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) { 1003 if (!host->mmc->parent->platform_data) { 1004 dev_err(mmc_dev(host->mmc), "no board data!\n"); 1005 err = -EINVAL; 1006 goto disable_clk; 1007 } 1008 imx_data->boarddata = *((struct esdhc_platform_data *) 1009 host->mmc->parent->platform_data); 1010 } 1011 1012 /* write_protect */ 1013 if (boarddata->wp_type == ESDHC_WP_GPIO) { 1014 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); 1015 if (err) { 1016 dev_err(mmc_dev(host->mmc), 1017 "failed to request write-protect gpio!\n"); 1018 goto disable_clk; 1019 } 1020 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 1021 } 1022 1023 /* card_detect */ 1024 switch (boarddata->cd_type) { 1025 case ESDHC_CD_GPIO: 1026 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); 1027 if (err) { 1028 dev_err(mmc_dev(host->mmc), 1029 "failed to request card-detect gpio!\n"); 1030 goto disable_clk; 1031 } 1032 /* fall through */ 1033 1034 case ESDHC_CD_CONTROLLER: 1035 /* we have a working card_detect back */ 1036 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1037 break; 1038 1039 case ESDHC_CD_PERMANENT: 1040 host->mmc->caps |= MMC_CAP_NONREMOVABLE; 1041 break; 1042 1043 case ESDHC_CD_NONE: 1044 break; 1045 } 1046 1047 switch (boarddata->max_bus_width) { 1048 case 8: 1049 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 1050 break; 1051 case 4: 1052 host->mmc->caps |= MMC_CAP_4_BIT_DATA; 1053 break; 1054 case 1: 1055 default: 1056 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 1057 break; 1058 } 1059 1060 /* sdr50 and sdr104 needs work on 1.8v signal voltage */ 1061 if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) && 1062 !IS_ERR(imx_data->pins_default)) { 1063 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 1064 ESDHC_PINCTRL_STATE_100MHZ); 1065 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 1066 ESDHC_PINCTRL_STATE_200MHZ); 1067 if (IS_ERR(imx_data->pins_100mhz) || 1068 IS_ERR(imx_data->pins_200mhz)) { 1069 dev_warn(mmc_dev(host->mmc), 1070 "could not get ultra high speed state, work on normal mode\n"); 1071 /* fall back to not support uhs by specify no 1.8v quirk */ 1072 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1073 } 1074 } else { 1075 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1076 } 1077 1078 err = sdhci_add_host(host); 1079 if (err) 1080 goto disable_clk; 1081 1082 pm_runtime_set_active(&pdev->dev); 1083 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1084 pm_runtime_use_autosuspend(&pdev->dev); 1085 pm_suspend_ignore_children(&pdev->dev, 1); 1086 pm_runtime_enable(&pdev->dev); 1087 1088 return 0; 1089 1090 disable_clk: 1091 clk_disable_unprepare(imx_data->clk_per); 1092 clk_disable_unprepare(imx_data->clk_ipg); 1093 clk_disable_unprepare(imx_data->clk_ahb); 1094 free_sdhci: 1095 sdhci_pltfm_free(pdev); 1096 return err; 1097 } 1098 1099 static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 1100 { 1101 struct sdhci_host *host = platform_get_drvdata(pdev); 1102 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1103 struct pltfm_imx_data *imx_data = pltfm_host->priv; 1104 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 1105 1106 pm_runtime_get_sync(&pdev->dev); 1107 pm_runtime_disable(&pdev->dev); 1108 pm_runtime_put_noidle(&pdev->dev); 1109 1110 sdhci_remove_host(host, dead); 1111 1112 clk_disable_unprepare(imx_data->clk_per); 1113 clk_disable_unprepare(imx_data->clk_ipg); 1114 clk_disable_unprepare(imx_data->clk_ahb); 1115 1116 sdhci_pltfm_free(pdev); 1117 1118 return 0; 1119 } 1120 1121 #ifdef CONFIG_PM 1122 static int sdhci_esdhc_runtime_suspend(struct device *dev) 1123 { 1124 struct sdhci_host *host = dev_get_drvdata(dev); 1125 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1126 struct pltfm_imx_data *imx_data = pltfm_host->priv; 1127 int ret; 1128 1129 ret = sdhci_runtime_suspend_host(host); 1130 1131 if (!sdhci_sdio_irq_enabled(host)) { 1132 clk_disable_unprepare(imx_data->clk_per); 1133 clk_disable_unprepare(imx_data->clk_ipg); 1134 } 1135 clk_disable_unprepare(imx_data->clk_ahb); 1136 1137 return ret; 1138 } 1139 1140 static int sdhci_esdhc_runtime_resume(struct device *dev) 1141 { 1142 struct sdhci_host *host = dev_get_drvdata(dev); 1143 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1144 struct pltfm_imx_data *imx_data = pltfm_host->priv; 1145 1146 if (!sdhci_sdio_irq_enabled(host)) { 1147 clk_prepare_enable(imx_data->clk_per); 1148 clk_prepare_enable(imx_data->clk_ipg); 1149 } 1150 clk_prepare_enable(imx_data->clk_ahb); 1151 1152 return sdhci_runtime_resume_host(host); 1153 } 1154 #endif 1155 1156 static const struct dev_pm_ops sdhci_esdhc_pmops = { 1157 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume) 1158 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 1159 sdhci_esdhc_runtime_resume, NULL) 1160 }; 1161 1162 static struct platform_driver sdhci_esdhc_imx_driver = { 1163 .driver = { 1164 .name = "sdhci-esdhc-imx", 1165 .of_match_table = imx_esdhc_dt_ids, 1166 .pm = &sdhci_esdhc_pmops, 1167 }, 1168 .id_table = imx_esdhc_devtype, 1169 .probe = sdhci_esdhc_imx_probe, 1170 .remove = sdhci_esdhc_imx_remove, 1171 }; 1172 1173 module_platform_driver(sdhci_esdhc_imx_driver); 1174 1175 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1176 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); 1177 MODULE_LICENSE("GPL v2"); 1178