1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Freescale eSDHC i.MX controller driver for the platform bus. 4 * 5 * derived from the OF-version. 6 * 7 * Copyright (c) 2010 Pengutronix e.K. 8 * Author: Wolfram Sang <kernel@pengutronix.de> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/delay.h> 15 #include <linux/err.h> 16 #include <linux/clk.h> 17 #include <linux/module.h> 18 #include <linux/slab.h> 19 #include <linux/pm_qos.h> 20 #include <linux/mmc/host.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/mmc/sdio.h> 23 #include <linux/mmc/slot-gpio.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/pm_runtime.h> 28 #include "sdhci-cqhci.h" 29 #include "sdhci-pltfm.h" 30 #include "sdhci-esdhc.h" 31 #include "cqhci.h" 32 33 #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f 34 #define ESDHC_CTRL_D3CD 0x08 35 #define ESDHC_BURST_LEN_EN_INCR (1 << 27) 36 /* VENDOR SPEC register */ 37 #define ESDHC_VENDOR_SPEC 0xc0 38 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 39 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 40 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 41 #define ESDHC_DEBUG_SEL_AND_STATUS_REG 0xc2 42 #define ESDHC_DEBUG_SEL_REG 0xc3 43 #define ESDHC_DEBUG_SEL_MASK 0xf 44 #define ESDHC_DEBUG_SEL_CMD_STATE 1 45 #define ESDHC_DEBUG_SEL_DATA_STATE 2 46 #define ESDHC_DEBUG_SEL_TRANS_STATE 3 47 #define ESDHC_DEBUG_SEL_DMA_STATE 4 48 #define ESDHC_DEBUG_SEL_ADMA_STATE 5 49 #define ESDHC_DEBUG_SEL_FIFO_STATE 6 50 #define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE 7 51 #define ESDHC_WTMK_LVL 0x44 52 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 53 #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF 54 #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0 55 #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000 56 #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16 57 #define ESDHC_WTMK_LVL_WML_VAL_DEF 64 58 #define ESDHC_WTMK_LVL_WML_VAL_MAX 128 59 #define ESDHC_MIX_CTRL 0x48 60 #define ESDHC_MIX_CTRL_DDREN (1 << 3) 61 #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 62 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 63 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 64 #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) 65 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 66 #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 67 #define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27) 68 /* Bits 3 and 6 are not SDHCI standard definitions */ 69 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 70 /* Tuning bits */ 71 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 72 73 /* dll control register */ 74 #define ESDHC_DLL_CTRL 0x60 75 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 76 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 77 78 /* tune control register */ 79 #define ESDHC_TUNE_CTRL_STATUS 0x68 80 #define ESDHC_TUNE_CTRL_STEP 1 81 #define ESDHC_TUNE_CTRL_MIN 0 82 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 83 84 /* strobe dll register */ 85 #define ESDHC_STROBE_DLL_CTRL 0x70 86 #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) 87 #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) 88 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7 89 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 90 #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20) 91 92 #define ESDHC_STROBE_DLL_STATUS 0x74 93 #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) 94 #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 95 96 #define ESDHC_VEND_SPEC2 0xc8 97 #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8) 98 #define ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN (1 << 4) 99 #define ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN (0 << 4) 100 #define ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN (2 << 4) 101 #define ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN (1 << 6) 102 #define ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK (7 << 4) 103 104 #define ESDHC_TUNING_CTRL 0xcc 105 #define ESDHC_STD_TUNING_EN (1 << 24) 106 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 107 #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 108 #define ESDHC_TUNING_START_TAP_MASK 0x7f 109 #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE (1 << 7) 110 #define ESDHC_TUNING_STEP_DEFAULT 0x1 111 #define ESDHC_TUNING_STEP_MASK 0x00070000 112 #define ESDHC_TUNING_STEP_SHIFT 16 113 114 /* pinctrl state */ 115 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 116 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 117 118 /* 119 * Our interpretation of the SDHCI_HOST_CONTROL register 120 */ 121 #define ESDHC_CTRL_4BITBUS (0x1 << 1) 122 #define ESDHC_CTRL_8BITBUS (0x2 << 1) 123 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 124 #define USDHC_GET_BUSWIDTH(c) (c & ESDHC_CTRL_BUSWIDTH_MASK) 125 126 /* 127 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC: 128 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 129 * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 130 * Define this macro DMA error INT for fsl eSDHC 131 */ 132 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 133 134 /* the address offset of CQHCI */ 135 #define ESDHC_CQHCI_ADDR_OFFSET 0x100 136 137 /* 138 * The CMDTYPE of the CMD register (offset 0xE) should be set to 139 * "11" when the STOP CMD12 is issued on imx53 to abort one 140 * open ended multi-blk IO. Otherwise the TC INT wouldn't 141 * be generated. 142 * In exact block transfer, the controller doesn't complete the 143 * operations automatically as required at the end of the 144 * transfer and remains on hold if the abort command is not sent. 145 * As a result, the TC flag is not asserted and SW received timeout 146 * exception. Bit1 of Vendor Spec register is used to fix it. 147 */ 148 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 149 /* 150 * The flag tells that the ESDHC controller is an USDHC block that is 151 * integrated on the i.MX6 series. 152 */ 153 #define ESDHC_FLAG_USDHC BIT(3) 154 /* The IP supports manual tuning process */ 155 #define ESDHC_FLAG_MAN_TUNING BIT(4) 156 /* The IP supports standard tuning process */ 157 #define ESDHC_FLAG_STD_TUNING BIT(5) 158 /* The IP has SDHCI_CAPABILITIES_1 register */ 159 #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 160 /* 161 * The IP has erratum ERR004536 162 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 163 * when reading data from the card 164 * This flag is also set for i.MX25 and i.MX35 in order to get 165 * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits). 166 */ 167 #define ESDHC_FLAG_ERR004536 BIT(7) 168 /* The IP supports HS200 mode */ 169 #define ESDHC_FLAG_HS200 BIT(8) 170 /* The IP supports HS400 mode */ 171 #define ESDHC_FLAG_HS400 BIT(9) 172 /* 173 * The IP has errata ERR010450 174 * uSDHC: At 1.8V due to the I/O timing limit, for SDR mode, SD card 175 * clock can't exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz. 176 */ 177 #define ESDHC_FLAG_ERR010450 BIT(10) 178 /* The IP supports HS400ES mode */ 179 #define ESDHC_FLAG_HS400_ES BIT(11) 180 /* The IP has Host Controller Interface for Command Queuing */ 181 #define ESDHC_FLAG_CQHCI BIT(12) 182 /* need request pmqos during low power */ 183 #define ESDHC_FLAG_PMQOS BIT(13) 184 /* The IP state got lost in low power mode */ 185 #define ESDHC_FLAG_STATE_LOST_IN_LPMODE BIT(14) 186 /* The IP lost clock rate in PM_RUNTIME */ 187 #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME BIT(15) 188 /* 189 * The IP do not support the ACMD23 feature completely when use ADMA mode. 190 * In ADMA mode, it only use the 16 bit block count of the register 0x4 191 * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will 192 * ignore the upper 16 bit of the CMD23's argument. This will block the reliable 193 * write operation in RPMB, because RPMB reliable write need to set the bit31 194 * of the CMD23's argument. 195 * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA 196 * do not has this limitation. so when these SoC use ADMA mode, it need to 197 * disable the ACMD23 feature. 198 */ 199 #define ESDHC_FLAG_BROKEN_AUTO_CMD23 BIT(16) 200 201 /* ERR004536 is not applicable for the IP */ 202 #define ESDHC_FLAG_SKIP_ERR004536 BIT(17) 203 204 enum wp_types { 205 ESDHC_WP_NONE, /* no WP, neither controller nor gpio */ 206 ESDHC_WP_CONTROLLER, /* mmc controller internal WP */ 207 ESDHC_WP_GPIO, /* external gpio pin for WP */ 208 }; 209 210 enum cd_types { 211 ESDHC_CD_NONE, /* no CD, neither controller nor gpio */ 212 ESDHC_CD_CONTROLLER, /* mmc controller internal CD */ 213 ESDHC_CD_GPIO, /* external gpio pin for CD */ 214 ESDHC_CD_PERMANENT, /* no CD, card permanently wired to host */ 215 }; 216 217 /* 218 * struct esdhc_platform_data - platform data for esdhc on i.MX 219 * 220 * ESDHC_WP(CD)_CONTROLLER type is not available on i.MX25/35. 221 * 222 * @wp_type: type of write_protect method (see wp_types enum above) 223 * @cd_type: type of card_detect method (see cd_types enum above) 224 */ 225 226 struct esdhc_platform_data { 227 enum wp_types wp_type; 228 enum cd_types cd_type; 229 int max_bus_width; 230 unsigned int delay_line; 231 unsigned int tuning_step; /* The delay cell steps in tuning procedure */ 232 unsigned int tuning_start_tap; /* The start delay cell point in tuning procedure */ 233 unsigned int strobe_dll_delay_target; /* The delay cell for strobe pad (read clock) */ 234 }; 235 236 struct esdhc_soc_data { 237 u32 flags; 238 u32 quirks; 239 }; 240 241 static const struct esdhc_soc_data esdhc_imx25_data = { 242 .flags = ESDHC_FLAG_ERR004536, 243 }; 244 245 static const struct esdhc_soc_data esdhc_imx35_data = { 246 .flags = ESDHC_FLAG_ERR004536, 247 }; 248 249 static const struct esdhc_soc_data esdhc_imx51_data = { 250 .flags = 0, 251 }; 252 253 static const struct esdhc_soc_data esdhc_imx53_data = { 254 .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 255 }; 256 257 static const struct esdhc_soc_data usdhc_imx6q_data = { 258 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 259 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 260 }; 261 262 static const struct esdhc_soc_data usdhc_imx6sl_data = { 263 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 264 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 265 | ESDHC_FLAG_HS200 266 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 267 }; 268 269 static const struct esdhc_soc_data usdhc_imx6sll_data = { 270 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 271 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 272 | ESDHC_FLAG_HS400 273 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 274 }; 275 276 static const struct esdhc_soc_data usdhc_imx6sx_data = { 277 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 278 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 279 | ESDHC_FLAG_STATE_LOST_IN_LPMODE 280 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 281 }; 282 283 static const struct esdhc_soc_data usdhc_imx6ull_data = { 284 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 285 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 286 | ESDHC_FLAG_ERR010450 287 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 288 }; 289 290 static const struct esdhc_soc_data usdhc_imx7d_data = { 291 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 292 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 293 | ESDHC_FLAG_HS400 294 | ESDHC_FLAG_STATE_LOST_IN_LPMODE 295 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 296 }; 297 298 static struct esdhc_soc_data usdhc_s32g2_data = { 299 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 300 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 301 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 302 | ESDHC_FLAG_SKIP_ERR004536, 303 }; 304 305 static struct esdhc_soc_data usdhc_imx7ulp_data = { 306 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 307 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 308 | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400 309 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 310 .quirks = SDHCI_QUIRK_NO_LED, 311 }; 312 static struct esdhc_soc_data usdhc_imxrt1050_data = { 313 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 314 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, 315 .quirks = SDHCI_QUIRK_NO_LED, 316 }; 317 318 static struct esdhc_soc_data usdhc_imx8qxp_data = { 319 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 320 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 321 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 322 | ESDHC_FLAG_STATE_LOST_IN_LPMODE 323 | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME, 324 .quirks = SDHCI_QUIRK_NO_LED, 325 }; 326 327 static struct esdhc_soc_data usdhc_imx8mm_data = { 328 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 329 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 330 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 331 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 332 .quirks = SDHCI_QUIRK_NO_LED, 333 }; 334 335 struct pltfm_imx_data { 336 u32 scratchpad; 337 struct pinctrl *pinctrl; 338 struct pinctrl_state *pins_100mhz; 339 struct pinctrl_state *pins_200mhz; 340 const struct esdhc_soc_data *socdata; 341 struct esdhc_platform_data boarddata; 342 struct clk *clk_ipg; 343 struct clk *clk_ahb; 344 struct clk *clk_per; 345 unsigned int actual_clock; 346 347 /* 348 * USDHC has one limition, require the SDIO device a different 349 * register setting. Driver has to recognize card type during 350 * the card init, but at this stage, mmc_host->card is not 351 * available. So involve this field to save the card type 352 * during card init through usdhc_init_card(). 353 */ 354 unsigned int init_card_type; 355 356 enum { 357 NO_CMD_PENDING, /* no multiblock command pending */ 358 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 359 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 360 } multiblock_status; 361 u32 is_ddr; 362 struct pm_qos_request pm_qos_req; 363 }; 364 365 static const struct of_device_id imx_esdhc_dt_ids[] = { 366 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 367 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 368 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 369 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 370 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 371 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 372 { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, }, 373 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 374 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, }, 375 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, 376 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, }, 377 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, }, 378 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, }, 379 { .compatible = "fsl,imxrt1050-usdhc", .data = &usdhc_imxrt1050_data, }, 380 { .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, }, 381 { /* sentinel */ } 382 }; 383 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 384 385 static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 386 { 387 return data->socdata == &esdhc_imx25_data; 388 } 389 390 static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 391 { 392 return data->socdata == &esdhc_imx53_data; 393 } 394 395 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 396 { 397 return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 398 } 399 400 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 401 { 402 void __iomem *base = host->ioaddr + (reg & ~0x3); 403 u32 shift = (reg & 0x3) * 8; 404 405 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 406 } 407 408 #define DRIVER_NAME "sdhci-esdhc-imx" 409 #define ESDHC_IMX_DUMP(f, x...) \ 410 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) 411 static void esdhc_dump_debug_regs(struct sdhci_host *host) 412 { 413 int i; 414 char *debug_status[7] = { 415 "cmd debug status", 416 "data debug status", 417 "trans debug status", 418 "dma debug status", 419 "adma debug status", 420 "fifo debug status", 421 "async fifo debug status" 422 }; 423 424 ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n"); 425 for (i = 0; i < 7; i++) { 426 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 427 ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG); 428 ESDHC_IMX_DUMP("%s: 0x%04x\n", debug_status[i], 429 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG)); 430 } 431 432 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG); 433 434 } 435 436 static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host) 437 { 438 u32 present_state; 439 int ret; 440 441 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state, 442 (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100); 443 if (ret == -ETIMEDOUT) 444 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__); 445 } 446 447 /* Enable the auto tuning circuit to check the CMD line and BUS line */ 448 static inline void usdhc_auto_tuning_mode_sel_and_en(struct sdhci_host *host) 449 { 450 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 451 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 452 u32 buswidth, auto_tune_buswidth; 453 u32 reg; 454 455 buswidth = USDHC_GET_BUSWIDTH(readl(host->ioaddr + SDHCI_HOST_CONTROL)); 456 457 switch (buswidth) { 458 case ESDHC_CTRL_8BITBUS: 459 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN; 460 break; 461 case ESDHC_CTRL_4BITBUS: 462 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN; 463 break; 464 default: /* 1BITBUS */ 465 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN; 466 break; 467 } 468 469 /* 470 * For USDHC, auto tuning circuit can not handle the async sdio 471 * device interrupt correctly. When sdio device use 4 data lines, 472 * async sdio interrupt will use the shared DAT[1], if enable auto 473 * tuning circuit check these 4 data lines, include the DAT[1], 474 * this circuit will detect this interrupt, take this as a data on 475 * DAT[1], and adjust the delay cell wrongly. 476 * This is the hardware design limitation, to avoid this, for sdio 477 * device, config the auto tuning circuit only check DAT[0] and CMD 478 * line. 479 */ 480 if (imx_data->init_card_type == MMC_TYPE_SDIO) 481 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN; 482 483 esdhc_clrset_le(host, ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK, 484 auto_tune_buswidth | ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN, 485 ESDHC_VEND_SPEC2); 486 487 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 488 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 489 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 490 } 491 492 static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 493 { 494 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 495 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 496 u32 val = readl(host->ioaddr + reg); 497 498 if (unlikely(reg == SDHCI_PRESENT_STATE)) { 499 u32 fsl_prss = val; 500 /* save the least 20 bits */ 501 val = fsl_prss & 0x000FFFFF; 502 /* move dat[0-3] bits */ 503 val |= (fsl_prss & 0x0F000000) >> 4; 504 /* move cmd line bit */ 505 val |= (fsl_prss & 0x00800000) << 1; 506 } 507 508 if (unlikely(reg == SDHCI_CAPABILITIES)) { 509 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 510 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 511 val &= 0xffff0000; 512 513 /* In FSL esdhc IC module, only bit20 is used to indicate the 514 * ADMA2 capability of esdhc, but this bit is messed up on 515 * some SOCs (e.g. on MX25, MX35 this bit is set, but they 516 * don't actually support ADMA2). So set the BROKEN_ADMA 517 * quirk on MX25/35 platforms. 518 */ 519 520 if (val & SDHCI_CAN_DO_ADMA1) { 521 val &= ~SDHCI_CAN_DO_ADMA1; 522 val |= SDHCI_CAN_DO_ADMA2; 523 } 524 } 525 526 if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 527 if (esdhc_is_usdhc(imx_data)) { 528 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 529 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 530 else 531 /* imx6q/dl does not have cap_1 register, fake one */ 532 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 533 | SDHCI_SUPPORT_SDR50 534 | SDHCI_USE_SDR50_TUNING 535 | FIELD_PREP(SDHCI_RETUNING_MODE_MASK, 536 SDHCI_TUNING_MODE_3); 537 538 /* 539 * Do not advertise faster UHS modes if there are no 540 * pinctrl states for 100MHz/200MHz. 541 */ 542 if (IS_ERR_OR_NULL(imx_data->pins_100mhz)) 543 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); 544 if (IS_ERR_OR_NULL(imx_data->pins_200mhz)) 545 val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400); 546 } 547 } 548 549 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 550 val = 0; 551 val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF); 552 val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF); 553 val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF); 554 } 555 556 if (unlikely(reg == SDHCI_INT_STATUS)) { 557 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 558 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 559 val |= SDHCI_INT_ADMA_ERROR; 560 } 561 562 /* 563 * mask off the interrupt we get in response to the manually 564 * sent CMD12 565 */ 566 if ((imx_data->multiblock_status == WAIT_FOR_INT) && 567 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 568 val &= ~SDHCI_INT_RESPONSE; 569 writel(SDHCI_INT_RESPONSE, host->ioaddr + 570 SDHCI_INT_STATUS); 571 imx_data->multiblock_status = NO_CMD_PENDING; 572 } 573 } 574 575 return val; 576 } 577 578 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 579 { 580 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 581 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 582 u32 data; 583 584 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || 585 reg == SDHCI_INT_STATUS)) { 586 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 587 /* 588 * Clear and then set D3CD bit to avoid missing the 589 * card interrupt. This is an eSDHC controller problem 590 * so we need to apply the following workaround: clear 591 * and set D3CD bit will make eSDHC re-sample the card 592 * interrupt. In case a card interrupt was lost, 593 * re-sample it by the following steps. 594 */ 595 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 596 data &= ~ESDHC_CTRL_D3CD; 597 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 598 data |= ESDHC_CTRL_D3CD; 599 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 600 } 601 602 if (val & SDHCI_INT_ADMA_ERROR) { 603 val &= ~SDHCI_INT_ADMA_ERROR; 604 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 605 } 606 } 607 608 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 609 && (reg == SDHCI_INT_STATUS) 610 && (val & SDHCI_INT_DATA_END))) { 611 u32 v; 612 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 613 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 614 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 615 616 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 617 { 618 /* send a manual CMD12 with RESPTYP=none */ 619 data = MMC_STOP_TRANSMISSION << 24 | 620 SDHCI_CMD_ABORTCMD << 16; 621 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 622 imx_data->multiblock_status = WAIT_FOR_INT; 623 } 624 } 625 626 writel(val, host->ioaddr + reg); 627 } 628 629 static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 630 { 631 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 632 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 633 u16 ret = 0; 634 u32 val; 635 636 if (unlikely(reg == SDHCI_HOST_VERSION)) { 637 reg ^= 2; 638 if (esdhc_is_usdhc(imx_data)) { 639 /* 640 * The usdhc register returns a wrong host version. 641 * Correct it here. 642 */ 643 return SDHCI_SPEC_300; 644 } 645 } 646 647 if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 648 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 649 if (val & ESDHC_VENDOR_SPEC_VSELECT) 650 ret |= SDHCI_CTRL_VDD_180; 651 652 if (esdhc_is_usdhc(imx_data)) { 653 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 654 val = readl(host->ioaddr + ESDHC_MIX_CTRL); 655 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 656 /* the std tuning bits is in ACMD12_ERR for imx6sl */ 657 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 658 } 659 660 if (val & ESDHC_MIX_CTRL_EXE_TUNE) 661 ret |= SDHCI_CTRL_EXEC_TUNING; 662 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 663 ret |= SDHCI_CTRL_TUNED_CLK; 664 665 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 666 667 return ret; 668 } 669 670 if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 671 if (esdhc_is_usdhc(imx_data)) { 672 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 673 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 674 /* Swap AC23 bit */ 675 if (m & ESDHC_MIX_CTRL_AC23EN) { 676 ret &= ~ESDHC_MIX_CTRL_AC23EN; 677 ret |= SDHCI_TRNS_AUTO_CMD23; 678 } 679 } else { 680 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 681 } 682 683 return ret; 684 } 685 686 return readw(host->ioaddr + reg); 687 } 688 689 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 690 { 691 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 692 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 693 u32 new_val = 0; 694 695 switch (reg) { 696 case SDHCI_CLOCK_CONTROL: 697 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 698 if (val & SDHCI_CLOCK_CARD_EN) 699 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 700 else 701 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 702 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 703 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON)) 704 esdhc_wait_for_card_clock_gate_off(host); 705 return; 706 case SDHCI_HOST_CONTROL2: 707 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 708 if (val & SDHCI_CTRL_VDD_180) 709 new_val |= ESDHC_VENDOR_SPEC_VSELECT; 710 else 711 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 712 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 713 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 714 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 715 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 716 if (val & SDHCI_CTRL_TUNED_CLK) { 717 v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 718 } else { 719 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 720 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 721 } 722 723 if (val & SDHCI_CTRL_EXEC_TUNING) { 724 v |= ESDHC_MIX_CTRL_EXE_TUNE; 725 m |= ESDHC_MIX_CTRL_FBCLK_SEL; 726 } else { 727 v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 728 } 729 730 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 731 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 732 } 733 return; 734 case SDHCI_TRANSFER_MODE: 735 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 736 && (host->cmd->opcode == SD_IO_RW_EXTENDED) 737 && (host->cmd->data->blocks > 1) 738 && (host->cmd->data->flags & MMC_DATA_READ)) { 739 u32 v; 740 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 741 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 742 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 743 } 744 745 if (esdhc_is_usdhc(imx_data)) { 746 u32 wml; 747 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 748 /* Swap AC23 bit */ 749 if (val & SDHCI_TRNS_AUTO_CMD23) { 750 val &= ~SDHCI_TRNS_AUTO_CMD23; 751 val |= ESDHC_MIX_CTRL_AC23EN; 752 } 753 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 754 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 755 756 /* Set watermark levels for PIO access to maximum value 757 * (128 words) to accommodate full 512 bytes buffer. 758 * For DMA access restore the levels to default value. 759 */ 760 m = readl(host->ioaddr + ESDHC_WTMK_LVL); 761 if (val & SDHCI_TRNS_DMA) { 762 wml = ESDHC_WTMK_LVL_WML_VAL_DEF; 763 } else { 764 u8 ctrl; 765 wml = ESDHC_WTMK_LVL_WML_VAL_MAX; 766 767 /* 768 * Since already disable DMA mode, so also need 769 * to clear the DMASEL. Otherwise, for standard 770 * tuning, when send tuning command, usdhc will 771 * still prefetch the ADMA script from wrong 772 * DMA address, then we will see IOMMU report 773 * some error which show lack of TLB mapping. 774 */ 775 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 776 ctrl &= ~SDHCI_CTRL_DMA_MASK; 777 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 778 } 779 m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK | 780 ESDHC_WTMK_LVL_WR_WML_MASK); 781 m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) | 782 (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT); 783 writel(m, host->ioaddr + ESDHC_WTMK_LVL); 784 } else { 785 /* 786 * Postpone this write, we must do it together with a 787 * command write that is down below. 788 */ 789 imx_data->scratchpad = val; 790 } 791 return; 792 case SDHCI_COMMAND: 793 if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 794 val |= SDHCI_CMD_ABORTCMD; 795 796 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 797 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 798 imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 799 800 if (esdhc_is_usdhc(imx_data)) 801 writel(val << 16, 802 host->ioaddr + SDHCI_TRANSFER_MODE); 803 else 804 writel(val << 16 | imx_data->scratchpad, 805 host->ioaddr + SDHCI_TRANSFER_MODE); 806 return; 807 case SDHCI_BLOCK_SIZE: 808 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 809 break; 810 } 811 esdhc_clrset_le(host, 0xffff, val, reg); 812 } 813 814 static u8 esdhc_readb_le(struct sdhci_host *host, int reg) 815 { 816 u8 ret; 817 u32 val; 818 819 switch (reg) { 820 case SDHCI_HOST_CONTROL: 821 val = readl(host->ioaddr + reg); 822 823 ret = val & SDHCI_CTRL_LED; 824 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; 825 ret |= (val & ESDHC_CTRL_4BITBUS); 826 ret |= (val & ESDHC_CTRL_8BITBUS) << 3; 827 return ret; 828 } 829 830 return readb(host->ioaddr + reg); 831 } 832 833 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 834 { 835 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 836 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 837 u32 new_val = 0; 838 u32 mask; 839 840 switch (reg) { 841 case SDHCI_POWER_CONTROL: 842 /* 843 * FSL put some DMA bits here 844 * If your board has a regulator, code should be here 845 */ 846 return; 847 case SDHCI_HOST_CONTROL: 848 /* FSL messed up here, so we need to manually compose it. */ 849 new_val = val & SDHCI_CTRL_LED; 850 /* ensure the endianness */ 851 new_val |= ESDHC_HOST_CONTROL_LE; 852 /* bits 8&9 are reserved on mx25 */ 853 if (!is_imx25_esdhc(imx_data)) { 854 /* DMA mode bits are shifted */ 855 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 856 } 857 858 /* 859 * Do not touch buswidth bits here. This is done in 860 * esdhc_pltfm_bus_width. 861 * Do not touch the D3CD bit either which is used for the 862 * SDIO interrupt erratum workaround. 863 */ 864 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 865 866 esdhc_clrset_le(host, mask, new_val, reg); 867 return; 868 case SDHCI_SOFTWARE_RESET: 869 if (val & SDHCI_RESET_DATA) 870 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); 871 break; 872 } 873 esdhc_clrset_le(host, 0xff, val, reg); 874 875 if (reg == SDHCI_SOFTWARE_RESET) { 876 if (val & SDHCI_RESET_ALL) { 877 /* 878 * The esdhc has a design violation to SDHC spec which 879 * tells that software reset should not affect card 880 * detection circuit. But esdhc clears its SYSCTL 881 * register bits [0..2] during the software reset. This 882 * will stop those clocks that card detection circuit 883 * relies on. To work around it, we turn the clocks on 884 * back to keep card detection circuit functional. 885 */ 886 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 887 /* 888 * The reset on usdhc fails to clear MIX_CTRL register. 889 * Do it manually here. 890 */ 891 if (esdhc_is_usdhc(imx_data)) { 892 /* 893 * the tuning bits should be kept during reset 894 */ 895 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 896 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 897 host->ioaddr + ESDHC_MIX_CTRL); 898 imx_data->is_ddr = 0; 899 } 900 } else if (val & SDHCI_RESET_DATA) { 901 /* 902 * The eSDHC DAT line software reset clears at least the 903 * data transfer width on i.MX25, so make sure that the 904 * Host Control register is unaffected. 905 */ 906 esdhc_clrset_le(host, 0xff, new_val, 907 SDHCI_HOST_CONTROL); 908 } 909 } 910 } 911 912 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 913 { 914 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 915 916 return pltfm_host->clock; 917 } 918 919 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 920 { 921 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 922 923 return pltfm_host->clock / 256 / 16; 924 } 925 926 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 927 unsigned int clock) 928 { 929 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 930 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 931 unsigned int host_clock = pltfm_host->clock; 932 int ddr_pre_div = imx_data->is_ddr ? 2 : 1; 933 int pre_div = 1; 934 int div = 1; 935 int ret; 936 u32 temp, val; 937 938 if (esdhc_is_usdhc(imx_data)) { 939 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 940 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 941 host->ioaddr + ESDHC_VENDOR_SPEC); 942 esdhc_wait_for_card_clock_gate_off(host); 943 } 944 945 if (clock == 0) { 946 host->mmc->actual_clock = 0; 947 return; 948 } 949 950 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ 951 if (is_imx53_esdhc(imx_data)) { 952 /* 953 * According to the i.MX53 reference manual, if DLLCTRL[10] can 954 * be set, then the controller is eSDHCv3, else it is eSDHCv2. 955 */ 956 val = readl(host->ioaddr + ESDHC_DLL_CTRL); 957 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); 958 temp = readl(host->ioaddr + ESDHC_DLL_CTRL); 959 writel(val, host->ioaddr + ESDHC_DLL_CTRL); 960 if (temp & BIT(10)) 961 pre_div = 2; 962 } 963 964 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 965 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 966 | ESDHC_CLOCK_MASK); 967 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 968 969 if ((imx_data->socdata->flags & ESDHC_FLAG_ERR010450) && 970 (!(host->quirks2 & SDHCI_QUIRK2_NO_1_8_V))) { 971 unsigned int max_clock; 972 973 max_clock = imx_data->is_ddr ? 45000000 : 150000000; 974 975 clock = min(clock, max_clock); 976 } 977 978 while (host_clock / (16 * pre_div * ddr_pre_div) > clock && 979 pre_div < 256) 980 pre_div *= 2; 981 982 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16) 983 div++; 984 985 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); 986 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 987 clock, host->mmc->actual_clock); 988 989 pre_div >>= 1; 990 div--; 991 992 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 993 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 994 | (div << ESDHC_DIVIDER_SHIFT) 995 | (pre_div << ESDHC_PREDIV_SHIFT)); 996 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 997 998 /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */ 999 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp, 1000 (temp & ESDHC_CLOCK_STABLE), 2, 100); 1001 if (ret == -ETIMEDOUT) 1002 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n"); 1003 1004 if (esdhc_is_usdhc(imx_data)) { 1005 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 1006 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 1007 host->ioaddr + ESDHC_VENDOR_SPEC); 1008 } 1009 1010 } 1011 1012 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 1013 { 1014 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1015 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1016 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1017 1018 switch (boarddata->wp_type) { 1019 case ESDHC_WP_GPIO: 1020 return mmc_gpio_get_ro(host->mmc); 1021 case ESDHC_WP_CONTROLLER: 1022 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 1023 SDHCI_WRITE_PROTECT); 1024 case ESDHC_WP_NONE: 1025 break; 1026 } 1027 1028 return -ENOSYS; 1029 } 1030 1031 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 1032 { 1033 u32 ctrl; 1034 1035 switch (width) { 1036 case MMC_BUS_WIDTH_8: 1037 ctrl = ESDHC_CTRL_8BITBUS; 1038 break; 1039 case MMC_BUS_WIDTH_4: 1040 ctrl = ESDHC_CTRL_4BITBUS; 1041 break; 1042 default: 1043 ctrl = 0; 1044 break; 1045 } 1046 1047 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 1048 SDHCI_HOST_CONTROL); 1049 } 1050 1051 static void esdhc_reset_tuning(struct sdhci_host *host) 1052 { 1053 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1054 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1055 u32 ctrl; 1056 int ret; 1057 1058 /* Reset the tuning circuit */ 1059 if (esdhc_is_usdhc(imx_data)) { 1060 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); 1061 ctrl &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 1062 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1063 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1064 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 1065 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 1066 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1067 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1068 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 1069 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1070 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1071 ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE; 1072 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1073 /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */ 1074 ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS, 1075 ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50); 1076 if (ret == -ETIMEDOUT) 1077 dev_warn(mmc_dev(host->mmc), 1078 "Warning! clear execute tuning bit failed\n"); 1079 /* 1080 * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the 1081 * usdhc IP internal logic flag execute_tuning_with_clr_buf, which 1082 * will finally make sure the normal data transfer logic correct. 1083 */ 1084 ctrl = readl(host->ioaddr + SDHCI_INT_STATUS); 1085 ctrl |= SDHCI_INT_DATA_AVAIL; 1086 writel(ctrl, host->ioaddr + SDHCI_INT_STATUS); 1087 } 1088 } 1089 } 1090 1091 static void usdhc_init_card(struct mmc_host *mmc, struct mmc_card *card) 1092 { 1093 struct sdhci_host *host = mmc_priv(mmc); 1094 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1095 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1096 1097 imx_data->init_card_type = card->type; 1098 } 1099 1100 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1101 { 1102 struct sdhci_host *host = mmc_priv(mmc); 1103 int err; 1104 1105 /* 1106 * i.MX uSDHC internally already uses a fixed optimized timing for 1107 * DDR50, normally does not require tuning for DDR50 mode. 1108 */ 1109 if (host->timing == MMC_TIMING_UHS_DDR50) 1110 return 0; 1111 1112 /* 1113 * Reset tuning circuit logic. If not, the previous tuning result 1114 * will impact current tuning, make current tuning can't set the 1115 * correct delay cell. 1116 */ 1117 esdhc_reset_tuning(host); 1118 err = sdhci_execute_tuning(mmc, opcode); 1119 /* If tuning done, enable auto tuning */ 1120 if (!err && !host->tuning_err) 1121 usdhc_auto_tuning_mode_sel_and_en(host); 1122 1123 return err; 1124 } 1125 1126 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 1127 { 1128 u32 reg; 1129 u8 sw_rst; 1130 int ret; 1131 1132 /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 1133 mdelay(1); 1134 1135 /* IC suggest to reset USDHC before every tuning command */ 1136 esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET); 1137 ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst, 1138 !(sw_rst & SDHCI_RESET_ALL), 10, 100); 1139 if (ret == -ETIMEDOUT) 1140 dev_warn(mmc_dev(host->mmc), 1141 "warning! RESET_ALL never complete before sending tuning command\n"); 1142 1143 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 1144 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 1145 ESDHC_MIX_CTRL_FBCLK_SEL; 1146 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 1147 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1148 dev_dbg(mmc_dev(host->mmc), 1149 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 1150 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 1151 } 1152 1153 static void esdhc_post_tuning(struct sdhci_host *host) 1154 { 1155 u32 reg; 1156 1157 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 1158 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 1159 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 1160 } 1161 1162 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 1163 { 1164 int min, max, avg, ret; 1165 1166 /* find the mininum delay first which can pass tuning */ 1167 min = ESDHC_TUNE_CTRL_MIN; 1168 while (min < ESDHC_TUNE_CTRL_MAX) { 1169 esdhc_prepare_tuning(host, min); 1170 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 1171 break; 1172 min += ESDHC_TUNE_CTRL_STEP; 1173 } 1174 1175 /* find the maxinum delay which can not pass tuning */ 1176 max = min + ESDHC_TUNE_CTRL_STEP; 1177 while (max < ESDHC_TUNE_CTRL_MAX) { 1178 esdhc_prepare_tuning(host, max); 1179 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1180 max -= ESDHC_TUNE_CTRL_STEP; 1181 break; 1182 } 1183 max += ESDHC_TUNE_CTRL_STEP; 1184 } 1185 1186 /* use average delay to get the best timing */ 1187 avg = (min + max) / 2; 1188 esdhc_prepare_tuning(host, avg); 1189 ret = mmc_send_tuning(host->mmc, opcode, NULL); 1190 esdhc_post_tuning(host); 1191 1192 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 1193 ret ? "failed" : "passed", avg, ret); 1194 1195 return ret; 1196 } 1197 1198 static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) 1199 { 1200 struct sdhci_host *host = mmc_priv(mmc); 1201 u32 m; 1202 1203 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 1204 if (ios->enhanced_strobe) 1205 m |= ESDHC_MIX_CTRL_HS400_ES_EN; 1206 else 1207 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN; 1208 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1209 } 1210 1211 static int esdhc_change_pinstate(struct sdhci_host *host, 1212 unsigned int uhs) 1213 { 1214 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1215 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1216 struct pinctrl_state *pinctrl; 1217 1218 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 1219 1220 if (IS_ERR(imx_data->pinctrl) || 1221 IS_ERR(imx_data->pins_100mhz) || 1222 IS_ERR(imx_data->pins_200mhz)) 1223 return -EINVAL; 1224 1225 switch (uhs) { 1226 case MMC_TIMING_UHS_SDR50: 1227 case MMC_TIMING_UHS_DDR50: 1228 pinctrl = imx_data->pins_100mhz; 1229 break; 1230 case MMC_TIMING_UHS_SDR104: 1231 case MMC_TIMING_MMC_HS200: 1232 case MMC_TIMING_MMC_HS400: 1233 pinctrl = imx_data->pins_200mhz; 1234 break; 1235 default: 1236 /* back to default state for other legacy timing */ 1237 return pinctrl_select_default_state(mmc_dev(host->mmc)); 1238 } 1239 1240 return pinctrl_select_state(imx_data->pinctrl, pinctrl); 1241 } 1242 1243 /* 1244 * For HS400 eMMC, there is a data_strobe line. This signal is generated 1245 * by the device and used for data output and CRC status response output 1246 * in HS400 mode. The frequency of this signal follows the frequency of 1247 * CLK generated by host. The host receives the data which is aligned to the 1248 * edge of data_strobe line. Due to the time delay between CLK line and 1249 * data_strobe line, if the delay time is larger than one clock cycle, 1250 * then CLK and data_strobe line will be misaligned, read error shows up. 1251 */ 1252 static void esdhc_set_strobe_dll(struct sdhci_host *host) 1253 { 1254 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1255 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1256 u32 strobe_delay; 1257 u32 v; 1258 int ret; 1259 1260 /* disable clock before enabling strobe dll */ 1261 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & 1262 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 1263 host->ioaddr + ESDHC_VENDOR_SPEC); 1264 esdhc_wait_for_card_clock_gate_off(host); 1265 1266 /* force a reset on strobe dll */ 1267 writel(ESDHC_STROBE_DLL_CTRL_RESET, 1268 host->ioaddr + ESDHC_STROBE_DLL_CTRL); 1269 /* clear the reset bit on strobe dll before any setting */ 1270 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 1271 1272 /* 1273 * enable strobe dll ctrl and adjust the delay target 1274 * for the uSDHC loopback read clock 1275 */ 1276 if (imx_data->boarddata.strobe_dll_delay_target) 1277 strobe_delay = imx_data->boarddata.strobe_dll_delay_target; 1278 else 1279 strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT; 1280 v = ESDHC_STROBE_DLL_CTRL_ENABLE | 1281 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT | 1282 (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 1283 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 1284 1285 /* wait max 50us to get the REF/SLV lock */ 1286 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v, 1287 ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50); 1288 if (ret == -ETIMEDOUT) 1289 dev_warn(mmc_dev(host->mmc), 1290 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v); 1291 } 1292 1293 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1294 { 1295 u32 m; 1296 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1297 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1298 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1299 1300 /* disable ddr mode and disable HS400 mode */ 1301 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 1302 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); 1303 imx_data->is_ddr = 0; 1304 1305 switch (timing) { 1306 case MMC_TIMING_UHS_SDR12: 1307 case MMC_TIMING_UHS_SDR25: 1308 case MMC_TIMING_UHS_SDR50: 1309 case MMC_TIMING_UHS_SDR104: 1310 case MMC_TIMING_MMC_HS: 1311 case MMC_TIMING_MMC_HS200: 1312 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1313 break; 1314 case MMC_TIMING_UHS_DDR50: 1315 case MMC_TIMING_MMC_DDR52: 1316 m |= ESDHC_MIX_CTRL_DDREN; 1317 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1318 imx_data->is_ddr = 1; 1319 if (boarddata->delay_line) { 1320 u32 v; 1321 v = boarddata->delay_line << 1322 ESDHC_DLL_OVERRIDE_VAL_SHIFT | 1323 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 1324 if (is_imx53_esdhc(imx_data)) 1325 v <<= 1; 1326 writel(v, host->ioaddr + ESDHC_DLL_CTRL); 1327 } 1328 break; 1329 case MMC_TIMING_MMC_HS400: 1330 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 1331 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1332 imx_data->is_ddr = 1; 1333 /* update clock after enable DDR for strobe DLL lock */ 1334 host->ops->set_clock(host, host->clock); 1335 esdhc_set_strobe_dll(host); 1336 break; 1337 case MMC_TIMING_LEGACY: 1338 default: 1339 esdhc_reset_tuning(host); 1340 break; 1341 } 1342 1343 esdhc_change_pinstate(host, timing); 1344 } 1345 1346 static void esdhc_reset(struct sdhci_host *host, u8 mask) 1347 { 1348 sdhci_and_cqhci_reset(host, mask); 1349 1350 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1351 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1352 } 1353 1354 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 1355 { 1356 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1357 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1358 1359 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */ 1360 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27; 1361 } 1362 1363 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 1364 { 1365 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1366 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1367 1368 /* use maximum timeout counter */ 1369 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, 1370 esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 1371 SDHCI_TIMEOUT_CONTROL); 1372 } 1373 1374 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask) 1375 { 1376 int cmd_error = 0; 1377 int data_error = 0; 1378 1379 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1380 return intmask; 1381 1382 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1383 1384 return 0; 1385 } 1386 1387 static struct sdhci_ops sdhci_esdhc_ops = { 1388 .read_l = esdhc_readl_le, 1389 .read_w = esdhc_readw_le, 1390 .read_b = esdhc_readb_le, 1391 .write_l = esdhc_writel_le, 1392 .write_w = esdhc_writew_le, 1393 .write_b = esdhc_writeb_le, 1394 .set_clock = esdhc_pltfm_set_clock, 1395 .get_max_clock = esdhc_pltfm_get_max_clock, 1396 .get_min_clock = esdhc_pltfm_get_min_clock, 1397 .get_max_timeout_count = esdhc_get_max_timeout_count, 1398 .get_ro = esdhc_pltfm_get_ro, 1399 .set_timeout = esdhc_set_timeout, 1400 .set_bus_width = esdhc_pltfm_set_bus_width, 1401 .set_uhs_signaling = esdhc_set_uhs_signaling, 1402 .reset = esdhc_reset, 1403 .irq = esdhc_cqhci_irq, 1404 .dump_vendor_regs = esdhc_dump_debug_regs, 1405 }; 1406 1407 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 1408 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 1409 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 1410 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 1411 | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 1412 .ops = &sdhci_esdhc_ops, 1413 }; 1414 1415 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) 1416 { 1417 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1418 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1419 struct cqhci_host *cq_host = host->mmc->cqe_private; 1420 u32 tmp; 1421 1422 if (esdhc_is_usdhc(imx_data)) { 1423 /* 1424 * The imx6q ROM code will change the default watermark 1425 * level setting to something insane. Change it back here. 1426 */ 1427 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); 1428 1429 /* 1430 * ROM code will change the bit burst_length_enable setting 1431 * to zero if this usdhc is chosen to boot system. Change 1432 * it back here, otherwise it will impact the performance a 1433 * lot. This bit is used to enable/disable the burst length 1434 * for the external AHB2AXI bridge. It's useful especially 1435 * for INCR transfer because without burst length indicator, 1436 * the AHB2AXI bridge does not know the burst length in 1437 * advance. And without burst length indicator, AHB INCR 1438 * transfer can only be converted to singles on the AXI side. 1439 */ 1440 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) 1441 | ESDHC_BURST_LEN_EN_INCR, 1442 host->ioaddr + SDHCI_HOST_CONTROL); 1443 1444 /* 1445 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 1446 * TO1.1, it's harmless for MX6SL 1447 */ 1448 if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_ERR004536)) { 1449 writel(readl(host->ioaddr + 0x6c) & ~BIT(7), 1450 host->ioaddr + 0x6c); 1451 } 1452 1453 /* disable DLL_CTRL delay line settings */ 1454 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); 1455 1456 /* 1457 * For the case of command with busy, if set the bit 1458 * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a 1459 * transfer complete interrupt when busy is deasserted. 1460 * When CQHCI use DCMD to send a CMD need R1b respons, 1461 * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ, 1462 * otherwise DCMD will always meet timeout waiting for 1463 * hardware interrupt issue. 1464 */ 1465 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1466 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2); 1467 tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ; 1468 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2); 1469 1470 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1471 } 1472 1473 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1474 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1475 tmp |= ESDHC_STD_TUNING_EN; 1476 1477 /* 1478 * ROM code or bootloader may config the start tap 1479 * and step, unmask them first. 1480 */ 1481 tmp &= ~(ESDHC_TUNING_START_TAP_MASK | ESDHC_TUNING_STEP_MASK); 1482 if (imx_data->boarddata.tuning_start_tap) 1483 tmp |= imx_data->boarddata.tuning_start_tap; 1484 else 1485 tmp |= ESDHC_TUNING_START_TAP_DEFAULT; 1486 1487 if (imx_data->boarddata.tuning_step) { 1488 tmp |= imx_data->boarddata.tuning_step 1489 << ESDHC_TUNING_STEP_SHIFT; 1490 } else { 1491 tmp |= ESDHC_TUNING_STEP_DEFAULT 1492 << ESDHC_TUNING_STEP_SHIFT; 1493 } 1494 1495 /* Disable the CMD CRC check for tuning, if not, need to 1496 * add some delay after every tuning command, because 1497 * hardware standard tuning logic will directly go to next 1498 * step once it detect the CMD CRC error, will not wait for 1499 * the card side to finally send out the tuning data, trigger 1500 * the buffer read ready interrupt immediately. If usdhc send 1501 * the next tuning command some eMMC card will stuck, can't 1502 * response, block the tuning procedure or the first command 1503 * after the whole tuning procedure always can't get any response. 1504 */ 1505 tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE; 1506 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1507 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1508 /* 1509 * ESDHC_STD_TUNING_EN may be configed in bootloader 1510 * or ROM code, so clear this bit here to make sure 1511 * the manual tuning can work. 1512 */ 1513 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1514 tmp &= ~ESDHC_STD_TUNING_EN; 1515 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1516 } 1517 1518 /* 1519 * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card 1520 * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let 1521 * the 1st linux configure power/clock for the 2nd Linux. 1522 * 1523 * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux 1524 * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump. 1525 * After we clear the pending interrupt and halt CQCTL, issue gone. 1526 */ 1527 if (cq_host) { 1528 tmp = cqhci_readl(cq_host, CQHCI_IS); 1529 cqhci_writel(cq_host, tmp, CQHCI_IS); 1530 cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL); 1531 } 1532 } 1533 } 1534 1535 static void esdhc_cqe_enable(struct mmc_host *mmc) 1536 { 1537 struct sdhci_host *host = mmc_priv(mmc); 1538 struct cqhci_host *cq_host = mmc->cqe_private; 1539 u32 reg; 1540 u16 mode; 1541 int count = 10; 1542 1543 /* 1544 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be 1545 * the case after tuning, so ensure the buffer is drained. 1546 */ 1547 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1548 while (reg & SDHCI_DATA_AVAILABLE) { 1549 sdhci_readl(host, SDHCI_BUFFER); 1550 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1551 if (count-- == 0) { 1552 dev_warn(mmc_dev(host->mmc), 1553 "CQE may get stuck because the Buffer Read Enable bit is set\n"); 1554 break; 1555 } 1556 mdelay(1); 1557 } 1558 1559 /* 1560 * Runtime resume will reset the entire host controller, which 1561 * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL. 1562 * Here set DMAEN and BCEN when enable CMDQ. 1563 */ 1564 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 1565 if (host->flags & SDHCI_REQ_USE_DMA) 1566 mode |= SDHCI_TRNS_DMA; 1567 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 1568 mode |= SDHCI_TRNS_BLK_CNT_EN; 1569 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 1570 1571 /* 1572 * Though Runtime resume reset the entire host controller, 1573 * but do not impact the CQHCI side, need to clear the 1574 * HALT bit, avoid CQHCI stuck in the first request when 1575 * system resume back. 1576 */ 1577 cqhci_writel(cq_host, 0, CQHCI_CTL); 1578 if (cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) 1579 dev_err(mmc_dev(host->mmc), 1580 "failed to exit halt state when enable CQE\n"); 1581 1582 1583 sdhci_cqe_enable(mmc); 1584 } 1585 1586 static void esdhc_sdhci_dumpregs(struct mmc_host *mmc) 1587 { 1588 sdhci_dumpregs(mmc_priv(mmc)); 1589 } 1590 1591 static const struct cqhci_host_ops esdhc_cqhci_ops = { 1592 .enable = esdhc_cqe_enable, 1593 .disable = sdhci_cqe_disable, 1594 .dumpregs = esdhc_sdhci_dumpregs, 1595 }; 1596 1597 static int 1598 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 1599 struct sdhci_host *host, 1600 struct pltfm_imx_data *imx_data) 1601 { 1602 struct device_node *np = pdev->dev.of_node; 1603 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1604 int ret; 1605 1606 if (of_property_read_bool(np, "fsl,wp-controller")) 1607 boarddata->wp_type = ESDHC_WP_CONTROLLER; 1608 1609 /* 1610 * If we have this property, then activate WP check. 1611 * Retrieveing and requesting the actual WP GPIO will happen 1612 * in the call to mmc_of_parse(). 1613 */ 1614 if (of_property_read_bool(np, "wp-gpios")) 1615 boarddata->wp_type = ESDHC_WP_GPIO; 1616 1617 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 1618 of_property_read_u32(np, "fsl,tuning-start-tap", 1619 &boarddata->tuning_start_tap); 1620 1621 of_property_read_u32(np, "fsl,strobe-dll-delay-target", 1622 &boarddata->strobe_dll_delay_target); 1623 if (of_property_read_bool(np, "no-1-8-v")) 1624 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1625 1626 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 1627 boarddata->delay_line = 0; 1628 1629 mmc_of_parse_voltage(host->mmc, &host->ocr_mask); 1630 1631 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) { 1632 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 1633 ESDHC_PINCTRL_STATE_100MHZ); 1634 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 1635 ESDHC_PINCTRL_STATE_200MHZ); 1636 } 1637 1638 /* call to generic mmc_of_parse to support additional capabilities */ 1639 ret = mmc_of_parse(host->mmc); 1640 if (ret) 1641 return ret; 1642 1643 /* HS400/HS400ES require 8 bit bus */ 1644 if (!(host->mmc->caps & MMC_CAP_8_BIT_DATA)) 1645 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 1646 1647 if (mmc_gpio_get_cd(host->mmc) >= 0) 1648 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1649 1650 return 0; 1651 } 1652 1653 static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 1654 { 1655 struct sdhci_pltfm_host *pltfm_host; 1656 struct sdhci_host *host; 1657 struct cqhci_host *cq_host; 1658 int err; 1659 struct pltfm_imx_data *imx_data; 1660 1661 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 1662 sizeof(*imx_data)); 1663 if (IS_ERR(host)) 1664 return PTR_ERR(host); 1665 1666 pltfm_host = sdhci_priv(host); 1667 1668 imx_data = sdhci_pltfm_priv(pltfm_host); 1669 1670 imx_data->socdata = device_get_match_data(&pdev->dev); 1671 1672 host->quirks |= imx_data->socdata->quirks; 1673 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1674 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); 1675 1676 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1677 if (IS_ERR(imx_data->clk_ipg)) { 1678 err = PTR_ERR(imx_data->clk_ipg); 1679 goto free_sdhci; 1680 } 1681 1682 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1683 if (IS_ERR(imx_data->clk_ahb)) { 1684 err = PTR_ERR(imx_data->clk_ahb); 1685 goto free_sdhci; 1686 } 1687 1688 imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 1689 if (IS_ERR(imx_data->clk_per)) { 1690 err = PTR_ERR(imx_data->clk_per); 1691 goto free_sdhci; 1692 } 1693 1694 pltfm_host->clk = imx_data->clk_per; 1695 pltfm_host->clock = clk_get_rate(pltfm_host->clk); 1696 err = clk_prepare_enable(imx_data->clk_per); 1697 if (err) 1698 goto free_sdhci; 1699 err = clk_prepare_enable(imx_data->clk_ipg); 1700 if (err) 1701 goto disable_per_clk; 1702 err = clk_prepare_enable(imx_data->clk_ahb); 1703 if (err) 1704 goto disable_ipg_clk; 1705 1706 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1707 if (IS_ERR(imx_data->pinctrl)) 1708 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n"); 1709 1710 if (esdhc_is_usdhc(imx_data)) { 1711 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 1712 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; 1713 1714 /* GPIO CD can be set as a wakeup source */ 1715 host->mmc->caps |= MMC_CAP_CD_WAKE; 1716 1717 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 1718 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 1719 1720 /* clear tuning bits in case ROM has set it already */ 1721 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); 1722 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1723 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1724 1725 /* 1726 * Link usdhc specific mmc_host_ops execute_tuning function, 1727 * to replace the standard one in sdhci_ops. 1728 */ 1729 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning; 1730 1731 /* 1732 * Link usdhc specific mmc_host_ops init card function, 1733 * to distinguish the card type. 1734 */ 1735 host->mmc_host_ops.init_card = usdhc_init_card; 1736 } 1737 1738 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 1739 sdhci_esdhc_ops.platform_execute_tuning = 1740 esdhc_executing_tuning; 1741 1742 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 1743 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1744 1745 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 1746 host->mmc->caps2 |= MMC_CAP2_HS400; 1747 1748 if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23) 1749 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN; 1750 1751 if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) { 1752 host->mmc->caps2 |= MMC_CAP2_HS400_ES; 1753 host->mmc_host_ops.hs400_enhanced_strobe = 1754 esdhc_hs400_enhanced_strobe; 1755 } 1756 1757 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1758 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1759 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); 1760 if (!cq_host) { 1761 err = -ENOMEM; 1762 goto disable_ahb_clk; 1763 } 1764 1765 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET; 1766 cq_host->ops = &esdhc_cqhci_ops; 1767 1768 err = cqhci_init(cq_host, host->mmc, false); 1769 if (err) 1770 goto disable_ahb_clk; 1771 } 1772 1773 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 1774 if (err) 1775 goto disable_ahb_clk; 1776 1777 sdhci_esdhc_imx_hwinit(host); 1778 1779 err = sdhci_add_host(host); 1780 if (err) 1781 goto disable_ahb_clk; 1782 1783 /* 1784 * Setup the wakeup capability here, let user to decide 1785 * whether need to enable this wakeup through sysfs interface. 1786 */ 1787 if ((host->mmc->pm_caps & MMC_PM_KEEP_POWER) && 1788 (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)) 1789 device_set_wakeup_capable(&pdev->dev, true); 1790 1791 pm_runtime_set_active(&pdev->dev); 1792 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1793 pm_runtime_use_autosuspend(&pdev->dev); 1794 pm_suspend_ignore_children(&pdev->dev, 1); 1795 pm_runtime_enable(&pdev->dev); 1796 1797 return 0; 1798 1799 disable_ahb_clk: 1800 clk_disable_unprepare(imx_data->clk_ahb); 1801 disable_ipg_clk: 1802 clk_disable_unprepare(imx_data->clk_ipg); 1803 disable_per_clk: 1804 clk_disable_unprepare(imx_data->clk_per); 1805 free_sdhci: 1806 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1807 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 1808 sdhci_pltfm_free(pdev); 1809 return err; 1810 } 1811 1812 static void sdhci_esdhc_imx_remove(struct platform_device *pdev) 1813 { 1814 struct sdhci_host *host = platform_get_drvdata(pdev); 1815 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1816 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1817 int dead; 1818 1819 pm_runtime_get_sync(&pdev->dev); 1820 dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 1821 pm_runtime_disable(&pdev->dev); 1822 pm_runtime_put_noidle(&pdev->dev); 1823 1824 sdhci_remove_host(host, dead); 1825 1826 clk_disable_unprepare(imx_data->clk_per); 1827 clk_disable_unprepare(imx_data->clk_ipg); 1828 clk_disable_unprepare(imx_data->clk_ahb); 1829 1830 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1831 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 1832 1833 sdhci_pltfm_free(pdev); 1834 } 1835 1836 #ifdef CONFIG_PM_SLEEP 1837 static int sdhci_esdhc_suspend(struct device *dev) 1838 { 1839 struct sdhci_host *host = dev_get_drvdata(dev); 1840 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1841 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1842 int ret; 1843 1844 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1845 ret = cqhci_suspend(host->mmc); 1846 if (ret) 1847 return ret; 1848 } 1849 1850 if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) && 1851 (host->tuning_mode != SDHCI_TUNING_MODE_1)) { 1852 mmc_retune_timer_stop(host->mmc); 1853 mmc_retune_needed(host->mmc); 1854 } 1855 1856 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1857 mmc_retune_needed(host->mmc); 1858 1859 ret = sdhci_suspend_host(host); 1860 if (ret) 1861 return ret; 1862 1863 ret = pinctrl_pm_select_sleep_state(dev); 1864 if (ret) 1865 return ret; 1866 1867 ret = mmc_gpio_set_cd_wake(host->mmc, true); 1868 1869 return ret; 1870 } 1871 1872 static int sdhci_esdhc_resume(struct device *dev) 1873 { 1874 struct sdhci_host *host = dev_get_drvdata(dev); 1875 int ret; 1876 1877 ret = pinctrl_pm_select_default_state(dev); 1878 if (ret) 1879 return ret; 1880 1881 /* re-initialize hw state in case it's lost in low power mode */ 1882 sdhci_esdhc_imx_hwinit(host); 1883 1884 ret = sdhci_resume_host(host); 1885 if (ret) 1886 return ret; 1887 1888 if (host->mmc->caps2 & MMC_CAP2_CQE) 1889 ret = cqhci_resume(host->mmc); 1890 1891 if (!ret) 1892 ret = mmc_gpio_set_cd_wake(host->mmc, false); 1893 1894 return ret; 1895 } 1896 #endif 1897 1898 #ifdef CONFIG_PM 1899 static int sdhci_esdhc_runtime_suspend(struct device *dev) 1900 { 1901 struct sdhci_host *host = dev_get_drvdata(dev); 1902 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1903 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1904 int ret; 1905 1906 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1907 ret = cqhci_suspend(host->mmc); 1908 if (ret) 1909 return ret; 1910 } 1911 1912 ret = sdhci_runtime_suspend_host(host); 1913 if (ret) 1914 return ret; 1915 1916 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1917 mmc_retune_needed(host->mmc); 1918 1919 imx_data->actual_clock = host->mmc->actual_clock; 1920 esdhc_pltfm_set_clock(host, 0); 1921 clk_disable_unprepare(imx_data->clk_per); 1922 clk_disable_unprepare(imx_data->clk_ipg); 1923 clk_disable_unprepare(imx_data->clk_ahb); 1924 1925 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1926 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 1927 1928 return ret; 1929 } 1930 1931 static int sdhci_esdhc_runtime_resume(struct device *dev) 1932 { 1933 struct sdhci_host *host = dev_get_drvdata(dev); 1934 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1935 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1936 int err; 1937 1938 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1939 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); 1940 1941 if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME) 1942 clk_set_rate(imx_data->clk_per, pltfm_host->clock); 1943 1944 err = clk_prepare_enable(imx_data->clk_ahb); 1945 if (err) 1946 goto remove_pm_qos_request; 1947 1948 err = clk_prepare_enable(imx_data->clk_per); 1949 if (err) 1950 goto disable_ahb_clk; 1951 1952 err = clk_prepare_enable(imx_data->clk_ipg); 1953 if (err) 1954 goto disable_per_clk; 1955 1956 esdhc_pltfm_set_clock(host, imx_data->actual_clock); 1957 1958 err = sdhci_runtime_resume_host(host, 0); 1959 if (err) 1960 goto disable_ipg_clk; 1961 1962 if (host->mmc->caps2 & MMC_CAP2_CQE) 1963 err = cqhci_resume(host->mmc); 1964 1965 return err; 1966 1967 disable_ipg_clk: 1968 clk_disable_unprepare(imx_data->clk_ipg); 1969 disable_per_clk: 1970 clk_disable_unprepare(imx_data->clk_per); 1971 disable_ahb_clk: 1972 clk_disable_unprepare(imx_data->clk_ahb); 1973 remove_pm_qos_request: 1974 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1975 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 1976 return err; 1977 } 1978 #endif 1979 1980 static const struct dev_pm_ops sdhci_esdhc_pmops = { 1981 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) 1982 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 1983 sdhci_esdhc_runtime_resume, NULL) 1984 }; 1985 1986 static struct platform_driver sdhci_esdhc_imx_driver = { 1987 .driver = { 1988 .name = "sdhci-esdhc-imx", 1989 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1990 .of_match_table = imx_esdhc_dt_ids, 1991 .pm = &sdhci_esdhc_pmops, 1992 }, 1993 .probe = sdhci_esdhc_imx_probe, 1994 .remove_new = sdhci_esdhc_imx_remove, 1995 }; 1996 1997 module_platform_driver(sdhci_esdhc_imx_driver); 1998 1999 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 2000 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 2001 MODULE_LICENSE("GPL v2"); 2002