1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Freescale eSDHC i.MX controller driver for the platform bus. 4 * 5 * derived from the OF-version. 6 * 7 * Copyright (c) 2010 Pengutronix e.K. 8 * Author: Wolfram Sang <kernel@pengutronix.de> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/delay.h> 15 #include <linux/err.h> 16 #include <linux/clk.h> 17 #include <linux/module.h> 18 #include <linux/slab.h> 19 #include <linux/pm_qos.h> 20 #include <linux/mmc/host.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/mmc/sdio.h> 23 #include <linux/mmc/slot-gpio.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/pm_runtime.h> 28 #include "sdhci-pltfm.h" 29 #include "sdhci-esdhc.h" 30 #include "cqhci.h" 31 32 #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f 33 #define ESDHC_CTRL_D3CD 0x08 34 #define ESDHC_BURST_LEN_EN_INCR (1 << 27) 35 /* VENDOR SPEC register */ 36 #define ESDHC_VENDOR_SPEC 0xc0 37 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 38 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 39 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 40 #define ESDHC_DEBUG_SEL_AND_STATUS_REG 0xc2 41 #define ESDHC_DEBUG_SEL_REG 0xc3 42 #define ESDHC_DEBUG_SEL_MASK 0xf 43 #define ESDHC_DEBUG_SEL_CMD_STATE 1 44 #define ESDHC_DEBUG_SEL_DATA_STATE 2 45 #define ESDHC_DEBUG_SEL_TRANS_STATE 3 46 #define ESDHC_DEBUG_SEL_DMA_STATE 4 47 #define ESDHC_DEBUG_SEL_ADMA_STATE 5 48 #define ESDHC_DEBUG_SEL_FIFO_STATE 6 49 #define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE 7 50 #define ESDHC_WTMK_LVL 0x44 51 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 52 #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF 53 #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0 54 #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000 55 #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16 56 #define ESDHC_WTMK_LVL_WML_VAL_DEF 64 57 #define ESDHC_WTMK_LVL_WML_VAL_MAX 128 58 #define ESDHC_MIX_CTRL 0x48 59 #define ESDHC_MIX_CTRL_DDREN (1 << 3) 60 #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 61 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 62 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 63 #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) 64 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 65 #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 66 #define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27) 67 /* Bits 3 and 6 are not SDHCI standard definitions */ 68 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 69 /* Tuning bits */ 70 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 71 72 /* dll control register */ 73 #define ESDHC_DLL_CTRL 0x60 74 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 75 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 76 77 /* tune control register */ 78 #define ESDHC_TUNE_CTRL_STATUS 0x68 79 #define ESDHC_TUNE_CTRL_STEP 1 80 #define ESDHC_TUNE_CTRL_MIN 0 81 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 82 83 /* strobe dll register */ 84 #define ESDHC_STROBE_DLL_CTRL 0x70 85 #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) 86 #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) 87 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7 88 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 89 #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20) 90 91 #define ESDHC_STROBE_DLL_STATUS 0x74 92 #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) 93 #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 94 95 #define ESDHC_VEND_SPEC2 0xc8 96 #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8) 97 #define ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN (1 << 4) 98 #define ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN (0 << 4) 99 #define ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN (2 << 4) 100 #define ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN (1 << 6) 101 #define ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK (7 << 4) 102 103 #define ESDHC_TUNING_CTRL 0xcc 104 #define ESDHC_STD_TUNING_EN (1 << 24) 105 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 106 #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 107 #define ESDHC_TUNING_START_TAP_MASK 0x7f 108 #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE (1 << 7) 109 #define ESDHC_TUNING_STEP_MASK 0x00070000 110 #define ESDHC_TUNING_STEP_SHIFT 16 111 112 /* pinctrl state */ 113 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 114 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 115 116 /* 117 * Our interpretation of the SDHCI_HOST_CONTROL register 118 */ 119 #define ESDHC_CTRL_4BITBUS (0x1 << 1) 120 #define ESDHC_CTRL_8BITBUS (0x2 << 1) 121 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 122 #define USDHC_GET_BUSWIDTH(c) (c & ESDHC_CTRL_BUSWIDTH_MASK) 123 124 /* 125 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC: 126 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 127 * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 128 * Define this macro DMA error INT for fsl eSDHC 129 */ 130 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 131 132 /* the address offset of CQHCI */ 133 #define ESDHC_CQHCI_ADDR_OFFSET 0x100 134 135 /* 136 * The CMDTYPE of the CMD register (offset 0xE) should be set to 137 * "11" when the STOP CMD12 is issued on imx53 to abort one 138 * open ended multi-blk IO. Otherwise the TC INT wouldn't 139 * be generated. 140 * In exact block transfer, the controller doesn't complete the 141 * operations automatically as required at the end of the 142 * transfer and remains on hold if the abort command is not sent. 143 * As a result, the TC flag is not asserted and SW received timeout 144 * exception. Bit1 of Vendor Spec register is used to fix it. 145 */ 146 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 147 /* 148 * The flag tells that the ESDHC controller is an USDHC block that is 149 * integrated on the i.MX6 series. 150 */ 151 #define ESDHC_FLAG_USDHC BIT(3) 152 /* The IP supports manual tuning process */ 153 #define ESDHC_FLAG_MAN_TUNING BIT(4) 154 /* The IP supports standard tuning process */ 155 #define ESDHC_FLAG_STD_TUNING BIT(5) 156 /* The IP has SDHCI_CAPABILITIES_1 register */ 157 #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 158 /* 159 * The IP has erratum ERR004536 160 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 161 * when reading data from the card 162 * This flag is also set for i.MX25 and i.MX35 in order to get 163 * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits). 164 */ 165 #define ESDHC_FLAG_ERR004536 BIT(7) 166 /* The IP supports HS200 mode */ 167 #define ESDHC_FLAG_HS200 BIT(8) 168 /* The IP supports HS400 mode */ 169 #define ESDHC_FLAG_HS400 BIT(9) 170 /* 171 * The IP has errata ERR010450 172 * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't 173 * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz. 174 */ 175 #define ESDHC_FLAG_ERR010450 BIT(10) 176 /* The IP supports HS400ES mode */ 177 #define ESDHC_FLAG_HS400_ES BIT(11) 178 /* The IP has Host Controller Interface for Command Queuing */ 179 #define ESDHC_FLAG_CQHCI BIT(12) 180 /* need request pmqos during low power */ 181 #define ESDHC_FLAG_PMQOS BIT(13) 182 /* The IP state got lost in low power mode */ 183 #define ESDHC_FLAG_STATE_LOST_IN_LPMODE BIT(14) 184 /* The IP lost clock rate in PM_RUNTIME */ 185 #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME BIT(15) 186 /* 187 * The IP do not support the ACMD23 feature completely when use ADMA mode. 188 * In ADMA mode, it only use the 16 bit block count of the register 0x4 189 * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will 190 * ignore the upper 16 bit of the CMD23's argument. This will block the reliable 191 * write operation in RPMB, because RPMB reliable write need to set the bit31 192 * of the CMD23's argument. 193 * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA 194 * do not has this limitation. so when these SoC use ADMA mode, it need to 195 * disable the ACMD23 feature. 196 */ 197 #define ESDHC_FLAG_BROKEN_AUTO_CMD23 BIT(16) 198 199 enum wp_types { 200 ESDHC_WP_NONE, /* no WP, neither controller nor gpio */ 201 ESDHC_WP_CONTROLLER, /* mmc controller internal WP */ 202 ESDHC_WP_GPIO, /* external gpio pin for WP */ 203 }; 204 205 enum cd_types { 206 ESDHC_CD_NONE, /* no CD, neither controller nor gpio */ 207 ESDHC_CD_CONTROLLER, /* mmc controller internal CD */ 208 ESDHC_CD_GPIO, /* external gpio pin for CD */ 209 ESDHC_CD_PERMANENT, /* no CD, card permanently wired to host */ 210 }; 211 212 /* 213 * struct esdhc_platform_data - platform data for esdhc on i.MX 214 * 215 * ESDHC_WP(CD)_CONTROLLER type is not available on i.MX25/35. 216 * 217 * @wp_type: type of write_protect method (see wp_types enum above) 218 * @cd_type: type of card_detect method (see cd_types enum above) 219 */ 220 221 struct esdhc_platform_data { 222 enum wp_types wp_type; 223 enum cd_types cd_type; 224 int max_bus_width; 225 unsigned int delay_line; 226 unsigned int tuning_step; /* The delay cell steps in tuning procedure */ 227 unsigned int tuning_start_tap; /* The start delay cell point in tuning procedure */ 228 unsigned int strobe_dll_delay_target; /* The delay cell for strobe pad (read clock) */ 229 }; 230 231 struct esdhc_soc_data { 232 u32 flags; 233 }; 234 235 static const struct esdhc_soc_data esdhc_imx25_data = { 236 .flags = ESDHC_FLAG_ERR004536, 237 }; 238 239 static const struct esdhc_soc_data esdhc_imx35_data = { 240 .flags = ESDHC_FLAG_ERR004536, 241 }; 242 243 static const struct esdhc_soc_data esdhc_imx51_data = { 244 .flags = 0, 245 }; 246 247 static const struct esdhc_soc_data esdhc_imx53_data = { 248 .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 249 }; 250 251 static const struct esdhc_soc_data usdhc_imx6q_data = { 252 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 253 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 254 }; 255 256 static const struct esdhc_soc_data usdhc_imx6sl_data = { 257 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 258 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 259 | ESDHC_FLAG_HS200 260 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 261 }; 262 263 static const struct esdhc_soc_data usdhc_imx6sll_data = { 264 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 265 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 266 | ESDHC_FLAG_HS400 267 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 268 }; 269 270 static const struct esdhc_soc_data usdhc_imx6sx_data = { 271 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 272 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 273 | ESDHC_FLAG_STATE_LOST_IN_LPMODE 274 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 275 }; 276 277 static const struct esdhc_soc_data usdhc_imx6ull_data = { 278 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 279 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 280 | ESDHC_FLAG_ERR010450 281 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 282 }; 283 284 static const struct esdhc_soc_data usdhc_imx7d_data = { 285 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 286 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 287 | ESDHC_FLAG_HS400 288 | ESDHC_FLAG_STATE_LOST_IN_LPMODE 289 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 290 }; 291 292 static struct esdhc_soc_data usdhc_imx7ulp_data = { 293 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 294 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 295 | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400 296 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 297 }; 298 299 static struct esdhc_soc_data usdhc_imx8qxp_data = { 300 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 301 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 302 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 303 | ESDHC_FLAG_STATE_LOST_IN_LPMODE 304 | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME, 305 }; 306 307 static struct esdhc_soc_data usdhc_imx8mm_data = { 308 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 309 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 310 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 311 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 312 }; 313 314 struct pltfm_imx_data { 315 u32 scratchpad; 316 struct pinctrl *pinctrl; 317 struct pinctrl_state *pins_100mhz; 318 struct pinctrl_state *pins_200mhz; 319 const struct esdhc_soc_data *socdata; 320 struct esdhc_platform_data boarddata; 321 struct clk *clk_ipg; 322 struct clk *clk_ahb; 323 struct clk *clk_per; 324 unsigned int actual_clock; 325 enum { 326 NO_CMD_PENDING, /* no multiblock command pending */ 327 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 328 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 329 } multiblock_status; 330 u32 is_ddr; 331 struct pm_qos_request pm_qos_req; 332 }; 333 334 static const struct of_device_id imx_esdhc_dt_ids[] = { 335 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 336 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 337 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 338 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 339 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 340 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 341 { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, }, 342 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 343 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, }, 344 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, 345 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, }, 346 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, }, 347 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, }, 348 { /* sentinel */ } 349 }; 350 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 351 352 static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 353 { 354 return data->socdata == &esdhc_imx25_data; 355 } 356 357 static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 358 { 359 return data->socdata == &esdhc_imx53_data; 360 } 361 362 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 363 { 364 return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 365 } 366 367 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 368 { 369 void __iomem *base = host->ioaddr + (reg & ~0x3); 370 u32 shift = (reg & 0x3) * 8; 371 372 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 373 } 374 375 #define DRIVER_NAME "sdhci-esdhc-imx" 376 #define ESDHC_IMX_DUMP(f, x...) \ 377 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) 378 static void esdhc_dump_debug_regs(struct sdhci_host *host) 379 { 380 int i; 381 char *debug_status[7] = { 382 "cmd debug status", 383 "data debug status", 384 "trans debug status", 385 "dma debug status", 386 "adma debug status", 387 "fifo debug status", 388 "async fifo debug status" 389 }; 390 391 ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n"); 392 for (i = 0; i < 7; i++) { 393 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 394 ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG); 395 ESDHC_IMX_DUMP("%s: 0x%04x\n", debug_status[i], 396 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG)); 397 } 398 399 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG); 400 401 } 402 403 static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host) 404 { 405 u32 present_state; 406 int ret; 407 408 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state, 409 (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100); 410 if (ret == -ETIMEDOUT) 411 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__); 412 } 413 414 /* Enable the auto tuning circuit to check the CMD line and BUS line */ 415 static inline void usdhc_auto_tuning_mode_sel(struct sdhci_host *host) 416 { 417 u32 buswidth, auto_tune_buswidth; 418 419 buswidth = USDHC_GET_BUSWIDTH(readl(host->ioaddr + SDHCI_HOST_CONTROL)); 420 421 switch (buswidth) { 422 case ESDHC_CTRL_8BITBUS: 423 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN; 424 break; 425 case ESDHC_CTRL_4BITBUS: 426 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN; 427 break; 428 default: /* 1BITBUS */ 429 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN; 430 break; 431 } 432 433 esdhc_clrset_le(host, ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK, 434 auto_tune_buswidth | ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN, 435 ESDHC_VEND_SPEC2); 436 } 437 438 static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 439 { 440 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 441 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 442 u32 val = readl(host->ioaddr + reg); 443 444 if (unlikely(reg == SDHCI_PRESENT_STATE)) { 445 u32 fsl_prss = val; 446 /* save the least 20 bits */ 447 val = fsl_prss & 0x000FFFFF; 448 /* move dat[0-3] bits */ 449 val |= (fsl_prss & 0x0F000000) >> 4; 450 /* move cmd line bit */ 451 val |= (fsl_prss & 0x00800000) << 1; 452 } 453 454 if (unlikely(reg == SDHCI_CAPABILITIES)) { 455 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 456 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 457 val &= 0xffff0000; 458 459 /* In FSL esdhc IC module, only bit20 is used to indicate the 460 * ADMA2 capability of esdhc, but this bit is messed up on 461 * some SOCs (e.g. on MX25, MX35 this bit is set, but they 462 * don't actually support ADMA2). So set the BROKEN_ADMA 463 * quirk on MX25/35 platforms. 464 */ 465 466 if (val & SDHCI_CAN_DO_ADMA1) { 467 val &= ~SDHCI_CAN_DO_ADMA1; 468 val |= SDHCI_CAN_DO_ADMA2; 469 } 470 } 471 472 if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 473 if (esdhc_is_usdhc(imx_data)) { 474 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 475 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 476 else 477 /* imx6q/dl does not have cap_1 register, fake one */ 478 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 479 | SDHCI_SUPPORT_SDR50 480 | SDHCI_USE_SDR50_TUNING 481 | FIELD_PREP(SDHCI_RETUNING_MODE_MASK, 482 SDHCI_TUNING_MODE_3); 483 484 /* 485 * Do not advertise faster UHS modes if there are no 486 * pinctrl states for 100MHz/200MHz. 487 */ 488 if (IS_ERR_OR_NULL(imx_data->pins_100mhz)) 489 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); 490 if (IS_ERR_OR_NULL(imx_data->pins_200mhz)) 491 val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400); 492 } 493 } 494 495 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 496 val = 0; 497 val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF); 498 val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF); 499 val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF); 500 } 501 502 if (unlikely(reg == SDHCI_INT_STATUS)) { 503 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 504 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 505 val |= SDHCI_INT_ADMA_ERROR; 506 } 507 508 /* 509 * mask off the interrupt we get in response to the manually 510 * sent CMD12 511 */ 512 if ((imx_data->multiblock_status == WAIT_FOR_INT) && 513 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 514 val &= ~SDHCI_INT_RESPONSE; 515 writel(SDHCI_INT_RESPONSE, host->ioaddr + 516 SDHCI_INT_STATUS); 517 imx_data->multiblock_status = NO_CMD_PENDING; 518 } 519 } 520 521 return val; 522 } 523 524 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 525 { 526 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 527 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 528 u32 data; 529 530 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || 531 reg == SDHCI_INT_STATUS)) { 532 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 533 /* 534 * Clear and then set D3CD bit to avoid missing the 535 * card interrupt. This is an eSDHC controller problem 536 * so we need to apply the following workaround: clear 537 * and set D3CD bit will make eSDHC re-sample the card 538 * interrupt. In case a card interrupt was lost, 539 * re-sample it by the following steps. 540 */ 541 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 542 data &= ~ESDHC_CTRL_D3CD; 543 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 544 data |= ESDHC_CTRL_D3CD; 545 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 546 } 547 548 if (val & SDHCI_INT_ADMA_ERROR) { 549 val &= ~SDHCI_INT_ADMA_ERROR; 550 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 551 } 552 } 553 554 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 555 && (reg == SDHCI_INT_STATUS) 556 && (val & SDHCI_INT_DATA_END))) { 557 u32 v; 558 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 559 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 560 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 561 562 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 563 { 564 /* send a manual CMD12 with RESPTYP=none */ 565 data = MMC_STOP_TRANSMISSION << 24 | 566 SDHCI_CMD_ABORTCMD << 16; 567 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 568 imx_data->multiblock_status = WAIT_FOR_INT; 569 } 570 } 571 572 writel(val, host->ioaddr + reg); 573 } 574 575 static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 576 { 577 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 578 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 579 u16 ret = 0; 580 u32 val; 581 582 if (unlikely(reg == SDHCI_HOST_VERSION)) { 583 reg ^= 2; 584 if (esdhc_is_usdhc(imx_data)) { 585 /* 586 * The usdhc register returns a wrong host version. 587 * Correct it here. 588 */ 589 return SDHCI_SPEC_300; 590 } 591 } 592 593 if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 594 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 595 if (val & ESDHC_VENDOR_SPEC_VSELECT) 596 ret |= SDHCI_CTRL_VDD_180; 597 598 if (esdhc_is_usdhc(imx_data)) { 599 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 600 val = readl(host->ioaddr + ESDHC_MIX_CTRL); 601 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 602 /* the std tuning bits is in ACMD12_ERR for imx6sl */ 603 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 604 } 605 606 if (val & ESDHC_MIX_CTRL_EXE_TUNE) 607 ret |= SDHCI_CTRL_EXEC_TUNING; 608 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 609 ret |= SDHCI_CTRL_TUNED_CLK; 610 611 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 612 613 return ret; 614 } 615 616 if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 617 if (esdhc_is_usdhc(imx_data)) { 618 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 619 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 620 /* Swap AC23 bit */ 621 if (m & ESDHC_MIX_CTRL_AC23EN) { 622 ret &= ~ESDHC_MIX_CTRL_AC23EN; 623 ret |= SDHCI_TRNS_AUTO_CMD23; 624 } 625 } else { 626 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 627 } 628 629 return ret; 630 } 631 632 return readw(host->ioaddr + reg); 633 } 634 635 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 636 { 637 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 638 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 639 u32 new_val = 0; 640 641 switch (reg) { 642 case SDHCI_CLOCK_CONTROL: 643 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 644 if (val & SDHCI_CLOCK_CARD_EN) 645 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 646 else 647 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 648 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 649 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON)) 650 esdhc_wait_for_card_clock_gate_off(host); 651 return; 652 case SDHCI_HOST_CONTROL2: 653 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 654 if (val & SDHCI_CTRL_VDD_180) 655 new_val |= ESDHC_VENDOR_SPEC_VSELECT; 656 else 657 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 658 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 659 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 660 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 661 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 662 if (val & SDHCI_CTRL_TUNED_CLK) { 663 v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 664 } else { 665 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 666 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 667 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 668 } 669 670 if (val & SDHCI_CTRL_EXEC_TUNING) { 671 v |= ESDHC_MIX_CTRL_EXE_TUNE; 672 m |= ESDHC_MIX_CTRL_FBCLK_SEL; 673 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 674 usdhc_auto_tuning_mode_sel(host); 675 } else { 676 v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 677 } 678 679 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 680 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 681 } 682 return; 683 case SDHCI_TRANSFER_MODE: 684 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 685 && (host->cmd->opcode == SD_IO_RW_EXTENDED) 686 && (host->cmd->data->blocks > 1) 687 && (host->cmd->data->flags & MMC_DATA_READ)) { 688 u32 v; 689 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 690 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 691 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 692 } 693 694 if (esdhc_is_usdhc(imx_data)) { 695 u32 wml; 696 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 697 /* Swap AC23 bit */ 698 if (val & SDHCI_TRNS_AUTO_CMD23) { 699 val &= ~SDHCI_TRNS_AUTO_CMD23; 700 val |= ESDHC_MIX_CTRL_AC23EN; 701 } 702 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 703 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 704 705 /* Set watermark levels for PIO access to maximum value 706 * (128 words) to accommodate full 512 bytes buffer. 707 * For DMA access restore the levels to default value. 708 */ 709 m = readl(host->ioaddr + ESDHC_WTMK_LVL); 710 if (val & SDHCI_TRNS_DMA) { 711 wml = ESDHC_WTMK_LVL_WML_VAL_DEF; 712 } else { 713 u8 ctrl; 714 wml = ESDHC_WTMK_LVL_WML_VAL_MAX; 715 716 /* 717 * Since already disable DMA mode, so also need 718 * to clear the DMASEL. Otherwise, for standard 719 * tuning, when send tuning command, usdhc will 720 * still prefetch the ADMA script from wrong 721 * DMA address, then we will see IOMMU report 722 * some error which show lack of TLB mapping. 723 */ 724 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 725 ctrl &= ~SDHCI_CTRL_DMA_MASK; 726 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 727 } 728 m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK | 729 ESDHC_WTMK_LVL_WR_WML_MASK); 730 m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) | 731 (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT); 732 writel(m, host->ioaddr + ESDHC_WTMK_LVL); 733 } else { 734 /* 735 * Postpone this write, we must do it together with a 736 * command write that is down below. 737 */ 738 imx_data->scratchpad = val; 739 } 740 return; 741 case SDHCI_COMMAND: 742 if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 743 val |= SDHCI_CMD_ABORTCMD; 744 745 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 746 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 747 imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 748 749 if (esdhc_is_usdhc(imx_data)) 750 writel(val << 16, 751 host->ioaddr + SDHCI_TRANSFER_MODE); 752 else 753 writel(val << 16 | imx_data->scratchpad, 754 host->ioaddr + SDHCI_TRANSFER_MODE); 755 return; 756 case SDHCI_BLOCK_SIZE: 757 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 758 break; 759 } 760 esdhc_clrset_le(host, 0xffff, val, reg); 761 } 762 763 static u8 esdhc_readb_le(struct sdhci_host *host, int reg) 764 { 765 u8 ret; 766 u32 val; 767 768 switch (reg) { 769 case SDHCI_HOST_CONTROL: 770 val = readl(host->ioaddr + reg); 771 772 ret = val & SDHCI_CTRL_LED; 773 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; 774 ret |= (val & ESDHC_CTRL_4BITBUS); 775 ret |= (val & ESDHC_CTRL_8BITBUS) << 3; 776 return ret; 777 } 778 779 return readb(host->ioaddr + reg); 780 } 781 782 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 783 { 784 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 785 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 786 u32 new_val = 0; 787 u32 mask; 788 789 switch (reg) { 790 case SDHCI_POWER_CONTROL: 791 /* 792 * FSL put some DMA bits here 793 * If your board has a regulator, code should be here 794 */ 795 return; 796 case SDHCI_HOST_CONTROL: 797 /* FSL messed up here, so we need to manually compose it. */ 798 new_val = val & SDHCI_CTRL_LED; 799 /* ensure the endianness */ 800 new_val |= ESDHC_HOST_CONTROL_LE; 801 /* bits 8&9 are reserved on mx25 */ 802 if (!is_imx25_esdhc(imx_data)) { 803 /* DMA mode bits are shifted */ 804 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 805 } 806 807 /* 808 * Do not touch buswidth bits here. This is done in 809 * esdhc_pltfm_bus_width. 810 * Do not touch the D3CD bit either which is used for the 811 * SDIO interrupt erratum workaround. 812 */ 813 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 814 815 esdhc_clrset_le(host, mask, new_val, reg); 816 return; 817 case SDHCI_SOFTWARE_RESET: 818 if (val & SDHCI_RESET_DATA) 819 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); 820 break; 821 } 822 esdhc_clrset_le(host, 0xff, val, reg); 823 824 if (reg == SDHCI_SOFTWARE_RESET) { 825 if (val & SDHCI_RESET_ALL) { 826 /* 827 * The esdhc has a design violation to SDHC spec which 828 * tells that software reset should not affect card 829 * detection circuit. But esdhc clears its SYSCTL 830 * register bits [0..2] during the software reset. This 831 * will stop those clocks that card detection circuit 832 * relies on. To work around it, we turn the clocks on 833 * back to keep card detection circuit functional. 834 */ 835 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 836 /* 837 * The reset on usdhc fails to clear MIX_CTRL register. 838 * Do it manually here. 839 */ 840 if (esdhc_is_usdhc(imx_data)) { 841 /* 842 * the tuning bits should be kept during reset 843 */ 844 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 845 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 846 host->ioaddr + ESDHC_MIX_CTRL); 847 imx_data->is_ddr = 0; 848 } 849 } else if (val & SDHCI_RESET_DATA) { 850 /* 851 * The eSDHC DAT line software reset clears at least the 852 * data transfer width on i.MX25, so make sure that the 853 * Host Control register is unaffected. 854 */ 855 esdhc_clrset_le(host, 0xff, new_val, 856 SDHCI_HOST_CONTROL); 857 } 858 } 859 } 860 861 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 862 { 863 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 864 865 return pltfm_host->clock; 866 } 867 868 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 869 { 870 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 871 872 return pltfm_host->clock / 256 / 16; 873 } 874 875 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 876 unsigned int clock) 877 { 878 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 879 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 880 unsigned int host_clock = pltfm_host->clock; 881 int ddr_pre_div = imx_data->is_ddr ? 2 : 1; 882 int pre_div = 1; 883 int div = 1; 884 int ret; 885 u32 temp, val; 886 887 if (esdhc_is_usdhc(imx_data)) { 888 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 889 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 890 host->ioaddr + ESDHC_VENDOR_SPEC); 891 esdhc_wait_for_card_clock_gate_off(host); 892 } 893 894 if (clock == 0) { 895 host->mmc->actual_clock = 0; 896 return; 897 } 898 899 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ 900 if (is_imx53_esdhc(imx_data)) { 901 /* 902 * According to the i.MX53 reference manual, if DLLCTRL[10] can 903 * be set, then the controller is eSDHCv3, else it is eSDHCv2. 904 */ 905 val = readl(host->ioaddr + ESDHC_DLL_CTRL); 906 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); 907 temp = readl(host->ioaddr + ESDHC_DLL_CTRL); 908 writel(val, host->ioaddr + ESDHC_DLL_CTRL); 909 if (temp & BIT(10)) 910 pre_div = 2; 911 } 912 913 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 914 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 915 | ESDHC_CLOCK_MASK); 916 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 917 918 if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) { 919 unsigned int max_clock; 920 921 max_clock = imx_data->is_ddr ? 45000000 : 150000000; 922 923 clock = min(clock, max_clock); 924 } 925 926 while (host_clock / (16 * pre_div * ddr_pre_div) > clock && 927 pre_div < 256) 928 pre_div *= 2; 929 930 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16) 931 div++; 932 933 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); 934 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 935 clock, host->mmc->actual_clock); 936 937 pre_div >>= 1; 938 div--; 939 940 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 941 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 942 | (div << ESDHC_DIVIDER_SHIFT) 943 | (pre_div << ESDHC_PREDIV_SHIFT)); 944 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 945 946 /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */ 947 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp, 948 (temp & ESDHC_CLOCK_STABLE), 2, 100); 949 if (ret == -ETIMEDOUT) 950 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n"); 951 952 if (esdhc_is_usdhc(imx_data)) { 953 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 954 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 955 host->ioaddr + ESDHC_VENDOR_SPEC); 956 } 957 958 } 959 960 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 961 { 962 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 963 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 964 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 965 966 switch (boarddata->wp_type) { 967 case ESDHC_WP_GPIO: 968 return mmc_gpio_get_ro(host->mmc); 969 case ESDHC_WP_CONTROLLER: 970 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 971 SDHCI_WRITE_PROTECT); 972 case ESDHC_WP_NONE: 973 break; 974 } 975 976 return -ENOSYS; 977 } 978 979 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 980 { 981 u32 ctrl; 982 983 switch (width) { 984 case MMC_BUS_WIDTH_8: 985 ctrl = ESDHC_CTRL_8BITBUS; 986 break; 987 case MMC_BUS_WIDTH_4: 988 ctrl = ESDHC_CTRL_4BITBUS; 989 break; 990 default: 991 ctrl = 0; 992 break; 993 } 994 995 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 996 SDHCI_HOST_CONTROL); 997 } 998 999 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1000 { 1001 struct sdhci_host *host = mmc_priv(mmc); 1002 1003 /* 1004 * i.MX uSDHC internally already uses a fixed optimized timing for 1005 * DDR50, normally does not require tuning for DDR50 mode. 1006 */ 1007 if (host->timing == MMC_TIMING_UHS_DDR50) 1008 return 0; 1009 1010 return sdhci_execute_tuning(mmc, opcode); 1011 } 1012 1013 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 1014 { 1015 u32 reg; 1016 u8 sw_rst; 1017 int ret; 1018 1019 /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 1020 mdelay(1); 1021 1022 /* IC suggest to reset USDHC before every tuning command */ 1023 esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET); 1024 ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst, 1025 !(sw_rst & SDHCI_RESET_ALL), 10, 100); 1026 if (ret == -ETIMEDOUT) 1027 dev_warn(mmc_dev(host->mmc), 1028 "warning! RESET_ALL never complete before sending tuning command\n"); 1029 1030 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 1031 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 1032 ESDHC_MIX_CTRL_FBCLK_SEL; 1033 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 1034 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1035 dev_dbg(mmc_dev(host->mmc), 1036 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 1037 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 1038 } 1039 1040 static void esdhc_post_tuning(struct sdhci_host *host) 1041 { 1042 u32 reg; 1043 1044 usdhc_auto_tuning_mode_sel(host); 1045 1046 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 1047 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 1048 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 1049 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 1050 } 1051 1052 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 1053 { 1054 int min, max, avg, ret; 1055 1056 /* find the mininum delay first which can pass tuning */ 1057 min = ESDHC_TUNE_CTRL_MIN; 1058 while (min < ESDHC_TUNE_CTRL_MAX) { 1059 esdhc_prepare_tuning(host, min); 1060 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 1061 break; 1062 min += ESDHC_TUNE_CTRL_STEP; 1063 } 1064 1065 /* find the maxinum delay which can not pass tuning */ 1066 max = min + ESDHC_TUNE_CTRL_STEP; 1067 while (max < ESDHC_TUNE_CTRL_MAX) { 1068 esdhc_prepare_tuning(host, max); 1069 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1070 max -= ESDHC_TUNE_CTRL_STEP; 1071 break; 1072 } 1073 max += ESDHC_TUNE_CTRL_STEP; 1074 } 1075 1076 /* use average delay to get the best timing */ 1077 avg = (min + max) / 2; 1078 esdhc_prepare_tuning(host, avg); 1079 ret = mmc_send_tuning(host->mmc, opcode, NULL); 1080 esdhc_post_tuning(host); 1081 1082 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 1083 ret ? "failed" : "passed", avg, ret); 1084 1085 return ret; 1086 } 1087 1088 static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) 1089 { 1090 struct sdhci_host *host = mmc_priv(mmc); 1091 u32 m; 1092 1093 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 1094 if (ios->enhanced_strobe) 1095 m |= ESDHC_MIX_CTRL_HS400_ES_EN; 1096 else 1097 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN; 1098 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1099 } 1100 1101 static int esdhc_change_pinstate(struct sdhci_host *host, 1102 unsigned int uhs) 1103 { 1104 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1105 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1106 struct pinctrl_state *pinctrl; 1107 1108 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 1109 1110 if (IS_ERR(imx_data->pinctrl) || 1111 IS_ERR(imx_data->pins_100mhz) || 1112 IS_ERR(imx_data->pins_200mhz)) 1113 return -EINVAL; 1114 1115 switch (uhs) { 1116 case MMC_TIMING_UHS_SDR50: 1117 case MMC_TIMING_UHS_DDR50: 1118 pinctrl = imx_data->pins_100mhz; 1119 break; 1120 case MMC_TIMING_UHS_SDR104: 1121 case MMC_TIMING_MMC_HS200: 1122 case MMC_TIMING_MMC_HS400: 1123 pinctrl = imx_data->pins_200mhz; 1124 break; 1125 default: 1126 /* back to default state for other legacy timing */ 1127 return pinctrl_select_default_state(mmc_dev(host->mmc)); 1128 } 1129 1130 return pinctrl_select_state(imx_data->pinctrl, pinctrl); 1131 } 1132 1133 /* 1134 * For HS400 eMMC, there is a data_strobe line. This signal is generated 1135 * by the device and used for data output and CRC status response output 1136 * in HS400 mode. The frequency of this signal follows the frequency of 1137 * CLK generated by host. The host receives the data which is aligned to the 1138 * edge of data_strobe line. Due to the time delay between CLK line and 1139 * data_strobe line, if the delay time is larger than one clock cycle, 1140 * then CLK and data_strobe line will be misaligned, read error shows up. 1141 */ 1142 static void esdhc_set_strobe_dll(struct sdhci_host *host) 1143 { 1144 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1145 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1146 u32 strobe_delay; 1147 u32 v; 1148 int ret; 1149 1150 /* disable clock before enabling strobe dll */ 1151 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & 1152 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 1153 host->ioaddr + ESDHC_VENDOR_SPEC); 1154 esdhc_wait_for_card_clock_gate_off(host); 1155 1156 /* force a reset on strobe dll */ 1157 writel(ESDHC_STROBE_DLL_CTRL_RESET, 1158 host->ioaddr + ESDHC_STROBE_DLL_CTRL); 1159 /* clear the reset bit on strobe dll before any setting */ 1160 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 1161 1162 /* 1163 * enable strobe dll ctrl and adjust the delay target 1164 * for the uSDHC loopback read clock 1165 */ 1166 if (imx_data->boarddata.strobe_dll_delay_target) 1167 strobe_delay = imx_data->boarddata.strobe_dll_delay_target; 1168 else 1169 strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT; 1170 v = ESDHC_STROBE_DLL_CTRL_ENABLE | 1171 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT | 1172 (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 1173 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 1174 1175 /* wait max 50us to get the REF/SLV lock */ 1176 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v, 1177 ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50); 1178 if (ret == -ETIMEDOUT) 1179 dev_warn(mmc_dev(host->mmc), 1180 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v); 1181 } 1182 1183 static void esdhc_reset_tuning(struct sdhci_host *host) 1184 { 1185 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1186 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1187 u32 ctrl; 1188 int ret; 1189 1190 /* Reset the tuning circuit */ 1191 if (esdhc_is_usdhc(imx_data)) { 1192 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1193 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); 1194 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1195 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 1196 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 1197 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1198 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1199 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1200 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1201 ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE; 1202 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1203 /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */ 1204 ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS, 1205 ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50); 1206 if (ret == -ETIMEDOUT) 1207 dev_warn(mmc_dev(host->mmc), 1208 "Warning! clear execute tuning bit failed\n"); 1209 /* 1210 * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the 1211 * usdhc IP internal logic flag execute_tuning_with_clr_buf, which 1212 * will finally make sure the normal data transfer logic correct. 1213 */ 1214 ctrl = readl(host->ioaddr + SDHCI_INT_STATUS); 1215 ctrl |= SDHCI_INT_DATA_AVAIL; 1216 writel(ctrl, host->ioaddr + SDHCI_INT_STATUS); 1217 } 1218 } 1219 } 1220 1221 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1222 { 1223 u32 m; 1224 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1225 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1226 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1227 1228 /* disable ddr mode and disable HS400 mode */ 1229 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 1230 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); 1231 imx_data->is_ddr = 0; 1232 1233 switch (timing) { 1234 case MMC_TIMING_UHS_SDR12: 1235 case MMC_TIMING_UHS_SDR25: 1236 case MMC_TIMING_UHS_SDR50: 1237 case MMC_TIMING_UHS_SDR104: 1238 case MMC_TIMING_MMC_HS: 1239 case MMC_TIMING_MMC_HS200: 1240 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1241 break; 1242 case MMC_TIMING_UHS_DDR50: 1243 case MMC_TIMING_MMC_DDR52: 1244 m |= ESDHC_MIX_CTRL_DDREN; 1245 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1246 imx_data->is_ddr = 1; 1247 if (boarddata->delay_line) { 1248 u32 v; 1249 v = boarddata->delay_line << 1250 ESDHC_DLL_OVERRIDE_VAL_SHIFT | 1251 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 1252 if (is_imx53_esdhc(imx_data)) 1253 v <<= 1; 1254 writel(v, host->ioaddr + ESDHC_DLL_CTRL); 1255 } 1256 break; 1257 case MMC_TIMING_MMC_HS400: 1258 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 1259 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1260 imx_data->is_ddr = 1; 1261 /* update clock after enable DDR for strobe DLL lock */ 1262 host->ops->set_clock(host, host->clock); 1263 esdhc_set_strobe_dll(host); 1264 break; 1265 case MMC_TIMING_LEGACY: 1266 default: 1267 esdhc_reset_tuning(host); 1268 break; 1269 } 1270 1271 esdhc_change_pinstate(host, timing); 1272 } 1273 1274 static void esdhc_reset(struct sdhci_host *host, u8 mask) 1275 { 1276 sdhci_reset(host, mask); 1277 1278 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1279 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1280 } 1281 1282 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 1283 { 1284 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1285 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1286 1287 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */ 1288 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27; 1289 } 1290 1291 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 1292 { 1293 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1294 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1295 1296 /* use maximum timeout counter */ 1297 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, 1298 esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 1299 SDHCI_TIMEOUT_CONTROL); 1300 } 1301 1302 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask) 1303 { 1304 int cmd_error = 0; 1305 int data_error = 0; 1306 1307 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1308 return intmask; 1309 1310 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1311 1312 return 0; 1313 } 1314 1315 static struct sdhci_ops sdhci_esdhc_ops = { 1316 .read_l = esdhc_readl_le, 1317 .read_w = esdhc_readw_le, 1318 .read_b = esdhc_readb_le, 1319 .write_l = esdhc_writel_le, 1320 .write_w = esdhc_writew_le, 1321 .write_b = esdhc_writeb_le, 1322 .set_clock = esdhc_pltfm_set_clock, 1323 .get_max_clock = esdhc_pltfm_get_max_clock, 1324 .get_min_clock = esdhc_pltfm_get_min_clock, 1325 .get_max_timeout_count = esdhc_get_max_timeout_count, 1326 .get_ro = esdhc_pltfm_get_ro, 1327 .set_timeout = esdhc_set_timeout, 1328 .set_bus_width = esdhc_pltfm_set_bus_width, 1329 .set_uhs_signaling = esdhc_set_uhs_signaling, 1330 .reset = esdhc_reset, 1331 .irq = esdhc_cqhci_irq, 1332 .dump_vendor_regs = esdhc_dump_debug_regs, 1333 }; 1334 1335 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 1336 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 1337 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 1338 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 1339 | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 1340 .ops = &sdhci_esdhc_ops, 1341 }; 1342 1343 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) 1344 { 1345 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1346 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1347 struct cqhci_host *cq_host = host->mmc->cqe_private; 1348 int tmp; 1349 1350 if (esdhc_is_usdhc(imx_data)) { 1351 /* 1352 * The imx6q ROM code will change the default watermark 1353 * level setting to something insane. Change it back here. 1354 */ 1355 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); 1356 1357 /* 1358 * ROM code will change the bit burst_length_enable setting 1359 * to zero if this usdhc is chosen to boot system. Change 1360 * it back here, otherwise it will impact the performance a 1361 * lot. This bit is used to enable/disable the burst length 1362 * for the external AHB2AXI bridge. It's useful especially 1363 * for INCR transfer because without burst length indicator, 1364 * the AHB2AXI bridge does not know the burst length in 1365 * advance. And without burst length indicator, AHB INCR 1366 * transfer can only be converted to singles on the AXI side. 1367 */ 1368 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) 1369 | ESDHC_BURST_LEN_EN_INCR, 1370 host->ioaddr + SDHCI_HOST_CONTROL); 1371 1372 /* 1373 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 1374 * TO1.1, it's harmless for MX6SL 1375 */ 1376 writel(readl(host->ioaddr + 0x6c) & ~BIT(7), 1377 host->ioaddr + 0x6c); 1378 1379 /* disable DLL_CTRL delay line settings */ 1380 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); 1381 1382 /* 1383 * For the case of command with busy, if set the bit 1384 * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a 1385 * transfer complete interrupt when busy is deasserted. 1386 * When CQHCI use DCMD to send a CMD need R1b respons, 1387 * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ, 1388 * otherwise DCMD will always meet timeout waiting for 1389 * hardware interrupt issue. 1390 */ 1391 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1392 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2); 1393 tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ; 1394 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2); 1395 1396 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1397 } 1398 1399 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1400 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1401 tmp |= ESDHC_STD_TUNING_EN | 1402 ESDHC_TUNING_START_TAP_DEFAULT; 1403 if (imx_data->boarddata.tuning_start_tap) { 1404 tmp &= ~ESDHC_TUNING_START_TAP_MASK; 1405 tmp |= imx_data->boarddata.tuning_start_tap; 1406 } 1407 1408 if (imx_data->boarddata.tuning_step) { 1409 tmp &= ~ESDHC_TUNING_STEP_MASK; 1410 tmp |= imx_data->boarddata.tuning_step 1411 << ESDHC_TUNING_STEP_SHIFT; 1412 } 1413 1414 /* Disable the CMD CRC check for tuning, if not, need to 1415 * add some delay after every tuning command, because 1416 * hardware standard tuning logic will directly go to next 1417 * step once it detect the CMD CRC error, will not wait for 1418 * the card side to finally send out the tuning data, trigger 1419 * the buffer read ready interrupt immediately. If usdhc send 1420 * the next tuning command some eMMC card will stuck, can't 1421 * response, block the tuning procedure or the first command 1422 * after the whole tuning procedure always can't get any response. 1423 */ 1424 tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE; 1425 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1426 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1427 /* 1428 * ESDHC_STD_TUNING_EN may be configed in bootloader 1429 * or ROM code, so clear this bit here to make sure 1430 * the manual tuning can work. 1431 */ 1432 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1433 tmp &= ~ESDHC_STD_TUNING_EN; 1434 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1435 } 1436 1437 /* 1438 * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card 1439 * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let the 1440 * the 1st linux configure power/clock for the 2nd Linux. 1441 * 1442 * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux 1443 * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump. 1444 * After we clear the pending interrupt and halt CQCTL, issue gone. 1445 */ 1446 if (cq_host) { 1447 tmp = cqhci_readl(cq_host, CQHCI_IS); 1448 cqhci_writel(cq_host, tmp, CQHCI_IS); 1449 cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL); 1450 } 1451 } 1452 } 1453 1454 static void esdhc_cqe_enable(struct mmc_host *mmc) 1455 { 1456 struct sdhci_host *host = mmc_priv(mmc); 1457 struct cqhci_host *cq_host = mmc->cqe_private; 1458 u32 reg; 1459 u16 mode; 1460 int count = 10; 1461 1462 /* 1463 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be 1464 * the case after tuning, so ensure the buffer is drained. 1465 */ 1466 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1467 while (reg & SDHCI_DATA_AVAILABLE) { 1468 sdhci_readl(host, SDHCI_BUFFER); 1469 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1470 if (count-- == 0) { 1471 dev_warn(mmc_dev(host->mmc), 1472 "CQE may get stuck because the Buffer Read Enable bit is set\n"); 1473 break; 1474 } 1475 mdelay(1); 1476 } 1477 1478 /* 1479 * Runtime resume will reset the entire host controller, which 1480 * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL. 1481 * Here set DMAEN and BCEN when enable CMDQ. 1482 */ 1483 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 1484 if (host->flags & SDHCI_REQ_USE_DMA) 1485 mode |= SDHCI_TRNS_DMA; 1486 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 1487 mode |= SDHCI_TRNS_BLK_CNT_EN; 1488 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 1489 1490 /* 1491 * Though Runtime resume reset the entire host controller, 1492 * but do not impact the CQHCI side, need to clear the 1493 * HALT bit, avoid CQHCI stuck in the first request when 1494 * system resume back. 1495 */ 1496 cqhci_writel(cq_host, 0, CQHCI_CTL); 1497 if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT) 1498 dev_err(mmc_dev(host->mmc), 1499 "failed to exit halt state when enable CQE\n"); 1500 1501 1502 sdhci_cqe_enable(mmc); 1503 } 1504 1505 static void esdhc_sdhci_dumpregs(struct mmc_host *mmc) 1506 { 1507 sdhci_dumpregs(mmc_priv(mmc)); 1508 } 1509 1510 static const struct cqhci_host_ops esdhc_cqhci_ops = { 1511 .enable = esdhc_cqe_enable, 1512 .disable = sdhci_cqe_disable, 1513 .dumpregs = esdhc_sdhci_dumpregs, 1514 }; 1515 1516 static int 1517 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 1518 struct sdhci_host *host, 1519 struct pltfm_imx_data *imx_data) 1520 { 1521 struct device_node *np = pdev->dev.of_node; 1522 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1523 int ret; 1524 1525 if (of_get_property(np, "fsl,wp-controller", NULL)) 1526 boarddata->wp_type = ESDHC_WP_CONTROLLER; 1527 1528 /* 1529 * If we have this property, then activate WP check. 1530 * Retrieveing and requesting the actual WP GPIO will happen 1531 * in the call to mmc_of_parse(). 1532 */ 1533 if (of_property_read_bool(np, "wp-gpios")) 1534 boarddata->wp_type = ESDHC_WP_GPIO; 1535 1536 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 1537 of_property_read_u32(np, "fsl,tuning-start-tap", 1538 &boarddata->tuning_start_tap); 1539 1540 of_property_read_u32(np, "fsl,strobe-dll-delay-target", 1541 &boarddata->strobe_dll_delay_target); 1542 if (of_find_property(np, "no-1-8-v", NULL)) 1543 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1544 1545 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 1546 boarddata->delay_line = 0; 1547 1548 mmc_of_parse_voltage(host->mmc, &host->ocr_mask); 1549 1550 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) { 1551 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 1552 ESDHC_PINCTRL_STATE_100MHZ); 1553 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 1554 ESDHC_PINCTRL_STATE_200MHZ); 1555 } 1556 1557 /* call to generic mmc_of_parse to support additional capabilities */ 1558 ret = mmc_of_parse(host->mmc); 1559 if (ret) 1560 return ret; 1561 1562 if (mmc_gpio_get_cd(host->mmc) >= 0) 1563 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1564 1565 return 0; 1566 } 1567 1568 static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 1569 { 1570 struct sdhci_pltfm_host *pltfm_host; 1571 struct sdhci_host *host; 1572 struct cqhci_host *cq_host; 1573 int err; 1574 struct pltfm_imx_data *imx_data; 1575 1576 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 1577 sizeof(*imx_data)); 1578 if (IS_ERR(host)) 1579 return PTR_ERR(host); 1580 1581 pltfm_host = sdhci_priv(host); 1582 1583 imx_data = sdhci_pltfm_priv(pltfm_host); 1584 1585 imx_data->socdata = device_get_match_data(&pdev->dev); 1586 1587 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1588 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); 1589 1590 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1591 if (IS_ERR(imx_data->clk_ipg)) { 1592 err = PTR_ERR(imx_data->clk_ipg); 1593 goto free_sdhci; 1594 } 1595 1596 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1597 if (IS_ERR(imx_data->clk_ahb)) { 1598 err = PTR_ERR(imx_data->clk_ahb); 1599 goto free_sdhci; 1600 } 1601 1602 imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 1603 if (IS_ERR(imx_data->clk_per)) { 1604 err = PTR_ERR(imx_data->clk_per); 1605 goto free_sdhci; 1606 } 1607 1608 pltfm_host->clk = imx_data->clk_per; 1609 pltfm_host->clock = clk_get_rate(pltfm_host->clk); 1610 err = clk_prepare_enable(imx_data->clk_per); 1611 if (err) 1612 goto free_sdhci; 1613 err = clk_prepare_enable(imx_data->clk_ipg); 1614 if (err) 1615 goto disable_per_clk; 1616 err = clk_prepare_enable(imx_data->clk_ahb); 1617 if (err) 1618 goto disable_ipg_clk; 1619 1620 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1621 if (IS_ERR(imx_data->pinctrl)) 1622 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n"); 1623 1624 if (esdhc_is_usdhc(imx_data)) { 1625 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 1626 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; 1627 1628 /* GPIO CD can be set as a wakeup source */ 1629 host->mmc->caps |= MMC_CAP_CD_WAKE; 1630 1631 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 1632 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 1633 1634 /* clear tuning bits in case ROM has set it already */ 1635 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); 1636 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1637 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1638 1639 /* 1640 * Link usdhc specific mmc_host_ops execute_tuning function, 1641 * to replace the standard one in sdhci_ops. 1642 */ 1643 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning; 1644 } 1645 1646 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 1647 if (err) 1648 goto disable_ahb_clk; 1649 1650 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 1651 sdhci_esdhc_ops.platform_execute_tuning = 1652 esdhc_executing_tuning; 1653 1654 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 1655 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1656 1657 if (host->caps & MMC_CAP_8_BIT_DATA && 1658 imx_data->socdata->flags & ESDHC_FLAG_HS400) 1659 host->mmc->caps2 |= MMC_CAP2_HS400; 1660 1661 if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23) 1662 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN; 1663 1664 if (host->caps & MMC_CAP_8_BIT_DATA && 1665 imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) { 1666 host->mmc->caps2 |= MMC_CAP2_HS400_ES; 1667 host->mmc_host_ops.hs400_enhanced_strobe = 1668 esdhc_hs400_enhanced_strobe; 1669 } 1670 1671 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1672 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1673 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); 1674 if (!cq_host) { 1675 err = -ENOMEM; 1676 goto disable_ahb_clk; 1677 } 1678 1679 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET; 1680 cq_host->ops = &esdhc_cqhci_ops; 1681 1682 err = cqhci_init(cq_host, host->mmc, false); 1683 if (err) 1684 goto disable_ahb_clk; 1685 } 1686 1687 sdhci_esdhc_imx_hwinit(host); 1688 1689 err = sdhci_add_host(host); 1690 if (err) 1691 goto disable_ahb_clk; 1692 1693 /* 1694 * Setup the wakeup capability here, let user to decide 1695 * whether need to enable this wakeup through sysfs interface. 1696 */ 1697 if ((host->mmc->pm_caps & MMC_PM_KEEP_POWER) && 1698 (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)) 1699 device_set_wakeup_capable(&pdev->dev, true); 1700 1701 pm_runtime_set_active(&pdev->dev); 1702 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1703 pm_runtime_use_autosuspend(&pdev->dev); 1704 pm_suspend_ignore_children(&pdev->dev, 1); 1705 pm_runtime_enable(&pdev->dev); 1706 1707 return 0; 1708 1709 disable_ahb_clk: 1710 clk_disable_unprepare(imx_data->clk_ahb); 1711 disable_ipg_clk: 1712 clk_disable_unprepare(imx_data->clk_ipg); 1713 disable_per_clk: 1714 clk_disable_unprepare(imx_data->clk_per); 1715 free_sdhci: 1716 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1717 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 1718 sdhci_pltfm_free(pdev); 1719 return err; 1720 } 1721 1722 static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 1723 { 1724 struct sdhci_host *host = platform_get_drvdata(pdev); 1725 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1726 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1727 int dead; 1728 1729 pm_runtime_get_sync(&pdev->dev); 1730 dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 1731 pm_runtime_disable(&pdev->dev); 1732 pm_runtime_put_noidle(&pdev->dev); 1733 1734 sdhci_remove_host(host, dead); 1735 1736 clk_disable_unprepare(imx_data->clk_per); 1737 clk_disable_unprepare(imx_data->clk_ipg); 1738 clk_disable_unprepare(imx_data->clk_ahb); 1739 1740 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1741 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 1742 1743 sdhci_pltfm_free(pdev); 1744 1745 return 0; 1746 } 1747 1748 #ifdef CONFIG_PM_SLEEP 1749 static int sdhci_esdhc_suspend(struct device *dev) 1750 { 1751 struct sdhci_host *host = dev_get_drvdata(dev); 1752 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1753 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1754 int ret; 1755 1756 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1757 ret = cqhci_suspend(host->mmc); 1758 if (ret) 1759 return ret; 1760 } 1761 1762 if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) && 1763 (host->tuning_mode != SDHCI_TUNING_MODE_1)) { 1764 mmc_retune_timer_stop(host->mmc); 1765 mmc_retune_needed(host->mmc); 1766 } 1767 1768 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1769 mmc_retune_needed(host->mmc); 1770 1771 ret = sdhci_suspend_host(host); 1772 if (ret) 1773 return ret; 1774 1775 ret = pinctrl_pm_select_sleep_state(dev); 1776 if (ret) 1777 return ret; 1778 1779 ret = mmc_gpio_set_cd_wake(host->mmc, true); 1780 1781 return ret; 1782 } 1783 1784 static int sdhci_esdhc_resume(struct device *dev) 1785 { 1786 struct sdhci_host *host = dev_get_drvdata(dev); 1787 int ret; 1788 1789 ret = pinctrl_pm_select_default_state(dev); 1790 if (ret) 1791 return ret; 1792 1793 /* re-initialize hw state in case it's lost in low power mode */ 1794 sdhci_esdhc_imx_hwinit(host); 1795 1796 ret = sdhci_resume_host(host); 1797 if (ret) 1798 return ret; 1799 1800 if (host->mmc->caps2 & MMC_CAP2_CQE) 1801 ret = cqhci_resume(host->mmc); 1802 1803 if (!ret) 1804 ret = mmc_gpio_set_cd_wake(host->mmc, false); 1805 1806 return ret; 1807 } 1808 #endif 1809 1810 #ifdef CONFIG_PM 1811 static int sdhci_esdhc_runtime_suspend(struct device *dev) 1812 { 1813 struct sdhci_host *host = dev_get_drvdata(dev); 1814 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1815 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1816 int ret; 1817 1818 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1819 ret = cqhci_suspend(host->mmc); 1820 if (ret) 1821 return ret; 1822 } 1823 1824 ret = sdhci_runtime_suspend_host(host); 1825 if (ret) 1826 return ret; 1827 1828 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1829 mmc_retune_needed(host->mmc); 1830 1831 imx_data->actual_clock = host->mmc->actual_clock; 1832 esdhc_pltfm_set_clock(host, 0); 1833 clk_disable_unprepare(imx_data->clk_per); 1834 clk_disable_unprepare(imx_data->clk_ipg); 1835 clk_disable_unprepare(imx_data->clk_ahb); 1836 1837 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1838 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 1839 1840 return ret; 1841 } 1842 1843 static int sdhci_esdhc_runtime_resume(struct device *dev) 1844 { 1845 struct sdhci_host *host = dev_get_drvdata(dev); 1846 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1847 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1848 int err; 1849 1850 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1851 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); 1852 1853 if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME) 1854 clk_set_rate(imx_data->clk_per, pltfm_host->clock); 1855 1856 err = clk_prepare_enable(imx_data->clk_ahb); 1857 if (err) 1858 goto remove_pm_qos_request; 1859 1860 err = clk_prepare_enable(imx_data->clk_per); 1861 if (err) 1862 goto disable_ahb_clk; 1863 1864 err = clk_prepare_enable(imx_data->clk_ipg); 1865 if (err) 1866 goto disable_per_clk; 1867 1868 esdhc_pltfm_set_clock(host, imx_data->actual_clock); 1869 1870 err = sdhci_runtime_resume_host(host, 0); 1871 if (err) 1872 goto disable_ipg_clk; 1873 1874 if (host->mmc->caps2 & MMC_CAP2_CQE) 1875 err = cqhci_resume(host->mmc); 1876 1877 return err; 1878 1879 disable_ipg_clk: 1880 clk_disable_unprepare(imx_data->clk_ipg); 1881 disable_per_clk: 1882 clk_disable_unprepare(imx_data->clk_per); 1883 disable_ahb_clk: 1884 clk_disable_unprepare(imx_data->clk_ahb); 1885 remove_pm_qos_request: 1886 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1887 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 1888 return err; 1889 } 1890 #endif 1891 1892 static const struct dev_pm_ops sdhci_esdhc_pmops = { 1893 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) 1894 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 1895 sdhci_esdhc_runtime_resume, NULL) 1896 }; 1897 1898 static struct platform_driver sdhci_esdhc_imx_driver = { 1899 .driver = { 1900 .name = "sdhci-esdhc-imx", 1901 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1902 .of_match_table = imx_esdhc_dt_ids, 1903 .pm = &sdhci_esdhc_pmops, 1904 }, 1905 .probe = sdhci_esdhc_imx_probe, 1906 .remove = sdhci_esdhc_imx_remove, 1907 }; 1908 1909 module_platform_driver(sdhci_esdhc_imx_driver); 1910 1911 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1912 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 1913 MODULE_LICENSE("GPL v2"); 1914