195f25efeSWolfram Sang /* 295f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 395f25efeSWolfram Sang * 495f25efeSWolfram Sang * derived from the OF-version. 595f25efeSWolfram Sang * 695f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 7035ff831SWolfram Sang * Author: Wolfram Sang <kernel@pengutronix.de> 895f25efeSWolfram Sang * 995f25efeSWolfram Sang * This program is free software; you can redistribute it and/or modify 1095f25efeSWolfram Sang * it under the terms of the GNU General Public License as published by 1195f25efeSWolfram Sang * the Free Software Foundation; either version 2 of the License. 1295f25efeSWolfram Sang */ 1395f25efeSWolfram Sang 1495f25efeSWolfram Sang #include <linux/io.h> 1595f25efeSWolfram Sang #include <linux/delay.h> 1695f25efeSWolfram Sang #include <linux/err.h> 1795f25efeSWolfram Sang #include <linux/clk.h> 180c6d49ceSWolfram Sang #include <linux/gpio.h> 1966506f76SShawn Guo #include <linux/module.h> 20e149860dSRichard Zhu #include <linux/slab.h> 2195f25efeSWolfram Sang #include <linux/mmc/host.h> 2258ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2358ac8177SRichard Zhu #include <linux/mmc/sdio.h> 24fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 25abfafc2dSShawn Guo #include <linux/of.h> 26abfafc2dSShawn Guo #include <linux/of_device.h> 27abfafc2dSShawn Guo #include <linux/of_gpio.h> 28e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2982906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 3089d7e5c1SDong Aisheng #include <linux/pm_runtime.h> 3195f25efeSWolfram Sang #include "sdhci-pltfm.h" 3295f25efeSWolfram Sang #include "sdhci-esdhc.h" 3395f25efeSWolfram Sang 3460bf6396SShawn Guo #define ESDHC_CTRL_D3CD 0x08 35fd44954eSHaibo Chen #define ESDHC_BURST_LEN_EN_INCR (1 << 27) 3658ac8177SRichard Zhu /* VENDOR SPEC register */ 3760bf6396SShawn Guo #define ESDHC_VENDOR_SPEC 0xc0 3860bf6396SShawn Guo #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 390322191eSDong Aisheng #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 40fed2f6e2SDong Aisheng #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 4160bf6396SShawn Guo #define ESDHC_WTMK_LVL 0x44 4260bf6396SShawn Guo #define ESDHC_MIX_CTRL 0x48 43de5bdbffSDong Aisheng #define ESDHC_MIX_CTRL_DDREN (1 << 3) 442a15f981SShawn Guo #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 450322191eSDong Aisheng #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 460322191eSDong Aisheng #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 470322191eSDong Aisheng #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 4828b07674SHaibo Chen #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 492a15f981SShawn Guo /* Bits 3 and 6 are not SDHCI standard definitions */ 502a15f981SShawn Guo #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 51d131a71cSDong Aisheng /* Tuning bits */ 52d131a71cSDong Aisheng #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 5358ac8177SRichard Zhu 54602519b2SDong Aisheng /* dll control register */ 55602519b2SDong Aisheng #define ESDHC_DLL_CTRL 0x60 56602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 57602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 58602519b2SDong Aisheng 590322191eSDong Aisheng /* tune control register */ 600322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STATUS 0x68 610322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STEP 1 620322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MIN 0 630322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 640322191eSDong Aisheng 6528b07674SHaibo Chen /* strobe dll register */ 6628b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL 0x70 6728b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) 6828b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) 6928b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 7028b07674SHaibo Chen 7128b07674SHaibo Chen #define ESDHC_STROBE_DLL_STATUS 0x74 7228b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) 7328b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 7428b07674SHaibo Chen 756e9fd28eSDong Aisheng #define ESDHC_TUNING_CTRL 0xcc 766e9fd28eSDong Aisheng #define ESDHC_STD_TUNING_EN (1 << 24) 776e9fd28eSDong Aisheng /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 786e9fd28eSDong Aisheng #define ESDHC_TUNING_START_TAP 0x1 79d407e30bSHaibo Chen #define ESDHC_TUNING_STEP_SHIFT 16 806e9fd28eSDong Aisheng 81ad93220dSDong Aisheng /* pinctrl state */ 82ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 83ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 84ad93220dSDong Aisheng 8558ac8177SRichard Zhu /* 86af51079eSSascha Hauer * Our interpretation of the SDHCI_HOST_CONTROL register 87af51079eSSascha Hauer */ 88af51079eSSascha Hauer #define ESDHC_CTRL_4BITBUS (0x1 << 1) 89af51079eSSascha Hauer #define ESDHC_CTRL_8BITBUS (0x2 << 1) 90af51079eSSascha Hauer #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 91af51079eSSascha Hauer 92af51079eSSascha Hauer /* 9397e4ba6aSRichard Zhu * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: 9497e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 9597e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 9697e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 9797e4ba6aSRichard Zhu */ 9860bf6396SShawn Guo #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 9997e4ba6aSRichard Zhu 10097e4ba6aSRichard Zhu /* 10158ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 10258ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 10358ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 10458ac8177SRichard Zhu * be generated. 10558ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 10658ac8177SRichard Zhu * operations automatically as required at the end of the 10758ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 10858ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 10958ac8177SRichard Zhu * exeception. Bit1 of Vendor Spec registor is used to fix it. 11058ac8177SRichard Zhu */ 11131fbb301SShawn Guo #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 11231fbb301SShawn Guo /* 11331fbb301SShawn Guo * The flag enables the workaround for ESDHC errata ENGcm07207 which 11431fbb301SShawn Guo * affects i.MX25 and i.MX35. 11531fbb301SShawn Guo */ 11631fbb301SShawn Guo #define ESDHC_FLAG_ENGCM07207 BIT(2) 1179d61c009SShawn Guo /* 1189d61c009SShawn Guo * The flag tells that the ESDHC controller is an USDHC block that is 1199d61c009SShawn Guo * integrated on the i.MX6 series. 1209d61c009SShawn Guo */ 1219d61c009SShawn Guo #define ESDHC_FLAG_USDHC BIT(3) 1226e9fd28eSDong Aisheng /* The IP supports manual tuning process */ 1236e9fd28eSDong Aisheng #define ESDHC_FLAG_MAN_TUNING BIT(4) 1246e9fd28eSDong Aisheng /* The IP supports standard tuning process */ 1256e9fd28eSDong Aisheng #define ESDHC_FLAG_STD_TUNING BIT(5) 1266e9fd28eSDong Aisheng /* The IP has SDHCI_CAPABILITIES_1 register */ 1276e9fd28eSDong Aisheng #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 12818094430SDong Aisheng /* 12918094430SDong Aisheng * The IP has errata ERR004536 13018094430SDong Aisheng * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 13118094430SDong Aisheng * when reading data from the card 13218094430SDong Aisheng */ 13318094430SDong Aisheng #define ESDHC_FLAG_ERR004536 BIT(7) 1344245afffSDong Aisheng /* The IP supports HS200 mode */ 1354245afffSDong Aisheng #define ESDHC_FLAG_HS200 BIT(8) 13628b07674SHaibo Chen /* The IP supports HS400 mode */ 13728b07674SHaibo Chen #define ESDHC_FLAG_HS400 BIT(9) 13828b07674SHaibo Chen 13928b07674SHaibo Chen /* A higher clock ferquency than this rate requires strobell dll control */ 14028b07674SHaibo Chen #define ESDHC_STROBE_DLL_CLK_FREQ 100000000 141e149860dSRichard Zhu 142f47c4bbfSShawn Guo struct esdhc_soc_data { 143f47c4bbfSShawn Guo u32 flags; 144f47c4bbfSShawn Guo }; 145f47c4bbfSShawn Guo 146f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx25_data = { 147f47c4bbfSShawn Guo .flags = ESDHC_FLAG_ENGCM07207, 148f47c4bbfSShawn Guo }; 149f47c4bbfSShawn Guo 150f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx35_data = { 151f47c4bbfSShawn Guo .flags = ESDHC_FLAG_ENGCM07207, 152f47c4bbfSShawn Guo }; 153f47c4bbfSShawn Guo 154f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx51_data = { 155f47c4bbfSShawn Guo .flags = 0, 156f47c4bbfSShawn Guo }; 157f47c4bbfSShawn Guo 158f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx53_data = { 159f47c4bbfSShawn Guo .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 160f47c4bbfSShawn Guo }; 161f47c4bbfSShawn Guo 162f47c4bbfSShawn Guo static struct esdhc_soc_data usdhc_imx6q_data = { 1636e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, 1646e9fd28eSDong Aisheng }; 1656e9fd28eSDong Aisheng 1666e9fd28eSDong Aisheng static struct esdhc_soc_data usdhc_imx6sl_data = { 1676e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1684245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 1694245afffSDong Aisheng | ESDHC_FLAG_HS200, 17057ed3314SShawn Guo }; 17157ed3314SShawn Guo 172913d4951SDong Aisheng static struct esdhc_soc_data usdhc_imx6sx_data = { 173913d4951SDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1744245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, 175913d4951SDong Aisheng }; 176913d4951SDong Aisheng 17728b07674SHaibo Chen static struct esdhc_soc_data usdhc_imx7d_data = { 17828b07674SHaibo Chen .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 17928b07674SHaibo Chen | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 18028b07674SHaibo Chen | ESDHC_FLAG_HS400, 18128b07674SHaibo Chen }; 18228b07674SHaibo Chen 183e149860dSRichard Zhu struct pltfm_imx_data { 184e149860dSRichard Zhu u32 scratchpad; 185e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 186ad93220dSDong Aisheng struct pinctrl_state *pins_default; 187ad93220dSDong Aisheng struct pinctrl_state *pins_100mhz; 188ad93220dSDong Aisheng struct pinctrl_state *pins_200mhz; 189f47c4bbfSShawn Guo const struct esdhc_soc_data *socdata; 190842afc02SShawn Guo struct esdhc_platform_data boarddata; 19152dac615SSascha Hauer struct clk *clk_ipg; 19252dac615SSascha Hauer struct clk *clk_ahb; 19352dac615SSascha Hauer struct clk *clk_per; 194361b8482SLucas Stach enum { 195361b8482SLucas Stach NO_CMD_PENDING, /* no multiblock command pending*/ 196361b8482SLucas Stach MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 197361b8482SLucas Stach WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 198361b8482SLucas Stach } multiblock_status; 199de5bdbffSDong Aisheng u32 is_ddr; 200e149860dSRichard Zhu }; 201e149860dSRichard Zhu 202f8cbf461SKrzysztof Kozlowski static const struct platform_device_id imx_esdhc_devtype[] = { 20357ed3314SShawn Guo { 20457ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 205f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 20657ed3314SShawn Guo }, { 20757ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 208f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 20957ed3314SShawn Guo }, { 21057ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 211f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 21257ed3314SShawn Guo }, { 21357ed3314SShawn Guo /* sentinel */ 21457ed3314SShawn Guo } 21557ed3314SShawn Guo }; 21657ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 21757ed3314SShawn Guo 218abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 219f47c4bbfSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 220f47c4bbfSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 221f47c4bbfSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 222f47c4bbfSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 223913d4951SDong Aisheng { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 2246e9fd28eSDong Aisheng { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 225f47c4bbfSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 22628b07674SHaibo Chen { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, 227abfafc2dSShawn Guo { /* sentinel */ } 228abfafc2dSShawn Guo }; 229abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 230abfafc2dSShawn Guo 23157ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 23257ed3314SShawn Guo { 233f47c4bbfSShawn Guo return data->socdata == &esdhc_imx25_data; 23457ed3314SShawn Guo } 23557ed3314SShawn Guo 23657ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 23757ed3314SShawn Guo { 238f47c4bbfSShawn Guo return data->socdata == &esdhc_imx53_data; 23957ed3314SShawn Guo } 24057ed3314SShawn Guo 24195a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 24295a2482aSShawn Guo { 243f47c4bbfSShawn Guo return data->socdata == &usdhc_imx6q_data; 24495a2482aSShawn Guo } 24595a2482aSShawn Guo 2469d61c009SShawn Guo static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 2479d61c009SShawn Guo { 248f47c4bbfSShawn Guo return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 2499d61c009SShawn Guo } 2509d61c009SShawn Guo 25195f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 25295f25efeSWolfram Sang { 25395f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 25495f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 25595f25efeSWolfram Sang 25695f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 25795f25efeSWolfram Sang } 25895f25efeSWolfram Sang 2597e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 2607e29c306SWolfram Sang { 261361b8482SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 262361b8482SLucas Stach struct pltfm_imx_data *imx_data = pltfm_host->priv; 263913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 264913413c3SShawn Guo 2650322191eSDong Aisheng if (unlikely(reg == SDHCI_PRESENT_STATE)) { 2660322191eSDong Aisheng u32 fsl_prss = val; 2670322191eSDong Aisheng /* save the least 20 bits */ 2680322191eSDong Aisheng val = fsl_prss & 0x000FFFFF; 2690322191eSDong Aisheng /* move dat[0-3] bits */ 2700322191eSDong Aisheng val |= (fsl_prss & 0x0F000000) >> 4; 2710322191eSDong Aisheng /* move cmd line bit */ 2720322191eSDong Aisheng val |= (fsl_prss & 0x00800000) << 1; 2730322191eSDong Aisheng } 2740322191eSDong Aisheng 27597e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 2766b4fb671SDong Aisheng /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 2776b4fb671SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 2786b4fb671SDong Aisheng val &= 0xffff0000; 2796b4fb671SDong Aisheng 28097e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 28197e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 28297e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 28397e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 28497e4ba6aSRichard Zhu * uirk on MX25/35 platforms. 28597e4ba6aSRichard Zhu */ 28697e4ba6aSRichard Zhu 28797e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 28897e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 28997e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 29097e4ba6aSRichard Zhu } 29197e4ba6aSRichard Zhu } 29297e4ba6aSRichard Zhu 2936e9fd28eSDong Aisheng if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 2946e9fd28eSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 2956e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 2966e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 2976e9fd28eSDong Aisheng else 2986e9fd28eSDong Aisheng /* imx6q/dl does not have cap_1 register, fake one */ 2990322191eSDong Aisheng val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 300888824bbSDong Aisheng | SDHCI_SUPPORT_SDR50 301888824bbSDong Aisheng | SDHCI_USE_SDR50_TUNING; 30228b07674SHaibo Chen 30328b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 30428b07674SHaibo Chen val |= SDHCI_SUPPORT_HS400; 3056e9fd28eSDong Aisheng } 3066e9fd28eSDong Aisheng } 3070322191eSDong Aisheng 3089d61c009SShawn Guo if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 3090322191eSDong Aisheng val = 0; 3100322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 3110322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 3120322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 3130322191eSDong Aisheng } 3140322191eSDong Aisheng 31597e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 31660bf6396SShawn Guo if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 31760bf6396SShawn Guo val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 31897e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 31997e4ba6aSRichard Zhu } 320361b8482SLucas Stach 321361b8482SLucas Stach /* 322361b8482SLucas Stach * mask off the interrupt we get in response to the manually 323361b8482SLucas Stach * sent CMD12 324361b8482SLucas Stach */ 325361b8482SLucas Stach if ((imx_data->multiblock_status == WAIT_FOR_INT) && 326361b8482SLucas Stach ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 327361b8482SLucas Stach val &= ~SDHCI_INT_RESPONSE; 328361b8482SLucas Stach writel(SDHCI_INT_RESPONSE, host->ioaddr + 329361b8482SLucas Stach SDHCI_INT_STATUS); 330361b8482SLucas Stach imx_data->multiblock_status = NO_CMD_PENDING; 331361b8482SLucas Stach } 33297e4ba6aSRichard Zhu } 33397e4ba6aSRichard Zhu 3347e29c306SWolfram Sang return val; 3357e29c306SWolfram Sang } 3367e29c306SWolfram Sang 3377e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 3387e29c306SWolfram Sang { 339e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 340e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 3410d58864bSTony Lin u32 data; 342e149860dSRichard Zhu 3430d58864bSTony Lin if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 344b7321042SDong Aisheng if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 3450d58864bSTony Lin /* 3460d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 3470d58864bSTony Lin * card interrupt. This is a eSDHC controller problem 3480d58864bSTony Lin * so we need to apply the following workaround: clear 3490d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 3500d58864bSTony Lin * interrupt. In case a card interrupt was lost, 3510d58864bSTony Lin * re-sample it by the following steps. 3520d58864bSTony Lin */ 3530d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 35460bf6396SShawn Guo data &= ~ESDHC_CTRL_D3CD; 3550d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 35660bf6396SShawn Guo data |= ESDHC_CTRL_D3CD; 3570d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 3580d58864bSTony Lin } 359915be485SDong Aisheng 360915be485SDong Aisheng if (val & SDHCI_INT_ADMA_ERROR) { 361915be485SDong Aisheng val &= ~SDHCI_INT_ADMA_ERROR; 362915be485SDong Aisheng val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 363915be485SDong Aisheng } 3640d58864bSTony Lin } 3650d58864bSTony Lin 366f47c4bbfSShawn Guo if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 36758ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 36858ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 36958ac8177SRichard Zhu u32 v; 37060bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 37160bf6396SShawn Guo v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 37260bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 373361b8482SLucas Stach 374361b8482SLucas Stach if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 375361b8482SLucas Stach { 376361b8482SLucas Stach /* send a manual CMD12 with RESPTYP=none */ 377361b8482SLucas Stach data = MMC_STOP_TRANSMISSION << 24 | 378361b8482SLucas Stach SDHCI_CMD_ABORTCMD << 16; 379361b8482SLucas Stach writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 380361b8482SLucas Stach imx_data->multiblock_status = WAIT_FOR_INT; 381361b8482SLucas Stach } 38258ac8177SRichard Zhu } 38358ac8177SRichard Zhu 3847e29c306SWolfram Sang writel(val, host->ioaddr + reg); 3857e29c306SWolfram Sang } 3867e29c306SWolfram Sang 38795f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 38895f25efeSWolfram Sang { 389ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 390ef4d0888SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 3910322191eSDong Aisheng u16 ret = 0; 3920322191eSDong Aisheng u32 val; 393ef4d0888SShawn Guo 39495a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 395ef4d0888SShawn Guo reg ^= 2; 3969d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 39795a2482aSShawn Guo /* 398ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 399ef4d0888SShawn Guo * Correct it here. 40095a2482aSShawn Guo */ 401ef4d0888SShawn Guo return SDHCI_SPEC_300; 402ef4d0888SShawn Guo } 40395a2482aSShawn Guo } 40495f25efeSWolfram Sang 4050322191eSDong Aisheng if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 4060322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4070322191eSDong Aisheng if (val & ESDHC_VENDOR_SPEC_VSELECT) 4080322191eSDong Aisheng ret |= SDHCI_CTRL_VDD_180; 4090322191eSDong Aisheng 4109d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 4116e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 4120322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_MIX_CTRL); 4136e9fd28eSDong Aisheng else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 4146e9fd28eSDong Aisheng /* the std tuning bits is in ACMD12_ERR for imx6sl */ 4156e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_ACMD12_ERR); 4166e9fd28eSDong Aisheng } 4176e9fd28eSDong Aisheng 4180322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_EXE_TUNE) 4190322191eSDong Aisheng ret |= SDHCI_CTRL_EXEC_TUNING; 4200322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 4210322191eSDong Aisheng ret |= SDHCI_CTRL_TUNED_CLK; 4220322191eSDong Aisheng 4230322191eSDong Aisheng ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 4240322191eSDong Aisheng 4250322191eSDong Aisheng return ret; 4260322191eSDong Aisheng } 4270322191eSDong Aisheng 4287dd109efSDong Aisheng if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 4297dd109efSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 4307dd109efSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4317dd109efSDong Aisheng ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 4327dd109efSDong Aisheng /* Swap AC23 bit */ 4337dd109efSDong Aisheng if (m & ESDHC_MIX_CTRL_AC23EN) { 4347dd109efSDong Aisheng ret &= ~ESDHC_MIX_CTRL_AC23EN; 4357dd109efSDong Aisheng ret |= SDHCI_TRNS_AUTO_CMD23; 4367dd109efSDong Aisheng } 4377dd109efSDong Aisheng } else { 4387dd109efSDong Aisheng ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 4397dd109efSDong Aisheng } 4407dd109efSDong Aisheng 4417dd109efSDong Aisheng return ret; 4427dd109efSDong Aisheng } 4437dd109efSDong Aisheng 44495f25efeSWolfram Sang return readw(host->ioaddr + reg); 44595f25efeSWolfram Sang } 44695f25efeSWolfram Sang 44795f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 44895f25efeSWolfram Sang { 44995f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 450e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 4510322191eSDong Aisheng u32 new_val = 0; 45295f25efeSWolfram Sang 45395f25efeSWolfram Sang switch (reg) { 4540322191eSDong Aisheng case SDHCI_CLOCK_CONTROL: 4550322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4560322191eSDong Aisheng if (val & SDHCI_CLOCK_CARD_EN) 4570322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4580322191eSDong Aisheng else 4590322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4600322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4610322191eSDong Aisheng return; 4620322191eSDong Aisheng case SDHCI_HOST_CONTROL2: 4630322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4640322191eSDong Aisheng if (val & SDHCI_CTRL_VDD_180) 4650322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_VSELECT; 4660322191eSDong Aisheng else 4670322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 4680322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4696e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 4700322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 4710322191eSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) 4720322191eSDong Aisheng new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 4730322191eSDong Aisheng else 4740322191eSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 4750322191eSDong Aisheng writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 4766e9fd28eSDong Aisheng } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 4776e9fd28eSDong Aisheng u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); 4786e9fd28eSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 479d407e30bSHaibo Chen u32 tuning_ctrl; 4808b2bb0adSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 4818b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 4826e9fd28eSDong Aisheng } else { 4838b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 4846e9fd28eSDong Aisheng m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 4856e9fd28eSDong Aisheng } 4866e9fd28eSDong Aisheng 4878b2bb0adSDong Aisheng if (val & SDHCI_CTRL_EXEC_TUNING) { 4888b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_EXE_TUNE; 4898b2bb0adSDong Aisheng m |= ESDHC_MIX_CTRL_FBCLK_SEL; 490d407e30bSHaibo Chen tuning_ctrl = readl(host->ioaddr + ESDHC_TUNING_CTRL); 491d407e30bSHaibo Chen tuning_ctrl |= ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP; 492d407e30bSHaibo Chen if (imx_data->boarddata.tuning_step) 493d407e30bSHaibo Chen tuning_ctrl |= imx_data->boarddata.tuning_step << ESDHC_TUNING_STEP_SHIFT; 494d407e30bSHaibo Chen writel(tuning_ctrl, host->ioaddr + ESDHC_TUNING_CTRL); 4958b2bb0adSDong Aisheng } else { 4968b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 4978b2bb0adSDong Aisheng } 4986e9fd28eSDong Aisheng 4996e9fd28eSDong Aisheng writel(v, host->ioaddr + SDHCI_ACMD12_ERR); 5006e9fd28eSDong Aisheng writel(m, host->ioaddr + ESDHC_MIX_CTRL); 5016e9fd28eSDong Aisheng } 5020322191eSDong Aisheng return; 50395f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 504f47c4bbfSShawn Guo if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 50558ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 50658ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 50758ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 50858ac8177SRichard Zhu u32 v; 50960bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 51060bf6396SShawn Guo v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 51160bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 51258ac8177SRichard Zhu } 51369f54698SShawn Guo 5149d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 51569f54698SShawn Guo u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 5162a15f981SShawn Guo /* Swap AC23 bit */ 5172a15f981SShawn Guo if (val & SDHCI_TRNS_AUTO_CMD23) { 5182a15f981SShawn Guo val &= ~SDHCI_TRNS_AUTO_CMD23; 5192a15f981SShawn Guo val |= ESDHC_MIX_CTRL_AC23EN; 5202a15f981SShawn Guo } 5212a15f981SShawn Guo m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 52269f54698SShawn Guo writel(m, host->ioaddr + ESDHC_MIX_CTRL); 52369f54698SShawn Guo } else { 52469f54698SShawn Guo /* 52569f54698SShawn Guo * Postpone this write, we must do it together with a 52669f54698SShawn Guo * command write that is down below. 52769f54698SShawn Guo */ 528e149860dSRichard Zhu imx_data->scratchpad = val; 52969f54698SShawn Guo } 53095f25efeSWolfram Sang return; 53195f25efeSWolfram Sang case SDHCI_COMMAND: 532361b8482SLucas Stach if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 53358ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 53495a2482aSShawn Guo 535361b8482SLucas Stach if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 536f47c4bbfSShawn Guo (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 537361b8482SLucas Stach imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 538361b8482SLucas Stach 5399d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 54095a2482aSShawn Guo writel(val << 16, 54195a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 54269f54698SShawn Guo else 543e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 54495f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 54595f25efeSWolfram Sang return; 54695f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 54795f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 54895f25efeSWolfram Sang break; 54995f25efeSWolfram Sang } 55095f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 55195f25efeSWolfram Sang } 55295f25efeSWolfram Sang 55395f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 55495f25efeSWolfram Sang { 5559a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 5569a0985b7SWilson Callan struct pltfm_imx_data *imx_data = pltfm_host->priv; 55795f25efeSWolfram Sang u32 new_val; 558af51079eSSascha Hauer u32 mask; 55995f25efeSWolfram Sang 56095f25efeSWolfram Sang switch (reg) { 56195f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 56295f25efeSWolfram Sang /* 56395f25efeSWolfram Sang * FSL put some DMA bits here 56495f25efeSWolfram Sang * If your board has a regulator, code should be here 56595f25efeSWolfram Sang */ 56695f25efeSWolfram Sang return; 56795f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 5686b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 569af51079eSSascha Hauer new_val = val & SDHCI_CTRL_LED; 5707122bbb0SMasanari Iida /* ensure the endianness */ 57195f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 5729a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 5739a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 57495f25efeSWolfram Sang /* DMA mode bits are shifted */ 57595f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 5769a0985b7SWilson Callan } 57795f25efeSWolfram Sang 578af51079eSSascha Hauer /* 579af51079eSSascha Hauer * Do not touch buswidth bits here. This is done in 580af51079eSSascha Hauer * esdhc_pltfm_bus_width. 581f6825748SMartin Fuzzey * Do not touch the D3CD bit either which is used for the 582f6825748SMartin Fuzzey * SDIO interrupt errata workaround. 583af51079eSSascha Hauer */ 584f6825748SMartin Fuzzey mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 585af51079eSSascha Hauer 586af51079eSSascha Hauer esdhc_clrset_le(host, mask, new_val, reg); 58795f25efeSWolfram Sang return; 58895f25efeSWolfram Sang } 58995f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 590913413c3SShawn Guo 591913413c3SShawn Guo /* 592913413c3SShawn Guo * The esdhc has a design violation to SDHC spec which tells 593913413c3SShawn Guo * that software reset should not affect card detection circuit. 594913413c3SShawn Guo * But esdhc clears its SYSCTL register bits [0..2] during the 595913413c3SShawn Guo * software reset. This will stop those clocks that card detection 596913413c3SShawn Guo * circuit relies on. To work around it, we turn the clocks on back 597913413c3SShawn Guo * to keep card detection circuit functional. 598913413c3SShawn Guo */ 59958c8c4fbSShawn Guo if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { 600913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 60158c8c4fbSShawn Guo /* 60258c8c4fbSShawn Guo * The reset on usdhc fails to clear MIX_CTRL register. 60358c8c4fbSShawn Guo * Do it manually here. 60458c8c4fbSShawn Guo */ 605de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 606d131a71cSDong Aisheng /* the tuning bits should be kept during reset */ 607d131a71cSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 608d131a71cSDong Aisheng writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 609d131a71cSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 610de5bdbffSDong Aisheng imx_data->is_ddr = 0; 611de5bdbffSDong Aisheng } 61258c8c4fbSShawn Guo } 61395f25efeSWolfram Sang } 61495f25efeSWolfram Sang 6150ddf03c9SLucas Stach static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 6160ddf03c9SLucas Stach { 6170ddf03c9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 6180ddf03c9SLucas Stach 619a974862fSDong Aisheng return pltfm_host->clock; 6200ddf03c9SLucas Stach } 6210ddf03c9SLucas Stach 62295f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 62395f25efeSWolfram Sang { 62495f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 62595f25efeSWolfram Sang 626a974862fSDong Aisheng return pltfm_host->clock / 256 / 16; 62795f25efeSWolfram Sang } 62895f25efeSWolfram Sang 6298ba9580aSLucas Stach static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 6308ba9580aSLucas Stach unsigned int clock) 6318ba9580aSLucas Stach { 6328ba9580aSLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 633fed2f6e2SDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 634a974862fSDong Aisheng unsigned int host_clock = pltfm_host->clock; 635d31fc00aSDong Aisheng int pre_div = 2; 636d31fc00aSDong Aisheng int div = 1; 637fed2f6e2SDong Aisheng u32 temp, val; 6388ba9580aSLucas Stach 639fed2f6e2SDong Aisheng if (clock == 0) { 6401650d0c7SRussell King host->mmc->actual_clock = 0; 6411650d0c7SRussell King 6429d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 643fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 644fed2f6e2SDong Aisheng writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 645fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 646fed2f6e2SDong Aisheng } 647373073efSRussell King return; 648fed2f6e2SDong Aisheng } 649d31fc00aSDong Aisheng 650de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) 6515f7886c5SDong Aisheng pre_div = 1; 6525f7886c5SDong Aisheng 653d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 654d31fc00aSDong Aisheng temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 655d31fc00aSDong Aisheng | ESDHC_CLOCK_MASK); 656d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 657d31fc00aSDong Aisheng 658d31fc00aSDong Aisheng while (host_clock / pre_div / 16 > clock && pre_div < 256) 659d31fc00aSDong Aisheng pre_div *= 2; 660d31fc00aSDong Aisheng 661d31fc00aSDong Aisheng while (host_clock / pre_div / div > clock && div < 16) 662d31fc00aSDong Aisheng div++; 663d31fc00aSDong Aisheng 664e76b8559SDong Aisheng host->mmc->actual_clock = host_clock / pre_div / div; 665d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 666e76b8559SDong Aisheng clock, host->mmc->actual_clock); 667d31fc00aSDong Aisheng 668de5bdbffSDong Aisheng if (imx_data->is_ddr) 669de5bdbffSDong Aisheng pre_div >>= 2; 670de5bdbffSDong Aisheng else 671d31fc00aSDong Aisheng pre_div >>= 1; 672d31fc00aSDong Aisheng div--; 673d31fc00aSDong Aisheng 674d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 675d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 676d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 677d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 678d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 679fed2f6e2SDong Aisheng 6809d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 681fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 682fed2f6e2SDong Aisheng writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 683fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 684fed2f6e2SDong Aisheng } 685fed2f6e2SDong Aisheng 686d31fc00aSDong Aisheng mdelay(1); 6878ba9580aSLucas Stach } 6888ba9580aSLucas Stach 689913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 690913413c3SShawn Guo { 691842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 692842afc02SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 693842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 694913413c3SShawn Guo 695913413c3SShawn Guo switch (boarddata->wp_type) { 696913413c3SShawn Guo case ESDHC_WP_GPIO: 697fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 698913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 699913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 700913413c3SShawn Guo SDHCI_WRITE_PROTECT); 701913413c3SShawn Guo case ESDHC_WP_NONE: 702913413c3SShawn Guo break; 703913413c3SShawn Guo } 704913413c3SShawn Guo 705913413c3SShawn Guo return -ENOSYS; 706913413c3SShawn Guo } 707913413c3SShawn Guo 7082317f56cSRussell King static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 709af51079eSSascha Hauer { 710af51079eSSascha Hauer u32 ctrl; 711af51079eSSascha Hauer 712af51079eSSascha Hauer switch (width) { 713af51079eSSascha Hauer case MMC_BUS_WIDTH_8: 714af51079eSSascha Hauer ctrl = ESDHC_CTRL_8BITBUS; 715af51079eSSascha Hauer break; 716af51079eSSascha Hauer case MMC_BUS_WIDTH_4: 717af51079eSSascha Hauer ctrl = ESDHC_CTRL_4BITBUS; 718af51079eSSascha Hauer break; 719af51079eSSascha Hauer default: 720af51079eSSascha Hauer ctrl = 0; 721af51079eSSascha Hauer break; 722af51079eSSascha Hauer } 723af51079eSSascha Hauer 724af51079eSSascha Hauer esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 725af51079eSSascha Hauer SDHCI_HOST_CONTROL); 726af51079eSSascha Hauer } 727af51079eSSascha Hauer 7280322191eSDong Aisheng static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 7290322191eSDong Aisheng { 7300322191eSDong Aisheng u32 reg; 7310322191eSDong Aisheng 7320322191eSDong Aisheng /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 7330322191eSDong Aisheng mdelay(1); 7340322191eSDong Aisheng 7350322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 7360322191eSDong Aisheng reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 7370322191eSDong Aisheng ESDHC_MIX_CTRL_FBCLK_SEL; 7380322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 7390322191eSDong Aisheng writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 7400322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), 7410322191eSDong Aisheng "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 7420322191eSDong Aisheng val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 7430322191eSDong Aisheng } 7440322191eSDong Aisheng 7450322191eSDong Aisheng static void esdhc_post_tuning(struct sdhci_host *host) 7460322191eSDong Aisheng { 7470322191eSDong Aisheng u32 reg; 7480322191eSDong Aisheng 7490322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 7500322191eSDong Aisheng reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 7510322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 7520322191eSDong Aisheng } 7530322191eSDong Aisheng 7540322191eSDong Aisheng static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 7550322191eSDong Aisheng { 7560322191eSDong Aisheng int min, max, avg, ret; 7570322191eSDong Aisheng 7580322191eSDong Aisheng /* find the mininum delay first which can pass tuning */ 7590322191eSDong Aisheng min = ESDHC_TUNE_CTRL_MIN; 7600322191eSDong Aisheng while (min < ESDHC_TUNE_CTRL_MAX) { 7610322191eSDong Aisheng esdhc_prepare_tuning(host, min); 762d1785326SUlf Hansson if (!mmc_send_tuning(host->mmc)) 7630322191eSDong Aisheng break; 7640322191eSDong Aisheng min += ESDHC_TUNE_CTRL_STEP; 7650322191eSDong Aisheng } 7660322191eSDong Aisheng 7670322191eSDong Aisheng /* find the maxinum delay which can not pass tuning */ 7680322191eSDong Aisheng max = min + ESDHC_TUNE_CTRL_STEP; 7690322191eSDong Aisheng while (max < ESDHC_TUNE_CTRL_MAX) { 7700322191eSDong Aisheng esdhc_prepare_tuning(host, max); 771d1785326SUlf Hansson if (mmc_send_tuning(host->mmc)) { 7720322191eSDong Aisheng max -= ESDHC_TUNE_CTRL_STEP; 7730322191eSDong Aisheng break; 7740322191eSDong Aisheng } 7750322191eSDong Aisheng max += ESDHC_TUNE_CTRL_STEP; 7760322191eSDong Aisheng } 7770322191eSDong Aisheng 7780322191eSDong Aisheng /* use average delay to get the best timing */ 7790322191eSDong Aisheng avg = (min + max) / 2; 7800322191eSDong Aisheng esdhc_prepare_tuning(host, avg); 781d1785326SUlf Hansson ret = mmc_send_tuning(host->mmc); 7820322191eSDong Aisheng esdhc_post_tuning(host); 7830322191eSDong Aisheng 7840322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", 7850322191eSDong Aisheng ret ? "failed" : "passed", avg, ret); 7860322191eSDong Aisheng 7870322191eSDong Aisheng return ret; 7880322191eSDong Aisheng } 7890322191eSDong Aisheng 790ad93220dSDong Aisheng static int esdhc_change_pinstate(struct sdhci_host *host, 791ad93220dSDong Aisheng unsigned int uhs) 792ad93220dSDong Aisheng { 793ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 794ad93220dSDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 795ad93220dSDong Aisheng struct pinctrl_state *pinctrl; 796ad93220dSDong Aisheng 797ad93220dSDong Aisheng dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 798ad93220dSDong Aisheng 799ad93220dSDong Aisheng if (IS_ERR(imx_data->pinctrl) || 800ad93220dSDong Aisheng IS_ERR(imx_data->pins_default) || 801ad93220dSDong Aisheng IS_ERR(imx_data->pins_100mhz) || 802ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) 803ad93220dSDong Aisheng return -EINVAL; 804ad93220dSDong Aisheng 805ad93220dSDong Aisheng switch (uhs) { 806ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 807ad93220dSDong Aisheng pinctrl = imx_data->pins_100mhz; 808ad93220dSDong Aisheng break; 809ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 810429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 81128b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 812ad93220dSDong Aisheng pinctrl = imx_data->pins_200mhz; 813ad93220dSDong Aisheng break; 814ad93220dSDong Aisheng default: 815ad93220dSDong Aisheng /* back to default state for other legacy timing */ 816ad93220dSDong Aisheng pinctrl = imx_data->pins_default; 817ad93220dSDong Aisheng } 818ad93220dSDong Aisheng 819ad93220dSDong Aisheng return pinctrl_select_state(imx_data->pinctrl, pinctrl); 820ad93220dSDong Aisheng } 821ad93220dSDong Aisheng 82228b07674SHaibo Chen /* 82328b07674SHaibo Chen * For HS400 eMMC, there is a data_strobe line, this signal is generated 82428b07674SHaibo Chen * by the device and used for data output and CRC status response output 82528b07674SHaibo Chen * in HS400 mode. The frequency of this signal follows the frequency of 82628b07674SHaibo Chen * CLK generated by host. Host receive the data which is aligned to the 82728b07674SHaibo Chen * edge of data_strobe line. Due to the time delay between CLK line and 82828b07674SHaibo Chen * data_strobe line, if the delay time is larger than one clock cycle, 82928b07674SHaibo Chen * then CLK and data_strobe line will misaligned, read error shows up. 83028b07674SHaibo Chen * So when the CLK is higher than 100MHz, each clock cycle is short enough, 83128b07674SHaibo Chen * host should config the delay target. 83228b07674SHaibo Chen */ 83328b07674SHaibo Chen static void esdhc_set_strobe_dll(struct sdhci_host *host) 83428b07674SHaibo Chen { 83528b07674SHaibo Chen u32 v; 83628b07674SHaibo Chen 83728b07674SHaibo Chen if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) { 83828b07674SHaibo Chen /* force a reset on strobe dll */ 83928b07674SHaibo Chen writel(ESDHC_STROBE_DLL_CTRL_RESET, 84028b07674SHaibo Chen host->ioaddr + ESDHC_STROBE_DLL_CTRL); 84128b07674SHaibo Chen /* 84228b07674SHaibo Chen * enable strobe dll ctrl and adjust the delay target 84328b07674SHaibo Chen * for the uSDHC loopback read clock 84428b07674SHaibo Chen */ 84528b07674SHaibo Chen v = ESDHC_STROBE_DLL_CTRL_ENABLE | 84628b07674SHaibo Chen (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 84728b07674SHaibo Chen writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 84828b07674SHaibo Chen /* wait 1us to make sure strobe dll status register stable */ 84928b07674SHaibo Chen udelay(1); 85028b07674SHaibo Chen v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS); 85128b07674SHaibo Chen if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK)) 85228b07674SHaibo Chen dev_warn(mmc_dev(host->mmc), 85328b07674SHaibo Chen "warning! HS400 strobe DLL status REF not lock!\n"); 85428b07674SHaibo Chen if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK)) 85528b07674SHaibo Chen dev_warn(mmc_dev(host->mmc), 85628b07674SHaibo Chen "warning! HS400 strobe DLL status SLV not lock!\n"); 85728b07674SHaibo Chen } 85828b07674SHaibo Chen } 85928b07674SHaibo Chen 860850a29b8SRussell King static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 861ad93220dSDong Aisheng { 86228b07674SHaibo Chen u32 m; 863ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 864ad93220dSDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 865602519b2SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 866ad93220dSDong Aisheng 86728b07674SHaibo Chen /* disable ddr mode and disable HS400 mode */ 86828b07674SHaibo Chen m = readl(host->ioaddr + ESDHC_MIX_CTRL); 86928b07674SHaibo Chen m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); 87028b07674SHaibo Chen imx_data->is_ddr = 0; 87128b07674SHaibo Chen 872850a29b8SRussell King switch (timing) { 873ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR12: 874ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR25: 875ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 876ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 877429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 87828b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 879ad93220dSDong Aisheng break; 880ad93220dSDong Aisheng case MMC_TIMING_UHS_DDR50: 88169f5bf38SAisheng Dong case MMC_TIMING_MMC_DDR52: 88228b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN; 88328b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 884de5bdbffSDong Aisheng imx_data->is_ddr = 1; 885602519b2SDong Aisheng if (boarddata->delay_line) { 886602519b2SDong Aisheng u32 v; 887602519b2SDong Aisheng v = boarddata->delay_line << 888602519b2SDong Aisheng ESDHC_DLL_OVERRIDE_VAL_SHIFT | 889602519b2SDong Aisheng (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 890602519b2SDong Aisheng if (is_imx53_esdhc(imx_data)) 891602519b2SDong Aisheng v <<= 1; 892602519b2SDong Aisheng writel(v, host->ioaddr + ESDHC_DLL_CTRL); 893602519b2SDong Aisheng } 894ad93220dSDong Aisheng break; 89528b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 89628b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 89728b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 89828b07674SHaibo Chen imx_data->is_ddr = 1; 89928b07674SHaibo Chen esdhc_set_strobe_dll(host); 90028b07674SHaibo Chen break; 901ad93220dSDong Aisheng } 902ad93220dSDong Aisheng 903850a29b8SRussell King esdhc_change_pinstate(host, timing); 904ad93220dSDong Aisheng } 905ad93220dSDong Aisheng 9060718e59aSRussell King static void esdhc_reset(struct sdhci_host *host, u8 mask) 9070718e59aSRussell King { 9080718e59aSRussell King sdhci_reset(host, mask); 9090718e59aSRussell King 9100718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 9110718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 9120718e59aSRussell King } 9130718e59aSRussell King 91410fd0ad9SAisheng Dong static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 91510fd0ad9SAisheng Dong { 91610fd0ad9SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 91710fd0ad9SAisheng Dong struct pltfm_imx_data *imx_data = pltfm_host->priv; 91810fd0ad9SAisheng Dong 91910fd0ad9SAisheng Dong return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27; 92010fd0ad9SAisheng Dong } 92110fd0ad9SAisheng Dong 922e33eb8e2SAisheng Dong static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 923e33eb8e2SAisheng Dong { 924e33eb8e2SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 925e33eb8e2SAisheng Dong struct pltfm_imx_data *imx_data = pltfm_host->priv; 926e33eb8e2SAisheng Dong 927e33eb8e2SAisheng Dong /* use maximum timeout counter */ 928e33eb8e2SAisheng Dong sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 929e33eb8e2SAisheng Dong SDHCI_TIMEOUT_CONTROL); 930e33eb8e2SAisheng Dong } 931e33eb8e2SAisheng Dong 9326e9fd28eSDong Aisheng static struct sdhci_ops sdhci_esdhc_ops = { 933e149860dSRichard Zhu .read_l = esdhc_readl_le, 9340c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 935e149860dSRichard Zhu .write_l = esdhc_writel_le, 9360c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 9370c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 9388ba9580aSLucas Stach .set_clock = esdhc_pltfm_set_clock, 9390ddf03c9SLucas Stach .get_max_clock = esdhc_pltfm_get_max_clock, 9400c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 94110fd0ad9SAisheng Dong .get_max_timeout_count = esdhc_get_max_timeout_count, 942913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 943e33eb8e2SAisheng Dong .set_timeout = esdhc_set_timeout, 9442317f56cSRussell King .set_bus_width = esdhc_pltfm_set_bus_width, 945ad93220dSDong Aisheng .set_uhs_signaling = esdhc_set_uhs_signaling, 9460718e59aSRussell King .reset = esdhc_reset, 9470c6d49ceSWolfram Sang }; 9480c6d49ceSWolfram Sang 9491db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 95097e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 95197e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 95297e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 95385d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 95485d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 95585d6509dSShawn Guo }; 95685d6509dSShawn Guo 957abfafc2dSShawn Guo #ifdef CONFIG_OF 958c3be1efdSBill Pemberton static int 959abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 96007bf2b54SSascha Hauer struct sdhci_host *host, 96191fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 962abfafc2dSShawn Guo { 963abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 96491fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 9654800e87aSDong Aisheng int ret; 966abfafc2dSShawn Guo 967abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 968abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 969abfafc2dSShawn Guo 970abfafc2dSShawn Guo boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 971abfafc2dSShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 972abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 973abfafc2dSShawn Guo 974d407e30bSHaibo Chen of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 975d407e30bSHaibo Chen 976ad93220dSDong Aisheng if (of_find_property(np, "no-1-8-v", NULL)) 977ad93220dSDong Aisheng boarddata->support_vsel = false; 978ad93220dSDong Aisheng else 979ad93220dSDong Aisheng boarddata->support_vsel = true; 980ad93220dSDong Aisheng 981602519b2SDong Aisheng if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 982602519b2SDong Aisheng boarddata->delay_line = 0; 983602519b2SDong Aisheng 98407bf2b54SSascha Hauer mmc_of_parse_voltage(np, &host->ocr_mask); 98507bf2b54SSascha Hauer 98691fa4252SDong Aisheng /* sdr50 and sdr104 needs work on 1.8v signal voltage */ 98791fa4252SDong Aisheng if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) && 98891fa4252SDong Aisheng !IS_ERR(imx_data->pins_default)) { 98991fa4252SDong Aisheng imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 99091fa4252SDong Aisheng ESDHC_PINCTRL_STATE_100MHZ); 99191fa4252SDong Aisheng imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 99291fa4252SDong Aisheng ESDHC_PINCTRL_STATE_200MHZ); 99391fa4252SDong Aisheng if (IS_ERR(imx_data->pins_100mhz) || 99491fa4252SDong Aisheng IS_ERR(imx_data->pins_200mhz)) { 99591fa4252SDong Aisheng dev_warn(mmc_dev(host->mmc), 99691fa4252SDong Aisheng "could not get ultra high speed state, work on normal mode\n"); 99791fa4252SDong Aisheng /* 99891fa4252SDong Aisheng * fall back to not support uhs by specify no 1.8v quirk 99991fa4252SDong Aisheng */ 100091fa4252SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 100191fa4252SDong Aisheng } 100291fa4252SDong Aisheng } else { 100391fa4252SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 100491fa4252SDong Aisheng } 100591fa4252SDong Aisheng 100615064119SFabio Estevam /* call to generic mmc_of_parse to support additional capabilities */ 10074800e87aSDong Aisheng ret = mmc_of_parse(host->mmc); 10084800e87aSDong Aisheng if (ret) 10094800e87aSDong Aisheng return ret; 10104800e87aSDong Aisheng 10114800e87aSDong Aisheng if (!IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc))) 10124800e87aSDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 10134800e87aSDong Aisheng 10144800e87aSDong Aisheng return 0; 1015abfafc2dSShawn Guo } 1016abfafc2dSShawn Guo #else 1017abfafc2dSShawn Guo static inline int 1018abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 101907bf2b54SSascha Hauer struct sdhci_host *host, 102091fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1021abfafc2dSShawn Guo { 1022abfafc2dSShawn Guo return -ENODEV; 1023abfafc2dSShawn Guo } 1024abfafc2dSShawn Guo #endif 1025abfafc2dSShawn Guo 102691fa4252SDong Aisheng static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev, 102791fa4252SDong Aisheng struct sdhci_host *host, 102891fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 102991fa4252SDong Aisheng { 103091fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 103191fa4252SDong Aisheng int err; 103291fa4252SDong Aisheng 103391fa4252SDong Aisheng if (!host->mmc->parent->platform_data) { 103491fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), "no board data!\n"); 103591fa4252SDong Aisheng return -EINVAL; 103691fa4252SDong Aisheng } 103791fa4252SDong Aisheng 103891fa4252SDong Aisheng imx_data->boarddata = *((struct esdhc_platform_data *) 103991fa4252SDong Aisheng host->mmc->parent->platform_data); 104091fa4252SDong Aisheng /* write_protect */ 104191fa4252SDong Aisheng if (boarddata->wp_type == ESDHC_WP_GPIO) { 104291fa4252SDong Aisheng err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); 104391fa4252SDong Aisheng if (err) { 104491fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 104591fa4252SDong Aisheng "failed to request write-protect gpio!\n"); 104691fa4252SDong Aisheng return err; 104791fa4252SDong Aisheng } 104891fa4252SDong Aisheng host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 104991fa4252SDong Aisheng } 105091fa4252SDong Aisheng 105191fa4252SDong Aisheng /* card_detect */ 105291fa4252SDong Aisheng switch (boarddata->cd_type) { 105391fa4252SDong Aisheng case ESDHC_CD_GPIO: 105491fa4252SDong Aisheng err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); 105591fa4252SDong Aisheng if (err) { 105691fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 105791fa4252SDong Aisheng "failed to request card-detect gpio!\n"); 105891fa4252SDong Aisheng return err; 105991fa4252SDong Aisheng } 106091fa4252SDong Aisheng /* fall through */ 106191fa4252SDong Aisheng 106291fa4252SDong Aisheng case ESDHC_CD_CONTROLLER: 106391fa4252SDong Aisheng /* we have a working card_detect back */ 106491fa4252SDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 106591fa4252SDong Aisheng break; 106691fa4252SDong Aisheng 106791fa4252SDong Aisheng case ESDHC_CD_PERMANENT: 106891fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_NONREMOVABLE; 106991fa4252SDong Aisheng break; 107091fa4252SDong Aisheng 107191fa4252SDong Aisheng case ESDHC_CD_NONE: 107291fa4252SDong Aisheng break; 107391fa4252SDong Aisheng } 107491fa4252SDong Aisheng 107591fa4252SDong Aisheng switch (boarddata->max_bus_width) { 107691fa4252SDong Aisheng case 8: 107791fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 107891fa4252SDong Aisheng break; 107991fa4252SDong Aisheng case 4: 108091fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_4_BIT_DATA; 108191fa4252SDong Aisheng break; 108291fa4252SDong Aisheng case 1: 108391fa4252SDong Aisheng default: 108491fa4252SDong Aisheng host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 108591fa4252SDong Aisheng break; 108691fa4252SDong Aisheng } 108791fa4252SDong Aisheng 108891fa4252SDong Aisheng return 0; 108991fa4252SDong Aisheng } 109091fa4252SDong Aisheng 1091c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 109295f25efeSWolfram Sang { 1093abfafc2dSShawn Guo const struct of_device_id *of_id = 1094abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 109585d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 109685d6509dSShawn Guo struct sdhci_host *host; 10970c6d49ceSWolfram Sang int err; 1098e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 109995f25efeSWolfram Sang 11000e748234SChristian Daudt host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0); 110185d6509dSShawn Guo if (IS_ERR(host)) 110285d6509dSShawn Guo return PTR_ERR(host); 110385d6509dSShawn Guo 110485d6509dSShawn Guo pltfm_host = sdhci_priv(host); 110585d6509dSShawn Guo 1106e3af31c6SShawn Guo imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); 1107abfafc2dSShawn Guo if (!imx_data) { 1108abfafc2dSShawn Guo err = -ENOMEM; 1109e3af31c6SShawn Guo goto free_sdhci; 1110abfafc2dSShawn Guo } 111157ed3314SShawn Guo 1112f47c4bbfSShawn Guo imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 11133770ee8fSShawn Guo pdev->id_entry->driver_data; 111485d6509dSShawn Guo pltfm_host->priv = imx_data; 111585d6509dSShawn Guo 111652dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 111752dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 111852dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 1119e3af31c6SShawn Guo goto free_sdhci; 112095f25efeSWolfram Sang } 112152dac615SSascha Hauer 112252dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 112352dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 112452dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 1125e3af31c6SShawn Guo goto free_sdhci; 112652dac615SSascha Hauer } 112752dac615SSascha Hauer 112852dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 112952dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 113052dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 1131e3af31c6SShawn Guo goto free_sdhci; 113252dac615SSascha Hauer } 113352dac615SSascha Hauer 113452dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 1135a974862fSDong Aisheng pltfm_host->clock = clk_get_rate(pltfm_host->clk); 113652dac615SSascha Hauer clk_prepare_enable(imx_data->clk_per); 113752dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ipg); 113852dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ahb); 113995f25efeSWolfram Sang 1140ad93220dSDong Aisheng imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1141e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 1142e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 1143e3af31c6SShawn Guo goto disable_clk; 1144e62d8b8fSDong Aisheng } 1145e62d8b8fSDong Aisheng 1146ad93220dSDong Aisheng imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, 1147ad93220dSDong Aisheng PINCTRL_STATE_DEFAULT); 1148cd529af7SDirk Behme if (IS_ERR(imx_data->pins_default)) 1149cd529af7SDirk Behme dev_warn(mmc_dev(host->mmc), "could not get default state\n"); 1150ad93220dSDong Aisheng 115137865fe9SEric Bénard host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 115237865fe9SEric Bénard 1153f47c4bbfSShawn Guo if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) 11540c6d49ceSWolfram Sang /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ 115597e4ba6aSRichard Zhu host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK 115697e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA; 11570c6d49ceSWolfram Sang 1158f750ba9bSShawn Guo /* 1159f750ba9bSShawn Guo * The imx6q ROM code will change the default watermark level setting 1160f750ba9bSShawn Guo * to something insane. Change it back here. 1161f750ba9bSShawn Guo */ 116269ed60e0SDong Aisheng if (esdhc_is_usdhc(imx_data)) { 116360bf6396SShawn Guo writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); 116469ed60e0SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 1165e2997c94SDong Aisheng host->mmc->caps |= MMC_CAP_1_8V_DDR; 116618094430SDong Aisheng 1167fd44954eSHaibo Chen /* 1168fd44954eSHaibo Chen * ROM code will change the bit burst_length_enable setting 1169fd44954eSHaibo Chen * to zero if this usdhc is choosed to boot system. Change 1170fd44954eSHaibo Chen * it back here, otherwise it will impact the performance a 1171fd44954eSHaibo Chen * lot. This bit is used to enable/disable the burst length 1172fd44954eSHaibo Chen * for the external AHB2AXI bridge, it's usefully especially 1173fd44954eSHaibo Chen * for INCR transfer because without burst length indicator, 1174fd44954eSHaibo Chen * the AHB2AXI bridge does not know the burst length in 1175fd44954eSHaibo Chen * advance. And without burst length indicator, AHB INCR 1176fd44954eSHaibo Chen * transfer can only be converted to singles on the AXI side. 1177fd44954eSHaibo Chen */ 1178fd44954eSHaibo Chen writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) 1179fd44954eSHaibo Chen | ESDHC_BURST_LEN_EN_INCR, 1180fd44954eSHaibo Chen host->ioaddr + SDHCI_HOST_CONTROL); 1181fd44954eSHaibo Chen 11824245afffSDong Aisheng if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 11834245afffSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 11844245afffSDong Aisheng 118518094430SDong Aisheng /* 118618094430SDong Aisheng * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 118718094430SDong Aisheng * TO1.1, it's harmless for MX6SL 118818094430SDong Aisheng */ 118918094430SDong Aisheng writel(readl(host->ioaddr + 0x6c) | BIT(7), 119018094430SDong Aisheng host->ioaddr + 0x6c); 119169ed60e0SDong Aisheng } 1192f750ba9bSShawn Guo 11936e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 11946e9fd28eSDong Aisheng sdhci_esdhc_ops.platform_execute_tuning = 11956e9fd28eSDong Aisheng esdhc_executing_tuning; 11968b2bb0adSDong Aisheng 11978b2bb0adSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 11988b2bb0adSDong Aisheng writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) | 11998b2bb0adSDong Aisheng ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP, 12008b2bb0adSDong Aisheng host->ioaddr + ESDHC_TUNING_CTRL); 12018b2bb0adSDong Aisheng 120218094430SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 120318094430SDong Aisheng host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 120418094430SDong Aisheng 120528b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 120628b07674SHaibo Chen host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; 120728b07674SHaibo Chen 120891fa4252SDong Aisheng if (of_id) 120991fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 121091fa4252SDong Aisheng else 121191fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data); 121291fa4252SDong Aisheng if (err) 1213e3af31c6SShawn Guo goto disable_clk; 1214ad93220dSDong Aisheng 121585d6509dSShawn Guo err = sdhci_add_host(host); 121685d6509dSShawn Guo if (err) 1217e3af31c6SShawn Guo goto disable_clk; 121885d6509dSShawn Guo 121989d7e5c1SDong Aisheng pm_runtime_set_active(&pdev->dev); 122089d7e5c1SDong Aisheng pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 122189d7e5c1SDong Aisheng pm_runtime_use_autosuspend(&pdev->dev); 122289d7e5c1SDong Aisheng pm_suspend_ignore_children(&pdev->dev, 1); 122377903c01SUlf Hansson pm_runtime_enable(&pdev->dev); 122489d7e5c1SDong Aisheng 12257e29c306SWolfram Sang return 0; 12267e29c306SWolfram Sang 1227e3af31c6SShawn Guo disable_clk: 122852dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 122952dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 123052dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 1231e3af31c6SShawn Guo free_sdhci: 123285d6509dSShawn Guo sdhci_pltfm_free(pdev); 123385d6509dSShawn Guo return err; 123495f25efeSWolfram Sang } 123595f25efeSWolfram Sang 12366e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 123795f25efeSWolfram Sang { 123885d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 123995f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1240e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 124185d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 124285d6509dSShawn Guo 12430b414368SUlf Hansson pm_runtime_get_sync(&pdev->dev); 12440b414368SUlf Hansson pm_runtime_disable(&pdev->dev); 12450b414368SUlf Hansson pm_runtime_put_noidle(&pdev->dev); 12460b414368SUlf Hansson 124785d6509dSShawn Guo sdhci_remove_host(host, dead); 12480c6d49ceSWolfram Sang 124952dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 125052dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 125152dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 125252dac615SSascha Hauer 125385d6509dSShawn Guo sdhci_pltfm_free(pdev); 125485d6509dSShawn Guo 125585d6509dSShawn Guo return 0; 125695f25efeSWolfram Sang } 125795f25efeSWolfram Sang 1258162d6f98SRafael J. Wysocki #ifdef CONFIG_PM 125989d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_suspend(struct device *dev) 126089d7e5c1SDong Aisheng { 126189d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 126289d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 126389d7e5c1SDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 126489d7e5c1SDong Aisheng int ret; 126589d7e5c1SDong Aisheng 126689d7e5c1SDong Aisheng ret = sdhci_runtime_suspend_host(host); 126789d7e5c1SDong Aisheng 1268be138554SRussell King if (!sdhci_sdio_irq_enabled(host)) { 126989d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_per); 127089d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ipg); 1271be138554SRussell King } 127289d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ahb); 127389d7e5c1SDong Aisheng 127489d7e5c1SDong Aisheng return ret; 127589d7e5c1SDong Aisheng } 127689d7e5c1SDong Aisheng 127789d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_resume(struct device *dev) 127889d7e5c1SDong Aisheng { 127989d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 128089d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 128189d7e5c1SDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 128289d7e5c1SDong Aisheng 1283be138554SRussell King if (!sdhci_sdio_irq_enabled(host)) { 128489d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_per); 128589d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_ipg); 1286be138554SRussell King } 128789d7e5c1SDong Aisheng clk_prepare_enable(imx_data->clk_ahb); 128889d7e5c1SDong Aisheng 128989d7e5c1SDong Aisheng return sdhci_runtime_resume_host(host); 129089d7e5c1SDong Aisheng } 129189d7e5c1SDong Aisheng #endif 129289d7e5c1SDong Aisheng 129389d7e5c1SDong Aisheng static const struct dev_pm_ops sdhci_esdhc_pmops = { 129489d7e5c1SDong Aisheng SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume) 129589d7e5c1SDong Aisheng SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 129689d7e5c1SDong Aisheng sdhci_esdhc_runtime_resume, NULL) 129789d7e5c1SDong Aisheng }; 129889d7e5c1SDong Aisheng 129985d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 130085d6509dSShawn Guo .driver = { 130185d6509dSShawn Guo .name = "sdhci-esdhc-imx", 1302abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 130389d7e5c1SDong Aisheng .pm = &sdhci_esdhc_pmops, 130485d6509dSShawn Guo }, 130557ed3314SShawn Guo .id_table = imx_esdhc_devtype, 130685d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 13070433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 130895f25efeSWolfram Sang }; 130985d6509dSShawn Guo 1310d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 131185d6509dSShawn Guo 131285d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1313035ff831SWolfram Sang MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 131485d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1315