195f25efeSWolfram Sang /*
295f25efeSWolfram Sang  * Freescale eSDHC i.MX controller driver for the platform bus.
395f25efeSWolfram Sang  *
495f25efeSWolfram Sang  * derived from the OF-version.
595f25efeSWolfram Sang  *
695f25efeSWolfram Sang  * Copyright (c) 2010 Pengutronix e.K.
795f25efeSWolfram Sang  *   Author: Wolfram Sang <w.sang@pengutronix.de>
895f25efeSWolfram Sang  *
995f25efeSWolfram Sang  * This program is free software; you can redistribute it and/or modify
1095f25efeSWolfram Sang  * it under the terms of the GNU General Public License as published by
1195f25efeSWolfram Sang  * the Free Software Foundation; either version 2 of the License.
1295f25efeSWolfram Sang  */
1395f25efeSWolfram Sang 
1495f25efeSWolfram Sang #include <linux/io.h>
1595f25efeSWolfram Sang #include <linux/delay.h>
1695f25efeSWolfram Sang #include <linux/err.h>
1795f25efeSWolfram Sang #include <linux/clk.h>
180c6d49ceSWolfram Sang #include <linux/gpio.h>
1966506f76SShawn Guo #include <linux/module.h>
20e149860dSRichard Zhu #include <linux/slab.h>
2195f25efeSWolfram Sang #include <linux/mmc/host.h>
2258ac8177SRichard Zhu #include <linux/mmc/mmc.h>
2358ac8177SRichard Zhu #include <linux/mmc/sdio.h>
24fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h>
25abfafc2dSShawn Guo #include <linux/of.h>
26abfafc2dSShawn Guo #include <linux/of_device.h>
27abfafc2dSShawn Guo #include <linux/of_gpio.h>
28e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h>
2982906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h>
3095f25efeSWolfram Sang #include "sdhci-pltfm.h"
3195f25efeSWolfram Sang #include "sdhci-esdhc.h"
3295f25efeSWolfram Sang 
330d58864bSTony Lin #define	SDHCI_CTRL_D3CD			0x08
3458ac8177SRichard Zhu /* VENDOR SPEC register */
3558ac8177SRichard Zhu #define SDHCI_VENDOR_SPEC		0xC0
3658ac8177SRichard Zhu #define  SDHCI_VENDOR_SPEC_SDIO_QUIRK	0x00000002
37f750ba9bSShawn Guo #define SDHCI_WTMK_LVL			0x44
3895a2482aSShawn Guo #define SDHCI_MIX_CTRL			0x48
3958ac8177SRichard Zhu 
4058ac8177SRichard Zhu /*
4197e4ba6aSRichard Zhu  * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
4297e4ba6aSRichard Zhu  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
4397e4ba6aSRichard Zhu  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
4497e4ba6aSRichard Zhu  * Define this macro DMA error INT for fsl eSDHC
4597e4ba6aSRichard Zhu  */
4697e4ba6aSRichard Zhu #define SDHCI_INT_VENDOR_SPEC_DMA_ERR	0x10000000
4797e4ba6aSRichard Zhu 
4897e4ba6aSRichard Zhu /*
4958ac8177SRichard Zhu  * The CMDTYPE of the CMD register (offset 0xE) should be set to
5058ac8177SRichard Zhu  * "11" when the STOP CMD12 is issued on imx53 to abort one
5158ac8177SRichard Zhu  * open ended multi-blk IO. Otherwise the TC INT wouldn't
5258ac8177SRichard Zhu  * be generated.
5358ac8177SRichard Zhu  * In exact block transfer, the controller doesn't complete the
5458ac8177SRichard Zhu  * operations automatically as required at the end of the
5558ac8177SRichard Zhu  * transfer and remains on hold if the abort command is not sent.
5658ac8177SRichard Zhu  * As a result, the TC flag is not asserted and SW  received timeout
5758ac8177SRichard Zhu  * exeception. Bit1 of Vendor Spec registor is used to fix it.
5858ac8177SRichard Zhu  */
5958ac8177SRichard Zhu #define ESDHC_FLAG_MULTIBLK_NO_INT	(1 << 1)
60e149860dSRichard Zhu 
6157ed3314SShawn Guo enum imx_esdhc_type {
6257ed3314SShawn Guo 	IMX25_ESDHC,
6357ed3314SShawn Guo 	IMX35_ESDHC,
6457ed3314SShawn Guo 	IMX51_ESDHC,
6557ed3314SShawn Guo 	IMX53_ESDHC,
6695a2482aSShawn Guo 	IMX6Q_USDHC,
6757ed3314SShawn Guo };
6857ed3314SShawn Guo 
69e149860dSRichard Zhu struct pltfm_imx_data {
70e149860dSRichard Zhu 	int flags;
71e149860dSRichard Zhu 	u32 scratchpad;
7257ed3314SShawn Guo 	enum imx_esdhc_type devtype;
73e62d8b8fSDong Aisheng 	struct pinctrl *pinctrl;
74842afc02SShawn Guo 	struct esdhc_platform_data boarddata;
7552dac615SSascha Hauer 	struct clk *clk_ipg;
7652dac615SSascha Hauer 	struct clk *clk_ahb;
7752dac615SSascha Hauer 	struct clk *clk_per;
78e149860dSRichard Zhu };
79e149860dSRichard Zhu 
8057ed3314SShawn Guo static struct platform_device_id imx_esdhc_devtype[] = {
8157ed3314SShawn Guo 	{
8257ed3314SShawn Guo 		.name = "sdhci-esdhc-imx25",
8357ed3314SShawn Guo 		.driver_data = IMX25_ESDHC,
8457ed3314SShawn Guo 	}, {
8557ed3314SShawn Guo 		.name = "sdhci-esdhc-imx35",
8657ed3314SShawn Guo 		.driver_data = IMX35_ESDHC,
8757ed3314SShawn Guo 	}, {
8857ed3314SShawn Guo 		.name = "sdhci-esdhc-imx51",
8957ed3314SShawn Guo 		.driver_data = IMX51_ESDHC,
9057ed3314SShawn Guo 	}, {
9157ed3314SShawn Guo 		.name = "sdhci-esdhc-imx53",
9257ed3314SShawn Guo 		.driver_data = IMX53_ESDHC,
9357ed3314SShawn Guo 	}, {
9495a2482aSShawn Guo 		.name = "sdhci-usdhc-imx6q",
9595a2482aSShawn Guo 		.driver_data = IMX6Q_USDHC,
9695a2482aSShawn Guo 	}, {
9757ed3314SShawn Guo 		/* sentinel */
9857ed3314SShawn Guo 	}
9957ed3314SShawn Guo };
10057ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
10157ed3314SShawn Guo 
102abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = {
103abfafc2dSShawn Guo 	{ .compatible = "fsl,imx25-esdhc", .data = &imx_esdhc_devtype[IMX25_ESDHC], },
104abfafc2dSShawn Guo 	{ .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], },
105abfafc2dSShawn Guo 	{ .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], },
106abfafc2dSShawn Guo 	{ .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], },
10795a2482aSShawn Guo 	{ .compatible = "fsl,imx6q-usdhc", .data = &imx_esdhc_devtype[IMX6Q_USDHC], },
108abfafc2dSShawn Guo 	{ /* sentinel */ }
109abfafc2dSShawn Guo };
110abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
111abfafc2dSShawn Guo 
11257ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
11357ed3314SShawn Guo {
11457ed3314SShawn Guo 	return data->devtype == IMX25_ESDHC;
11557ed3314SShawn Guo }
11657ed3314SShawn Guo 
11757ed3314SShawn Guo static inline int is_imx35_esdhc(struct pltfm_imx_data *data)
11857ed3314SShawn Guo {
11957ed3314SShawn Guo 	return data->devtype == IMX35_ESDHC;
12057ed3314SShawn Guo }
12157ed3314SShawn Guo 
12257ed3314SShawn Guo static inline int is_imx51_esdhc(struct pltfm_imx_data *data)
12357ed3314SShawn Guo {
12457ed3314SShawn Guo 	return data->devtype == IMX51_ESDHC;
12557ed3314SShawn Guo }
12657ed3314SShawn Guo 
12757ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
12857ed3314SShawn Guo {
12957ed3314SShawn Guo 	return data->devtype == IMX53_ESDHC;
13057ed3314SShawn Guo }
13157ed3314SShawn Guo 
13295a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
13395a2482aSShawn Guo {
13495a2482aSShawn Guo 	return data->devtype == IMX6Q_USDHC;
13595a2482aSShawn Guo }
13695a2482aSShawn Guo 
13795f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
13895f25efeSWolfram Sang {
13995f25efeSWolfram Sang 	void __iomem *base = host->ioaddr + (reg & ~0x3);
14095f25efeSWolfram Sang 	u32 shift = (reg & 0x3) * 8;
14195f25efeSWolfram Sang 
14295f25efeSWolfram Sang 	writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
14395f25efeSWolfram Sang }
14495f25efeSWolfram Sang 
1457e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
1467e29c306SWolfram Sang {
147842afc02SShawn Guo 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
148842afc02SShawn Guo 	struct pltfm_imx_data *imx_data = pltfm_host->priv;
149842afc02SShawn Guo 	struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1507e29c306SWolfram Sang 
151913413c3SShawn Guo 	u32 val = readl(host->ioaddr + reg);
152913413c3SShawn Guo 
153fbe5fdd1SShawn Guo 	if (unlikely(reg == SDHCI_PRESENT_STATE)) {
154fbe5fdd1SShawn Guo 		/*
155fbe5fdd1SShawn Guo 		 * After SDHCI core gets improved to never query
156fbe5fdd1SShawn Guo 		 * SDHCI_CARD_PRESENT state in GPIO case, we can
157fbe5fdd1SShawn Guo 		 * remove this check.
158fbe5fdd1SShawn Guo 		 */
159fbe5fdd1SShawn Guo 		if (boarddata->cd_type == ESDHC_CD_GPIO)
160803862a6SShawn Guo 			val &= ~SDHCI_CARD_PRESENT;
1617e29c306SWolfram Sang 	}
1627e29c306SWolfram Sang 
16397e4ba6aSRichard Zhu 	if (unlikely(reg == SDHCI_CAPABILITIES)) {
16497e4ba6aSRichard Zhu 		/* In FSL esdhc IC module, only bit20 is used to indicate the
16597e4ba6aSRichard Zhu 		 * ADMA2 capability of esdhc, but this bit is messed up on
16697e4ba6aSRichard Zhu 		 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
16797e4ba6aSRichard Zhu 		 * don't actually support ADMA2). So set the BROKEN_ADMA
16897e4ba6aSRichard Zhu 		 * uirk on MX25/35 platforms.
16997e4ba6aSRichard Zhu 		 */
17097e4ba6aSRichard Zhu 
17197e4ba6aSRichard Zhu 		if (val & SDHCI_CAN_DO_ADMA1) {
17297e4ba6aSRichard Zhu 			val &= ~SDHCI_CAN_DO_ADMA1;
17397e4ba6aSRichard Zhu 			val |= SDHCI_CAN_DO_ADMA2;
17497e4ba6aSRichard Zhu 		}
17597e4ba6aSRichard Zhu 	}
17697e4ba6aSRichard Zhu 
17797e4ba6aSRichard Zhu 	if (unlikely(reg == SDHCI_INT_STATUS)) {
17897e4ba6aSRichard Zhu 		if (val & SDHCI_INT_VENDOR_SPEC_DMA_ERR) {
17997e4ba6aSRichard Zhu 			val &= ~SDHCI_INT_VENDOR_SPEC_DMA_ERR;
18097e4ba6aSRichard Zhu 			val |= SDHCI_INT_ADMA_ERROR;
18197e4ba6aSRichard Zhu 		}
18297e4ba6aSRichard Zhu 	}
18397e4ba6aSRichard Zhu 
1847e29c306SWolfram Sang 	return val;
1857e29c306SWolfram Sang }
1867e29c306SWolfram Sang 
1877e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
1887e29c306SWolfram Sang {
189e149860dSRichard Zhu 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
190e149860dSRichard Zhu 	struct pltfm_imx_data *imx_data = pltfm_host->priv;
191842afc02SShawn Guo 	struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1920d58864bSTony Lin 	u32 data;
193e149860dSRichard Zhu 
1940d58864bSTony Lin 	if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
1950d58864bSTony Lin 		if (boarddata->cd_type == ESDHC_CD_GPIO)
1967e29c306SWolfram Sang 			/*
1970d58864bSTony Lin 			 * These interrupts won't work with a custom
1980d58864bSTony Lin 			 * card_detect gpio (only applied to mx25/35)
1997e29c306SWolfram Sang 			 */
2007e29c306SWolfram Sang 			val &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
2017e29c306SWolfram Sang 
2020d58864bSTony Lin 		if (val & SDHCI_INT_CARD_INT) {
2030d58864bSTony Lin 			/*
2040d58864bSTony Lin 			 * Clear and then set D3CD bit to avoid missing the
2050d58864bSTony Lin 			 * card interrupt.  This is a eSDHC controller problem
2060d58864bSTony Lin 			 * so we need to apply the following workaround: clear
2070d58864bSTony Lin 			 * and set D3CD bit will make eSDHC re-sample the card
2080d58864bSTony Lin 			 * interrupt. In case a card interrupt was lost,
2090d58864bSTony Lin 			 * re-sample it by the following steps.
2100d58864bSTony Lin 			 */
2110d58864bSTony Lin 			data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
2120d58864bSTony Lin 			data &= ~SDHCI_CTRL_D3CD;
2130d58864bSTony Lin 			writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
2140d58864bSTony Lin 			data |= SDHCI_CTRL_D3CD;
2150d58864bSTony Lin 			writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
2160d58864bSTony Lin 		}
2170d58864bSTony Lin 	}
2180d58864bSTony Lin 
21958ac8177SRichard Zhu 	if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
22058ac8177SRichard Zhu 				&& (reg == SDHCI_INT_STATUS)
22158ac8177SRichard Zhu 				&& (val & SDHCI_INT_DATA_END))) {
22258ac8177SRichard Zhu 			u32 v;
22358ac8177SRichard Zhu 			v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
22458ac8177SRichard Zhu 			v &= ~SDHCI_VENDOR_SPEC_SDIO_QUIRK;
22558ac8177SRichard Zhu 			writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
22658ac8177SRichard Zhu 	}
22758ac8177SRichard Zhu 
22897e4ba6aSRichard Zhu 	if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
22997e4ba6aSRichard Zhu 		if (val & SDHCI_INT_ADMA_ERROR) {
23097e4ba6aSRichard Zhu 			val &= ~SDHCI_INT_ADMA_ERROR;
23197e4ba6aSRichard Zhu 			val |= SDHCI_INT_VENDOR_SPEC_DMA_ERR;
23297e4ba6aSRichard Zhu 		}
23397e4ba6aSRichard Zhu 	}
23497e4ba6aSRichard Zhu 
2357e29c306SWolfram Sang 	writel(val, host->ioaddr + reg);
2367e29c306SWolfram Sang }
2377e29c306SWolfram Sang 
23895f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
23995f25efeSWolfram Sang {
24095a2482aSShawn Guo 	if (unlikely(reg == SDHCI_HOST_VERSION)) {
24195a2482aSShawn Guo 		u16 val = readw(host->ioaddr + (reg ^ 2));
24295a2482aSShawn Guo 		/*
24395a2482aSShawn Guo 		 * uSDHC supports SDHCI v3.0, but it's encoded as value
24495a2482aSShawn Guo 		 * 0x3 in host controller version register, which violates
24595a2482aSShawn Guo 		 * SDHCI_SPEC_300 definition.  Work it around here.
24695a2482aSShawn Guo 		 */
24795a2482aSShawn Guo 		if ((val & SDHCI_SPEC_VER_MASK) == 3)
24895a2482aSShawn Guo 			return --val;
24995a2482aSShawn Guo 	}
25095f25efeSWolfram Sang 
25195f25efeSWolfram Sang 	return readw(host->ioaddr + reg);
25295f25efeSWolfram Sang }
25395f25efeSWolfram Sang 
25495f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
25595f25efeSWolfram Sang {
25695f25efeSWolfram Sang 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
257e149860dSRichard Zhu 	struct pltfm_imx_data *imx_data = pltfm_host->priv;
25895f25efeSWolfram Sang 
25995f25efeSWolfram Sang 	switch (reg) {
26095f25efeSWolfram Sang 	case SDHCI_TRANSFER_MODE:
26195f25efeSWolfram Sang 		/*
26295f25efeSWolfram Sang 		 * Postpone this write, we must do it together with a
26395f25efeSWolfram Sang 		 * command write that is down below.
26495f25efeSWolfram Sang 		 */
26558ac8177SRichard Zhu 		if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
26658ac8177SRichard Zhu 				&& (host->cmd->opcode == SD_IO_RW_EXTENDED)
26758ac8177SRichard Zhu 				&& (host->cmd->data->blocks > 1)
26858ac8177SRichard Zhu 				&& (host->cmd->data->flags & MMC_DATA_READ)) {
26958ac8177SRichard Zhu 			u32 v;
27058ac8177SRichard Zhu 			v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
27158ac8177SRichard Zhu 			v |= SDHCI_VENDOR_SPEC_SDIO_QUIRK;
27258ac8177SRichard Zhu 			writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
27358ac8177SRichard Zhu 		}
274e149860dSRichard Zhu 		imx_data->scratchpad = val;
27595f25efeSWolfram Sang 		return;
27695f25efeSWolfram Sang 	case SDHCI_COMMAND:
2775b6b0ad6SSascha Hauer 		if ((host->cmd->opcode == MMC_STOP_TRANSMISSION ||
2785b6b0ad6SSascha Hauer 		     host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
2795b6b0ad6SSascha Hauer 	            (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
28058ac8177SRichard Zhu 			val |= SDHCI_CMD_ABORTCMD;
28195a2482aSShawn Guo 
28295a2482aSShawn Guo 		if (is_imx6q_usdhc(imx_data)) {
28395a2482aSShawn Guo 			u32 m = readl(host->ioaddr + SDHCI_MIX_CTRL);
28495a2482aSShawn Guo 			m = imx_data->scratchpad | (m & 0xffff0000);
28595a2482aSShawn Guo 			writel(m, host->ioaddr + SDHCI_MIX_CTRL);
28695a2482aSShawn Guo 			writel(val << 16,
28795a2482aSShawn Guo 			       host->ioaddr + SDHCI_TRANSFER_MODE);
28895a2482aSShawn Guo 		} else {
289e149860dSRichard Zhu 			writel(val << 16 | imx_data->scratchpad,
29095f25efeSWolfram Sang 			       host->ioaddr + SDHCI_TRANSFER_MODE);
29195a2482aSShawn Guo 		}
29295f25efeSWolfram Sang 		return;
29395f25efeSWolfram Sang 	case SDHCI_BLOCK_SIZE:
29495f25efeSWolfram Sang 		val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
29595f25efeSWolfram Sang 		break;
29695f25efeSWolfram Sang 	}
29795f25efeSWolfram Sang 	esdhc_clrset_le(host, 0xffff, val, reg);
29895f25efeSWolfram Sang }
29995f25efeSWolfram Sang 
30095f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
30195f25efeSWolfram Sang {
3029a0985b7SWilson Callan 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
3039a0985b7SWilson Callan 	struct pltfm_imx_data *imx_data = pltfm_host->priv;
30495f25efeSWolfram Sang 	u32 new_val;
30595f25efeSWolfram Sang 
30695f25efeSWolfram Sang 	switch (reg) {
30795f25efeSWolfram Sang 	case SDHCI_POWER_CONTROL:
30895f25efeSWolfram Sang 		/*
30995f25efeSWolfram Sang 		 * FSL put some DMA bits here
31095f25efeSWolfram Sang 		 * If your board has a regulator, code should be here
31195f25efeSWolfram Sang 		 */
31295f25efeSWolfram Sang 		return;
31395f25efeSWolfram Sang 	case SDHCI_HOST_CONTROL:
3140d58864bSTony Lin 		/* FSL messed up here, so we can just keep those three */
3150d58864bSTony Lin 		new_val = val & (SDHCI_CTRL_LED | \
3160d58864bSTony Lin 				SDHCI_CTRL_4BITBUS | \
3170d58864bSTony Lin 				SDHCI_CTRL_D3CD);
3187122bbb0SMasanari Iida 		/* ensure the endianness */
31995f25efeSWolfram Sang 		new_val |= ESDHC_HOST_CONTROL_LE;
3209a0985b7SWilson Callan 		/* bits 8&9 are reserved on mx25 */
3219a0985b7SWilson Callan 		if (!is_imx25_esdhc(imx_data)) {
32295f25efeSWolfram Sang 			/* DMA mode bits are shifted */
32395f25efeSWolfram Sang 			new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
3249a0985b7SWilson Callan 		}
32595f25efeSWolfram Sang 
32695f25efeSWolfram Sang 		esdhc_clrset_le(host, 0xffff, new_val, reg);
32795f25efeSWolfram Sang 		return;
32895f25efeSWolfram Sang 	}
32995f25efeSWolfram Sang 	esdhc_clrset_le(host, 0xff, val, reg);
330913413c3SShawn Guo 
331913413c3SShawn Guo 	/*
332913413c3SShawn Guo 	 * The esdhc has a design violation to SDHC spec which tells
333913413c3SShawn Guo 	 * that software reset should not affect card detection circuit.
334913413c3SShawn Guo 	 * But esdhc clears its SYSCTL register bits [0..2] during the
335913413c3SShawn Guo 	 * software reset.  This will stop those clocks that card detection
336913413c3SShawn Guo 	 * circuit relies on.  To work around it, we turn the clocks on back
337913413c3SShawn Guo 	 * to keep card detection circuit functional.
338913413c3SShawn Guo 	 */
339913413c3SShawn Guo 	if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1))
340913413c3SShawn Guo 		esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
34195f25efeSWolfram Sang }
34295f25efeSWolfram Sang 
34395f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
34495f25efeSWolfram Sang {
34595f25efeSWolfram Sang 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
34695f25efeSWolfram Sang 
34795f25efeSWolfram Sang 	return clk_get_rate(pltfm_host->clk);
34895f25efeSWolfram Sang }
34995f25efeSWolfram Sang 
35095f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
35195f25efeSWolfram Sang {
35295f25efeSWolfram Sang 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
35395f25efeSWolfram Sang 
35495f25efeSWolfram Sang 	return clk_get_rate(pltfm_host->clk) / 256 / 16;
35595f25efeSWolfram Sang }
35695f25efeSWolfram Sang 
357913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
358913413c3SShawn Guo {
359842afc02SShawn Guo 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
360842afc02SShawn Guo 	struct pltfm_imx_data *imx_data = pltfm_host->priv;
361842afc02SShawn Guo 	struct esdhc_platform_data *boarddata = &imx_data->boarddata;
362913413c3SShawn Guo 
363913413c3SShawn Guo 	switch (boarddata->wp_type) {
364913413c3SShawn Guo 	case ESDHC_WP_GPIO:
365fbe5fdd1SShawn Guo 		return mmc_gpio_get_ro(host->mmc);
366913413c3SShawn Guo 	case ESDHC_WP_CONTROLLER:
367913413c3SShawn Guo 		return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
368913413c3SShawn Guo 			       SDHCI_WRITE_PROTECT);
369913413c3SShawn Guo 	case ESDHC_WP_NONE:
370913413c3SShawn Guo 		break;
371913413c3SShawn Guo 	}
372913413c3SShawn Guo 
373913413c3SShawn Guo 	return -ENOSYS;
374913413c3SShawn Guo }
375913413c3SShawn Guo 
3760c6d49ceSWolfram Sang static struct sdhci_ops sdhci_esdhc_ops = {
377e149860dSRichard Zhu 	.read_l = esdhc_readl_le,
3780c6d49ceSWolfram Sang 	.read_w = esdhc_readw_le,
379e149860dSRichard Zhu 	.write_l = esdhc_writel_le,
3800c6d49ceSWolfram Sang 	.write_w = esdhc_writew_le,
3810c6d49ceSWolfram Sang 	.write_b = esdhc_writeb_le,
3820c6d49ceSWolfram Sang 	.set_clock = esdhc_set_clock,
3830c6d49ceSWolfram Sang 	.get_max_clock = esdhc_pltfm_get_max_clock,
3840c6d49ceSWolfram Sang 	.get_min_clock = esdhc_pltfm_get_min_clock,
385913413c3SShawn Guo 	.get_ro = esdhc_pltfm_get_ro,
3860c6d49ceSWolfram Sang };
3870c6d49ceSWolfram Sang 
38885d6509dSShawn Guo static struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
38997e4ba6aSRichard Zhu 	.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
39097e4ba6aSRichard Zhu 			| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
39197e4ba6aSRichard Zhu 			| SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
39285d6509dSShawn Guo 			| SDHCI_QUIRK_BROKEN_CARD_DETECTION,
39385d6509dSShawn Guo 	.ops = &sdhci_esdhc_ops,
39485d6509dSShawn Guo };
39585d6509dSShawn Guo 
396abfafc2dSShawn Guo #ifdef CONFIG_OF
397c3be1efdSBill Pemberton static int
398abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
399abfafc2dSShawn Guo 			 struct esdhc_platform_data *boarddata)
400abfafc2dSShawn Guo {
401abfafc2dSShawn Guo 	struct device_node *np = pdev->dev.of_node;
402abfafc2dSShawn Guo 
403abfafc2dSShawn Guo 	if (!np)
404abfafc2dSShawn Guo 		return -ENODEV;
405abfafc2dSShawn Guo 
4067f217794SArnd Bergmann 	if (of_get_property(np, "non-removable", NULL))
407abfafc2dSShawn Guo 		boarddata->cd_type = ESDHC_CD_PERMANENT;
408abfafc2dSShawn Guo 
409abfafc2dSShawn Guo 	if (of_get_property(np, "fsl,cd-controller", NULL))
410abfafc2dSShawn Guo 		boarddata->cd_type = ESDHC_CD_CONTROLLER;
411abfafc2dSShawn Guo 
412abfafc2dSShawn Guo 	if (of_get_property(np, "fsl,wp-controller", NULL))
413abfafc2dSShawn Guo 		boarddata->wp_type = ESDHC_WP_CONTROLLER;
414abfafc2dSShawn Guo 
415abfafc2dSShawn Guo 	boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
416abfafc2dSShawn Guo 	if (gpio_is_valid(boarddata->cd_gpio))
417abfafc2dSShawn Guo 		boarddata->cd_type = ESDHC_CD_GPIO;
418abfafc2dSShawn Guo 
419abfafc2dSShawn Guo 	boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
420abfafc2dSShawn Guo 	if (gpio_is_valid(boarddata->wp_gpio))
421abfafc2dSShawn Guo 		boarddata->wp_type = ESDHC_WP_GPIO;
422abfafc2dSShawn Guo 
423abfafc2dSShawn Guo 	return 0;
424abfafc2dSShawn Guo }
425abfafc2dSShawn Guo #else
426abfafc2dSShawn Guo static inline int
427abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
428abfafc2dSShawn Guo 			 struct esdhc_platform_data *boarddata)
429abfafc2dSShawn Guo {
430abfafc2dSShawn Guo 	return -ENODEV;
431abfafc2dSShawn Guo }
432abfafc2dSShawn Guo #endif
433abfafc2dSShawn Guo 
434c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
43595f25efeSWolfram Sang {
436abfafc2dSShawn Guo 	const struct of_device_id *of_id =
437abfafc2dSShawn Guo 			of_match_device(imx_esdhc_dt_ids, &pdev->dev);
43885d6509dSShawn Guo 	struct sdhci_pltfm_host *pltfm_host;
43985d6509dSShawn Guo 	struct sdhci_host *host;
44085d6509dSShawn Guo 	struct esdhc_platform_data *boarddata;
4410c6d49ceSWolfram Sang 	int err;
442e149860dSRichard Zhu 	struct pltfm_imx_data *imx_data;
44395f25efeSWolfram Sang 
44485d6509dSShawn Guo 	host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata);
44585d6509dSShawn Guo 	if (IS_ERR(host))
44685d6509dSShawn Guo 		return PTR_ERR(host);
44785d6509dSShawn Guo 
44885d6509dSShawn Guo 	pltfm_host = sdhci_priv(host);
44985d6509dSShawn Guo 
450e3af31c6SShawn Guo 	imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
451abfafc2dSShawn Guo 	if (!imx_data) {
452abfafc2dSShawn Guo 		err = -ENOMEM;
453e3af31c6SShawn Guo 		goto free_sdhci;
454abfafc2dSShawn Guo 	}
45557ed3314SShawn Guo 
456abfafc2dSShawn Guo 	if (of_id)
457abfafc2dSShawn Guo 		pdev->id_entry = of_id->data;
45857ed3314SShawn Guo 	imx_data->devtype = pdev->id_entry->driver_data;
45985d6509dSShawn Guo 	pltfm_host->priv = imx_data;
46085d6509dSShawn Guo 
46152dac615SSascha Hauer 	imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
46252dac615SSascha Hauer 	if (IS_ERR(imx_data->clk_ipg)) {
46352dac615SSascha Hauer 		err = PTR_ERR(imx_data->clk_ipg);
464e3af31c6SShawn Guo 		goto free_sdhci;
46595f25efeSWolfram Sang 	}
46652dac615SSascha Hauer 
46752dac615SSascha Hauer 	imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
46852dac615SSascha Hauer 	if (IS_ERR(imx_data->clk_ahb)) {
46952dac615SSascha Hauer 		err = PTR_ERR(imx_data->clk_ahb);
470e3af31c6SShawn Guo 		goto free_sdhci;
47152dac615SSascha Hauer 	}
47252dac615SSascha Hauer 
47352dac615SSascha Hauer 	imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
47452dac615SSascha Hauer 	if (IS_ERR(imx_data->clk_per)) {
47552dac615SSascha Hauer 		err = PTR_ERR(imx_data->clk_per);
476e3af31c6SShawn Guo 		goto free_sdhci;
47752dac615SSascha Hauer 	}
47852dac615SSascha Hauer 
47952dac615SSascha Hauer 	pltfm_host->clk = imx_data->clk_per;
48052dac615SSascha Hauer 
48152dac615SSascha Hauer 	clk_prepare_enable(imx_data->clk_per);
48252dac615SSascha Hauer 	clk_prepare_enable(imx_data->clk_ipg);
48352dac615SSascha Hauer 	clk_prepare_enable(imx_data->clk_ahb);
48495f25efeSWolfram Sang 
485e62d8b8fSDong Aisheng 	imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
486e62d8b8fSDong Aisheng 	if (IS_ERR(imx_data->pinctrl)) {
487e62d8b8fSDong Aisheng 		err = PTR_ERR(imx_data->pinctrl);
488e3af31c6SShawn Guo 		goto disable_clk;
489e62d8b8fSDong Aisheng 	}
490e62d8b8fSDong Aisheng 
49137865fe9SEric Bénard 	host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
49237865fe9SEric Bénard 
49357ed3314SShawn Guo 	if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
4940c6d49ceSWolfram Sang 		/* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
49597e4ba6aSRichard Zhu 		host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
49697e4ba6aSRichard Zhu 			| SDHCI_QUIRK_BROKEN_ADMA;
4970c6d49ceSWolfram Sang 
49857ed3314SShawn Guo 	if (is_imx53_esdhc(imx_data))
49958ac8177SRichard Zhu 		imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT;
50058ac8177SRichard Zhu 
501f750ba9bSShawn Guo 	/*
502f750ba9bSShawn Guo 	 * The imx6q ROM code will change the default watermark level setting
503f750ba9bSShawn Guo 	 * to something insane.  Change it back here.
504f750ba9bSShawn Guo 	 */
505f750ba9bSShawn Guo 	if (is_imx6q_usdhc(imx_data))
506f750ba9bSShawn Guo 		writel(0x08100810, host->ioaddr + SDHCI_WTMK_LVL);
507f750ba9bSShawn Guo 
508abfafc2dSShawn Guo 	boarddata = &imx_data->boarddata;
509abfafc2dSShawn Guo 	if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
510842afc02SShawn Guo 		if (!host->mmc->parent->platform_data) {
511913413c3SShawn Guo 			dev_err(mmc_dev(host->mmc), "no board data!\n");
512913413c3SShawn Guo 			err = -EINVAL;
513e3af31c6SShawn Guo 			goto disable_clk;
514913413c3SShawn Guo 		}
515842afc02SShawn Guo 		imx_data->boarddata = *((struct esdhc_platform_data *)
516842afc02SShawn Guo 					host->mmc->parent->platform_data);
517abfafc2dSShawn Guo 	}
518913413c3SShawn Guo 
519913413c3SShawn Guo 	/* write_protect */
520913413c3SShawn Guo 	if (boarddata->wp_type == ESDHC_WP_GPIO) {
521fbe5fdd1SShawn Guo 		err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
5220c6d49ceSWolfram Sang 		if (err) {
523fbe5fdd1SShawn Guo 			dev_err(mmc_dev(host->mmc),
524fbe5fdd1SShawn Guo 				"failed to request write-protect gpio!\n");
525fbe5fdd1SShawn Guo 			goto disable_clk;
526913413c3SShawn Guo 		}
527fbe5fdd1SShawn Guo 		host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
5280c6d49ceSWolfram Sang 	}
5297e29c306SWolfram Sang 
530913413c3SShawn Guo 	/* card_detect */
531913413c3SShawn Guo 	switch (boarddata->cd_type) {
532913413c3SShawn Guo 	case ESDHC_CD_GPIO:
533fbe5fdd1SShawn Guo 		err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio);
5347e29c306SWolfram Sang 		if (err) {
535913413c3SShawn Guo 			dev_err(mmc_dev(host->mmc),
536fbe5fdd1SShawn Guo 				"failed to request card-detect gpio!\n");
537e3af31c6SShawn Guo 			goto disable_clk;
5387e29c306SWolfram Sang 		}
539913413c3SShawn Guo 		/* fall through */
5407e29c306SWolfram Sang 
541913413c3SShawn Guo 	case ESDHC_CD_CONTROLLER:
542913413c3SShawn Guo 		/* we have a working card_detect back */
5437e29c306SWolfram Sang 		host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
544913413c3SShawn Guo 		break;
545913413c3SShawn Guo 
546913413c3SShawn Guo 	case ESDHC_CD_PERMANENT:
547913413c3SShawn Guo 		host->mmc->caps = MMC_CAP_NONREMOVABLE;
548913413c3SShawn Guo 		break;
549913413c3SShawn Guo 
550913413c3SShawn Guo 	case ESDHC_CD_NONE:
551913413c3SShawn Guo 		break;
5527e29c306SWolfram Sang 	}
5537e29c306SWolfram Sang 
55485d6509dSShawn Guo 	err = sdhci_add_host(host);
55585d6509dSShawn Guo 	if (err)
556e3af31c6SShawn Guo 		goto disable_clk;
55785d6509dSShawn Guo 
5587e29c306SWolfram Sang 	return 0;
5597e29c306SWolfram Sang 
560e3af31c6SShawn Guo disable_clk:
56152dac615SSascha Hauer 	clk_disable_unprepare(imx_data->clk_per);
56252dac615SSascha Hauer 	clk_disable_unprepare(imx_data->clk_ipg);
56352dac615SSascha Hauer 	clk_disable_unprepare(imx_data->clk_ahb);
564e3af31c6SShawn Guo free_sdhci:
56585d6509dSShawn Guo 	sdhci_pltfm_free(pdev);
56685d6509dSShawn Guo 	return err;
56795f25efeSWolfram Sang }
56895f25efeSWolfram Sang 
5696e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
57095f25efeSWolfram Sang {
57185d6509dSShawn Guo 	struct sdhci_host *host = platform_get_drvdata(pdev);
57295f25efeSWolfram Sang 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
573e149860dSRichard Zhu 	struct pltfm_imx_data *imx_data = pltfm_host->priv;
57485d6509dSShawn Guo 	int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
57585d6509dSShawn Guo 
57685d6509dSShawn Guo 	sdhci_remove_host(host, dead);
5770c6d49ceSWolfram Sang 
57852dac615SSascha Hauer 	clk_disable_unprepare(imx_data->clk_per);
57952dac615SSascha Hauer 	clk_disable_unprepare(imx_data->clk_ipg);
58052dac615SSascha Hauer 	clk_disable_unprepare(imx_data->clk_ahb);
58152dac615SSascha Hauer 
58285d6509dSShawn Guo 	sdhci_pltfm_free(pdev);
58385d6509dSShawn Guo 
58485d6509dSShawn Guo 	return 0;
58595f25efeSWolfram Sang }
58695f25efeSWolfram Sang 
58785d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = {
58885d6509dSShawn Guo 	.driver		= {
58985d6509dSShawn Guo 		.name	= "sdhci-esdhc-imx",
59085d6509dSShawn Guo 		.owner	= THIS_MODULE,
591abfafc2dSShawn Guo 		.of_match_table = imx_esdhc_dt_ids,
59229495aa0SManuel Lauss 		.pm	= SDHCI_PLTFM_PMOPS,
59385d6509dSShawn Guo 	},
59457ed3314SShawn Guo 	.id_table	= imx_esdhc_devtype,
59585d6509dSShawn Guo 	.probe		= sdhci_esdhc_imx_probe,
5960433c143SBill Pemberton 	.remove		= sdhci_esdhc_imx_remove,
59795f25efeSWolfram Sang };
59885d6509dSShawn Guo 
599d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver);
60085d6509dSShawn Guo 
60185d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
60285d6509dSShawn Guo MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
60385d6509dSShawn Guo MODULE_LICENSE("GPL v2");
604