195f25efeSWolfram Sang /* 295f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 395f25efeSWolfram Sang * 495f25efeSWolfram Sang * derived from the OF-version. 595f25efeSWolfram Sang * 695f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 795f25efeSWolfram Sang * Author: Wolfram Sang <w.sang@pengutronix.de> 895f25efeSWolfram Sang * 995f25efeSWolfram Sang * This program is free software; you can redistribute it and/or modify 1095f25efeSWolfram Sang * it under the terms of the GNU General Public License as published by 1195f25efeSWolfram Sang * the Free Software Foundation; either version 2 of the License. 1295f25efeSWolfram Sang */ 1395f25efeSWolfram Sang 1495f25efeSWolfram Sang #include <linux/io.h> 1595f25efeSWolfram Sang #include <linux/delay.h> 1695f25efeSWolfram Sang #include <linux/err.h> 1795f25efeSWolfram Sang #include <linux/clk.h> 180c6d49ceSWolfram Sang #include <linux/gpio.h> 1966506f76SShawn Guo #include <linux/module.h> 20e149860dSRichard Zhu #include <linux/slab.h> 2195f25efeSWolfram Sang #include <linux/mmc/host.h> 2258ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2358ac8177SRichard Zhu #include <linux/mmc/sdio.h> 24fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 25abfafc2dSShawn Guo #include <linux/of.h> 26abfafc2dSShawn Guo #include <linux/of_device.h> 27abfafc2dSShawn Guo #include <linux/of_gpio.h> 28e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2982906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 3095f25efeSWolfram Sang #include "sdhci-pltfm.h" 3195f25efeSWolfram Sang #include "sdhci-esdhc.h" 3295f25efeSWolfram Sang 3360bf6396SShawn Guo #define ESDHC_CTRL_D3CD 0x08 3458ac8177SRichard Zhu /* VENDOR SPEC register */ 3560bf6396SShawn Guo #define ESDHC_VENDOR_SPEC 0xc0 3660bf6396SShawn Guo #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 370322191eSDong Aisheng #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 38fed2f6e2SDong Aisheng #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 3960bf6396SShawn Guo #define ESDHC_WTMK_LVL 0x44 4060bf6396SShawn Guo #define ESDHC_MIX_CTRL 0x48 412a15f981SShawn Guo #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 420322191eSDong Aisheng #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 430322191eSDong Aisheng #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 440322191eSDong Aisheng #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 452a15f981SShawn Guo /* Bits 3 and 6 are not SDHCI standard definitions */ 462a15f981SShawn Guo #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 4758ac8177SRichard Zhu 480322191eSDong Aisheng /* tune control register */ 490322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STATUS 0x68 500322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STEP 1 510322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MIN 0 520322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 530322191eSDong Aisheng 540322191eSDong Aisheng #define ESDHC_TUNING_BLOCK_PATTERN_LEN 64 550322191eSDong Aisheng 56ad93220dSDong Aisheng /* pinctrl state */ 57ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 58ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 59ad93220dSDong Aisheng 6058ac8177SRichard Zhu /* 61af51079eSSascha Hauer * Our interpretation of the SDHCI_HOST_CONTROL register 62af51079eSSascha Hauer */ 63af51079eSSascha Hauer #define ESDHC_CTRL_4BITBUS (0x1 << 1) 64af51079eSSascha Hauer #define ESDHC_CTRL_8BITBUS (0x2 << 1) 65af51079eSSascha Hauer #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 66af51079eSSascha Hauer 67af51079eSSascha Hauer /* 6897e4ba6aSRichard Zhu * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: 6997e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 7097e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 7197e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 7297e4ba6aSRichard Zhu */ 7360bf6396SShawn Guo #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 7497e4ba6aSRichard Zhu 7597e4ba6aSRichard Zhu /* 7658ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 7758ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 7858ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 7958ac8177SRichard Zhu * be generated. 8058ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 8158ac8177SRichard Zhu * operations automatically as required at the end of the 8258ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 8358ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 8458ac8177SRichard Zhu * exeception. Bit1 of Vendor Spec registor is used to fix it. 8558ac8177SRichard Zhu */ 8631fbb301SShawn Guo #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 8731fbb301SShawn Guo /* 8831fbb301SShawn Guo * The flag enables the workaround for ESDHC errata ENGcm07207 which 8931fbb301SShawn Guo * affects i.MX25 and i.MX35. 9031fbb301SShawn Guo */ 9131fbb301SShawn Guo #define ESDHC_FLAG_ENGCM07207 BIT(2) 929d61c009SShawn Guo /* 939d61c009SShawn Guo * The flag tells that the ESDHC controller is an USDHC block that is 949d61c009SShawn Guo * integrated on the i.MX6 series. 959d61c009SShawn Guo */ 969d61c009SShawn Guo #define ESDHC_FLAG_USDHC BIT(3) 97e149860dSRichard Zhu 98f47c4bbfSShawn Guo struct esdhc_soc_data { 99f47c4bbfSShawn Guo u32 flags; 100f47c4bbfSShawn Guo }; 101f47c4bbfSShawn Guo 102f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx25_data = { 103f47c4bbfSShawn Guo .flags = ESDHC_FLAG_ENGCM07207, 104f47c4bbfSShawn Guo }; 105f47c4bbfSShawn Guo 106f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx35_data = { 107f47c4bbfSShawn Guo .flags = ESDHC_FLAG_ENGCM07207, 108f47c4bbfSShawn Guo }; 109f47c4bbfSShawn Guo 110f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx51_data = { 111f47c4bbfSShawn Guo .flags = 0, 112f47c4bbfSShawn Guo }; 113f47c4bbfSShawn Guo 114f47c4bbfSShawn Guo static struct esdhc_soc_data esdhc_imx53_data = { 115f47c4bbfSShawn Guo .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 116f47c4bbfSShawn Guo }; 117f47c4bbfSShawn Guo 118f47c4bbfSShawn Guo static struct esdhc_soc_data usdhc_imx6q_data = { 119f47c4bbfSShawn Guo .flags = ESDHC_FLAG_USDHC, 12057ed3314SShawn Guo }; 12157ed3314SShawn Guo 122e149860dSRichard Zhu struct pltfm_imx_data { 123e149860dSRichard Zhu u32 scratchpad; 124e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 125ad93220dSDong Aisheng struct pinctrl_state *pins_default; 126ad93220dSDong Aisheng struct pinctrl_state *pins_100mhz; 127ad93220dSDong Aisheng struct pinctrl_state *pins_200mhz; 128f47c4bbfSShawn Guo const struct esdhc_soc_data *socdata; 129842afc02SShawn Guo struct esdhc_platform_data boarddata; 13052dac615SSascha Hauer struct clk *clk_ipg; 13152dac615SSascha Hauer struct clk *clk_ahb; 13252dac615SSascha Hauer struct clk *clk_per; 133361b8482SLucas Stach enum { 134361b8482SLucas Stach NO_CMD_PENDING, /* no multiblock command pending*/ 135361b8482SLucas Stach MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 136361b8482SLucas Stach WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 137361b8482SLucas Stach } multiblock_status; 1380322191eSDong Aisheng u32 uhs_mode; 139e149860dSRichard Zhu }; 140e149860dSRichard Zhu 14157ed3314SShawn Guo static struct platform_device_id imx_esdhc_devtype[] = { 14257ed3314SShawn Guo { 14357ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 144f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 14557ed3314SShawn Guo }, { 14657ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 147f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 14857ed3314SShawn Guo }, { 14957ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 150f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 15157ed3314SShawn Guo }, { 15257ed3314SShawn Guo /* sentinel */ 15357ed3314SShawn Guo } 15457ed3314SShawn Guo }; 15557ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 15657ed3314SShawn Guo 157abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 158f47c4bbfSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 159f47c4bbfSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 160f47c4bbfSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 161f47c4bbfSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 162f47c4bbfSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 163abfafc2dSShawn Guo { /* sentinel */ } 164abfafc2dSShawn Guo }; 165abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 166abfafc2dSShawn Guo 16757ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 16857ed3314SShawn Guo { 169f47c4bbfSShawn Guo return data->socdata == &esdhc_imx25_data; 17057ed3314SShawn Guo } 17157ed3314SShawn Guo 17257ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 17357ed3314SShawn Guo { 174f47c4bbfSShawn Guo return data->socdata == &esdhc_imx53_data; 17557ed3314SShawn Guo } 17657ed3314SShawn Guo 17795a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 17895a2482aSShawn Guo { 179f47c4bbfSShawn Guo return data->socdata == &usdhc_imx6q_data; 18095a2482aSShawn Guo } 18195a2482aSShawn Guo 1829d61c009SShawn Guo static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 1839d61c009SShawn Guo { 184f47c4bbfSShawn Guo return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 1859d61c009SShawn Guo } 1869d61c009SShawn Guo 18795f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 18895f25efeSWolfram Sang { 18995f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 19095f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 19195f25efeSWolfram Sang 19295f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 19395f25efeSWolfram Sang } 19495f25efeSWolfram Sang 1957e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 1967e29c306SWolfram Sang { 197361b8482SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 198361b8482SLucas Stach struct pltfm_imx_data *imx_data = pltfm_host->priv; 199913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 200913413c3SShawn Guo 2010322191eSDong Aisheng if (unlikely(reg == SDHCI_PRESENT_STATE)) { 2020322191eSDong Aisheng u32 fsl_prss = val; 2030322191eSDong Aisheng /* save the least 20 bits */ 2040322191eSDong Aisheng val = fsl_prss & 0x000FFFFF; 2050322191eSDong Aisheng /* move dat[0-3] bits */ 2060322191eSDong Aisheng val |= (fsl_prss & 0x0F000000) >> 4; 2070322191eSDong Aisheng /* move cmd line bit */ 2080322191eSDong Aisheng val |= (fsl_prss & 0x00800000) << 1; 2090322191eSDong Aisheng } 2100322191eSDong Aisheng 21197e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 21297e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 21397e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 21497e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 21597e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 21697e4ba6aSRichard Zhu * uirk on MX25/35 platforms. 21797e4ba6aSRichard Zhu */ 21897e4ba6aSRichard Zhu 21997e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 22097e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 22197e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 22297e4ba6aSRichard Zhu } 22397e4ba6aSRichard Zhu } 22497e4ba6aSRichard Zhu 2259d61c009SShawn Guo if (unlikely(reg == SDHCI_CAPABILITIES_1) && esdhc_is_usdhc(imx_data)) 2260322191eSDong Aisheng val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 2270322191eSDong Aisheng | SDHCI_SUPPORT_SDR50; 2280322191eSDong Aisheng 2299d61c009SShawn Guo if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 2300322191eSDong Aisheng val = 0; 2310322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 2320322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 2330322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 2340322191eSDong Aisheng } 2350322191eSDong Aisheng 23697e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 23760bf6396SShawn Guo if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 23860bf6396SShawn Guo val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 23997e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 24097e4ba6aSRichard Zhu } 241361b8482SLucas Stach 242361b8482SLucas Stach /* 243361b8482SLucas Stach * mask off the interrupt we get in response to the manually 244361b8482SLucas Stach * sent CMD12 245361b8482SLucas Stach */ 246361b8482SLucas Stach if ((imx_data->multiblock_status == WAIT_FOR_INT) && 247361b8482SLucas Stach ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 248361b8482SLucas Stach val &= ~SDHCI_INT_RESPONSE; 249361b8482SLucas Stach writel(SDHCI_INT_RESPONSE, host->ioaddr + 250361b8482SLucas Stach SDHCI_INT_STATUS); 251361b8482SLucas Stach imx_data->multiblock_status = NO_CMD_PENDING; 252361b8482SLucas Stach } 25397e4ba6aSRichard Zhu } 25497e4ba6aSRichard Zhu 2557e29c306SWolfram Sang return val; 2567e29c306SWolfram Sang } 2577e29c306SWolfram Sang 2587e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 2597e29c306SWolfram Sang { 260e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 261e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 2620d58864bSTony Lin u32 data; 263e149860dSRichard Zhu 2640d58864bSTony Lin if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 2650d58864bSTony Lin if (val & SDHCI_INT_CARD_INT) { 2660d58864bSTony Lin /* 2670d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 2680d58864bSTony Lin * card interrupt. This is a eSDHC controller problem 2690d58864bSTony Lin * so we need to apply the following workaround: clear 2700d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 2710d58864bSTony Lin * interrupt. In case a card interrupt was lost, 2720d58864bSTony Lin * re-sample it by the following steps. 2730d58864bSTony Lin */ 2740d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 27560bf6396SShawn Guo data &= ~ESDHC_CTRL_D3CD; 2760d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 27760bf6396SShawn Guo data |= ESDHC_CTRL_D3CD; 2780d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 2790d58864bSTony Lin } 2800d58864bSTony Lin } 2810d58864bSTony Lin 282f47c4bbfSShawn Guo if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 28358ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 28458ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 28558ac8177SRichard Zhu u32 v; 28660bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 28760bf6396SShawn Guo v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 28860bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 289361b8482SLucas Stach 290361b8482SLucas Stach if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 291361b8482SLucas Stach { 292361b8482SLucas Stach /* send a manual CMD12 with RESPTYP=none */ 293361b8482SLucas Stach data = MMC_STOP_TRANSMISSION << 24 | 294361b8482SLucas Stach SDHCI_CMD_ABORTCMD << 16; 295361b8482SLucas Stach writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 296361b8482SLucas Stach imx_data->multiblock_status = WAIT_FOR_INT; 297361b8482SLucas Stach } 29858ac8177SRichard Zhu } 29958ac8177SRichard Zhu 30097e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 30197e4ba6aSRichard Zhu if (val & SDHCI_INT_ADMA_ERROR) { 30297e4ba6aSRichard Zhu val &= ~SDHCI_INT_ADMA_ERROR; 30360bf6396SShawn Guo val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 30497e4ba6aSRichard Zhu } 30597e4ba6aSRichard Zhu } 30697e4ba6aSRichard Zhu 3077e29c306SWolfram Sang writel(val, host->ioaddr + reg); 3087e29c306SWolfram Sang } 3097e29c306SWolfram Sang 31095f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 31195f25efeSWolfram Sang { 312ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 313ef4d0888SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 3140322191eSDong Aisheng u16 ret = 0; 3150322191eSDong Aisheng u32 val; 316ef4d0888SShawn Guo 31795a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 318ef4d0888SShawn Guo reg ^= 2; 3199d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 32095a2482aSShawn Guo /* 321ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 322ef4d0888SShawn Guo * Correct it here. 32395a2482aSShawn Guo */ 324ef4d0888SShawn Guo return SDHCI_SPEC_300; 325ef4d0888SShawn Guo } 32695a2482aSShawn Guo } 32795f25efeSWolfram Sang 3280322191eSDong Aisheng if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 3290322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 3300322191eSDong Aisheng if (val & ESDHC_VENDOR_SPEC_VSELECT) 3310322191eSDong Aisheng ret |= SDHCI_CTRL_VDD_180; 3320322191eSDong Aisheng 3339d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 3340322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_MIX_CTRL); 3350322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_EXE_TUNE) 3360322191eSDong Aisheng ret |= SDHCI_CTRL_EXEC_TUNING; 3370322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 3380322191eSDong Aisheng ret |= SDHCI_CTRL_TUNED_CLK; 3390322191eSDong Aisheng } 3400322191eSDong Aisheng 3410322191eSDong Aisheng ret |= (imx_data->uhs_mode & SDHCI_CTRL_UHS_MASK); 3420322191eSDong Aisheng ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 3430322191eSDong Aisheng 3440322191eSDong Aisheng return ret; 3450322191eSDong Aisheng } 3460322191eSDong Aisheng 34795f25efeSWolfram Sang return readw(host->ioaddr + reg); 34895f25efeSWolfram Sang } 34995f25efeSWolfram Sang 35095f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 35195f25efeSWolfram Sang { 35295f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 353e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 3540322191eSDong Aisheng u32 new_val = 0; 35595f25efeSWolfram Sang 35695f25efeSWolfram Sang switch (reg) { 3570322191eSDong Aisheng case SDHCI_CLOCK_CONTROL: 3580322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 3590322191eSDong Aisheng if (val & SDHCI_CLOCK_CARD_EN) 3600322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 3610322191eSDong Aisheng else 3620322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 3630322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 3640322191eSDong Aisheng return; 3650322191eSDong Aisheng case SDHCI_HOST_CONTROL2: 3660322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 3670322191eSDong Aisheng if (val & SDHCI_CTRL_VDD_180) 3680322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_VSELECT; 3690322191eSDong Aisheng else 3700322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 3710322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 3720322191eSDong Aisheng imx_data->uhs_mode = val & SDHCI_CTRL_UHS_MASK; 3730322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 3740322191eSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) 3750322191eSDong Aisheng new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 3760322191eSDong Aisheng else 3770322191eSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 3780322191eSDong Aisheng writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 3790322191eSDong Aisheng return; 38095f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 381f47c4bbfSShawn Guo if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 38258ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 38358ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 38458ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 38558ac8177SRichard Zhu u32 v; 38660bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 38760bf6396SShawn Guo v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 38860bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 38958ac8177SRichard Zhu } 39069f54698SShawn Guo 3919d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 39269f54698SShawn Guo u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 3932a15f981SShawn Guo /* Swap AC23 bit */ 3942a15f981SShawn Guo if (val & SDHCI_TRNS_AUTO_CMD23) { 3952a15f981SShawn Guo val &= ~SDHCI_TRNS_AUTO_CMD23; 3962a15f981SShawn Guo val |= ESDHC_MIX_CTRL_AC23EN; 3972a15f981SShawn Guo } 3982a15f981SShawn Guo m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 39969f54698SShawn Guo writel(m, host->ioaddr + ESDHC_MIX_CTRL); 40069f54698SShawn Guo } else { 40169f54698SShawn Guo /* 40269f54698SShawn Guo * Postpone this write, we must do it together with a 40369f54698SShawn Guo * command write that is down below. 40469f54698SShawn Guo */ 405e149860dSRichard Zhu imx_data->scratchpad = val; 40669f54698SShawn Guo } 40795f25efeSWolfram Sang return; 40895f25efeSWolfram Sang case SDHCI_COMMAND: 409361b8482SLucas Stach if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 41058ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 41195a2482aSShawn Guo 412361b8482SLucas Stach if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 413f47c4bbfSShawn Guo (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 414361b8482SLucas Stach imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 415361b8482SLucas Stach 4169d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 41795a2482aSShawn Guo writel(val << 16, 41895a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 41969f54698SShawn Guo else 420e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 42195f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 42295f25efeSWolfram Sang return; 42395f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 42495f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 42595f25efeSWolfram Sang break; 42695f25efeSWolfram Sang } 42795f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 42895f25efeSWolfram Sang } 42995f25efeSWolfram Sang 43095f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 43195f25efeSWolfram Sang { 4329a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 4339a0985b7SWilson Callan struct pltfm_imx_data *imx_data = pltfm_host->priv; 43495f25efeSWolfram Sang u32 new_val; 435af51079eSSascha Hauer u32 mask; 43695f25efeSWolfram Sang 43795f25efeSWolfram Sang switch (reg) { 43895f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 43995f25efeSWolfram Sang /* 44095f25efeSWolfram Sang * FSL put some DMA bits here 44195f25efeSWolfram Sang * If your board has a regulator, code should be here 44295f25efeSWolfram Sang */ 44395f25efeSWolfram Sang return; 44495f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 4456b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 446af51079eSSascha Hauer new_val = val & SDHCI_CTRL_LED; 4477122bbb0SMasanari Iida /* ensure the endianness */ 44895f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 4499a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 4509a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 45195f25efeSWolfram Sang /* DMA mode bits are shifted */ 45295f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 4539a0985b7SWilson Callan } 45495f25efeSWolfram Sang 455af51079eSSascha Hauer /* 456af51079eSSascha Hauer * Do not touch buswidth bits here. This is done in 457af51079eSSascha Hauer * esdhc_pltfm_bus_width. 458f6825748SMartin Fuzzey * Do not touch the D3CD bit either which is used for the 459f6825748SMartin Fuzzey * SDIO interrupt errata workaround. 460af51079eSSascha Hauer */ 461f6825748SMartin Fuzzey mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 462af51079eSSascha Hauer 463af51079eSSascha Hauer esdhc_clrset_le(host, mask, new_val, reg); 46495f25efeSWolfram Sang return; 46595f25efeSWolfram Sang } 46695f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 467913413c3SShawn Guo 468913413c3SShawn Guo /* 469913413c3SShawn Guo * The esdhc has a design violation to SDHC spec which tells 470913413c3SShawn Guo * that software reset should not affect card detection circuit. 471913413c3SShawn Guo * But esdhc clears its SYSCTL register bits [0..2] during the 472913413c3SShawn Guo * software reset. This will stop those clocks that card detection 473913413c3SShawn Guo * circuit relies on. To work around it, we turn the clocks on back 474913413c3SShawn Guo * to keep card detection circuit functional. 475913413c3SShawn Guo */ 47658c8c4fbSShawn Guo if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { 477913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 47858c8c4fbSShawn Guo /* 47958c8c4fbSShawn Guo * The reset on usdhc fails to clear MIX_CTRL register. 48058c8c4fbSShawn Guo * Do it manually here. 48158c8c4fbSShawn Guo */ 4829d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 48358c8c4fbSShawn Guo writel(0, host->ioaddr + ESDHC_MIX_CTRL); 48458c8c4fbSShawn Guo } 48595f25efeSWolfram Sang } 48695f25efeSWolfram Sang 4870ddf03c9SLucas Stach static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 4880ddf03c9SLucas Stach { 4890ddf03c9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 4900ddf03c9SLucas Stach struct pltfm_imx_data *imx_data = pltfm_host->priv; 4910ddf03c9SLucas Stach struct esdhc_platform_data *boarddata = &imx_data->boarddata; 4920ddf03c9SLucas Stach 4930ddf03c9SLucas Stach u32 f_host = clk_get_rate(pltfm_host->clk); 4940ddf03c9SLucas Stach 4950ddf03c9SLucas Stach if (boarddata->f_max && (boarddata->f_max < f_host)) 4960ddf03c9SLucas Stach return boarddata->f_max; 4970ddf03c9SLucas Stach else 4980ddf03c9SLucas Stach return f_host; 4990ddf03c9SLucas Stach } 5000ddf03c9SLucas Stach 50195f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 50295f25efeSWolfram Sang { 50395f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 50495f25efeSWolfram Sang 50595f25efeSWolfram Sang return clk_get_rate(pltfm_host->clk) / 256 / 16; 50695f25efeSWolfram Sang } 50795f25efeSWolfram Sang 5088ba9580aSLucas Stach static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 5098ba9580aSLucas Stach unsigned int clock) 5108ba9580aSLucas Stach { 5118ba9580aSLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 512fed2f6e2SDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 513d31fc00aSDong Aisheng unsigned int host_clock = clk_get_rate(pltfm_host->clk); 514d31fc00aSDong Aisheng int pre_div = 2; 515d31fc00aSDong Aisheng int div = 1; 516fed2f6e2SDong Aisheng u32 temp, val; 5178ba9580aSLucas Stach 518fed2f6e2SDong Aisheng if (clock == 0) { 5199d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 520fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 521fed2f6e2SDong Aisheng writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 522fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 523fed2f6e2SDong Aisheng } 524d31fc00aSDong Aisheng goto out; 525fed2f6e2SDong Aisheng } 526d31fc00aSDong Aisheng 5279d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 5285f7886c5SDong Aisheng pre_div = 1; 5295f7886c5SDong Aisheng 530d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 531d31fc00aSDong Aisheng temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 532d31fc00aSDong Aisheng | ESDHC_CLOCK_MASK); 533d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 534d31fc00aSDong Aisheng 535d31fc00aSDong Aisheng while (host_clock / pre_div / 16 > clock && pre_div < 256) 536d31fc00aSDong Aisheng pre_div *= 2; 537d31fc00aSDong Aisheng 538d31fc00aSDong Aisheng while (host_clock / pre_div / div > clock && div < 16) 539d31fc00aSDong Aisheng div++; 540d31fc00aSDong Aisheng 541e76b8559SDong Aisheng host->mmc->actual_clock = host_clock / pre_div / div; 542d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 543e76b8559SDong Aisheng clock, host->mmc->actual_clock); 544d31fc00aSDong Aisheng 545d31fc00aSDong Aisheng pre_div >>= 1; 546d31fc00aSDong Aisheng div--; 547d31fc00aSDong Aisheng 548d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 549d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 550d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 551d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 552d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 553fed2f6e2SDong Aisheng 5549d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 555fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 556fed2f6e2SDong Aisheng writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 557fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 558fed2f6e2SDong Aisheng } 559fed2f6e2SDong Aisheng 560d31fc00aSDong Aisheng mdelay(1); 561d31fc00aSDong Aisheng out: 562d31fc00aSDong Aisheng host->clock = clock; 5638ba9580aSLucas Stach } 5648ba9580aSLucas Stach 565913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 566913413c3SShawn Guo { 567842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 568842afc02SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 569842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 570913413c3SShawn Guo 571913413c3SShawn Guo switch (boarddata->wp_type) { 572913413c3SShawn Guo case ESDHC_WP_GPIO: 573fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 574913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 575913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 576913413c3SShawn Guo SDHCI_WRITE_PROTECT); 577913413c3SShawn Guo case ESDHC_WP_NONE: 578913413c3SShawn Guo break; 579913413c3SShawn Guo } 580913413c3SShawn Guo 581913413c3SShawn Guo return -ENOSYS; 582913413c3SShawn Guo } 583913413c3SShawn Guo 584af51079eSSascha Hauer static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width) 585af51079eSSascha Hauer { 586af51079eSSascha Hauer u32 ctrl; 587af51079eSSascha Hauer 588af51079eSSascha Hauer switch (width) { 589af51079eSSascha Hauer case MMC_BUS_WIDTH_8: 590af51079eSSascha Hauer ctrl = ESDHC_CTRL_8BITBUS; 591af51079eSSascha Hauer break; 592af51079eSSascha Hauer case MMC_BUS_WIDTH_4: 593af51079eSSascha Hauer ctrl = ESDHC_CTRL_4BITBUS; 594af51079eSSascha Hauer break; 595af51079eSSascha Hauer default: 596af51079eSSascha Hauer ctrl = 0; 597af51079eSSascha Hauer break; 598af51079eSSascha Hauer } 599af51079eSSascha Hauer 600af51079eSSascha Hauer esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 601af51079eSSascha Hauer SDHCI_HOST_CONTROL); 602af51079eSSascha Hauer 603af51079eSSascha Hauer return 0; 604af51079eSSascha Hauer } 605af51079eSSascha Hauer 6060322191eSDong Aisheng static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 6070322191eSDong Aisheng { 6080322191eSDong Aisheng u32 reg; 6090322191eSDong Aisheng 6100322191eSDong Aisheng /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 6110322191eSDong Aisheng mdelay(1); 6120322191eSDong Aisheng 6130322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 6140322191eSDong Aisheng reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 6150322191eSDong Aisheng ESDHC_MIX_CTRL_FBCLK_SEL; 6160322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 6170322191eSDong Aisheng writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 6180322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), 6190322191eSDong Aisheng "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 6200322191eSDong Aisheng val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 6210322191eSDong Aisheng } 6220322191eSDong Aisheng 6230322191eSDong Aisheng static void esdhc_request_done(struct mmc_request *mrq) 6240322191eSDong Aisheng { 6250322191eSDong Aisheng complete(&mrq->completion); 6260322191eSDong Aisheng } 6270322191eSDong Aisheng 6280322191eSDong Aisheng static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode) 6290322191eSDong Aisheng { 6300322191eSDong Aisheng struct mmc_command cmd = {0}; 6310322191eSDong Aisheng struct mmc_request mrq = {0}; 6320322191eSDong Aisheng struct mmc_data data = {0}; 6330322191eSDong Aisheng struct scatterlist sg; 6340322191eSDong Aisheng char tuning_pattern[ESDHC_TUNING_BLOCK_PATTERN_LEN]; 6350322191eSDong Aisheng 6360322191eSDong Aisheng cmd.opcode = opcode; 6370322191eSDong Aisheng cmd.arg = 0; 6380322191eSDong Aisheng cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 6390322191eSDong Aisheng 6400322191eSDong Aisheng data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN; 6410322191eSDong Aisheng data.blocks = 1; 6420322191eSDong Aisheng data.flags = MMC_DATA_READ; 6430322191eSDong Aisheng data.sg = &sg; 6440322191eSDong Aisheng data.sg_len = 1; 6450322191eSDong Aisheng 6460322191eSDong Aisheng sg_init_one(&sg, tuning_pattern, sizeof(tuning_pattern)); 6470322191eSDong Aisheng 6480322191eSDong Aisheng mrq.cmd = &cmd; 6490322191eSDong Aisheng mrq.cmd->mrq = &mrq; 6500322191eSDong Aisheng mrq.data = &data; 6510322191eSDong Aisheng mrq.data->mrq = &mrq; 6520322191eSDong Aisheng mrq.cmd->data = mrq.data; 6530322191eSDong Aisheng 6540322191eSDong Aisheng mrq.done = esdhc_request_done; 6550322191eSDong Aisheng init_completion(&(mrq.completion)); 6560322191eSDong Aisheng 6570322191eSDong Aisheng disable_irq(host->irq); 6580322191eSDong Aisheng spin_lock(&host->lock); 6590322191eSDong Aisheng host->mrq = &mrq; 6600322191eSDong Aisheng 6610322191eSDong Aisheng sdhci_send_command(host, mrq.cmd); 6620322191eSDong Aisheng 6630322191eSDong Aisheng spin_unlock(&host->lock); 6640322191eSDong Aisheng enable_irq(host->irq); 6650322191eSDong Aisheng 6660322191eSDong Aisheng wait_for_completion(&mrq.completion); 6670322191eSDong Aisheng 6680322191eSDong Aisheng if (cmd.error) 6690322191eSDong Aisheng return cmd.error; 6700322191eSDong Aisheng if (data.error) 6710322191eSDong Aisheng return data.error; 6720322191eSDong Aisheng 6730322191eSDong Aisheng return 0; 6740322191eSDong Aisheng } 6750322191eSDong Aisheng 6760322191eSDong Aisheng static void esdhc_post_tuning(struct sdhci_host *host) 6770322191eSDong Aisheng { 6780322191eSDong Aisheng u32 reg; 6790322191eSDong Aisheng 6800322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 6810322191eSDong Aisheng reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 6820322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 6830322191eSDong Aisheng } 6840322191eSDong Aisheng 6850322191eSDong Aisheng static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 6860322191eSDong Aisheng { 6870322191eSDong Aisheng int min, max, avg, ret; 6880322191eSDong Aisheng 6890322191eSDong Aisheng /* find the mininum delay first which can pass tuning */ 6900322191eSDong Aisheng min = ESDHC_TUNE_CTRL_MIN; 6910322191eSDong Aisheng while (min < ESDHC_TUNE_CTRL_MAX) { 6920322191eSDong Aisheng esdhc_prepare_tuning(host, min); 6930322191eSDong Aisheng if (!esdhc_send_tuning_cmd(host, opcode)) 6940322191eSDong Aisheng break; 6950322191eSDong Aisheng min += ESDHC_TUNE_CTRL_STEP; 6960322191eSDong Aisheng } 6970322191eSDong Aisheng 6980322191eSDong Aisheng /* find the maxinum delay which can not pass tuning */ 6990322191eSDong Aisheng max = min + ESDHC_TUNE_CTRL_STEP; 7000322191eSDong Aisheng while (max < ESDHC_TUNE_CTRL_MAX) { 7010322191eSDong Aisheng esdhc_prepare_tuning(host, max); 7020322191eSDong Aisheng if (esdhc_send_tuning_cmd(host, opcode)) { 7030322191eSDong Aisheng max -= ESDHC_TUNE_CTRL_STEP; 7040322191eSDong Aisheng break; 7050322191eSDong Aisheng } 7060322191eSDong Aisheng max += ESDHC_TUNE_CTRL_STEP; 7070322191eSDong Aisheng } 7080322191eSDong Aisheng 7090322191eSDong Aisheng /* use average delay to get the best timing */ 7100322191eSDong Aisheng avg = (min + max) / 2; 7110322191eSDong Aisheng esdhc_prepare_tuning(host, avg); 7120322191eSDong Aisheng ret = esdhc_send_tuning_cmd(host, opcode); 7130322191eSDong Aisheng esdhc_post_tuning(host); 7140322191eSDong Aisheng 7150322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", 7160322191eSDong Aisheng ret ? "failed" : "passed", avg, ret); 7170322191eSDong Aisheng 7180322191eSDong Aisheng return ret; 7190322191eSDong Aisheng } 7200322191eSDong Aisheng 721ad93220dSDong Aisheng static int esdhc_change_pinstate(struct sdhci_host *host, 722ad93220dSDong Aisheng unsigned int uhs) 723ad93220dSDong Aisheng { 724ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 725ad93220dSDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 726ad93220dSDong Aisheng struct pinctrl_state *pinctrl; 727ad93220dSDong Aisheng 728ad93220dSDong Aisheng dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 729ad93220dSDong Aisheng 730ad93220dSDong Aisheng if (IS_ERR(imx_data->pinctrl) || 731ad93220dSDong Aisheng IS_ERR(imx_data->pins_default) || 732ad93220dSDong Aisheng IS_ERR(imx_data->pins_100mhz) || 733ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) 734ad93220dSDong Aisheng return -EINVAL; 735ad93220dSDong Aisheng 736ad93220dSDong Aisheng switch (uhs) { 737ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 738ad93220dSDong Aisheng pinctrl = imx_data->pins_100mhz; 739ad93220dSDong Aisheng break; 740ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 741ad93220dSDong Aisheng pinctrl = imx_data->pins_200mhz; 742ad93220dSDong Aisheng break; 743ad93220dSDong Aisheng default: 744ad93220dSDong Aisheng /* back to default state for other legacy timing */ 745ad93220dSDong Aisheng pinctrl = imx_data->pins_default; 746ad93220dSDong Aisheng } 747ad93220dSDong Aisheng 748ad93220dSDong Aisheng return pinctrl_select_state(imx_data->pinctrl, pinctrl); 749ad93220dSDong Aisheng } 750ad93220dSDong Aisheng 751ad93220dSDong Aisheng static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) 752ad93220dSDong Aisheng { 753ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 754ad93220dSDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 755ad93220dSDong Aisheng 756ad93220dSDong Aisheng switch (uhs) { 757ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR12: 758ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR12; 759ad93220dSDong Aisheng break; 760ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR25: 761ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR25; 762ad93220dSDong Aisheng break; 763ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 764ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR50; 765ad93220dSDong Aisheng break; 766ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 767ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR104; 768ad93220dSDong Aisheng break; 769ad93220dSDong Aisheng case MMC_TIMING_UHS_DDR50: 770ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_DDR50; 771ad93220dSDong Aisheng break; 772ad93220dSDong Aisheng } 773ad93220dSDong Aisheng 774ad93220dSDong Aisheng return esdhc_change_pinstate(host, uhs); 775ad93220dSDong Aisheng } 776ad93220dSDong Aisheng 777c915568dSLars-Peter Clausen static const struct sdhci_ops sdhci_esdhc_ops = { 778e149860dSRichard Zhu .read_l = esdhc_readl_le, 7790c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 780e149860dSRichard Zhu .write_l = esdhc_writel_le, 7810c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 7820c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 7838ba9580aSLucas Stach .set_clock = esdhc_pltfm_set_clock, 7840ddf03c9SLucas Stach .get_max_clock = esdhc_pltfm_get_max_clock, 7850c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 786913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 787af51079eSSascha Hauer .platform_bus_width = esdhc_pltfm_bus_width, 788ad93220dSDong Aisheng .set_uhs_signaling = esdhc_set_uhs_signaling, 7890322191eSDong Aisheng .platform_execute_tuning = esdhc_executing_tuning, 7900c6d49ceSWolfram Sang }; 7910c6d49ceSWolfram Sang 7921db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 79397e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 79497e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 79597e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 79685d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 79785d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 79885d6509dSShawn Guo }; 79985d6509dSShawn Guo 800abfafc2dSShawn Guo #ifdef CONFIG_OF 801c3be1efdSBill Pemberton static int 802abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 803abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 804abfafc2dSShawn Guo { 805abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 806abfafc2dSShawn Guo 807abfafc2dSShawn Guo if (!np) 808abfafc2dSShawn Guo return -ENODEV; 809abfafc2dSShawn Guo 8107f217794SArnd Bergmann if (of_get_property(np, "non-removable", NULL)) 811abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_PERMANENT; 812abfafc2dSShawn Guo 813abfafc2dSShawn Guo if (of_get_property(np, "fsl,cd-controller", NULL)) 814abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_CONTROLLER; 815abfafc2dSShawn Guo 816abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 817abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 818abfafc2dSShawn Guo 819abfafc2dSShawn Guo boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 820abfafc2dSShawn Guo if (gpio_is_valid(boarddata->cd_gpio)) 821abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_GPIO; 822abfafc2dSShawn Guo 823abfafc2dSShawn Guo boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 824abfafc2dSShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 825abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 826abfafc2dSShawn Guo 827af51079eSSascha Hauer of_property_read_u32(np, "bus-width", &boarddata->max_bus_width); 828af51079eSSascha Hauer 8290ddf03c9SLucas Stach of_property_read_u32(np, "max-frequency", &boarddata->f_max); 8300ddf03c9SLucas Stach 831ad93220dSDong Aisheng if (of_find_property(np, "no-1-8-v", NULL)) 832ad93220dSDong Aisheng boarddata->support_vsel = false; 833ad93220dSDong Aisheng else 834ad93220dSDong Aisheng boarddata->support_vsel = true; 835ad93220dSDong Aisheng 836abfafc2dSShawn Guo return 0; 837abfafc2dSShawn Guo } 838abfafc2dSShawn Guo #else 839abfafc2dSShawn Guo static inline int 840abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 841abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 842abfafc2dSShawn Guo { 843abfafc2dSShawn Guo return -ENODEV; 844abfafc2dSShawn Guo } 845abfafc2dSShawn Guo #endif 846abfafc2dSShawn Guo 847c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 84895f25efeSWolfram Sang { 849abfafc2dSShawn Guo const struct of_device_id *of_id = 850abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 85185d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 85285d6509dSShawn Guo struct sdhci_host *host; 85385d6509dSShawn Guo struct esdhc_platform_data *boarddata; 8540c6d49ceSWolfram Sang int err; 855e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 85695f25efeSWolfram Sang 8570e748234SChristian Daudt host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0); 85885d6509dSShawn Guo if (IS_ERR(host)) 85985d6509dSShawn Guo return PTR_ERR(host); 86085d6509dSShawn Guo 86185d6509dSShawn Guo pltfm_host = sdhci_priv(host); 86285d6509dSShawn Guo 863e3af31c6SShawn Guo imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); 864abfafc2dSShawn Guo if (!imx_data) { 865abfafc2dSShawn Guo err = -ENOMEM; 866e3af31c6SShawn Guo goto free_sdhci; 867abfafc2dSShawn Guo } 86857ed3314SShawn Guo 869f47c4bbfSShawn Guo imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 8703770ee8fSShawn Guo pdev->id_entry->driver_data; 87185d6509dSShawn Guo pltfm_host->priv = imx_data; 87285d6509dSShawn Guo 87352dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 87452dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 87552dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 876e3af31c6SShawn Guo goto free_sdhci; 87795f25efeSWolfram Sang } 87852dac615SSascha Hauer 87952dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 88052dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 88152dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 882e3af31c6SShawn Guo goto free_sdhci; 88352dac615SSascha Hauer } 88452dac615SSascha Hauer 88552dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 88652dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 88752dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 888e3af31c6SShawn Guo goto free_sdhci; 88952dac615SSascha Hauer } 89052dac615SSascha Hauer 89152dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 89252dac615SSascha Hauer 89352dac615SSascha Hauer clk_prepare_enable(imx_data->clk_per); 89452dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ipg); 89552dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ahb); 89695f25efeSWolfram Sang 897ad93220dSDong Aisheng imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 898e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 899e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 900e3af31c6SShawn Guo goto disable_clk; 901e62d8b8fSDong Aisheng } 902e62d8b8fSDong Aisheng 903ad93220dSDong Aisheng imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, 904ad93220dSDong Aisheng PINCTRL_STATE_DEFAULT); 905ad93220dSDong Aisheng if (IS_ERR(imx_data->pins_default)) { 906ad93220dSDong Aisheng err = PTR_ERR(imx_data->pins_default); 907ad93220dSDong Aisheng dev_err(mmc_dev(host->mmc), "could not get default state\n"); 908ad93220dSDong Aisheng goto disable_clk; 909ad93220dSDong Aisheng } 910ad93220dSDong Aisheng 91137865fe9SEric Bénard host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 91237865fe9SEric Bénard 913f47c4bbfSShawn Guo if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) 9140c6d49ceSWolfram Sang /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ 91597e4ba6aSRichard Zhu host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK 91697e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA; 9170c6d49ceSWolfram Sang 918f750ba9bSShawn Guo /* 919f750ba9bSShawn Guo * The imx6q ROM code will change the default watermark level setting 920f750ba9bSShawn Guo * to something insane. Change it back here. 921f750ba9bSShawn Guo */ 9229d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 92360bf6396SShawn Guo writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); 924f750ba9bSShawn Guo 925abfafc2dSShawn Guo boarddata = &imx_data->boarddata; 926abfafc2dSShawn Guo if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) { 927842afc02SShawn Guo if (!host->mmc->parent->platform_data) { 928913413c3SShawn Guo dev_err(mmc_dev(host->mmc), "no board data!\n"); 929913413c3SShawn Guo err = -EINVAL; 930e3af31c6SShawn Guo goto disable_clk; 931913413c3SShawn Guo } 932842afc02SShawn Guo imx_data->boarddata = *((struct esdhc_platform_data *) 933842afc02SShawn Guo host->mmc->parent->platform_data); 934abfafc2dSShawn Guo } 935913413c3SShawn Guo 936913413c3SShawn Guo /* write_protect */ 937913413c3SShawn Guo if (boarddata->wp_type == ESDHC_WP_GPIO) { 938fbe5fdd1SShawn Guo err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); 9390c6d49ceSWolfram Sang if (err) { 940fbe5fdd1SShawn Guo dev_err(mmc_dev(host->mmc), 941fbe5fdd1SShawn Guo "failed to request write-protect gpio!\n"); 942fbe5fdd1SShawn Guo goto disable_clk; 943913413c3SShawn Guo } 944fbe5fdd1SShawn Guo host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 9450c6d49ceSWolfram Sang } 9467e29c306SWolfram Sang 947913413c3SShawn Guo /* card_detect */ 948913413c3SShawn Guo switch (boarddata->cd_type) { 949913413c3SShawn Guo case ESDHC_CD_GPIO: 950214fc309SLaurent Pinchart err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); 9517e29c306SWolfram Sang if (err) { 952913413c3SShawn Guo dev_err(mmc_dev(host->mmc), 953fbe5fdd1SShawn Guo "failed to request card-detect gpio!\n"); 954e3af31c6SShawn Guo goto disable_clk; 9557e29c306SWolfram Sang } 956913413c3SShawn Guo /* fall through */ 9577e29c306SWolfram Sang 958913413c3SShawn Guo case ESDHC_CD_CONTROLLER: 959913413c3SShawn Guo /* we have a working card_detect back */ 9607e29c306SWolfram Sang host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 961913413c3SShawn Guo break; 962913413c3SShawn Guo 963913413c3SShawn Guo case ESDHC_CD_PERMANENT: 964913413c3SShawn Guo host->mmc->caps = MMC_CAP_NONREMOVABLE; 965913413c3SShawn Guo break; 966913413c3SShawn Guo 967913413c3SShawn Guo case ESDHC_CD_NONE: 968913413c3SShawn Guo break; 9697e29c306SWolfram Sang } 9707e29c306SWolfram Sang 971af51079eSSascha Hauer switch (boarddata->max_bus_width) { 972af51079eSSascha Hauer case 8: 973af51079eSSascha Hauer host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 974af51079eSSascha Hauer break; 975af51079eSSascha Hauer case 4: 976af51079eSSascha Hauer host->mmc->caps |= MMC_CAP_4_BIT_DATA; 977af51079eSSascha Hauer break; 978af51079eSSascha Hauer case 1: 979af51079eSSascha Hauer default: 980af51079eSSascha Hauer host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 981af51079eSSascha Hauer break; 982af51079eSSascha Hauer } 983af51079eSSascha Hauer 984ad93220dSDong Aisheng /* sdr50 and sdr104 needs work on 1.8v signal voltage */ 9859d61c009SShawn Guo if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data)) { 986ad93220dSDong Aisheng imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 987ad93220dSDong Aisheng ESDHC_PINCTRL_STATE_100MHZ); 988ad93220dSDong Aisheng imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 989ad93220dSDong Aisheng ESDHC_PINCTRL_STATE_200MHZ); 990ad93220dSDong Aisheng if (IS_ERR(imx_data->pins_100mhz) || 991ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) { 992ad93220dSDong Aisheng dev_warn(mmc_dev(host->mmc), 993ad93220dSDong Aisheng "could not get ultra high speed state, work on normal mode\n"); 994ad93220dSDong Aisheng /* fall back to not support uhs by specify no 1.8v quirk */ 995ad93220dSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 996ad93220dSDong Aisheng } 997ad93220dSDong Aisheng } else { 998ad93220dSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 999ad93220dSDong Aisheng } 1000ad93220dSDong Aisheng 100185d6509dSShawn Guo err = sdhci_add_host(host); 100285d6509dSShawn Guo if (err) 1003e3af31c6SShawn Guo goto disable_clk; 100485d6509dSShawn Guo 10057e29c306SWolfram Sang return 0; 10067e29c306SWolfram Sang 1007e3af31c6SShawn Guo disable_clk: 100852dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 100952dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 101052dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 1011e3af31c6SShawn Guo free_sdhci: 101285d6509dSShawn Guo sdhci_pltfm_free(pdev); 101385d6509dSShawn Guo return err; 101495f25efeSWolfram Sang } 101595f25efeSWolfram Sang 10166e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 101795f25efeSWolfram Sang { 101885d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 101995f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1020e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 102185d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 102285d6509dSShawn Guo 102385d6509dSShawn Guo sdhci_remove_host(host, dead); 10240c6d49ceSWolfram Sang 102552dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 102652dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 102752dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 102852dac615SSascha Hauer 102985d6509dSShawn Guo sdhci_pltfm_free(pdev); 103085d6509dSShawn Guo 103185d6509dSShawn Guo return 0; 103295f25efeSWolfram Sang } 103395f25efeSWolfram Sang 103485d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 103585d6509dSShawn Guo .driver = { 103685d6509dSShawn Guo .name = "sdhci-esdhc-imx", 103785d6509dSShawn Guo .owner = THIS_MODULE, 1038abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 103929495aa0SManuel Lauss .pm = SDHCI_PLTFM_PMOPS, 104085d6509dSShawn Guo }, 104157ed3314SShawn Guo .id_table = imx_esdhc_devtype, 104285d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 10430433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 104495f25efeSWolfram Sang }; 104585d6509dSShawn Guo 1046d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 104785d6509dSShawn Guo 104885d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 104985d6509dSShawn Guo MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); 105085d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1051