195f25efeSWolfram Sang /* 295f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 395f25efeSWolfram Sang * 495f25efeSWolfram Sang * derived from the OF-version. 595f25efeSWolfram Sang * 695f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 795f25efeSWolfram Sang * Author: Wolfram Sang <w.sang@pengutronix.de> 895f25efeSWolfram Sang * 995f25efeSWolfram Sang * This program is free software; you can redistribute it and/or modify 1095f25efeSWolfram Sang * it under the terms of the GNU General Public License as published by 1195f25efeSWolfram Sang * the Free Software Foundation; either version 2 of the License. 1295f25efeSWolfram Sang */ 1395f25efeSWolfram Sang 1495f25efeSWolfram Sang #include <linux/io.h> 1595f25efeSWolfram Sang #include <linux/delay.h> 1695f25efeSWolfram Sang #include <linux/err.h> 1795f25efeSWolfram Sang #include <linux/clk.h> 180c6d49ceSWolfram Sang #include <linux/gpio.h> 1966506f76SShawn Guo #include <linux/module.h> 20e149860dSRichard Zhu #include <linux/slab.h> 2195f25efeSWolfram Sang #include <linux/mmc/host.h> 2258ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2358ac8177SRichard Zhu #include <linux/mmc/sdio.h> 24fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 25abfafc2dSShawn Guo #include <linux/of.h> 26abfafc2dSShawn Guo #include <linux/of_device.h> 27abfafc2dSShawn Guo #include <linux/of_gpio.h> 28e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2982906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 3095f25efeSWolfram Sang #include "sdhci-pltfm.h" 3195f25efeSWolfram Sang #include "sdhci-esdhc.h" 3295f25efeSWolfram Sang 3360bf6396SShawn Guo #define ESDHC_CTRL_D3CD 0x08 3458ac8177SRichard Zhu /* VENDOR SPEC register */ 3560bf6396SShawn Guo #define ESDHC_VENDOR_SPEC 0xc0 3660bf6396SShawn Guo #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 370322191eSDong Aisheng #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 38fed2f6e2SDong Aisheng #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 3960bf6396SShawn Guo #define ESDHC_WTMK_LVL 0x44 4060bf6396SShawn Guo #define ESDHC_MIX_CTRL 0x48 412a15f981SShawn Guo #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 420322191eSDong Aisheng #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 430322191eSDong Aisheng #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 440322191eSDong Aisheng #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 452a15f981SShawn Guo /* Bits 3 and 6 are not SDHCI standard definitions */ 462a15f981SShawn Guo #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 4758ac8177SRichard Zhu 480322191eSDong Aisheng /* tune control register */ 490322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STATUS 0x68 500322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STEP 1 510322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MIN 0 520322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 530322191eSDong Aisheng 540322191eSDong Aisheng #define ESDHC_TUNING_BLOCK_PATTERN_LEN 64 550322191eSDong Aisheng 56ad93220dSDong Aisheng /* pinctrl state */ 57ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 58ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 59ad93220dSDong Aisheng 6058ac8177SRichard Zhu /* 61af51079eSSascha Hauer * Our interpretation of the SDHCI_HOST_CONTROL register 62af51079eSSascha Hauer */ 63af51079eSSascha Hauer #define ESDHC_CTRL_4BITBUS (0x1 << 1) 64af51079eSSascha Hauer #define ESDHC_CTRL_8BITBUS (0x2 << 1) 65af51079eSSascha Hauer #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 66af51079eSSascha Hauer 67af51079eSSascha Hauer /* 6897e4ba6aSRichard Zhu * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: 6997e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 7097e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 7197e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 7297e4ba6aSRichard Zhu */ 7360bf6396SShawn Guo #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 7497e4ba6aSRichard Zhu 7597e4ba6aSRichard Zhu /* 7658ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 7758ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 7858ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 7958ac8177SRichard Zhu * be generated. 8058ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 8158ac8177SRichard Zhu * operations automatically as required at the end of the 8258ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 8358ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 8458ac8177SRichard Zhu * exeception. Bit1 of Vendor Spec registor is used to fix it. 8558ac8177SRichard Zhu */ 8658ac8177SRichard Zhu #define ESDHC_FLAG_MULTIBLK_NO_INT (1 << 1) 87e149860dSRichard Zhu 8857ed3314SShawn Guo enum imx_esdhc_type { 8957ed3314SShawn Guo IMX25_ESDHC, 9057ed3314SShawn Guo IMX35_ESDHC, 9157ed3314SShawn Guo IMX51_ESDHC, 9257ed3314SShawn Guo IMX53_ESDHC, 9395a2482aSShawn Guo IMX6Q_USDHC, 9457ed3314SShawn Guo }; 9557ed3314SShawn Guo 96e149860dSRichard Zhu struct pltfm_imx_data { 97e149860dSRichard Zhu int flags; 98e149860dSRichard Zhu u32 scratchpad; 9957ed3314SShawn Guo enum imx_esdhc_type devtype; 100e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 101ad93220dSDong Aisheng struct pinctrl_state *pins_default; 102ad93220dSDong Aisheng struct pinctrl_state *pins_100mhz; 103ad93220dSDong Aisheng struct pinctrl_state *pins_200mhz; 104842afc02SShawn Guo struct esdhc_platform_data boarddata; 10552dac615SSascha Hauer struct clk *clk_ipg; 10652dac615SSascha Hauer struct clk *clk_ahb; 10752dac615SSascha Hauer struct clk *clk_per; 108361b8482SLucas Stach enum { 109361b8482SLucas Stach NO_CMD_PENDING, /* no multiblock command pending*/ 110361b8482SLucas Stach MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 111361b8482SLucas Stach WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 112361b8482SLucas Stach } multiblock_status; 1130322191eSDong Aisheng u32 uhs_mode; 114e149860dSRichard Zhu }; 115e149860dSRichard Zhu 11657ed3314SShawn Guo static struct platform_device_id imx_esdhc_devtype[] = { 11757ed3314SShawn Guo { 11857ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 11957ed3314SShawn Guo .driver_data = IMX25_ESDHC, 12057ed3314SShawn Guo }, { 12157ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 12257ed3314SShawn Guo .driver_data = IMX35_ESDHC, 12357ed3314SShawn Guo }, { 12457ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 12557ed3314SShawn Guo .driver_data = IMX51_ESDHC, 12657ed3314SShawn Guo }, { 12757ed3314SShawn Guo .name = "sdhci-esdhc-imx53", 12857ed3314SShawn Guo .driver_data = IMX53_ESDHC, 12957ed3314SShawn Guo }, { 13095a2482aSShawn Guo .name = "sdhci-usdhc-imx6q", 13195a2482aSShawn Guo .driver_data = IMX6Q_USDHC, 13295a2482aSShawn Guo }, { 13357ed3314SShawn Guo /* sentinel */ 13457ed3314SShawn Guo } 13557ed3314SShawn Guo }; 13657ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 13757ed3314SShawn Guo 138abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 139abfafc2dSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &imx_esdhc_devtype[IMX25_ESDHC], }, 140abfafc2dSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], }, 141abfafc2dSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], }, 142abfafc2dSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], }, 14395a2482aSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &imx_esdhc_devtype[IMX6Q_USDHC], }, 144abfafc2dSShawn Guo { /* sentinel */ } 145abfafc2dSShawn Guo }; 146abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 147abfafc2dSShawn Guo 14857ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 14957ed3314SShawn Guo { 15057ed3314SShawn Guo return data->devtype == IMX25_ESDHC; 15157ed3314SShawn Guo } 15257ed3314SShawn Guo 15357ed3314SShawn Guo static inline int is_imx35_esdhc(struct pltfm_imx_data *data) 15457ed3314SShawn Guo { 15557ed3314SShawn Guo return data->devtype == IMX35_ESDHC; 15657ed3314SShawn Guo } 15757ed3314SShawn Guo 15857ed3314SShawn Guo static inline int is_imx51_esdhc(struct pltfm_imx_data *data) 15957ed3314SShawn Guo { 16057ed3314SShawn Guo return data->devtype == IMX51_ESDHC; 16157ed3314SShawn Guo } 16257ed3314SShawn Guo 16357ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 16457ed3314SShawn Guo { 16557ed3314SShawn Guo return data->devtype == IMX53_ESDHC; 16657ed3314SShawn Guo } 16757ed3314SShawn Guo 16895a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 16995a2482aSShawn Guo { 17095a2482aSShawn Guo return data->devtype == IMX6Q_USDHC; 17195a2482aSShawn Guo } 17295a2482aSShawn Guo 17395f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 17495f25efeSWolfram Sang { 17595f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 17695f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 17795f25efeSWolfram Sang 17895f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 17995f25efeSWolfram Sang } 18095f25efeSWolfram Sang 1817e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 1827e29c306SWolfram Sang { 183361b8482SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 184361b8482SLucas Stach struct pltfm_imx_data *imx_data = pltfm_host->priv; 185913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 186913413c3SShawn Guo 1870322191eSDong Aisheng if (unlikely(reg == SDHCI_PRESENT_STATE)) { 1880322191eSDong Aisheng u32 fsl_prss = val; 1890322191eSDong Aisheng /* save the least 20 bits */ 1900322191eSDong Aisheng val = fsl_prss & 0x000FFFFF; 1910322191eSDong Aisheng /* move dat[0-3] bits */ 1920322191eSDong Aisheng val |= (fsl_prss & 0x0F000000) >> 4; 1930322191eSDong Aisheng /* move cmd line bit */ 1940322191eSDong Aisheng val |= (fsl_prss & 0x00800000) << 1; 1950322191eSDong Aisheng } 1960322191eSDong Aisheng 19797e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 19897e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 19997e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 20097e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 20197e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 20297e4ba6aSRichard Zhu * uirk on MX25/35 platforms. 20397e4ba6aSRichard Zhu */ 20497e4ba6aSRichard Zhu 20597e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 20697e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 20797e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 20897e4ba6aSRichard Zhu } 20997e4ba6aSRichard Zhu } 21097e4ba6aSRichard Zhu 2110322191eSDong Aisheng if (unlikely(reg == SDHCI_CAPABILITIES_1) && is_imx6q_usdhc(imx_data)) 2120322191eSDong Aisheng val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 2130322191eSDong Aisheng | SDHCI_SUPPORT_SDR50; 2140322191eSDong Aisheng 2150322191eSDong Aisheng if (unlikely(reg == SDHCI_MAX_CURRENT) && is_imx6q_usdhc(imx_data)) { 2160322191eSDong Aisheng val = 0; 2170322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 2180322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 2190322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 2200322191eSDong Aisheng } 2210322191eSDong Aisheng 22297e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 22360bf6396SShawn Guo if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 22460bf6396SShawn Guo val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 22597e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 22697e4ba6aSRichard Zhu } 227361b8482SLucas Stach 228361b8482SLucas Stach /* 229361b8482SLucas Stach * mask off the interrupt we get in response to the manually 230361b8482SLucas Stach * sent CMD12 231361b8482SLucas Stach */ 232361b8482SLucas Stach if ((imx_data->multiblock_status == WAIT_FOR_INT) && 233361b8482SLucas Stach ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 234361b8482SLucas Stach val &= ~SDHCI_INT_RESPONSE; 235361b8482SLucas Stach writel(SDHCI_INT_RESPONSE, host->ioaddr + 236361b8482SLucas Stach SDHCI_INT_STATUS); 237361b8482SLucas Stach imx_data->multiblock_status = NO_CMD_PENDING; 238361b8482SLucas Stach } 23997e4ba6aSRichard Zhu } 24097e4ba6aSRichard Zhu 2417e29c306SWolfram Sang return val; 2427e29c306SWolfram Sang } 2437e29c306SWolfram Sang 2447e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 2457e29c306SWolfram Sang { 246e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 247e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 2480d58864bSTony Lin u32 data; 249e149860dSRichard Zhu 2500d58864bSTony Lin if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 2510d58864bSTony Lin if (val & SDHCI_INT_CARD_INT) { 2520d58864bSTony Lin /* 2530d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 2540d58864bSTony Lin * card interrupt. This is a eSDHC controller problem 2550d58864bSTony Lin * so we need to apply the following workaround: clear 2560d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 2570d58864bSTony Lin * interrupt. In case a card interrupt was lost, 2580d58864bSTony Lin * re-sample it by the following steps. 2590d58864bSTony Lin */ 2600d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 26160bf6396SShawn Guo data &= ~ESDHC_CTRL_D3CD; 2620d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 26360bf6396SShawn Guo data |= ESDHC_CTRL_D3CD; 2640d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 2650d58864bSTony Lin } 2660d58864bSTony Lin } 2670d58864bSTony Lin 26858ac8177SRichard Zhu if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 26958ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 27058ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 27158ac8177SRichard Zhu u32 v; 27260bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 27360bf6396SShawn Guo v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 27460bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 275361b8482SLucas Stach 276361b8482SLucas Stach if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 277361b8482SLucas Stach { 278361b8482SLucas Stach /* send a manual CMD12 with RESPTYP=none */ 279361b8482SLucas Stach data = MMC_STOP_TRANSMISSION << 24 | 280361b8482SLucas Stach SDHCI_CMD_ABORTCMD << 16; 281361b8482SLucas Stach writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 282361b8482SLucas Stach imx_data->multiblock_status = WAIT_FOR_INT; 283361b8482SLucas Stach } 28458ac8177SRichard Zhu } 28558ac8177SRichard Zhu 28697e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 28797e4ba6aSRichard Zhu if (val & SDHCI_INT_ADMA_ERROR) { 28897e4ba6aSRichard Zhu val &= ~SDHCI_INT_ADMA_ERROR; 28960bf6396SShawn Guo val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 29097e4ba6aSRichard Zhu } 29197e4ba6aSRichard Zhu } 29297e4ba6aSRichard Zhu 2937e29c306SWolfram Sang writel(val, host->ioaddr + reg); 2947e29c306SWolfram Sang } 2957e29c306SWolfram Sang 29695f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 29795f25efeSWolfram Sang { 298ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 299ef4d0888SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 3000322191eSDong Aisheng u16 ret = 0; 3010322191eSDong Aisheng u32 val; 302ef4d0888SShawn Guo 30395a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 304ef4d0888SShawn Guo reg ^= 2; 305ef4d0888SShawn Guo if (is_imx6q_usdhc(imx_data)) { 30695a2482aSShawn Guo /* 307ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 308ef4d0888SShawn Guo * Correct it here. 30995a2482aSShawn Guo */ 310ef4d0888SShawn Guo return SDHCI_SPEC_300; 311ef4d0888SShawn Guo } 31295a2482aSShawn Guo } 31395f25efeSWolfram Sang 3140322191eSDong Aisheng if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 3150322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 3160322191eSDong Aisheng if (val & ESDHC_VENDOR_SPEC_VSELECT) 3170322191eSDong Aisheng ret |= SDHCI_CTRL_VDD_180; 3180322191eSDong Aisheng 3190322191eSDong Aisheng if (is_imx6q_usdhc(imx_data)) { 3200322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_MIX_CTRL); 3210322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_EXE_TUNE) 3220322191eSDong Aisheng ret |= SDHCI_CTRL_EXEC_TUNING; 3230322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 3240322191eSDong Aisheng ret |= SDHCI_CTRL_TUNED_CLK; 3250322191eSDong Aisheng } 3260322191eSDong Aisheng 3270322191eSDong Aisheng ret |= (imx_data->uhs_mode & SDHCI_CTRL_UHS_MASK); 3280322191eSDong Aisheng ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 3290322191eSDong Aisheng 3300322191eSDong Aisheng return ret; 3310322191eSDong Aisheng } 3320322191eSDong Aisheng 33395f25efeSWolfram Sang return readw(host->ioaddr + reg); 33495f25efeSWolfram Sang } 33595f25efeSWolfram Sang 33695f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 33795f25efeSWolfram Sang { 33895f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 339e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 3400322191eSDong Aisheng u32 new_val = 0; 34195f25efeSWolfram Sang 34295f25efeSWolfram Sang switch (reg) { 3430322191eSDong Aisheng case SDHCI_CLOCK_CONTROL: 3440322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 3450322191eSDong Aisheng if (val & SDHCI_CLOCK_CARD_EN) 3460322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 3470322191eSDong Aisheng else 3480322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 3490322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 3500322191eSDong Aisheng return; 3510322191eSDong Aisheng case SDHCI_HOST_CONTROL2: 3520322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 3530322191eSDong Aisheng if (val & SDHCI_CTRL_VDD_180) 3540322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_VSELECT; 3550322191eSDong Aisheng else 3560322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 3570322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 3580322191eSDong Aisheng imx_data->uhs_mode = val & SDHCI_CTRL_UHS_MASK; 3590322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 3600322191eSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) 3610322191eSDong Aisheng new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 3620322191eSDong Aisheng else 3630322191eSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 3640322191eSDong Aisheng writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 3650322191eSDong Aisheng return; 36695f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 36758ac8177SRichard Zhu if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 36858ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 36958ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 37058ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 37158ac8177SRichard Zhu u32 v; 37260bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 37360bf6396SShawn Guo v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 37460bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 37558ac8177SRichard Zhu } 37669f54698SShawn Guo 37769f54698SShawn Guo if (is_imx6q_usdhc(imx_data)) { 37869f54698SShawn Guo u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 3792a15f981SShawn Guo /* Swap AC23 bit */ 3802a15f981SShawn Guo if (val & SDHCI_TRNS_AUTO_CMD23) { 3812a15f981SShawn Guo val &= ~SDHCI_TRNS_AUTO_CMD23; 3822a15f981SShawn Guo val |= ESDHC_MIX_CTRL_AC23EN; 3832a15f981SShawn Guo } 3842a15f981SShawn Guo m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 38569f54698SShawn Guo writel(m, host->ioaddr + ESDHC_MIX_CTRL); 38669f54698SShawn Guo } else { 38769f54698SShawn Guo /* 38869f54698SShawn Guo * Postpone this write, we must do it together with a 38969f54698SShawn Guo * command write that is down below. 39069f54698SShawn Guo */ 391e149860dSRichard Zhu imx_data->scratchpad = val; 39269f54698SShawn Guo } 39395f25efeSWolfram Sang return; 39495f25efeSWolfram Sang case SDHCI_COMMAND: 395361b8482SLucas Stach if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 39658ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 39795a2482aSShawn Guo 398361b8482SLucas Stach if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 399361b8482SLucas Stach (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 400361b8482SLucas Stach imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 401361b8482SLucas Stach 40269f54698SShawn Guo if (is_imx6q_usdhc(imx_data)) 40395a2482aSShawn Guo writel(val << 16, 40495a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 40569f54698SShawn Guo else 406e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 40795f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 40895f25efeSWolfram Sang return; 40995f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 41095f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 41195f25efeSWolfram Sang break; 41295f25efeSWolfram Sang } 41395f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 41495f25efeSWolfram Sang } 41595f25efeSWolfram Sang 41695f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 41795f25efeSWolfram Sang { 4189a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 4199a0985b7SWilson Callan struct pltfm_imx_data *imx_data = pltfm_host->priv; 42095f25efeSWolfram Sang u32 new_val; 421af51079eSSascha Hauer u32 mask; 42295f25efeSWolfram Sang 42395f25efeSWolfram Sang switch (reg) { 42495f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 42595f25efeSWolfram Sang /* 42695f25efeSWolfram Sang * FSL put some DMA bits here 42795f25efeSWolfram Sang * If your board has a regulator, code should be here 42895f25efeSWolfram Sang */ 42995f25efeSWolfram Sang return; 43095f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 4316b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 432af51079eSSascha Hauer new_val = val & SDHCI_CTRL_LED; 4337122bbb0SMasanari Iida /* ensure the endianness */ 43495f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 4359a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 4369a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 43795f25efeSWolfram Sang /* DMA mode bits are shifted */ 43895f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 4399a0985b7SWilson Callan } 44095f25efeSWolfram Sang 441af51079eSSascha Hauer /* 442af51079eSSascha Hauer * Do not touch buswidth bits here. This is done in 443af51079eSSascha Hauer * esdhc_pltfm_bus_width. 444f6825748SMartin Fuzzey * Do not touch the D3CD bit either which is used for the 445f6825748SMartin Fuzzey * SDIO interrupt errata workaround. 446af51079eSSascha Hauer */ 447f6825748SMartin Fuzzey mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 448af51079eSSascha Hauer 449af51079eSSascha Hauer esdhc_clrset_le(host, mask, new_val, reg); 45095f25efeSWolfram Sang return; 45195f25efeSWolfram Sang } 45295f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 453913413c3SShawn Guo 454913413c3SShawn Guo /* 455913413c3SShawn Guo * The esdhc has a design violation to SDHC spec which tells 456913413c3SShawn Guo * that software reset should not affect card detection circuit. 457913413c3SShawn Guo * But esdhc clears its SYSCTL register bits [0..2] during the 458913413c3SShawn Guo * software reset. This will stop those clocks that card detection 459913413c3SShawn Guo * circuit relies on. To work around it, we turn the clocks on back 460913413c3SShawn Guo * to keep card detection circuit functional. 461913413c3SShawn Guo */ 46258c8c4fbSShawn Guo if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { 463913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 46458c8c4fbSShawn Guo /* 46558c8c4fbSShawn Guo * The reset on usdhc fails to clear MIX_CTRL register. 46658c8c4fbSShawn Guo * Do it manually here. 46758c8c4fbSShawn Guo */ 46858c8c4fbSShawn Guo if (is_imx6q_usdhc(imx_data)) 46958c8c4fbSShawn Guo writel(0, host->ioaddr + ESDHC_MIX_CTRL); 47058c8c4fbSShawn Guo } 47195f25efeSWolfram Sang } 47295f25efeSWolfram Sang 4730ddf03c9SLucas Stach static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 4740ddf03c9SLucas Stach { 4750ddf03c9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 4760ddf03c9SLucas Stach struct pltfm_imx_data *imx_data = pltfm_host->priv; 4770ddf03c9SLucas Stach struct esdhc_platform_data *boarddata = &imx_data->boarddata; 4780ddf03c9SLucas Stach 4790ddf03c9SLucas Stach u32 f_host = clk_get_rate(pltfm_host->clk); 4800ddf03c9SLucas Stach 4810ddf03c9SLucas Stach if (boarddata->f_max && (boarddata->f_max < f_host)) 4820ddf03c9SLucas Stach return boarddata->f_max; 4830ddf03c9SLucas Stach else 4840ddf03c9SLucas Stach return f_host; 4850ddf03c9SLucas Stach } 4860ddf03c9SLucas Stach 48795f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 48895f25efeSWolfram Sang { 48995f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 49095f25efeSWolfram Sang 49195f25efeSWolfram Sang return clk_get_rate(pltfm_host->clk) / 256 / 16; 49295f25efeSWolfram Sang } 49395f25efeSWolfram Sang 4948ba9580aSLucas Stach static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 4958ba9580aSLucas Stach unsigned int clock) 4968ba9580aSLucas Stach { 4978ba9580aSLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 498fed2f6e2SDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 499d31fc00aSDong Aisheng unsigned int host_clock = clk_get_rate(pltfm_host->clk); 500d31fc00aSDong Aisheng int pre_div = 2; 501d31fc00aSDong Aisheng int div = 1; 502fed2f6e2SDong Aisheng u32 temp, val; 5038ba9580aSLucas Stach 504fed2f6e2SDong Aisheng if (clock == 0) { 505fed2f6e2SDong Aisheng if (is_imx6q_usdhc(imx_data)) { 506fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 507fed2f6e2SDong Aisheng writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 508fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 509fed2f6e2SDong Aisheng } 510d31fc00aSDong Aisheng goto out; 511fed2f6e2SDong Aisheng } 512d31fc00aSDong Aisheng 5135f7886c5SDong Aisheng if (is_imx6q_usdhc(imx_data)) 5145f7886c5SDong Aisheng pre_div = 1; 5155f7886c5SDong Aisheng 516d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 517d31fc00aSDong Aisheng temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 518d31fc00aSDong Aisheng | ESDHC_CLOCK_MASK); 519d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 520d31fc00aSDong Aisheng 521d31fc00aSDong Aisheng while (host_clock / pre_div / 16 > clock && pre_div < 256) 522d31fc00aSDong Aisheng pre_div *= 2; 523d31fc00aSDong Aisheng 524d31fc00aSDong Aisheng while (host_clock / pre_div / div > clock && div < 16) 525d31fc00aSDong Aisheng div++; 526d31fc00aSDong Aisheng 527e76b8559SDong Aisheng host->mmc->actual_clock = host_clock / pre_div / div; 528d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 529e76b8559SDong Aisheng clock, host->mmc->actual_clock); 530d31fc00aSDong Aisheng 531d31fc00aSDong Aisheng pre_div >>= 1; 532d31fc00aSDong Aisheng div--; 533d31fc00aSDong Aisheng 534d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 535d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 536d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 537d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 538d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 539fed2f6e2SDong Aisheng 540fed2f6e2SDong Aisheng if (is_imx6q_usdhc(imx_data)) { 541fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 542fed2f6e2SDong Aisheng writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 543fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 544fed2f6e2SDong Aisheng } 545fed2f6e2SDong Aisheng 546d31fc00aSDong Aisheng mdelay(1); 547d31fc00aSDong Aisheng out: 548d31fc00aSDong Aisheng host->clock = clock; 5498ba9580aSLucas Stach } 5508ba9580aSLucas Stach 551913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 552913413c3SShawn Guo { 553842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 554842afc02SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 555842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 556913413c3SShawn Guo 557913413c3SShawn Guo switch (boarddata->wp_type) { 558913413c3SShawn Guo case ESDHC_WP_GPIO: 559fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 560913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 561913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 562913413c3SShawn Guo SDHCI_WRITE_PROTECT); 563913413c3SShawn Guo case ESDHC_WP_NONE: 564913413c3SShawn Guo break; 565913413c3SShawn Guo } 566913413c3SShawn Guo 567913413c3SShawn Guo return -ENOSYS; 568913413c3SShawn Guo } 569913413c3SShawn Guo 570af51079eSSascha Hauer static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width) 571af51079eSSascha Hauer { 572af51079eSSascha Hauer u32 ctrl; 573af51079eSSascha Hauer 574af51079eSSascha Hauer switch (width) { 575af51079eSSascha Hauer case MMC_BUS_WIDTH_8: 576af51079eSSascha Hauer ctrl = ESDHC_CTRL_8BITBUS; 577af51079eSSascha Hauer break; 578af51079eSSascha Hauer case MMC_BUS_WIDTH_4: 579af51079eSSascha Hauer ctrl = ESDHC_CTRL_4BITBUS; 580af51079eSSascha Hauer break; 581af51079eSSascha Hauer default: 582af51079eSSascha Hauer ctrl = 0; 583af51079eSSascha Hauer break; 584af51079eSSascha Hauer } 585af51079eSSascha Hauer 586af51079eSSascha Hauer esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 587af51079eSSascha Hauer SDHCI_HOST_CONTROL); 588af51079eSSascha Hauer 589af51079eSSascha Hauer return 0; 590af51079eSSascha Hauer } 591af51079eSSascha Hauer 5920322191eSDong Aisheng static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 5930322191eSDong Aisheng { 5940322191eSDong Aisheng u32 reg; 5950322191eSDong Aisheng 5960322191eSDong Aisheng /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 5970322191eSDong Aisheng mdelay(1); 5980322191eSDong Aisheng 5990322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 6000322191eSDong Aisheng reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 6010322191eSDong Aisheng ESDHC_MIX_CTRL_FBCLK_SEL; 6020322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 6030322191eSDong Aisheng writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 6040322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), 6050322191eSDong Aisheng "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 6060322191eSDong Aisheng val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 6070322191eSDong Aisheng } 6080322191eSDong Aisheng 6090322191eSDong Aisheng static void esdhc_request_done(struct mmc_request *mrq) 6100322191eSDong Aisheng { 6110322191eSDong Aisheng complete(&mrq->completion); 6120322191eSDong Aisheng } 6130322191eSDong Aisheng 6140322191eSDong Aisheng static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode) 6150322191eSDong Aisheng { 6160322191eSDong Aisheng struct mmc_command cmd = {0}; 6170322191eSDong Aisheng struct mmc_request mrq = {0}; 6180322191eSDong Aisheng struct mmc_data data = {0}; 6190322191eSDong Aisheng struct scatterlist sg; 6200322191eSDong Aisheng char tuning_pattern[ESDHC_TUNING_BLOCK_PATTERN_LEN]; 6210322191eSDong Aisheng 6220322191eSDong Aisheng cmd.opcode = opcode; 6230322191eSDong Aisheng cmd.arg = 0; 6240322191eSDong Aisheng cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 6250322191eSDong Aisheng 6260322191eSDong Aisheng data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN; 6270322191eSDong Aisheng data.blocks = 1; 6280322191eSDong Aisheng data.flags = MMC_DATA_READ; 6290322191eSDong Aisheng data.sg = &sg; 6300322191eSDong Aisheng data.sg_len = 1; 6310322191eSDong Aisheng 6320322191eSDong Aisheng sg_init_one(&sg, tuning_pattern, sizeof(tuning_pattern)); 6330322191eSDong Aisheng 6340322191eSDong Aisheng mrq.cmd = &cmd; 6350322191eSDong Aisheng mrq.cmd->mrq = &mrq; 6360322191eSDong Aisheng mrq.data = &data; 6370322191eSDong Aisheng mrq.data->mrq = &mrq; 6380322191eSDong Aisheng mrq.cmd->data = mrq.data; 6390322191eSDong Aisheng 6400322191eSDong Aisheng mrq.done = esdhc_request_done; 6410322191eSDong Aisheng init_completion(&(mrq.completion)); 6420322191eSDong Aisheng 6430322191eSDong Aisheng disable_irq(host->irq); 6440322191eSDong Aisheng spin_lock(&host->lock); 6450322191eSDong Aisheng host->mrq = &mrq; 6460322191eSDong Aisheng 6470322191eSDong Aisheng sdhci_send_command(host, mrq.cmd); 6480322191eSDong Aisheng 6490322191eSDong Aisheng spin_unlock(&host->lock); 6500322191eSDong Aisheng enable_irq(host->irq); 6510322191eSDong Aisheng 6520322191eSDong Aisheng wait_for_completion(&mrq.completion); 6530322191eSDong Aisheng 6540322191eSDong Aisheng if (cmd.error) 6550322191eSDong Aisheng return cmd.error; 6560322191eSDong Aisheng if (data.error) 6570322191eSDong Aisheng return data.error; 6580322191eSDong Aisheng 6590322191eSDong Aisheng return 0; 6600322191eSDong Aisheng } 6610322191eSDong Aisheng 6620322191eSDong Aisheng static void esdhc_post_tuning(struct sdhci_host *host) 6630322191eSDong Aisheng { 6640322191eSDong Aisheng u32 reg; 6650322191eSDong Aisheng 6660322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 6670322191eSDong Aisheng reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 6680322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 6690322191eSDong Aisheng } 6700322191eSDong Aisheng 6710322191eSDong Aisheng static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 6720322191eSDong Aisheng { 6730322191eSDong Aisheng int min, max, avg, ret; 6740322191eSDong Aisheng 6750322191eSDong Aisheng /* find the mininum delay first which can pass tuning */ 6760322191eSDong Aisheng min = ESDHC_TUNE_CTRL_MIN; 6770322191eSDong Aisheng while (min < ESDHC_TUNE_CTRL_MAX) { 6780322191eSDong Aisheng esdhc_prepare_tuning(host, min); 6790322191eSDong Aisheng if (!esdhc_send_tuning_cmd(host, opcode)) 6800322191eSDong Aisheng break; 6810322191eSDong Aisheng min += ESDHC_TUNE_CTRL_STEP; 6820322191eSDong Aisheng } 6830322191eSDong Aisheng 6840322191eSDong Aisheng /* find the maxinum delay which can not pass tuning */ 6850322191eSDong Aisheng max = min + ESDHC_TUNE_CTRL_STEP; 6860322191eSDong Aisheng while (max < ESDHC_TUNE_CTRL_MAX) { 6870322191eSDong Aisheng esdhc_prepare_tuning(host, max); 6880322191eSDong Aisheng if (esdhc_send_tuning_cmd(host, opcode)) { 6890322191eSDong Aisheng max -= ESDHC_TUNE_CTRL_STEP; 6900322191eSDong Aisheng break; 6910322191eSDong Aisheng } 6920322191eSDong Aisheng max += ESDHC_TUNE_CTRL_STEP; 6930322191eSDong Aisheng } 6940322191eSDong Aisheng 6950322191eSDong Aisheng /* use average delay to get the best timing */ 6960322191eSDong Aisheng avg = (min + max) / 2; 6970322191eSDong Aisheng esdhc_prepare_tuning(host, avg); 6980322191eSDong Aisheng ret = esdhc_send_tuning_cmd(host, opcode); 6990322191eSDong Aisheng esdhc_post_tuning(host); 7000322191eSDong Aisheng 7010322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", 7020322191eSDong Aisheng ret ? "failed" : "passed", avg, ret); 7030322191eSDong Aisheng 7040322191eSDong Aisheng return ret; 7050322191eSDong Aisheng } 7060322191eSDong Aisheng 707ad93220dSDong Aisheng static int esdhc_change_pinstate(struct sdhci_host *host, 708ad93220dSDong Aisheng unsigned int uhs) 709ad93220dSDong Aisheng { 710ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 711ad93220dSDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 712ad93220dSDong Aisheng struct pinctrl_state *pinctrl; 713ad93220dSDong Aisheng 714ad93220dSDong Aisheng dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 715ad93220dSDong Aisheng 716ad93220dSDong Aisheng if (IS_ERR(imx_data->pinctrl) || 717ad93220dSDong Aisheng IS_ERR(imx_data->pins_default) || 718ad93220dSDong Aisheng IS_ERR(imx_data->pins_100mhz) || 719ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) 720ad93220dSDong Aisheng return -EINVAL; 721ad93220dSDong Aisheng 722ad93220dSDong Aisheng switch (uhs) { 723ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 724ad93220dSDong Aisheng pinctrl = imx_data->pins_100mhz; 725ad93220dSDong Aisheng break; 726ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 727ad93220dSDong Aisheng pinctrl = imx_data->pins_200mhz; 728ad93220dSDong Aisheng break; 729ad93220dSDong Aisheng default: 730ad93220dSDong Aisheng /* back to default state for other legacy timing */ 731ad93220dSDong Aisheng pinctrl = imx_data->pins_default; 732ad93220dSDong Aisheng } 733ad93220dSDong Aisheng 734ad93220dSDong Aisheng return pinctrl_select_state(imx_data->pinctrl, pinctrl); 735ad93220dSDong Aisheng } 736ad93220dSDong Aisheng 737ad93220dSDong Aisheng static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) 738ad93220dSDong Aisheng { 739ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 740ad93220dSDong Aisheng struct pltfm_imx_data *imx_data = pltfm_host->priv; 741ad93220dSDong Aisheng 742ad93220dSDong Aisheng switch (uhs) { 743ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR12: 744ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR12; 745ad93220dSDong Aisheng break; 746ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR25: 747ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR25; 748ad93220dSDong Aisheng break; 749ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 750ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR50; 751ad93220dSDong Aisheng break; 752ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 753ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR104; 754ad93220dSDong Aisheng break; 755ad93220dSDong Aisheng case MMC_TIMING_UHS_DDR50: 756ad93220dSDong Aisheng imx_data->uhs_mode = SDHCI_CTRL_UHS_DDR50; 757ad93220dSDong Aisheng break; 758ad93220dSDong Aisheng } 759ad93220dSDong Aisheng 760ad93220dSDong Aisheng return esdhc_change_pinstate(host, uhs); 761ad93220dSDong Aisheng } 762ad93220dSDong Aisheng 763c915568dSLars-Peter Clausen static const struct sdhci_ops sdhci_esdhc_ops = { 764e149860dSRichard Zhu .read_l = esdhc_readl_le, 7650c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 766e149860dSRichard Zhu .write_l = esdhc_writel_le, 7670c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 7680c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 7698ba9580aSLucas Stach .set_clock = esdhc_pltfm_set_clock, 7700ddf03c9SLucas Stach .get_max_clock = esdhc_pltfm_get_max_clock, 7710c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 772913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 773af51079eSSascha Hauer .platform_bus_width = esdhc_pltfm_bus_width, 774ad93220dSDong Aisheng .set_uhs_signaling = esdhc_set_uhs_signaling, 7750322191eSDong Aisheng .platform_execute_tuning = esdhc_executing_tuning, 7760c6d49ceSWolfram Sang }; 7770c6d49ceSWolfram Sang 7781db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 77997e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 78097e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 78197e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 78285d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 78385d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 78485d6509dSShawn Guo }; 78585d6509dSShawn Guo 786abfafc2dSShawn Guo #ifdef CONFIG_OF 787c3be1efdSBill Pemberton static int 788abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 789abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 790abfafc2dSShawn Guo { 791abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 792abfafc2dSShawn Guo 793abfafc2dSShawn Guo if (!np) 794abfafc2dSShawn Guo return -ENODEV; 795abfafc2dSShawn Guo 7967f217794SArnd Bergmann if (of_get_property(np, "non-removable", NULL)) 797abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_PERMANENT; 798abfafc2dSShawn Guo 799abfafc2dSShawn Guo if (of_get_property(np, "fsl,cd-controller", NULL)) 800abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_CONTROLLER; 801abfafc2dSShawn Guo 802abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 803abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 804abfafc2dSShawn Guo 805abfafc2dSShawn Guo boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 806abfafc2dSShawn Guo if (gpio_is_valid(boarddata->cd_gpio)) 807abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_GPIO; 808abfafc2dSShawn Guo 809abfafc2dSShawn Guo boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 810abfafc2dSShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 811abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 812abfafc2dSShawn Guo 813af51079eSSascha Hauer of_property_read_u32(np, "bus-width", &boarddata->max_bus_width); 814af51079eSSascha Hauer 8150ddf03c9SLucas Stach of_property_read_u32(np, "max-frequency", &boarddata->f_max); 8160ddf03c9SLucas Stach 817ad93220dSDong Aisheng if (of_find_property(np, "no-1-8-v", NULL)) 818ad93220dSDong Aisheng boarddata->support_vsel = false; 819ad93220dSDong Aisheng else 820ad93220dSDong Aisheng boarddata->support_vsel = true; 821ad93220dSDong Aisheng 822abfafc2dSShawn Guo return 0; 823abfafc2dSShawn Guo } 824abfafc2dSShawn Guo #else 825abfafc2dSShawn Guo static inline int 826abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 827abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 828abfafc2dSShawn Guo { 829abfafc2dSShawn Guo return -ENODEV; 830abfafc2dSShawn Guo } 831abfafc2dSShawn Guo #endif 832abfafc2dSShawn Guo 833c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 83495f25efeSWolfram Sang { 835abfafc2dSShawn Guo const struct of_device_id *of_id = 836abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 83785d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 83885d6509dSShawn Guo struct sdhci_host *host; 83985d6509dSShawn Guo struct esdhc_platform_data *boarddata; 8400c6d49ceSWolfram Sang int err; 841e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 84295f25efeSWolfram Sang 8430e748234SChristian Daudt host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0); 84485d6509dSShawn Guo if (IS_ERR(host)) 84585d6509dSShawn Guo return PTR_ERR(host); 84685d6509dSShawn Guo 84785d6509dSShawn Guo pltfm_host = sdhci_priv(host); 84885d6509dSShawn Guo 849e3af31c6SShawn Guo imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); 850abfafc2dSShawn Guo if (!imx_data) { 851abfafc2dSShawn Guo err = -ENOMEM; 852e3af31c6SShawn Guo goto free_sdhci; 853abfafc2dSShawn Guo } 85457ed3314SShawn Guo 855abfafc2dSShawn Guo if (of_id) 856abfafc2dSShawn Guo pdev->id_entry = of_id->data; 85757ed3314SShawn Guo imx_data->devtype = pdev->id_entry->driver_data; 85885d6509dSShawn Guo pltfm_host->priv = imx_data; 85985d6509dSShawn Guo 86052dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 86152dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 86252dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 863e3af31c6SShawn Guo goto free_sdhci; 86495f25efeSWolfram Sang } 86552dac615SSascha Hauer 86652dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 86752dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 86852dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 869e3af31c6SShawn Guo goto free_sdhci; 87052dac615SSascha Hauer } 87152dac615SSascha Hauer 87252dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 87352dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 87452dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 875e3af31c6SShawn Guo goto free_sdhci; 87652dac615SSascha Hauer } 87752dac615SSascha Hauer 87852dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 87952dac615SSascha Hauer 88052dac615SSascha Hauer clk_prepare_enable(imx_data->clk_per); 88152dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ipg); 88252dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ahb); 88395f25efeSWolfram Sang 884ad93220dSDong Aisheng imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 885e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 886e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 887e3af31c6SShawn Guo goto disable_clk; 888e62d8b8fSDong Aisheng } 889e62d8b8fSDong Aisheng 890ad93220dSDong Aisheng imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, 891ad93220dSDong Aisheng PINCTRL_STATE_DEFAULT); 892ad93220dSDong Aisheng if (IS_ERR(imx_data->pins_default)) { 893ad93220dSDong Aisheng err = PTR_ERR(imx_data->pins_default); 894ad93220dSDong Aisheng dev_err(mmc_dev(host->mmc), "could not get default state\n"); 895ad93220dSDong Aisheng goto disable_clk; 896ad93220dSDong Aisheng } 897ad93220dSDong Aisheng 89837865fe9SEric Bénard host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 89937865fe9SEric Bénard 90057ed3314SShawn Guo if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data)) 9010c6d49ceSWolfram Sang /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ 90297e4ba6aSRichard Zhu host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK 90397e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA; 9040c6d49ceSWolfram Sang 90557ed3314SShawn Guo if (is_imx53_esdhc(imx_data)) 90658ac8177SRichard Zhu imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT; 90758ac8177SRichard Zhu 908f750ba9bSShawn Guo /* 909f750ba9bSShawn Guo * The imx6q ROM code will change the default watermark level setting 910f750ba9bSShawn Guo * to something insane. Change it back here. 911f750ba9bSShawn Guo */ 912f750ba9bSShawn Guo if (is_imx6q_usdhc(imx_data)) 91360bf6396SShawn Guo writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); 914f750ba9bSShawn Guo 915abfafc2dSShawn Guo boarddata = &imx_data->boarddata; 916abfafc2dSShawn Guo if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) { 917842afc02SShawn Guo if (!host->mmc->parent->platform_data) { 918913413c3SShawn Guo dev_err(mmc_dev(host->mmc), "no board data!\n"); 919913413c3SShawn Guo err = -EINVAL; 920e3af31c6SShawn Guo goto disable_clk; 921913413c3SShawn Guo } 922842afc02SShawn Guo imx_data->boarddata = *((struct esdhc_platform_data *) 923842afc02SShawn Guo host->mmc->parent->platform_data); 924abfafc2dSShawn Guo } 925913413c3SShawn Guo 926913413c3SShawn Guo /* write_protect */ 927913413c3SShawn Guo if (boarddata->wp_type == ESDHC_WP_GPIO) { 928fbe5fdd1SShawn Guo err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); 9290c6d49ceSWolfram Sang if (err) { 930fbe5fdd1SShawn Guo dev_err(mmc_dev(host->mmc), 931fbe5fdd1SShawn Guo "failed to request write-protect gpio!\n"); 932fbe5fdd1SShawn Guo goto disable_clk; 933913413c3SShawn Guo } 934fbe5fdd1SShawn Guo host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 9350c6d49ceSWolfram Sang } 9367e29c306SWolfram Sang 937913413c3SShawn Guo /* card_detect */ 938913413c3SShawn Guo switch (boarddata->cd_type) { 939913413c3SShawn Guo case ESDHC_CD_GPIO: 940214fc309SLaurent Pinchart err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); 9417e29c306SWolfram Sang if (err) { 942913413c3SShawn Guo dev_err(mmc_dev(host->mmc), 943fbe5fdd1SShawn Guo "failed to request card-detect gpio!\n"); 944e3af31c6SShawn Guo goto disable_clk; 9457e29c306SWolfram Sang } 946913413c3SShawn Guo /* fall through */ 9477e29c306SWolfram Sang 948913413c3SShawn Guo case ESDHC_CD_CONTROLLER: 949913413c3SShawn Guo /* we have a working card_detect back */ 9507e29c306SWolfram Sang host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 951913413c3SShawn Guo break; 952913413c3SShawn Guo 953913413c3SShawn Guo case ESDHC_CD_PERMANENT: 954913413c3SShawn Guo host->mmc->caps = MMC_CAP_NONREMOVABLE; 955913413c3SShawn Guo break; 956913413c3SShawn Guo 957913413c3SShawn Guo case ESDHC_CD_NONE: 958913413c3SShawn Guo break; 9597e29c306SWolfram Sang } 9607e29c306SWolfram Sang 961af51079eSSascha Hauer switch (boarddata->max_bus_width) { 962af51079eSSascha Hauer case 8: 963af51079eSSascha Hauer host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 964af51079eSSascha Hauer break; 965af51079eSSascha Hauer case 4: 966af51079eSSascha Hauer host->mmc->caps |= MMC_CAP_4_BIT_DATA; 967af51079eSSascha Hauer break; 968af51079eSSascha Hauer case 1: 969af51079eSSascha Hauer default: 970af51079eSSascha Hauer host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 971af51079eSSascha Hauer break; 972af51079eSSascha Hauer } 973af51079eSSascha Hauer 974ad93220dSDong Aisheng /* sdr50 and sdr104 needs work on 1.8v signal voltage */ 975ad93220dSDong Aisheng if ((boarddata->support_vsel) && is_imx6q_usdhc(imx_data)) { 976ad93220dSDong Aisheng imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 977ad93220dSDong Aisheng ESDHC_PINCTRL_STATE_100MHZ); 978ad93220dSDong Aisheng imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 979ad93220dSDong Aisheng ESDHC_PINCTRL_STATE_200MHZ); 980ad93220dSDong Aisheng if (IS_ERR(imx_data->pins_100mhz) || 981ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) { 982ad93220dSDong Aisheng dev_warn(mmc_dev(host->mmc), 983ad93220dSDong Aisheng "could not get ultra high speed state, work on normal mode\n"); 984ad93220dSDong Aisheng /* fall back to not support uhs by specify no 1.8v quirk */ 985ad93220dSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 986ad93220dSDong Aisheng } 987ad93220dSDong Aisheng } else { 988ad93220dSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 989ad93220dSDong Aisheng } 990ad93220dSDong Aisheng 99185d6509dSShawn Guo err = sdhci_add_host(host); 99285d6509dSShawn Guo if (err) 993e3af31c6SShawn Guo goto disable_clk; 99485d6509dSShawn Guo 9957e29c306SWolfram Sang return 0; 9967e29c306SWolfram Sang 997e3af31c6SShawn Guo disable_clk: 99852dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 99952dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 100052dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 1001e3af31c6SShawn Guo free_sdhci: 100285d6509dSShawn Guo sdhci_pltfm_free(pdev); 100385d6509dSShawn Guo return err; 100495f25efeSWolfram Sang } 100595f25efeSWolfram Sang 10066e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 100795f25efeSWolfram Sang { 100885d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 100995f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1010e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 101185d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 101285d6509dSShawn Guo 101385d6509dSShawn Guo sdhci_remove_host(host, dead); 10140c6d49ceSWolfram Sang 101552dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 101652dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 101752dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 101852dac615SSascha Hauer 101985d6509dSShawn Guo sdhci_pltfm_free(pdev); 102085d6509dSShawn Guo 102185d6509dSShawn Guo return 0; 102295f25efeSWolfram Sang } 102395f25efeSWolfram Sang 102485d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 102585d6509dSShawn Guo .driver = { 102685d6509dSShawn Guo .name = "sdhci-esdhc-imx", 102785d6509dSShawn Guo .owner = THIS_MODULE, 1028abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 102929495aa0SManuel Lauss .pm = SDHCI_PLTFM_PMOPS, 103085d6509dSShawn Guo }, 103157ed3314SShawn Guo .id_table = imx_esdhc_devtype, 103285d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 10330433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 103495f25efeSWolfram Sang }; 103585d6509dSShawn Guo 1036d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 103785d6509dSShawn Guo 103885d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 103985d6509dSShawn Guo MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); 104085d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1041