1a6e7e407SFabio Estevam // SPDX-License-Identifier: GPL-2.0 295f25efeSWolfram Sang /* 395f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 495f25efeSWolfram Sang * 595f25efeSWolfram Sang * derived from the OF-version. 695f25efeSWolfram Sang * 795f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 8035ff831SWolfram Sang * Author: Wolfram Sang <kernel@pengutronix.de> 995f25efeSWolfram Sang */ 1095f25efeSWolfram Sang 1195f25efeSWolfram Sang #include <linux/io.h> 12f581e909SHaibo Chen #include <linux/iopoll.h> 1395f25efeSWolfram Sang #include <linux/delay.h> 1495f25efeSWolfram Sang #include <linux/err.h> 1595f25efeSWolfram Sang #include <linux/clk.h> 1666506f76SShawn Guo #include <linux/module.h> 17e149860dSRichard Zhu #include <linux/slab.h> 181c4989b0SBOUGH CHEN #include <linux/pm_qos.h> 1995f25efeSWolfram Sang #include <linux/mmc/host.h> 2058ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2158ac8177SRichard Zhu #include <linux/mmc/sdio.h> 22fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 23abfafc2dSShawn Guo #include <linux/of.h> 24abfafc2dSShawn Guo #include <linux/of_device.h> 25e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2682906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 2789d7e5c1SDong Aisheng #include <linux/pm_runtime.h> 2895f25efeSWolfram Sang #include "sdhci-pltfm.h" 2995f25efeSWolfram Sang #include "sdhci-esdhc.h" 30bb6e3581SBOUGH CHEN #include "cqhci.h" 3195f25efeSWolfram Sang 32a215186dSHaibo Chen #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f 3360bf6396SShawn Guo #define ESDHC_CTRL_D3CD 0x08 34fd44954eSHaibo Chen #define ESDHC_BURST_LEN_EN_INCR (1 << 27) 3558ac8177SRichard Zhu /* VENDOR SPEC register */ 3660bf6396SShawn Guo #define ESDHC_VENDOR_SPEC 0xc0 3760bf6396SShawn Guo #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 380322191eSDong Aisheng #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 39fed2f6e2SDong Aisheng #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 4060bf6396SShawn Guo #define ESDHC_WTMK_LVL 0x44 41cc17e129SDong Aisheng #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 423fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF 433fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0 443fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000 453fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16 463fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WML_VAL_DEF 64 473fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WML_VAL_MAX 128 4860bf6396SShawn Guo #define ESDHC_MIX_CTRL 0x48 49de5bdbffSDong Aisheng #define ESDHC_MIX_CTRL_DDREN (1 << 3) 502a15f981SShawn Guo #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 510322191eSDong Aisheng #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 520322191eSDong Aisheng #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 530b330e38SDong Aisheng #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) 540322191eSDong Aisheng #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 5528b07674SHaibo Chen #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 56029e2476SBOUGH CHEN #define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27) 572a15f981SShawn Guo /* Bits 3 and 6 are not SDHCI standard definitions */ 582a15f981SShawn Guo #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 59d131a71cSDong Aisheng /* Tuning bits */ 60d131a71cSDong Aisheng #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 6158ac8177SRichard Zhu 62602519b2SDong Aisheng /* dll control register */ 63602519b2SDong Aisheng #define ESDHC_DLL_CTRL 0x60 64602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 65602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 66602519b2SDong Aisheng 670322191eSDong Aisheng /* tune control register */ 680322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STATUS 0x68 690322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STEP 1 700322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MIN 0 710322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 720322191eSDong Aisheng 7328b07674SHaibo Chen /* strobe dll register */ 7428b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL 0x70 7528b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) 7628b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) 775bd2acdcSHaibo Chen #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7 7828b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 792eaf5a53SBOUGH CHEN #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20) 8028b07674SHaibo Chen 8128b07674SHaibo Chen #define ESDHC_STROBE_DLL_STATUS 0x74 8228b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) 8328b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 8428b07674SHaibo Chen 85bcdb5301SBOUGH CHEN #define ESDHC_VEND_SPEC2 0xc8 86bcdb5301SBOUGH CHEN #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8) 87bcdb5301SBOUGH CHEN 886e9fd28eSDong Aisheng #define ESDHC_TUNING_CTRL 0xcc 896e9fd28eSDong Aisheng #define ESDHC_STD_TUNING_EN (1 << 24) 906e9fd28eSDong Aisheng /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 91d87fc966SDong Aisheng #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 92d87fc966SDong Aisheng #define ESDHC_TUNING_START_TAP_MASK 0xff 93260ecb3cSHaibo Chen #define ESDHC_TUNING_STEP_MASK 0x00070000 94d407e30bSHaibo Chen #define ESDHC_TUNING_STEP_SHIFT 16 956e9fd28eSDong Aisheng 96ad93220dSDong Aisheng /* pinctrl state */ 97ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 98ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 99ad93220dSDong Aisheng 10058ac8177SRichard Zhu /* 101af51079eSSascha Hauer * Our interpretation of the SDHCI_HOST_CONTROL register 102af51079eSSascha Hauer */ 103af51079eSSascha Hauer #define ESDHC_CTRL_4BITBUS (0x1 << 1) 104af51079eSSascha Hauer #define ESDHC_CTRL_8BITBUS (0x2 << 1) 105af51079eSSascha Hauer #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 106af51079eSSascha Hauer 107af51079eSSascha Hauer /* 108d04f8d5bSBenoît Thébaudeau * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC: 10997e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 11097e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 11197e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 11297e4ba6aSRichard Zhu */ 11360bf6396SShawn Guo #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 11497e4ba6aSRichard Zhu 115bb6e3581SBOUGH CHEN /* the address offset of CQHCI */ 116bb6e3581SBOUGH CHEN #define ESDHC_CQHCI_ADDR_OFFSET 0x100 117bb6e3581SBOUGH CHEN 11897e4ba6aSRichard Zhu /* 11958ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 12058ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 12158ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 12258ac8177SRichard Zhu * be generated. 12358ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 12458ac8177SRichard Zhu * operations automatically as required at the end of the 12558ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 12658ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 127d04f8d5bSBenoît Thébaudeau * exception. Bit1 of Vendor Spec register is used to fix it. 12858ac8177SRichard Zhu */ 12931fbb301SShawn Guo #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 13031fbb301SShawn Guo /* 1319d61c009SShawn Guo * The flag tells that the ESDHC controller is an USDHC block that is 1329d61c009SShawn Guo * integrated on the i.MX6 series. 1339d61c009SShawn Guo */ 1349d61c009SShawn Guo #define ESDHC_FLAG_USDHC BIT(3) 1356e9fd28eSDong Aisheng /* The IP supports manual tuning process */ 1366e9fd28eSDong Aisheng #define ESDHC_FLAG_MAN_TUNING BIT(4) 1376e9fd28eSDong Aisheng /* The IP supports standard tuning process */ 1386e9fd28eSDong Aisheng #define ESDHC_FLAG_STD_TUNING BIT(5) 1396e9fd28eSDong Aisheng /* The IP has SDHCI_CAPABILITIES_1 register */ 1406e9fd28eSDong Aisheng #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 14118094430SDong Aisheng /* 142d04f8d5bSBenoît Thébaudeau * The IP has erratum ERR004536 14318094430SDong Aisheng * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 14418094430SDong Aisheng * when reading data from the card 145667123f6SBenoît Thébaudeau * This flag is also set for i.MX25 and i.MX35 in order to get 146667123f6SBenoît Thébaudeau * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits). 14718094430SDong Aisheng */ 14818094430SDong Aisheng #define ESDHC_FLAG_ERR004536 BIT(7) 1494245afffSDong Aisheng /* The IP supports HS200 mode */ 1504245afffSDong Aisheng #define ESDHC_FLAG_HS200 BIT(8) 15128b07674SHaibo Chen /* The IP supports HS400 mode */ 15228b07674SHaibo Chen #define ESDHC_FLAG_HS400 BIT(9) 153af6a50d4SBOUGH CHEN /* 154af6a50d4SBOUGH CHEN * The IP has errata ERR010450 155af6a50d4SBOUGH CHEN * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't 156af6a50d4SBOUGH CHEN * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz. 157af6a50d4SBOUGH CHEN */ 158af6a50d4SBOUGH CHEN #define ESDHC_FLAG_ERR010450 BIT(10) 159029e2476SBOUGH CHEN /* The IP supports HS400ES mode */ 160029e2476SBOUGH CHEN #define ESDHC_FLAG_HS400_ES BIT(11) 161bb6e3581SBOUGH CHEN /* The IP has Host Controller Interface for Command Queuing */ 162bb6e3581SBOUGH CHEN #define ESDHC_FLAG_CQHCI BIT(12) 1631c4989b0SBOUGH CHEN /* need request pmqos during low power */ 1641c4989b0SBOUGH CHEN #define ESDHC_FLAG_PMQOS BIT(13) 165a26a4f1bSHaibo Chen /* The IP state got lost in low power mode */ 166a26a4f1bSHaibo Chen #define ESDHC_FLAG_STATE_LOST_IN_LPMODE BIT(14) 1675c11f1ffSHaibo Chen /* The IP lost clock rate in PM_RUNTIME */ 1685c11f1ffSHaibo Chen #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME BIT(15) 16974898cbcSHaibo Chen /* 17074898cbcSHaibo Chen * The IP do not support the ACMD23 feature completely when use ADMA mode. 17174898cbcSHaibo Chen * In ADMA mode, it only use the 16 bit block count of the register 0x4 17274898cbcSHaibo Chen * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will 17374898cbcSHaibo Chen * ignore the upper 16 bit of the CMD23's argument. This will block the reliable 17474898cbcSHaibo Chen * write operation in RPMB, because RPMB reliable write need to set the bit31 17574898cbcSHaibo Chen * of the CMD23's argument. 17674898cbcSHaibo Chen * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA 17774898cbcSHaibo Chen * do not has this limitation. so when these SoC use ADMA mode, it need to 17874898cbcSHaibo Chen * disable the ACMD23 feature. 17974898cbcSHaibo Chen */ 18074898cbcSHaibo Chen #define ESDHC_FLAG_BROKEN_AUTO_CMD23 BIT(16) 181e149860dSRichard Zhu 182f47c4bbfSShawn Guo struct esdhc_soc_data { 183f47c4bbfSShawn Guo u32 flags; 184f47c4bbfSShawn Guo }; 185f47c4bbfSShawn Guo 1864f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx25_data = { 187667123f6SBenoît Thébaudeau .flags = ESDHC_FLAG_ERR004536, 188f47c4bbfSShawn Guo }; 189f47c4bbfSShawn Guo 1904f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx35_data = { 191667123f6SBenoît Thébaudeau .flags = ESDHC_FLAG_ERR004536, 192f47c4bbfSShawn Guo }; 193f47c4bbfSShawn Guo 1944f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx51_data = { 195f47c4bbfSShawn Guo .flags = 0, 196f47c4bbfSShawn Guo }; 197f47c4bbfSShawn Guo 1984f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx53_data = { 199f47c4bbfSShawn Guo .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 200f47c4bbfSShawn Guo }; 201f47c4bbfSShawn Guo 2024f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx6q_data = { 20374898cbcSHaibo Chen .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 20474898cbcSHaibo Chen | ESDHC_FLAG_BROKEN_AUTO_CMD23, 2056e9fd28eSDong Aisheng }; 2066e9fd28eSDong Aisheng 2074f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx6sl_data = { 2086e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 2094245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 21074898cbcSHaibo Chen | ESDHC_FLAG_HS200 21174898cbcSHaibo Chen | ESDHC_FLAG_BROKEN_AUTO_CMD23, 21274898cbcSHaibo Chen }; 21374898cbcSHaibo Chen 21474898cbcSHaibo Chen static const struct esdhc_soc_data usdhc_imx6sll_data = { 21574898cbcSHaibo Chen .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 21674898cbcSHaibo Chen | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 21774898cbcSHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 21857ed3314SShawn Guo }; 21957ed3314SShawn Guo 2204f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx6sx_data = { 221913d4951SDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 222a26a4f1bSHaibo Chen | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 22374898cbcSHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE 22474898cbcSHaibo Chen | ESDHC_FLAG_BROKEN_AUTO_CMD23, 225913d4951SDong Aisheng }; 226913d4951SDong Aisheng 227af6a50d4SBOUGH CHEN static const struct esdhc_soc_data usdhc_imx6ull_data = { 228af6a50d4SBOUGH CHEN .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 229af6a50d4SBOUGH CHEN | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 230a26a4f1bSHaibo Chen | ESDHC_FLAG_ERR010450 231a26a4f1bSHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 232af6a50d4SBOUGH CHEN }; 233af6a50d4SBOUGH CHEN 2344f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx7d_data = { 23528b07674SHaibo Chen .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 23628b07674SHaibo Chen | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 237a26a4f1bSHaibo Chen | ESDHC_FLAG_HS400 23874898cbcSHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE 23974898cbcSHaibo Chen | ESDHC_FLAG_BROKEN_AUTO_CMD23, 24028b07674SHaibo Chen }; 24128b07674SHaibo Chen 2421c4989b0SBOUGH CHEN static struct esdhc_soc_data usdhc_imx7ulp_data = { 2431c4989b0SBOUGH CHEN .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 2441c4989b0SBOUGH CHEN | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 245a26a4f1bSHaibo Chen | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400 246a26a4f1bSHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 2471c4989b0SBOUGH CHEN }; 2481c4989b0SBOUGH CHEN 249029e2476SBOUGH CHEN static struct esdhc_soc_data usdhc_imx8qxp_data = { 250029e2476SBOUGH CHEN .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 251029e2476SBOUGH CHEN | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 252bb6e3581SBOUGH CHEN | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 253a26a4f1bSHaibo Chen | ESDHC_FLAG_CQHCI 2545c11f1ffSHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE 2555c11f1ffSHaibo Chen | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME, 256029e2476SBOUGH CHEN }; 257029e2476SBOUGH CHEN 258cde5e8e9SHaibo Chen static struct esdhc_soc_data usdhc_imx8mm_data = { 259cde5e8e9SHaibo Chen .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 260cde5e8e9SHaibo Chen | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 261cde5e8e9SHaibo Chen | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 262cde5e8e9SHaibo Chen | ESDHC_FLAG_CQHCI 263cde5e8e9SHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 264cde5e8e9SHaibo Chen }; 265cde5e8e9SHaibo Chen 266e149860dSRichard Zhu struct pltfm_imx_data { 267e149860dSRichard Zhu u32 scratchpad; 268e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 269ad93220dSDong Aisheng struct pinctrl_state *pins_100mhz; 270ad93220dSDong Aisheng struct pinctrl_state *pins_200mhz; 271f47c4bbfSShawn Guo const struct esdhc_soc_data *socdata; 272842afc02SShawn Guo struct esdhc_platform_data boarddata; 27352dac615SSascha Hauer struct clk *clk_ipg; 27452dac615SSascha Hauer struct clk *clk_ahb; 27552dac615SSascha Hauer struct clk *clk_per; 2763602785bSMichael Trimarchi unsigned int actual_clock; 277361b8482SLucas Stach enum { 278361b8482SLucas Stach NO_CMD_PENDING, /* no multiblock command pending */ 279361b8482SLucas Stach MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 280361b8482SLucas Stach WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 281361b8482SLucas Stach } multiblock_status; 282de5bdbffSDong Aisheng u32 is_ddr; 2831c4989b0SBOUGH CHEN struct pm_qos_request pm_qos_req; 284e149860dSRichard Zhu }; 285e149860dSRichard Zhu 286f8cbf461SKrzysztof Kozlowski static const struct platform_device_id imx_esdhc_devtype[] = { 28757ed3314SShawn Guo { 28857ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 289f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 29057ed3314SShawn Guo }, { 29157ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 292f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 29357ed3314SShawn Guo }, { 29457ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 295f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 29657ed3314SShawn Guo }, { 29757ed3314SShawn Guo /* sentinel */ 29857ed3314SShawn Guo } 29957ed3314SShawn Guo }; 30057ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 30157ed3314SShawn Guo 302abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 303f47c4bbfSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 304f47c4bbfSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 305f47c4bbfSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 306f47c4bbfSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 307913d4951SDong Aisheng { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 3086e9fd28eSDong Aisheng { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 30974898cbcSHaibo Chen { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, }, 310f47c4bbfSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 311af6a50d4SBOUGH CHEN { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, }, 31228b07674SHaibo Chen { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, 3131c4989b0SBOUGH CHEN { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, }, 314029e2476SBOUGH CHEN { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, }, 315cde5e8e9SHaibo Chen { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, }, 316abfafc2dSShawn Guo { /* sentinel */ } 317abfafc2dSShawn Guo }; 318abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 319abfafc2dSShawn Guo 32057ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 32157ed3314SShawn Guo { 322f47c4bbfSShawn Guo return data->socdata == &esdhc_imx25_data; 32357ed3314SShawn Guo } 32457ed3314SShawn Guo 32557ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 32657ed3314SShawn Guo { 327f47c4bbfSShawn Guo return data->socdata == &esdhc_imx53_data; 32857ed3314SShawn Guo } 32957ed3314SShawn Guo 33095a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 33195a2482aSShawn Guo { 332f47c4bbfSShawn Guo return data->socdata == &usdhc_imx6q_data; 33395a2482aSShawn Guo } 33495a2482aSShawn Guo 3359d61c009SShawn Guo static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 3369d61c009SShawn Guo { 337f47c4bbfSShawn Guo return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 3389d61c009SShawn Guo } 3399d61c009SShawn Guo 34095f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 34195f25efeSWolfram Sang { 34295f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 34395f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 34495f25efeSWolfram Sang 34595f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 34695f25efeSWolfram Sang } 34795f25efeSWolfram Sang 348f581e909SHaibo Chen static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host) 349f581e909SHaibo Chen { 350f581e909SHaibo Chen u32 present_state; 351f581e909SHaibo Chen int ret; 352f581e909SHaibo Chen 353f581e909SHaibo Chen ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state, 354f581e909SHaibo Chen (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100); 355f581e909SHaibo Chen if (ret == -ETIMEDOUT) 356f581e909SHaibo Chen dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__); 357f581e909SHaibo Chen } 358f581e909SHaibo Chen 3597e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 3607e29c306SWolfram Sang { 361361b8482SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 362070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 363913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 364913413c3SShawn Guo 3650322191eSDong Aisheng if (unlikely(reg == SDHCI_PRESENT_STATE)) { 3660322191eSDong Aisheng u32 fsl_prss = val; 3670322191eSDong Aisheng /* save the least 20 bits */ 3680322191eSDong Aisheng val = fsl_prss & 0x000FFFFF; 3690322191eSDong Aisheng /* move dat[0-3] bits */ 3700322191eSDong Aisheng val |= (fsl_prss & 0x0F000000) >> 4; 3710322191eSDong Aisheng /* move cmd line bit */ 3720322191eSDong Aisheng val |= (fsl_prss & 0x00800000) << 1; 3730322191eSDong Aisheng } 3740322191eSDong Aisheng 37597e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 3766b4fb671SDong Aisheng /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 3776b4fb671SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 3786b4fb671SDong Aisheng val &= 0xffff0000; 3796b4fb671SDong Aisheng 38097e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 38197e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 38297e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 38397e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 384d04f8d5bSBenoît Thébaudeau * quirk on MX25/35 platforms. 38597e4ba6aSRichard Zhu */ 38697e4ba6aSRichard Zhu 38797e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 38897e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 38997e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 39097e4ba6aSRichard Zhu } 39197e4ba6aSRichard Zhu } 39297e4ba6aSRichard Zhu 3936e9fd28eSDong Aisheng if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 3946e9fd28eSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 3956e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 3966e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 3976e9fd28eSDong Aisheng else 3986e9fd28eSDong Aisheng /* imx6q/dl does not have cap_1 register, fake one */ 3990322191eSDong Aisheng val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 400888824bbSDong Aisheng | SDHCI_SUPPORT_SDR50 401da0295ffSDong Aisheng | SDHCI_USE_SDR50_TUNING 402da0295ffSDong Aisheng | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT); 40328b07674SHaibo Chen 40428b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 40528b07674SHaibo Chen val |= SDHCI_SUPPORT_HS400; 40692748beaSStefan Agner 40792748beaSStefan Agner /* 40892748beaSStefan Agner * Do not advertise faster UHS modes if there are no 40992748beaSStefan Agner * pinctrl states for 100MHz/200MHz. 41092748beaSStefan Agner */ 41192748beaSStefan Agner if (IS_ERR_OR_NULL(imx_data->pins_100mhz) || 41292748beaSStefan Agner IS_ERR_OR_NULL(imx_data->pins_200mhz)) 41392748beaSStefan Agner val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50 41492748beaSStefan Agner | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400); 4156e9fd28eSDong Aisheng } 4166e9fd28eSDong Aisheng } 4170322191eSDong Aisheng 4189d61c009SShawn Guo if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 4190322191eSDong Aisheng val = 0; 4200322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 4210322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 4220322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 4230322191eSDong Aisheng } 4240322191eSDong Aisheng 42597e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 42660bf6396SShawn Guo if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 42760bf6396SShawn Guo val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 42897e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 42997e4ba6aSRichard Zhu } 430361b8482SLucas Stach 431361b8482SLucas Stach /* 432361b8482SLucas Stach * mask off the interrupt we get in response to the manually 433361b8482SLucas Stach * sent CMD12 434361b8482SLucas Stach */ 435361b8482SLucas Stach if ((imx_data->multiblock_status == WAIT_FOR_INT) && 436361b8482SLucas Stach ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 437361b8482SLucas Stach val &= ~SDHCI_INT_RESPONSE; 438361b8482SLucas Stach writel(SDHCI_INT_RESPONSE, host->ioaddr + 439361b8482SLucas Stach SDHCI_INT_STATUS); 440361b8482SLucas Stach imx_data->multiblock_status = NO_CMD_PENDING; 441361b8482SLucas Stach } 44297e4ba6aSRichard Zhu } 44397e4ba6aSRichard Zhu 4447e29c306SWolfram Sang return val; 4457e29c306SWolfram Sang } 4467e29c306SWolfram Sang 4477e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 4487e29c306SWolfram Sang { 449e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 450070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 4510d58864bSTony Lin u32 data; 452e149860dSRichard Zhu 45377da3da0SAaron Brice if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || 45477da3da0SAaron Brice reg == SDHCI_INT_STATUS)) { 455b7321042SDong Aisheng if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 4560d58864bSTony Lin /* 4570d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 458d04f8d5bSBenoît Thébaudeau * card interrupt. This is an eSDHC controller problem 4590d58864bSTony Lin * so we need to apply the following workaround: clear 4600d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 4610d58864bSTony Lin * interrupt. In case a card interrupt was lost, 4620d58864bSTony Lin * re-sample it by the following steps. 4630d58864bSTony Lin */ 4640d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 46560bf6396SShawn Guo data &= ~ESDHC_CTRL_D3CD; 4660d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 46760bf6396SShawn Guo data |= ESDHC_CTRL_D3CD; 4680d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 4690d58864bSTony Lin } 470915be485SDong Aisheng 471915be485SDong Aisheng if (val & SDHCI_INT_ADMA_ERROR) { 472915be485SDong Aisheng val &= ~SDHCI_INT_ADMA_ERROR; 473915be485SDong Aisheng val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 474915be485SDong Aisheng } 4750d58864bSTony Lin } 4760d58864bSTony Lin 477f47c4bbfSShawn Guo if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 47858ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 47958ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 48058ac8177SRichard Zhu u32 v; 48160bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 48260bf6396SShawn Guo v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 48360bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 484361b8482SLucas Stach 485361b8482SLucas Stach if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 486361b8482SLucas Stach { 487361b8482SLucas Stach /* send a manual CMD12 with RESPTYP=none */ 488361b8482SLucas Stach data = MMC_STOP_TRANSMISSION << 24 | 489361b8482SLucas Stach SDHCI_CMD_ABORTCMD << 16; 490361b8482SLucas Stach writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 491361b8482SLucas Stach imx_data->multiblock_status = WAIT_FOR_INT; 492361b8482SLucas Stach } 49358ac8177SRichard Zhu } 49458ac8177SRichard Zhu 4957e29c306SWolfram Sang writel(val, host->ioaddr + reg); 4967e29c306SWolfram Sang } 4977e29c306SWolfram Sang 49895f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 49995f25efeSWolfram Sang { 500ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 501070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 5020322191eSDong Aisheng u16 ret = 0; 5030322191eSDong Aisheng u32 val; 504ef4d0888SShawn Guo 50595a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 506ef4d0888SShawn Guo reg ^= 2; 5079d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 50895a2482aSShawn Guo /* 509ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 510ef4d0888SShawn Guo * Correct it here. 51195a2482aSShawn Guo */ 512ef4d0888SShawn Guo return SDHCI_SPEC_300; 513ef4d0888SShawn Guo } 51495a2482aSShawn Guo } 51595f25efeSWolfram Sang 5160322191eSDong Aisheng if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 5170322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 5180322191eSDong Aisheng if (val & ESDHC_VENDOR_SPEC_VSELECT) 5190322191eSDong Aisheng ret |= SDHCI_CTRL_VDD_180; 5200322191eSDong Aisheng 5219d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 5226e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 5230322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_MIX_CTRL); 5246e9fd28eSDong Aisheng else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 5256e9fd28eSDong Aisheng /* the std tuning bits is in ACMD12_ERR for imx6sl */ 526869f8a69SAdrian Hunter val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 5276e9fd28eSDong Aisheng } 5286e9fd28eSDong Aisheng 5290322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_EXE_TUNE) 5300322191eSDong Aisheng ret |= SDHCI_CTRL_EXEC_TUNING; 5310322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 5320322191eSDong Aisheng ret |= SDHCI_CTRL_TUNED_CLK; 5330322191eSDong Aisheng 5340322191eSDong Aisheng ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 5350322191eSDong Aisheng 5360322191eSDong Aisheng return ret; 5370322191eSDong Aisheng } 5380322191eSDong Aisheng 5397dd109efSDong Aisheng if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 5407dd109efSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 5417dd109efSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 5427dd109efSDong Aisheng ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 5437dd109efSDong Aisheng /* Swap AC23 bit */ 5447dd109efSDong Aisheng if (m & ESDHC_MIX_CTRL_AC23EN) { 5457dd109efSDong Aisheng ret &= ~ESDHC_MIX_CTRL_AC23EN; 5467dd109efSDong Aisheng ret |= SDHCI_TRNS_AUTO_CMD23; 5477dd109efSDong Aisheng } 5487dd109efSDong Aisheng } else { 5497dd109efSDong Aisheng ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 5507dd109efSDong Aisheng } 5517dd109efSDong Aisheng 5527dd109efSDong Aisheng return ret; 5537dd109efSDong Aisheng } 5547dd109efSDong Aisheng 55595f25efeSWolfram Sang return readw(host->ioaddr + reg); 55695f25efeSWolfram Sang } 55795f25efeSWolfram Sang 55895f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 55995f25efeSWolfram Sang { 56095f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 561070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 5620322191eSDong Aisheng u32 new_val = 0; 56395f25efeSWolfram Sang 56495f25efeSWolfram Sang switch (reg) { 5650322191eSDong Aisheng case SDHCI_CLOCK_CONTROL: 5660322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 5670322191eSDong Aisheng if (val & SDHCI_CLOCK_CARD_EN) 5680322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 5690322191eSDong Aisheng else 5700322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 5710322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 572f581e909SHaibo Chen if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON)) 573f581e909SHaibo Chen esdhc_wait_for_card_clock_gate_off(host); 5740322191eSDong Aisheng return; 5750322191eSDong Aisheng case SDHCI_HOST_CONTROL2: 5760322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 5770322191eSDong Aisheng if (val & SDHCI_CTRL_VDD_180) 5780322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_VSELECT; 5790322191eSDong Aisheng else 5800322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 5810322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 5826e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 5830322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 584da0295ffSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 5850322191eSDong Aisheng new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 586da0295ffSDong Aisheng new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 587da0295ffSDong Aisheng } else { 5880322191eSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 589da0295ffSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 590da0295ffSDong Aisheng } 5910322191eSDong Aisheng writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 5926e9fd28eSDong Aisheng } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 593869f8a69SAdrian Hunter u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 5946e9fd28eSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 5958b2bb0adSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 5968b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 5976e9fd28eSDong Aisheng } else { 5988b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 5996e9fd28eSDong Aisheng m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 6000b330e38SDong Aisheng m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 6016e9fd28eSDong Aisheng } 6026e9fd28eSDong Aisheng 6038b2bb0adSDong Aisheng if (val & SDHCI_CTRL_EXEC_TUNING) { 6048b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_EXE_TUNE; 6058b2bb0adSDong Aisheng m |= ESDHC_MIX_CTRL_FBCLK_SEL; 6060b330e38SDong Aisheng m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 6078b2bb0adSDong Aisheng } else { 6088b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 6098b2bb0adSDong Aisheng } 6106e9fd28eSDong Aisheng 611869f8a69SAdrian Hunter writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 6126e9fd28eSDong Aisheng writel(m, host->ioaddr + ESDHC_MIX_CTRL); 6136e9fd28eSDong Aisheng } 6140322191eSDong Aisheng return; 61595f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 616f47c4bbfSShawn Guo if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 61758ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 61858ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 61958ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 62058ac8177SRichard Zhu u32 v; 62160bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 62260bf6396SShawn Guo v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 62360bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 62458ac8177SRichard Zhu } 62569f54698SShawn Guo 6269d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 6273fbd4322SAndrew Gabbasov u32 wml; 62869f54698SShawn Guo u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 6292a15f981SShawn Guo /* Swap AC23 bit */ 6302a15f981SShawn Guo if (val & SDHCI_TRNS_AUTO_CMD23) { 6312a15f981SShawn Guo val &= ~SDHCI_TRNS_AUTO_CMD23; 6322a15f981SShawn Guo val |= ESDHC_MIX_CTRL_AC23EN; 6332a15f981SShawn Guo } 6342a15f981SShawn Guo m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 63569f54698SShawn Guo writel(m, host->ioaddr + ESDHC_MIX_CTRL); 6363fbd4322SAndrew Gabbasov 6373fbd4322SAndrew Gabbasov /* Set watermark levels for PIO access to maximum value 6383fbd4322SAndrew Gabbasov * (128 words) to accommodate full 512 bytes buffer. 6393fbd4322SAndrew Gabbasov * For DMA access restore the levels to default value. 6403fbd4322SAndrew Gabbasov */ 6413fbd4322SAndrew Gabbasov m = readl(host->ioaddr + ESDHC_WTMK_LVL); 642e534b82fSHaibo Chen if (val & SDHCI_TRNS_DMA) { 6433fbd4322SAndrew Gabbasov wml = ESDHC_WTMK_LVL_WML_VAL_DEF; 644e534b82fSHaibo Chen } else { 645e534b82fSHaibo Chen u8 ctrl; 6463fbd4322SAndrew Gabbasov wml = ESDHC_WTMK_LVL_WML_VAL_MAX; 647e534b82fSHaibo Chen 648e534b82fSHaibo Chen /* 649e534b82fSHaibo Chen * Since already disable DMA mode, so also need 650e534b82fSHaibo Chen * to clear the DMASEL. Otherwise, for standard 651e534b82fSHaibo Chen * tuning, when send tuning command, usdhc will 652e534b82fSHaibo Chen * still prefetch the ADMA script from wrong 653e534b82fSHaibo Chen * DMA address, then we will see IOMMU report 654e534b82fSHaibo Chen * some error which show lack of TLB mapping. 655e534b82fSHaibo Chen */ 656e534b82fSHaibo Chen ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 657e534b82fSHaibo Chen ctrl &= ~SDHCI_CTRL_DMA_MASK; 658e534b82fSHaibo Chen sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 659e534b82fSHaibo Chen } 6603fbd4322SAndrew Gabbasov m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK | 6613fbd4322SAndrew Gabbasov ESDHC_WTMK_LVL_WR_WML_MASK); 6623fbd4322SAndrew Gabbasov m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) | 6633fbd4322SAndrew Gabbasov (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT); 6643fbd4322SAndrew Gabbasov writel(m, host->ioaddr + ESDHC_WTMK_LVL); 66569f54698SShawn Guo } else { 66669f54698SShawn Guo /* 66769f54698SShawn Guo * Postpone this write, we must do it together with a 66869f54698SShawn Guo * command write that is down below. 66969f54698SShawn Guo */ 670e149860dSRichard Zhu imx_data->scratchpad = val; 67169f54698SShawn Guo } 67295f25efeSWolfram Sang return; 67395f25efeSWolfram Sang case SDHCI_COMMAND: 674361b8482SLucas Stach if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 67558ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 67695a2482aSShawn Guo 677361b8482SLucas Stach if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 678f47c4bbfSShawn Guo (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 679361b8482SLucas Stach imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 680361b8482SLucas Stach 6819d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 68295a2482aSShawn Guo writel(val << 16, 68395a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 68469f54698SShawn Guo else 685e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 68695f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 68795f25efeSWolfram Sang return; 68895f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 68995f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 69095f25efeSWolfram Sang break; 69195f25efeSWolfram Sang } 69295f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 69395f25efeSWolfram Sang } 69495f25efeSWolfram Sang 69577da3da0SAaron Brice static u8 esdhc_readb_le(struct sdhci_host *host, int reg) 69677da3da0SAaron Brice { 69777da3da0SAaron Brice u8 ret; 69877da3da0SAaron Brice u32 val; 69977da3da0SAaron Brice 70077da3da0SAaron Brice switch (reg) { 70177da3da0SAaron Brice case SDHCI_HOST_CONTROL: 70277da3da0SAaron Brice val = readl(host->ioaddr + reg); 70377da3da0SAaron Brice 70477da3da0SAaron Brice ret = val & SDHCI_CTRL_LED; 70577da3da0SAaron Brice ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; 70677da3da0SAaron Brice ret |= (val & ESDHC_CTRL_4BITBUS); 70777da3da0SAaron Brice ret |= (val & ESDHC_CTRL_8BITBUS) << 3; 70877da3da0SAaron Brice return ret; 70977da3da0SAaron Brice } 71077da3da0SAaron Brice 71177da3da0SAaron Brice return readb(host->ioaddr + reg); 71277da3da0SAaron Brice } 71377da3da0SAaron Brice 71495f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 71595f25efeSWolfram Sang { 7169a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 717070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 71881a0a8bcSBenoît Thébaudeau u32 new_val = 0; 719af51079eSSascha Hauer u32 mask; 72095f25efeSWolfram Sang 72195f25efeSWolfram Sang switch (reg) { 72295f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 72395f25efeSWolfram Sang /* 72495f25efeSWolfram Sang * FSL put some DMA bits here 72595f25efeSWolfram Sang * If your board has a regulator, code should be here 72695f25efeSWolfram Sang */ 72795f25efeSWolfram Sang return; 72895f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 7296b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 730af51079eSSascha Hauer new_val = val & SDHCI_CTRL_LED; 7317122bbb0SMasanari Iida /* ensure the endianness */ 73295f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 7339a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 7349a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 73595f25efeSWolfram Sang /* DMA mode bits are shifted */ 73695f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 7379a0985b7SWilson Callan } 73895f25efeSWolfram Sang 739af51079eSSascha Hauer /* 740af51079eSSascha Hauer * Do not touch buswidth bits here. This is done in 741af51079eSSascha Hauer * esdhc_pltfm_bus_width. 742f6825748SMartin Fuzzey * Do not touch the D3CD bit either which is used for the 743d04f8d5bSBenoît Thébaudeau * SDIO interrupt erratum workaround. 744af51079eSSascha Hauer */ 745f6825748SMartin Fuzzey mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 746af51079eSSascha Hauer 747af51079eSSascha Hauer esdhc_clrset_le(host, mask, new_val, reg); 74895f25efeSWolfram Sang return; 74981a0a8bcSBenoît Thébaudeau case SDHCI_SOFTWARE_RESET: 75081a0a8bcSBenoît Thébaudeau if (val & SDHCI_RESET_DATA) 75181a0a8bcSBenoît Thébaudeau new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); 75281a0a8bcSBenoît Thébaudeau break; 75395f25efeSWolfram Sang } 75495f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 755913413c3SShawn Guo 75681a0a8bcSBenoît Thébaudeau if (reg == SDHCI_SOFTWARE_RESET) { 75781a0a8bcSBenoît Thébaudeau if (val & SDHCI_RESET_ALL) { 758913413c3SShawn Guo /* 75981a0a8bcSBenoît Thébaudeau * The esdhc has a design violation to SDHC spec which 76081a0a8bcSBenoît Thébaudeau * tells that software reset should not affect card 76181a0a8bcSBenoît Thébaudeau * detection circuit. But esdhc clears its SYSCTL 76281a0a8bcSBenoît Thébaudeau * register bits [0..2] during the software reset. This 76381a0a8bcSBenoît Thébaudeau * will stop those clocks that card detection circuit 76481a0a8bcSBenoît Thébaudeau * relies on. To work around it, we turn the clocks on 76581a0a8bcSBenoît Thébaudeau * back to keep card detection circuit functional. 766913413c3SShawn Guo */ 767913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 76858c8c4fbSShawn Guo /* 76958c8c4fbSShawn Guo * The reset on usdhc fails to clear MIX_CTRL register. 77058c8c4fbSShawn Guo * Do it manually here. 77158c8c4fbSShawn Guo */ 772de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 77381a0a8bcSBenoît Thébaudeau /* 77481a0a8bcSBenoît Thébaudeau * the tuning bits should be kept during reset 77581a0a8bcSBenoît Thébaudeau */ 776d131a71cSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 777d131a71cSDong Aisheng writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 778d131a71cSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 779de5bdbffSDong Aisheng imx_data->is_ddr = 0; 780de5bdbffSDong Aisheng } 78181a0a8bcSBenoît Thébaudeau } else if (val & SDHCI_RESET_DATA) { 78281a0a8bcSBenoît Thébaudeau /* 78381a0a8bcSBenoît Thébaudeau * The eSDHC DAT line software reset clears at least the 78481a0a8bcSBenoît Thébaudeau * data transfer width on i.MX25, so make sure that the 78581a0a8bcSBenoît Thébaudeau * Host Control register is unaffected. 78681a0a8bcSBenoît Thébaudeau */ 78781a0a8bcSBenoît Thébaudeau esdhc_clrset_le(host, 0xff, new_val, 78881a0a8bcSBenoît Thébaudeau SDHCI_HOST_CONTROL); 78981a0a8bcSBenoît Thébaudeau } 79058c8c4fbSShawn Guo } 79195f25efeSWolfram Sang } 79295f25efeSWolfram Sang 7930ddf03c9SLucas Stach static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 7940ddf03c9SLucas Stach { 7950ddf03c9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 7960ddf03c9SLucas Stach 797a974862fSDong Aisheng return pltfm_host->clock; 7980ddf03c9SLucas Stach } 7990ddf03c9SLucas Stach 80095f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 80195f25efeSWolfram Sang { 80295f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 80395f25efeSWolfram Sang 804a974862fSDong Aisheng return pltfm_host->clock / 256 / 16; 80595f25efeSWolfram Sang } 80695f25efeSWolfram Sang 8078ba9580aSLucas Stach static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 8088ba9580aSLucas Stach unsigned int clock) 8098ba9580aSLucas Stach { 8108ba9580aSLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 811070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 812a974862fSDong Aisheng unsigned int host_clock = pltfm_host->clock; 8135143c953SBenoît Thébaudeau int ddr_pre_div = imx_data->is_ddr ? 2 : 1; 8145143c953SBenoît Thébaudeau int pre_div = 1; 815d31fc00aSDong Aisheng int div = 1; 816f581e909SHaibo Chen int ret; 817fed2f6e2SDong Aisheng u32 temp, val; 8188ba9580aSLucas Stach 8199d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 820fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 821fed2f6e2SDong Aisheng writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 822fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 823f581e909SHaibo Chen esdhc_wait_for_card_clock_gate_off(host); 824fed2f6e2SDong Aisheng } 82573e736f8SStefan Agner 82673e736f8SStefan Agner if (clock == 0) { 82773e736f8SStefan Agner host->mmc->actual_clock = 0; 828373073efSRussell King return; 829fed2f6e2SDong Aisheng } 830d31fc00aSDong Aisheng 831499ed50fSBenoît Thébaudeau /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ 832499ed50fSBenoît Thébaudeau if (is_imx53_esdhc(imx_data)) { 833499ed50fSBenoît Thébaudeau /* 834499ed50fSBenoît Thébaudeau * According to the i.MX53 reference manual, if DLLCTRL[10] can 835499ed50fSBenoît Thébaudeau * be set, then the controller is eSDHCv3, else it is eSDHCv2. 836499ed50fSBenoît Thébaudeau */ 837499ed50fSBenoît Thébaudeau val = readl(host->ioaddr + ESDHC_DLL_CTRL); 838499ed50fSBenoît Thébaudeau writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); 839499ed50fSBenoît Thébaudeau temp = readl(host->ioaddr + ESDHC_DLL_CTRL); 840499ed50fSBenoît Thébaudeau writel(val, host->ioaddr + ESDHC_DLL_CTRL); 841499ed50fSBenoît Thébaudeau if (temp & BIT(10)) 842499ed50fSBenoît Thébaudeau pre_div = 2; 843499ed50fSBenoît Thébaudeau } 844499ed50fSBenoît Thébaudeau 845d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 846d31fc00aSDong Aisheng temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 847d31fc00aSDong Aisheng | ESDHC_CLOCK_MASK); 848d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 849d31fc00aSDong Aisheng 850af6a50d4SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) { 851af6a50d4SBOUGH CHEN unsigned int max_clock; 852af6a50d4SBOUGH CHEN 853af6a50d4SBOUGH CHEN max_clock = imx_data->is_ddr ? 45000000 : 150000000; 854af6a50d4SBOUGH CHEN 855af6a50d4SBOUGH CHEN clock = min(clock, max_clock); 856af6a50d4SBOUGH CHEN } 857af6a50d4SBOUGH CHEN 8585143c953SBenoît Thébaudeau while (host_clock / (16 * pre_div * ddr_pre_div) > clock && 8595143c953SBenoît Thébaudeau pre_div < 256) 860d31fc00aSDong Aisheng pre_div *= 2; 861d31fc00aSDong Aisheng 8625143c953SBenoît Thébaudeau while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16) 863d31fc00aSDong Aisheng div++; 864d31fc00aSDong Aisheng 8655143c953SBenoît Thébaudeau host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); 866d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 867e76b8559SDong Aisheng clock, host->mmc->actual_clock); 868d31fc00aSDong Aisheng 869d31fc00aSDong Aisheng pre_div >>= 1; 870d31fc00aSDong Aisheng div--; 871d31fc00aSDong Aisheng 872d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 873d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 874d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 875d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 876d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 877fed2f6e2SDong Aisheng 878f581e909SHaibo Chen /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */ 879f581e909SHaibo Chen ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp, 880f581e909SHaibo Chen (temp & ESDHC_CLOCK_STABLE), 2, 100); 881f581e909SHaibo Chen if (ret == -ETIMEDOUT) 882f581e909SHaibo Chen dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n"); 883f581e909SHaibo Chen 8849d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 885fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 886fed2f6e2SDong Aisheng writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 887fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 888fed2f6e2SDong Aisheng } 889fed2f6e2SDong Aisheng 8908ba9580aSLucas Stach } 8918ba9580aSLucas Stach 892913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 893913413c3SShawn Guo { 894842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 895070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 896842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 897913413c3SShawn Guo 898913413c3SShawn Guo switch (boarddata->wp_type) { 899913413c3SShawn Guo case ESDHC_WP_GPIO: 900fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 901913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 902913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 903913413c3SShawn Guo SDHCI_WRITE_PROTECT); 904913413c3SShawn Guo case ESDHC_WP_NONE: 905913413c3SShawn Guo break; 906913413c3SShawn Guo } 907913413c3SShawn Guo 908913413c3SShawn Guo return -ENOSYS; 909913413c3SShawn Guo } 910913413c3SShawn Guo 9112317f56cSRussell King static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 912af51079eSSascha Hauer { 913af51079eSSascha Hauer u32 ctrl; 914af51079eSSascha Hauer 915af51079eSSascha Hauer switch (width) { 916af51079eSSascha Hauer case MMC_BUS_WIDTH_8: 917af51079eSSascha Hauer ctrl = ESDHC_CTRL_8BITBUS; 918af51079eSSascha Hauer break; 919af51079eSSascha Hauer case MMC_BUS_WIDTH_4: 920af51079eSSascha Hauer ctrl = ESDHC_CTRL_4BITBUS; 921af51079eSSascha Hauer break; 922af51079eSSascha Hauer default: 923af51079eSSascha Hauer ctrl = 0; 924af51079eSSascha Hauer break; 925af51079eSSascha Hauer } 926af51079eSSascha Hauer 927af51079eSSascha Hauer esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 928af51079eSSascha Hauer SDHCI_HOST_CONTROL); 929af51079eSSascha Hauer } 930af51079eSSascha Hauer 931de3e1dd0SBOUGH CHEN static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 932de3e1dd0SBOUGH CHEN { 933de3e1dd0SBOUGH CHEN struct sdhci_host *host = mmc_priv(mmc); 934de3e1dd0SBOUGH CHEN 935de3e1dd0SBOUGH CHEN /* 936de3e1dd0SBOUGH CHEN * i.MX uSDHC internally already uses a fixed optimized timing for 937de3e1dd0SBOUGH CHEN * DDR50, normally does not require tuning for DDR50 mode. 938de3e1dd0SBOUGH CHEN */ 939de3e1dd0SBOUGH CHEN if (host->timing == MMC_TIMING_UHS_DDR50) 940de3e1dd0SBOUGH CHEN return 0; 941de3e1dd0SBOUGH CHEN 942de3e1dd0SBOUGH CHEN return sdhci_execute_tuning(mmc, opcode); 943de3e1dd0SBOUGH CHEN } 944de3e1dd0SBOUGH CHEN 9450322191eSDong Aisheng static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 9460322191eSDong Aisheng { 9470322191eSDong Aisheng u32 reg; 9480322191eSDong Aisheng 9490322191eSDong Aisheng /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 9500322191eSDong Aisheng mdelay(1); 9510322191eSDong Aisheng 9520322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 9530322191eSDong Aisheng reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 9540322191eSDong Aisheng ESDHC_MIX_CTRL_FBCLK_SEL; 9550322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 9560322191eSDong Aisheng writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 9570322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), 958d04f8d5bSBenoît Thébaudeau "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 9590322191eSDong Aisheng val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 9600322191eSDong Aisheng } 9610322191eSDong Aisheng 9620322191eSDong Aisheng static void esdhc_post_tuning(struct sdhci_host *host) 9630322191eSDong Aisheng { 9640322191eSDong Aisheng u32 reg; 9650322191eSDong Aisheng 9660322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 9670322191eSDong Aisheng reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 968da0295ffSDong Aisheng reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 9690322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 9700322191eSDong Aisheng } 9710322191eSDong Aisheng 9720322191eSDong Aisheng static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 9730322191eSDong Aisheng { 9740322191eSDong Aisheng int min, max, avg, ret; 9750322191eSDong Aisheng 9760322191eSDong Aisheng /* find the mininum delay first which can pass tuning */ 9770322191eSDong Aisheng min = ESDHC_TUNE_CTRL_MIN; 9780322191eSDong Aisheng while (min < ESDHC_TUNE_CTRL_MAX) { 9790322191eSDong Aisheng esdhc_prepare_tuning(host, min); 9809979dbe5SChaotian Jing if (!mmc_send_tuning(host->mmc, opcode, NULL)) 9810322191eSDong Aisheng break; 9820322191eSDong Aisheng min += ESDHC_TUNE_CTRL_STEP; 9830322191eSDong Aisheng } 9840322191eSDong Aisheng 9850322191eSDong Aisheng /* find the maxinum delay which can not pass tuning */ 9860322191eSDong Aisheng max = min + ESDHC_TUNE_CTRL_STEP; 9870322191eSDong Aisheng while (max < ESDHC_TUNE_CTRL_MAX) { 9880322191eSDong Aisheng esdhc_prepare_tuning(host, max); 9899979dbe5SChaotian Jing if (mmc_send_tuning(host->mmc, opcode, NULL)) { 9900322191eSDong Aisheng max -= ESDHC_TUNE_CTRL_STEP; 9910322191eSDong Aisheng break; 9920322191eSDong Aisheng } 9930322191eSDong Aisheng max += ESDHC_TUNE_CTRL_STEP; 9940322191eSDong Aisheng } 9950322191eSDong Aisheng 9960322191eSDong Aisheng /* use average delay to get the best timing */ 9970322191eSDong Aisheng avg = (min + max) / 2; 9980322191eSDong Aisheng esdhc_prepare_tuning(host, avg); 9999979dbe5SChaotian Jing ret = mmc_send_tuning(host->mmc, opcode, NULL); 10000322191eSDong Aisheng esdhc_post_tuning(host); 10010322191eSDong Aisheng 1002d04f8d5bSBenoît Thébaudeau dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 10030322191eSDong Aisheng ret ? "failed" : "passed", avg, ret); 10040322191eSDong Aisheng 10050322191eSDong Aisheng return ret; 10060322191eSDong Aisheng } 10070322191eSDong Aisheng 1008029e2476SBOUGH CHEN static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) 1009029e2476SBOUGH CHEN { 1010029e2476SBOUGH CHEN struct sdhci_host *host = mmc_priv(mmc); 1011029e2476SBOUGH CHEN u32 m; 1012029e2476SBOUGH CHEN 1013029e2476SBOUGH CHEN m = readl(host->ioaddr + ESDHC_MIX_CTRL); 1014029e2476SBOUGH CHEN if (ios->enhanced_strobe) 1015029e2476SBOUGH CHEN m |= ESDHC_MIX_CTRL_HS400_ES_EN; 1016029e2476SBOUGH CHEN else 1017029e2476SBOUGH CHEN m &= ~ESDHC_MIX_CTRL_HS400_ES_EN; 1018029e2476SBOUGH CHEN writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1019029e2476SBOUGH CHEN } 1020029e2476SBOUGH CHEN 1021ad93220dSDong Aisheng static int esdhc_change_pinstate(struct sdhci_host *host, 1022ad93220dSDong Aisheng unsigned int uhs) 1023ad93220dSDong Aisheng { 1024ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1025070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1026ad93220dSDong Aisheng struct pinctrl_state *pinctrl; 1027ad93220dSDong Aisheng 1028ad93220dSDong Aisheng dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 1029ad93220dSDong Aisheng 1030ad93220dSDong Aisheng if (IS_ERR(imx_data->pinctrl) || 1031ad93220dSDong Aisheng IS_ERR(imx_data->pins_100mhz) || 1032ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) 1033ad93220dSDong Aisheng return -EINVAL; 1034ad93220dSDong Aisheng 1035ad93220dSDong Aisheng switch (uhs) { 1036ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 10379f327845SHaibo Chen case MMC_TIMING_UHS_DDR50: 1038ad93220dSDong Aisheng pinctrl = imx_data->pins_100mhz; 1039ad93220dSDong Aisheng break; 1040ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 1041429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 104228b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 1043ad93220dSDong Aisheng pinctrl = imx_data->pins_200mhz; 1044ad93220dSDong Aisheng break; 1045ad93220dSDong Aisheng default: 1046ad93220dSDong Aisheng /* back to default state for other legacy timing */ 10472480b720SUlf Hansson return pinctrl_select_default_state(mmc_dev(host->mmc)); 1048ad93220dSDong Aisheng } 1049ad93220dSDong Aisheng 1050ad93220dSDong Aisheng return pinctrl_select_state(imx_data->pinctrl, pinctrl); 1051ad93220dSDong Aisheng } 1052ad93220dSDong Aisheng 105328b07674SHaibo Chen /* 1054d04f8d5bSBenoît Thébaudeau * For HS400 eMMC, there is a data_strobe line. This signal is generated 105528b07674SHaibo Chen * by the device and used for data output and CRC status response output 105628b07674SHaibo Chen * in HS400 mode. The frequency of this signal follows the frequency of 1057d04f8d5bSBenoît Thébaudeau * CLK generated by host. The host receives the data which is aligned to the 105828b07674SHaibo Chen * edge of data_strobe line. Due to the time delay between CLK line and 105928b07674SHaibo Chen * data_strobe line, if the delay time is larger than one clock cycle, 1060d04f8d5bSBenoît Thébaudeau * then CLK and data_strobe line will be misaligned, read error shows up. 106128b07674SHaibo Chen */ 106228b07674SHaibo Chen static void esdhc_set_strobe_dll(struct sdhci_host *host) 106328b07674SHaibo Chen { 10645bd2acdcSHaibo Chen struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 10655bd2acdcSHaibo Chen struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 10665bd2acdcSHaibo Chen u32 strobe_delay; 106728b07674SHaibo Chen u32 v; 1068373e800bSHaibo Chen int ret; 106928b07674SHaibo Chen 10707ac6da26SDong Aisheng /* disable clock before enabling strobe dll */ 10717ac6da26SDong Aisheng writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & 10727ac6da26SDong Aisheng ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 10737ac6da26SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 1074f581e909SHaibo Chen esdhc_wait_for_card_clock_gate_off(host); 10757ac6da26SDong Aisheng 107628b07674SHaibo Chen /* force a reset on strobe dll */ 107728b07674SHaibo Chen writel(ESDHC_STROBE_DLL_CTRL_RESET, 107828b07674SHaibo Chen host->ioaddr + ESDHC_STROBE_DLL_CTRL); 10792eaf5a53SBOUGH CHEN /* clear the reset bit on strobe dll before any setting */ 10802eaf5a53SBOUGH CHEN writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 10812eaf5a53SBOUGH CHEN 108228b07674SHaibo Chen /* 108328b07674SHaibo Chen * enable strobe dll ctrl and adjust the delay target 108428b07674SHaibo Chen * for the uSDHC loopback read clock 108528b07674SHaibo Chen */ 10865bd2acdcSHaibo Chen if (imx_data->boarddata.strobe_dll_delay_target) 10875bd2acdcSHaibo Chen strobe_delay = imx_data->boarddata.strobe_dll_delay_target; 10885bd2acdcSHaibo Chen else 10895bd2acdcSHaibo Chen strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT; 109028b07674SHaibo Chen v = ESDHC_STROBE_DLL_CTRL_ENABLE | 10912eaf5a53SBOUGH CHEN ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT | 10925bd2acdcSHaibo Chen (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 109328b07674SHaibo Chen writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 1094373e800bSHaibo Chen 1095373e800bSHaibo Chen /* wait max 50us to get the REF/SLV lock */ 1096373e800bSHaibo Chen ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v, 1097373e800bSHaibo Chen ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50); 1098373e800bSHaibo Chen if (ret == -ETIMEDOUT) 109928b07674SHaibo Chen dev_warn(mmc_dev(host->mmc), 1100373e800bSHaibo Chen "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v); 110128b07674SHaibo Chen } 110228b07674SHaibo Chen 1103d9370424SHaibo Chen static void esdhc_reset_tuning(struct sdhci_host *host) 1104d9370424SHaibo Chen { 1105d9370424SHaibo Chen struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1106d9370424SHaibo Chen struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1107d9370424SHaibo Chen u32 ctrl; 1108d9370424SHaibo Chen 1109d04f8d5bSBenoît Thébaudeau /* Reset the tuning circuit */ 1110d9370424SHaibo Chen if (esdhc_is_usdhc(imx_data)) { 1111d9370424SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1112d9370424SHaibo Chen ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); 1113d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1114d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 1115d9370424SHaibo Chen writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 1116d9370424SHaibo Chen writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1117d9370424SHaibo Chen } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1118869f8a69SAdrian Hunter ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1119d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1120869f8a69SAdrian Hunter writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1121d9370424SHaibo Chen } 1122d9370424SHaibo Chen } 1123d9370424SHaibo Chen } 1124d9370424SHaibo Chen 1125850a29b8SRussell King static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1126ad93220dSDong Aisheng { 112728b07674SHaibo Chen u32 m; 1128ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1129070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1130602519b2SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1131ad93220dSDong Aisheng 113228b07674SHaibo Chen /* disable ddr mode and disable HS400 mode */ 113328b07674SHaibo Chen m = readl(host->ioaddr + ESDHC_MIX_CTRL); 113428b07674SHaibo Chen m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); 113528b07674SHaibo Chen imx_data->is_ddr = 0; 113628b07674SHaibo Chen 1137850a29b8SRussell King switch (timing) { 1138ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR12: 1139ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR25: 1140ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 1141ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 1142de0a0decSBOUGH CHEN case MMC_TIMING_MMC_HS: 1143429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 114428b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1145ad93220dSDong Aisheng break; 1146ad93220dSDong Aisheng case MMC_TIMING_UHS_DDR50: 114769f5bf38SAisheng Dong case MMC_TIMING_MMC_DDR52: 114828b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN; 114928b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1150de5bdbffSDong Aisheng imx_data->is_ddr = 1; 1151602519b2SDong Aisheng if (boarddata->delay_line) { 1152602519b2SDong Aisheng u32 v; 1153602519b2SDong Aisheng v = boarddata->delay_line << 1154602519b2SDong Aisheng ESDHC_DLL_OVERRIDE_VAL_SHIFT | 1155602519b2SDong Aisheng (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 1156602519b2SDong Aisheng if (is_imx53_esdhc(imx_data)) 1157602519b2SDong Aisheng v <<= 1; 1158602519b2SDong Aisheng writel(v, host->ioaddr + ESDHC_DLL_CTRL); 1159602519b2SDong Aisheng } 1160ad93220dSDong Aisheng break; 116128b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 116228b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 116328b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 116428b07674SHaibo Chen imx_data->is_ddr = 1; 11657ac6da26SDong Aisheng /* update clock after enable DDR for strobe DLL lock */ 11667ac6da26SDong Aisheng host->ops->set_clock(host, host->clock); 116728b07674SHaibo Chen esdhc_set_strobe_dll(host); 116828b07674SHaibo Chen break; 1169d9370424SHaibo Chen case MMC_TIMING_LEGACY: 1170d9370424SHaibo Chen default: 1171d9370424SHaibo Chen esdhc_reset_tuning(host); 1172d9370424SHaibo Chen break; 1173ad93220dSDong Aisheng } 1174ad93220dSDong Aisheng 1175850a29b8SRussell King esdhc_change_pinstate(host, timing); 1176ad93220dSDong Aisheng } 1177ad93220dSDong Aisheng 11780718e59aSRussell King static void esdhc_reset(struct sdhci_host *host, u8 mask) 11790718e59aSRussell King { 11800718e59aSRussell King sdhci_reset(host, mask); 11810718e59aSRussell King 11820718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 11830718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 11840718e59aSRussell King } 11850718e59aSRussell King 118610fd0ad9SAisheng Dong static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 118710fd0ad9SAisheng Dong { 118810fd0ad9SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1189070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 119010fd0ad9SAisheng Dong 1191d04f8d5bSBenoît Thébaudeau /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */ 11922fb0b02bSHaibo Chen return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27; 119310fd0ad9SAisheng Dong } 119410fd0ad9SAisheng Dong 1195e33eb8e2SAisheng Dong static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 1196e33eb8e2SAisheng Dong { 1197e33eb8e2SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1198070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1199e33eb8e2SAisheng Dong 1200e33eb8e2SAisheng Dong /* use maximum timeout counter */ 1201a215186dSHaibo Chen esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, 1202a215186dSHaibo Chen esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 1203e33eb8e2SAisheng Dong SDHCI_TIMEOUT_CONTROL); 1204e33eb8e2SAisheng Dong } 1205e33eb8e2SAisheng Dong 1206bb6e3581SBOUGH CHEN static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask) 1207bb6e3581SBOUGH CHEN { 1208bb6e3581SBOUGH CHEN int cmd_error = 0; 1209bb6e3581SBOUGH CHEN int data_error = 0; 1210bb6e3581SBOUGH CHEN 1211bb6e3581SBOUGH CHEN if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1212bb6e3581SBOUGH CHEN return intmask; 1213bb6e3581SBOUGH CHEN 1214bb6e3581SBOUGH CHEN cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1215bb6e3581SBOUGH CHEN 1216bb6e3581SBOUGH CHEN return 0; 1217bb6e3581SBOUGH CHEN } 1218bb6e3581SBOUGH CHEN 12196e9fd28eSDong Aisheng static struct sdhci_ops sdhci_esdhc_ops = { 1220e149860dSRichard Zhu .read_l = esdhc_readl_le, 12210c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 122277da3da0SAaron Brice .read_b = esdhc_readb_le, 1223e149860dSRichard Zhu .write_l = esdhc_writel_le, 12240c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 12250c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 12268ba9580aSLucas Stach .set_clock = esdhc_pltfm_set_clock, 12270ddf03c9SLucas Stach .get_max_clock = esdhc_pltfm_get_max_clock, 12280c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 122910fd0ad9SAisheng Dong .get_max_timeout_count = esdhc_get_max_timeout_count, 1230913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 1231e33eb8e2SAisheng Dong .set_timeout = esdhc_set_timeout, 12322317f56cSRussell King .set_bus_width = esdhc_pltfm_set_bus_width, 1233ad93220dSDong Aisheng .set_uhs_signaling = esdhc_set_uhs_signaling, 12340718e59aSRussell King .reset = esdhc_reset, 1235bb6e3581SBOUGH CHEN .irq = esdhc_cqhci_irq, 12360c6d49ceSWolfram Sang }; 12370c6d49ceSWolfram Sang 12381db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 123997e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 124097e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 124197e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 124285d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 124385d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 124485d6509dSShawn Guo }; 124585d6509dSShawn Guo 1246f3f5cf3dSDong Aisheng static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) 1247f3f5cf3dSDong Aisheng { 1248f3f5cf3dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1249f3f5cf3dSDong Aisheng struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1250982cf37dSHaibo Chen struct cqhci_host *cq_host = host->mmc->cqe_private; 12512b16cf32SDong Aisheng int tmp; 1252f3f5cf3dSDong Aisheng 1253f3f5cf3dSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 1254f3f5cf3dSDong Aisheng /* 1255f3f5cf3dSDong Aisheng * The imx6q ROM code will change the default watermark 1256f3f5cf3dSDong Aisheng * level setting to something insane. Change it back here. 1257f3f5cf3dSDong Aisheng */ 1258f3f5cf3dSDong Aisheng writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); 1259f3f5cf3dSDong Aisheng 1260f3f5cf3dSDong Aisheng /* 1261f3f5cf3dSDong Aisheng * ROM code will change the bit burst_length_enable setting 1262d04f8d5bSBenoît Thébaudeau * to zero if this usdhc is chosen to boot system. Change 1263f3f5cf3dSDong Aisheng * it back here, otherwise it will impact the performance a 1264f3f5cf3dSDong Aisheng * lot. This bit is used to enable/disable the burst length 1265d04f8d5bSBenoît Thébaudeau * for the external AHB2AXI bridge. It's useful especially 1266f3f5cf3dSDong Aisheng * for INCR transfer because without burst length indicator, 1267f3f5cf3dSDong Aisheng * the AHB2AXI bridge does not know the burst length in 1268f3f5cf3dSDong Aisheng * advance. And without burst length indicator, AHB INCR 1269f3f5cf3dSDong Aisheng * transfer can only be converted to singles on the AXI side. 1270f3f5cf3dSDong Aisheng */ 1271f3f5cf3dSDong Aisheng writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) 1272f3f5cf3dSDong Aisheng | ESDHC_BURST_LEN_EN_INCR, 1273f3f5cf3dSDong Aisheng host->ioaddr + SDHCI_HOST_CONTROL); 1274e30be063SBOUGH CHEN 1275f3f5cf3dSDong Aisheng /* 1276d04f8d5bSBenoît Thébaudeau * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 1277f3f5cf3dSDong Aisheng * TO1.1, it's harmless for MX6SL 1278f3f5cf3dSDong Aisheng */ 1279e30be063SBOUGH CHEN writel(readl(host->ioaddr + 0x6c) & ~BIT(7), 1280f3f5cf3dSDong Aisheng host->ioaddr + 0x6c); 1281f3f5cf3dSDong Aisheng 1282f3f5cf3dSDong Aisheng /* disable DLL_CTRL delay line settings */ 1283f3f5cf3dSDong Aisheng writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); 12842b16cf32SDong Aisheng 1285bcdb5301SBOUGH CHEN /* 1286bcdb5301SBOUGH CHEN * For the case of command with busy, if set the bit 1287bcdb5301SBOUGH CHEN * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a 1288bcdb5301SBOUGH CHEN * transfer complete interrupt when busy is deasserted. 1289bcdb5301SBOUGH CHEN * When CQHCI use DCMD to send a CMD need R1b respons, 1290bcdb5301SBOUGH CHEN * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ, 1291bcdb5301SBOUGH CHEN * otherwise DCMD will always meet timeout waiting for 1292bcdb5301SBOUGH CHEN * hardware interrupt issue. 1293bcdb5301SBOUGH CHEN */ 1294bcdb5301SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1295bcdb5301SBOUGH CHEN tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2); 1296bcdb5301SBOUGH CHEN tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ; 1297bcdb5301SBOUGH CHEN writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2); 1298bcdb5301SBOUGH CHEN 1299bcdb5301SBOUGH CHEN host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1300bcdb5301SBOUGH CHEN } 1301bcdb5301SBOUGH CHEN 13022b16cf32SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 13032b16cf32SDong Aisheng tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 13042b16cf32SDong Aisheng tmp |= ESDHC_STD_TUNING_EN | 13052b16cf32SDong Aisheng ESDHC_TUNING_START_TAP_DEFAULT; 13062b16cf32SDong Aisheng if (imx_data->boarddata.tuning_start_tap) { 13072b16cf32SDong Aisheng tmp &= ~ESDHC_TUNING_START_TAP_MASK; 13082b16cf32SDong Aisheng tmp |= imx_data->boarddata.tuning_start_tap; 13092b16cf32SDong Aisheng } 13102b16cf32SDong Aisheng 13112b16cf32SDong Aisheng if (imx_data->boarddata.tuning_step) { 13122b16cf32SDong Aisheng tmp &= ~ESDHC_TUNING_STEP_MASK; 13132b16cf32SDong Aisheng tmp |= imx_data->boarddata.tuning_step 13142b16cf32SDong Aisheng << ESDHC_TUNING_STEP_SHIFT; 13152b16cf32SDong Aisheng } 13162b16cf32SDong Aisheng writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1317a98c557eSBOUGH CHEN } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1318a98c557eSBOUGH CHEN /* 1319a98c557eSBOUGH CHEN * ESDHC_STD_TUNING_EN may be configed in bootloader 1320a98c557eSBOUGH CHEN * or ROM code, so clear this bit here to make sure 1321a98c557eSBOUGH CHEN * the manual tuning can work. 1322a98c557eSBOUGH CHEN */ 1323a98c557eSBOUGH CHEN tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1324a98c557eSBOUGH CHEN tmp &= ~ESDHC_STD_TUNING_EN; 1325a98c557eSBOUGH CHEN writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 13262b16cf32SDong Aisheng } 1327982cf37dSHaibo Chen 1328982cf37dSHaibo Chen /* 1329982cf37dSHaibo Chen * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card 1330982cf37dSHaibo Chen * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let the 1331982cf37dSHaibo Chen * the 1st linux configure power/clock for the 2nd Linux. 1332982cf37dSHaibo Chen * 1333982cf37dSHaibo Chen * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux 1334982cf37dSHaibo Chen * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump. 1335982cf37dSHaibo Chen * After we clear the pending interrupt and halt CQCTL, issue gone. 1336982cf37dSHaibo Chen */ 1337982cf37dSHaibo Chen if (cq_host) { 1338982cf37dSHaibo Chen tmp = cqhci_readl(cq_host, CQHCI_IS); 1339982cf37dSHaibo Chen cqhci_writel(cq_host, tmp, CQHCI_IS); 1340982cf37dSHaibo Chen cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL); 1341982cf37dSHaibo Chen } 1342f3f5cf3dSDong Aisheng } 1343f3f5cf3dSDong Aisheng } 1344f3f5cf3dSDong Aisheng 1345bb6e3581SBOUGH CHEN static void esdhc_cqe_enable(struct mmc_host *mmc) 1346bb6e3581SBOUGH CHEN { 1347bb6e3581SBOUGH CHEN struct sdhci_host *host = mmc_priv(mmc); 134885236d2bSBOUGH CHEN struct cqhci_host *cq_host = mmc->cqe_private; 1349bb6e3581SBOUGH CHEN u32 reg; 1350bb6e3581SBOUGH CHEN u16 mode; 1351bb6e3581SBOUGH CHEN int count = 10; 1352bb6e3581SBOUGH CHEN 1353bb6e3581SBOUGH CHEN /* 1354bb6e3581SBOUGH CHEN * CQE gets stuck if it sees Buffer Read Enable bit set, which can be 1355bb6e3581SBOUGH CHEN * the case after tuning, so ensure the buffer is drained. 1356bb6e3581SBOUGH CHEN */ 1357bb6e3581SBOUGH CHEN reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1358bb6e3581SBOUGH CHEN while (reg & SDHCI_DATA_AVAILABLE) { 1359bb6e3581SBOUGH CHEN sdhci_readl(host, SDHCI_BUFFER); 1360bb6e3581SBOUGH CHEN reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1361bb6e3581SBOUGH CHEN if (count-- == 0) { 1362bb6e3581SBOUGH CHEN dev_warn(mmc_dev(host->mmc), 1363bb6e3581SBOUGH CHEN "CQE may get stuck because the Buffer Read Enable bit is set\n"); 1364bb6e3581SBOUGH CHEN break; 1365bb6e3581SBOUGH CHEN } 1366bb6e3581SBOUGH CHEN mdelay(1); 1367bb6e3581SBOUGH CHEN } 1368bb6e3581SBOUGH CHEN 1369bb6e3581SBOUGH CHEN /* 1370bb6e3581SBOUGH CHEN * Runtime resume will reset the entire host controller, which 1371bb6e3581SBOUGH CHEN * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL. 1372bb6e3581SBOUGH CHEN * Here set DMAEN and BCEN when enable CMDQ. 1373bb6e3581SBOUGH CHEN */ 1374bb6e3581SBOUGH CHEN mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 1375bb6e3581SBOUGH CHEN if (host->flags & SDHCI_REQ_USE_DMA) 1376bb6e3581SBOUGH CHEN mode |= SDHCI_TRNS_DMA; 1377bb6e3581SBOUGH CHEN if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 1378bb6e3581SBOUGH CHEN mode |= SDHCI_TRNS_BLK_CNT_EN; 1379bb6e3581SBOUGH CHEN sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 1380bb6e3581SBOUGH CHEN 138185236d2bSBOUGH CHEN /* 138285236d2bSBOUGH CHEN * Though Runtime resume reset the entire host controller, 138385236d2bSBOUGH CHEN * but do not impact the CQHCI side, need to clear the 138485236d2bSBOUGH CHEN * HALT bit, avoid CQHCI stuck in the first request when 138585236d2bSBOUGH CHEN * system resume back. 138685236d2bSBOUGH CHEN */ 138785236d2bSBOUGH CHEN cqhci_writel(cq_host, 0, CQHCI_CTL); 138885236d2bSBOUGH CHEN if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT) 138985236d2bSBOUGH CHEN dev_err(mmc_dev(host->mmc), 139085236d2bSBOUGH CHEN "failed to exit halt state when enable CQE\n"); 139185236d2bSBOUGH CHEN 139285236d2bSBOUGH CHEN 1393bb6e3581SBOUGH CHEN sdhci_cqe_enable(mmc); 1394bb6e3581SBOUGH CHEN } 1395bb6e3581SBOUGH CHEN 1396bb6e3581SBOUGH CHEN static void esdhc_sdhci_dumpregs(struct mmc_host *mmc) 1397bb6e3581SBOUGH CHEN { 1398bb6e3581SBOUGH CHEN sdhci_dumpregs(mmc_priv(mmc)); 1399bb6e3581SBOUGH CHEN } 1400bb6e3581SBOUGH CHEN 1401bb6e3581SBOUGH CHEN static const struct cqhci_host_ops esdhc_cqhci_ops = { 1402bb6e3581SBOUGH CHEN .enable = esdhc_cqe_enable, 1403bb6e3581SBOUGH CHEN .disable = sdhci_cqe_disable, 1404bb6e3581SBOUGH CHEN .dumpregs = esdhc_sdhci_dumpregs, 1405bb6e3581SBOUGH CHEN }; 1406bb6e3581SBOUGH CHEN 1407abfafc2dSShawn Guo #ifdef CONFIG_OF 1408c3be1efdSBill Pemberton static int 1409abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 141007bf2b54SSascha Hauer struct sdhci_host *host, 141191fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1412abfafc2dSShawn Guo { 1413abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 141491fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 14154800e87aSDong Aisheng int ret; 1416abfafc2dSShawn Guo 1417abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 1418abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 1419abfafc2dSShawn Guo 142074ff81e1SLinus Walleij /* 142174ff81e1SLinus Walleij * If we have this property, then activate WP check. 142274ff81e1SLinus Walleij * Retrieveing and requesting the actual WP GPIO will happen 142374ff81e1SLinus Walleij * in the call to mmc_of_parse(). 142474ff81e1SLinus Walleij */ 142574ff81e1SLinus Walleij if (of_property_read_bool(np, "wp-gpios")) 1426abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 1427abfafc2dSShawn Guo 1428d407e30bSHaibo Chen of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 1429d87fc966SDong Aisheng of_property_read_u32(np, "fsl,tuning-start-tap", 1430d87fc966SDong Aisheng &boarddata->tuning_start_tap); 1431d407e30bSHaibo Chen 14325bd2acdcSHaibo Chen of_property_read_u32(np, "fsl,strobe-dll-delay-target", 14335bd2acdcSHaibo Chen &boarddata->strobe_dll_delay_target); 1434ad93220dSDong Aisheng if (of_find_property(np, "no-1-8-v", NULL)) 143586f495c5SStefan Agner host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1436ad93220dSDong Aisheng 1437602519b2SDong Aisheng if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 1438602519b2SDong Aisheng boarddata->delay_line = 0; 1439602519b2SDong Aisheng 144007bf2b54SSascha Hauer mmc_of_parse_voltage(np, &host->ocr_mask); 144107bf2b54SSascha Hauer 14422480b720SUlf Hansson if (esdhc_is_usdhc(imx_data)) { 144391fa4252SDong Aisheng imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 144491fa4252SDong Aisheng ESDHC_PINCTRL_STATE_100MHZ); 144591fa4252SDong Aisheng imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 144691fa4252SDong Aisheng ESDHC_PINCTRL_STATE_200MHZ); 144791fa4252SDong Aisheng } 144891fa4252SDong Aisheng 144915064119SFabio Estevam /* call to generic mmc_of_parse to support additional capabilities */ 14504800e87aSDong Aisheng ret = mmc_of_parse(host->mmc); 14514800e87aSDong Aisheng if (ret) 14524800e87aSDong Aisheng return ret; 14534800e87aSDong Aisheng 1454287980e4SArnd Bergmann if (mmc_gpio_get_cd(host->mmc) >= 0) 14554800e87aSDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 14564800e87aSDong Aisheng 14574800e87aSDong Aisheng return 0; 1458abfafc2dSShawn Guo } 1459abfafc2dSShawn Guo #else 1460abfafc2dSShawn Guo static inline int 1461abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 146207bf2b54SSascha Hauer struct sdhci_host *host, 146391fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1464abfafc2dSShawn Guo { 1465abfafc2dSShawn Guo return -ENODEV; 1466abfafc2dSShawn Guo } 1467abfafc2dSShawn Guo #endif 1468abfafc2dSShawn Guo 146991fa4252SDong Aisheng static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev, 147091fa4252SDong Aisheng struct sdhci_host *host, 147191fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 147291fa4252SDong Aisheng { 147391fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 147491fa4252SDong Aisheng int err; 147591fa4252SDong Aisheng 147691fa4252SDong Aisheng if (!host->mmc->parent->platform_data) { 147791fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), "no board data!\n"); 147891fa4252SDong Aisheng return -EINVAL; 147991fa4252SDong Aisheng } 148091fa4252SDong Aisheng 148191fa4252SDong Aisheng imx_data->boarddata = *((struct esdhc_platform_data *) 148291fa4252SDong Aisheng host->mmc->parent->platform_data); 148391fa4252SDong Aisheng /* write_protect */ 148491fa4252SDong Aisheng if (boarddata->wp_type == ESDHC_WP_GPIO) { 14859073d10bSMichał Mirosław host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 14869073d10bSMichał Mirosław 1487d0052ad9SMichał Mirosław err = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0); 148891fa4252SDong Aisheng if (err) { 148991fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 149091fa4252SDong Aisheng "failed to request write-protect gpio!\n"); 149191fa4252SDong Aisheng return err; 149291fa4252SDong Aisheng } 149391fa4252SDong Aisheng } 149491fa4252SDong Aisheng 149591fa4252SDong Aisheng /* card_detect */ 149691fa4252SDong Aisheng switch (boarddata->cd_type) { 149791fa4252SDong Aisheng case ESDHC_CD_GPIO: 1498d0052ad9SMichał Mirosław err = mmc_gpiod_request_cd(host->mmc, "cd", 0, false, 0); 149991fa4252SDong Aisheng if (err) { 150091fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 150191fa4252SDong Aisheng "failed to request card-detect gpio!\n"); 150291fa4252SDong Aisheng return err; 150391fa4252SDong Aisheng } 150491fa4252SDong Aisheng /* fall through */ 150591fa4252SDong Aisheng 150691fa4252SDong Aisheng case ESDHC_CD_CONTROLLER: 150791fa4252SDong Aisheng /* we have a working card_detect back */ 150891fa4252SDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 150991fa4252SDong Aisheng break; 151091fa4252SDong Aisheng 151191fa4252SDong Aisheng case ESDHC_CD_PERMANENT: 151291fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_NONREMOVABLE; 151391fa4252SDong Aisheng break; 151491fa4252SDong Aisheng 151591fa4252SDong Aisheng case ESDHC_CD_NONE: 151691fa4252SDong Aisheng break; 151791fa4252SDong Aisheng } 151891fa4252SDong Aisheng 151991fa4252SDong Aisheng switch (boarddata->max_bus_width) { 152091fa4252SDong Aisheng case 8: 152191fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 152291fa4252SDong Aisheng break; 152391fa4252SDong Aisheng case 4: 152491fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_4_BIT_DATA; 152591fa4252SDong Aisheng break; 152691fa4252SDong Aisheng case 1: 152791fa4252SDong Aisheng default: 152891fa4252SDong Aisheng host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 152991fa4252SDong Aisheng break; 153091fa4252SDong Aisheng } 153191fa4252SDong Aisheng 153291fa4252SDong Aisheng return 0; 153391fa4252SDong Aisheng } 153491fa4252SDong Aisheng 1535c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 153695f25efeSWolfram Sang { 1537abfafc2dSShawn Guo const struct of_device_id *of_id = 1538abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 153985d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 154085d6509dSShawn Guo struct sdhci_host *host; 1541bb6e3581SBOUGH CHEN struct cqhci_host *cq_host; 15420c6d49ceSWolfram Sang int err; 1543e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 154495f25efeSWolfram Sang 1545070e6d3fSJisheng Zhang host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 1546070e6d3fSJisheng Zhang sizeof(*imx_data)); 154785d6509dSShawn Guo if (IS_ERR(host)) 154885d6509dSShawn Guo return PTR_ERR(host); 154985d6509dSShawn Guo 155085d6509dSShawn Guo pltfm_host = sdhci_priv(host); 155185d6509dSShawn Guo 1552070e6d3fSJisheng Zhang imx_data = sdhci_pltfm_priv(pltfm_host); 155357ed3314SShawn Guo 1554f47c4bbfSShawn Guo imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 15553770ee8fSShawn Guo pdev->id_entry->driver_data; 155685d6509dSShawn Guo 15571c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 15581c4989b0SBOUGH CHEN pm_qos_add_request(&imx_data->pm_qos_req, 15591c4989b0SBOUGH CHEN PM_QOS_CPU_DMA_LATENCY, 0); 15601c4989b0SBOUGH CHEN 156152dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 156252dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 156352dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 1564e3af31c6SShawn Guo goto free_sdhci; 156595f25efeSWolfram Sang } 156652dac615SSascha Hauer 156752dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 156852dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 156952dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 1570e3af31c6SShawn Guo goto free_sdhci; 157152dac615SSascha Hauer } 157252dac615SSascha Hauer 157352dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 157452dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 157552dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 1576e3af31c6SShawn Guo goto free_sdhci; 157752dac615SSascha Hauer } 157852dac615SSascha Hauer 157952dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 1580a974862fSDong Aisheng pltfm_host->clock = clk_get_rate(pltfm_host->clk); 158117b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_per); 158217b1eb7fSFabio Estevam if (err) 158317b1eb7fSFabio Estevam goto free_sdhci; 158417b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ipg); 158517b1eb7fSFabio Estevam if (err) 158617b1eb7fSFabio Estevam goto disable_per_clk; 158717b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ahb); 158817b1eb7fSFabio Estevam if (err) 158917b1eb7fSFabio Estevam goto disable_ipg_clk; 159095f25efeSWolfram Sang 1591ad93220dSDong Aisheng imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1592e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 1593e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 1594b62eee9fSHaibo Chen dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n"); 1595e62d8b8fSDong Aisheng } 1596e62d8b8fSDong Aisheng 159769ed60e0SDong Aisheng if (esdhc_is_usdhc(imx_data)) { 159869ed60e0SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 159909c8192bSStefan Agner host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; 16004245afffSDong Aisheng if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 16014245afffSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 1602a75dcbf4SDong Aisheng 1603a75dcbf4SDong Aisheng /* clear tuning bits in case ROM has set it already */ 1604a75dcbf4SDong Aisheng writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); 1605869f8a69SAdrian Hunter writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1606a75dcbf4SDong Aisheng writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1607de3e1dd0SBOUGH CHEN 1608de3e1dd0SBOUGH CHEN /* 1609de3e1dd0SBOUGH CHEN * Link usdhc specific mmc_host_ops execute_tuning function, 1610de3e1dd0SBOUGH CHEN * to replace the standard one in sdhci_ops. 1611de3e1dd0SBOUGH CHEN */ 1612de3e1dd0SBOUGH CHEN host->mmc_host_ops.execute_tuning = usdhc_execute_tuning; 161369ed60e0SDong Aisheng } 1614f750ba9bSShawn Guo 16156e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 16166e9fd28eSDong Aisheng sdhci_esdhc_ops.platform_execute_tuning = 16176e9fd28eSDong Aisheng esdhc_executing_tuning; 16188b2bb0adSDong Aisheng 161918094430SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 162018094430SDong Aisheng host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 162118094430SDong Aisheng 162228b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 162328b07674SHaibo Chen host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; 162428b07674SHaibo Chen 162574898cbcSHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23) 162674898cbcSHaibo Chen host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN; 162774898cbcSHaibo Chen 1628029e2476SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) { 1629029e2476SBOUGH CHEN host->mmc->caps2 |= MMC_CAP2_HS400_ES; 1630029e2476SBOUGH CHEN host->mmc_host_ops.hs400_enhanced_strobe = 1631029e2476SBOUGH CHEN esdhc_hs400_enhanced_strobe; 1632029e2476SBOUGH CHEN } 1633029e2476SBOUGH CHEN 1634bb6e3581SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1635bcdb5301SBOUGH CHEN host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1636bb6e3581SBOUGH CHEN cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); 16379a633f3bSWei Yongjun if (!cq_host) { 16389a633f3bSWei Yongjun err = -ENOMEM; 1639bb6e3581SBOUGH CHEN goto disable_ahb_clk; 1640bb6e3581SBOUGH CHEN } 1641bb6e3581SBOUGH CHEN 1642bb6e3581SBOUGH CHEN cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET; 1643bb6e3581SBOUGH CHEN cq_host->ops = &esdhc_cqhci_ops; 1644bb6e3581SBOUGH CHEN 1645bb6e3581SBOUGH CHEN err = cqhci_init(cq_host, host->mmc, false); 1646bb6e3581SBOUGH CHEN if (err) 1647bb6e3581SBOUGH CHEN goto disable_ahb_clk; 1648bb6e3581SBOUGH CHEN } 1649bb6e3581SBOUGH CHEN 165091fa4252SDong Aisheng if (of_id) 165191fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 165291fa4252SDong Aisheng else 165391fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data); 165491fa4252SDong Aisheng if (err) 165517b1eb7fSFabio Estevam goto disable_ahb_clk; 1656ad93220dSDong Aisheng 1657d00ab101SBOUGH CHEN host->tuning_delay = 1; 1658d00ab101SBOUGH CHEN 1659f3f5cf3dSDong Aisheng sdhci_esdhc_imx_hwinit(host); 1660f3f5cf3dSDong Aisheng 166185d6509dSShawn Guo err = sdhci_add_host(host); 166285d6509dSShawn Guo if (err) 166317b1eb7fSFabio Estevam goto disable_ahb_clk; 166485d6509dSShawn Guo 166589d7e5c1SDong Aisheng pm_runtime_set_active(&pdev->dev); 166689d7e5c1SDong Aisheng pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 166789d7e5c1SDong Aisheng pm_runtime_use_autosuspend(&pdev->dev); 166889d7e5c1SDong Aisheng pm_suspend_ignore_children(&pdev->dev, 1); 166977903c01SUlf Hansson pm_runtime_enable(&pdev->dev); 167089d7e5c1SDong Aisheng 16717e29c306SWolfram Sang return 0; 16727e29c306SWolfram Sang 167317b1eb7fSFabio Estevam disable_ahb_clk: 167452dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 167517b1eb7fSFabio Estevam disable_ipg_clk: 167617b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_ipg); 167717b1eb7fSFabio Estevam disable_per_clk: 167817b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_per); 1679e3af31c6SShawn Guo free_sdhci: 16801c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 16811c4989b0SBOUGH CHEN pm_qos_remove_request(&imx_data->pm_qos_req); 168285d6509dSShawn Guo sdhci_pltfm_free(pdev); 168385d6509dSShawn Guo return err; 168495f25efeSWolfram Sang } 168595f25efeSWolfram Sang 16866e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 168795f25efeSWolfram Sang { 168885d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 168995f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1690070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 169185d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 169285d6509dSShawn Guo 16930b414368SUlf Hansson pm_runtime_get_sync(&pdev->dev); 16940b414368SUlf Hansson pm_runtime_disable(&pdev->dev); 16950b414368SUlf Hansson pm_runtime_put_noidle(&pdev->dev); 16960b414368SUlf Hansson 169785d6509dSShawn Guo sdhci_remove_host(host, dead); 16980c6d49ceSWolfram Sang 169952dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 170052dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 170152dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 170252dac615SSascha Hauer 17031c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 17041c4989b0SBOUGH CHEN pm_qos_remove_request(&imx_data->pm_qos_req); 17051c4989b0SBOUGH CHEN 170685d6509dSShawn Guo sdhci_pltfm_free(pdev); 170785d6509dSShawn Guo 170885d6509dSShawn Guo return 0; 170995f25efeSWolfram Sang } 171095f25efeSWolfram Sang 17112788ed42SUlf Hansson #ifdef CONFIG_PM_SLEEP 171204143fbaSDong Aisheng static int sdhci_esdhc_suspend(struct device *dev) 171304143fbaSDong Aisheng { 17143e3274abSUlf Hansson struct sdhci_host *host = dev_get_drvdata(dev); 1715a26a4f1bSHaibo Chen struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1716a26a4f1bSHaibo Chen struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1717bb6e3581SBOUGH CHEN int ret; 1718bb6e3581SBOUGH CHEN 1719bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) { 1720bb6e3581SBOUGH CHEN ret = cqhci_suspend(host->mmc); 1721bb6e3581SBOUGH CHEN if (ret) 1722bb6e3581SBOUGH CHEN return ret; 1723bb6e3581SBOUGH CHEN } 17243e3274abSUlf Hansson 1725a26a4f1bSHaibo Chen if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) && 1726a26a4f1bSHaibo Chen (host->tuning_mode != SDHCI_TUNING_MODE_1)) { 1727a26a4f1bSHaibo Chen mmc_retune_timer_stop(host->mmc); 1728a26a4f1bSHaibo Chen mmc_retune_needed(host->mmc); 1729a26a4f1bSHaibo Chen } 1730a26a4f1bSHaibo Chen 1731d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1732d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 1733d38dcad4SAdrian Hunter 17343e3274abSUlf Hansson return sdhci_suspend_host(host); 173504143fbaSDong Aisheng } 173604143fbaSDong Aisheng 173704143fbaSDong Aisheng static int sdhci_esdhc_resume(struct device *dev) 173804143fbaSDong Aisheng { 1739cc17e129SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 1740bb6e3581SBOUGH CHEN int ret; 1741cc17e129SDong Aisheng 174219dbfdd3SDong Aisheng /* re-initialize hw state in case it's lost in low power mode */ 174319dbfdd3SDong Aisheng sdhci_esdhc_imx_hwinit(host); 1744cc17e129SDong Aisheng 1745bb6e3581SBOUGH CHEN ret = sdhci_resume_host(host); 1746bb6e3581SBOUGH CHEN if (ret) 1747bb6e3581SBOUGH CHEN return ret; 1748bb6e3581SBOUGH CHEN 1749bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) 1750bb6e3581SBOUGH CHEN ret = cqhci_resume(host->mmc); 1751bb6e3581SBOUGH CHEN 1752bb6e3581SBOUGH CHEN return ret; 175304143fbaSDong Aisheng } 17542788ed42SUlf Hansson #endif 175504143fbaSDong Aisheng 17562788ed42SUlf Hansson #ifdef CONFIG_PM 175789d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_suspend(struct device *dev) 175889d7e5c1SDong Aisheng { 175989d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 176089d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1761070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 176289d7e5c1SDong Aisheng int ret; 176389d7e5c1SDong Aisheng 1764bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) { 1765bb6e3581SBOUGH CHEN ret = cqhci_suspend(host->mmc); 1766bb6e3581SBOUGH CHEN if (ret) 1767bb6e3581SBOUGH CHEN return ret; 1768bb6e3581SBOUGH CHEN } 1769bb6e3581SBOUGH CHEN 177089d7e5c1SDong Aisheng ret = sdhci_runtime_suspend_host(host); 1771371d39faSMichael Trimarchi if (ret) 1772371d39faSMichael Trimarchi return ret; 177389d7e5c1SDong Aisheng 1774d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1775d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 1776d38dcad4SAdrian Hunter 17773602785bSMichael Trimarchi imx_data->actual_clock = host->mmc->actual_clock; 17783602785bSMichael Trimarchi esdhc_pltfm_set_clock(host, 0); 177989d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_per); 178089d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ipg); 178189d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ahb); 178289d7e5c1SDong Aisheng 17831c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 17841c4989b0SBOUGH CHEN pm_qos_remove_request(&imx_data->pm_qos_req); 17851c4989b0SBOUGH CHEN 178689d7e5c1SDong Aisheng return ret; 178789d7e5c1SDong Aisheng } 178889d7e5c1SDong Aisheng 178989d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_resume(struct device *dev) 179089d7e5c1SDong Aisheng { 179189d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 179289d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1793070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 179417b1eb7fSFabio Estevam int err; 179589d7e5c1SDong Aisheng 17961c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 17971c4989b0SBOUGH CHEN pm_qos_add_request(&imx_data->pm_qos_req, 17981c4989b0SBOUGH CHEN PM_QOS_CPU_DMA_LATENCY, 0); 17991c4989b0SBOUGH CHEN 18005c11f1ffSHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME) 18015c11f1ffSHaibo Chen clk_set_rate(imx_data->clk_per, pltfm_host->clock); 18025c11f1ffSHaibo Chen 1803a0ad3087SMichael Trimarchi err = clk_prepare_enable(imx_data->clk_ahb); 1804a0ad3087SMichael Trimarchi if (err) 18051c4989b0SBOUGH CHEN goto remove_pm_qos_request; 1806a0ad3087SMichael Trimarchi 180717b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_per); 180817b1eb7fSFabio Estevam if (err) 1809a0ad3087SMichael Trimarchi goto disable_ahb_clk; 1810af5d2b7bSUlf Hansson 181117b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ipg); 181217b1eb7fSFabio Estevam if (err) 181317b1eb7fSFabio Estevam goto disable_per_clk; 1814af5d2b7bSUlf Hansson 18153602785bSMichael Trimarchi esdhc_pltfm_set_clock(host, imx_data->actual_clock); 1816a0ad3087SMichael Trimarchi 1817c6303c5dSBaolin Wang err = sdhci_runtime_resume_host(host, 0); 181817b1eb7fSFabio Estevam if (err) 1819a0ad3087SMichael Trimarchi goto disable_ipg_clk; 182089d7e5c1SDong Aisheng 1821bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) 1822bb6e3581SBOUGH CHEN err = cqhci_resume(host->mmc); 1823bb6e3581SBOUGH CHEN 1824bb6e3581SBOUGH CHEN return err; 182517b1eb7fSFabio Estevam 182617b1eb7fSFabio Estevam disable_ipg_clk: 182717b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_ipg); 182817b1eb7fSFabio Estevam disable_per_clk: 182917b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_per); 1830a0ad3087SMichael Trimarchi disable_ahb_clk: 1831a0ad3087SMichael Trimarchi clk_disable_unprepare(imx_data->clk_ahb); 18321c4989b0SBOUGH CHEN remove_pm_qos_request: 18331c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 18341c4989b0SBOUGH CHEN pm_qos_remove_request(&imx_data->pm_qos_req); 183517b1eb7fSFabio Estevam return err; 183689d7e5c1SDong Aisheng } 183789d7e5c1SDong Aisheng #endif 183889d7e5c1SDong Aisheng 183989d7e5c1SDong Aisheng static const struct dev_pm_ops sdhci_esdhc_pmops = { 184004143fbaSDong Aisheng SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) 184189d7e5c1SDong Aisheng SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 184289d7e5c1SDong Aisheng sdhci_esdhc_runtime_resume, NULL) 184389d7e5c1SDong Aisheng }; 184489d7e5c1SDong Aisheng 184585d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 184685d6509dSShawn Guo .driver = { 184785d6509dSShawn Guo .name = "sdhci-esdhc-imx", 1848abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 184989d7e5c1SDong Aisheng .pm = &sdhci_esdhc_pmops, 185085d6509dSShawn Guo }, 185157ed3314SShawn Guo .id_table = imx_esdhc_devtype, 185285d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 18530433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 185495f25efeSWolfram Sang }; 185585d6509dSShawn Guo 1856d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 185785d6509dSShawn Guo 185885d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1859035ff831SWolfram Sang MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 186085d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1861