1a6e7e407SFabio Estevam // SPDX-License-Identifier: GPL-2.0 295f25efeSWolfram Sang /* 395f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 495f25efeSWolfram Sang * 595f25efeSWolfram Sang * derived from the OF-version. 695f25efeSWolfram Sang * 795f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 8035ff831SWolfram Sang * Author: Wolfram Sang <kernel@pengutronix.de> 995f25efeSWolfram Sang */ 1095f25efeSWolfram Sang 1195f25efeSWolfram Sang #include <linux/io.h> 1295f25efeSWolfram Sang #include <linux/delay.h> 1395f25efeSWolfram Sang #include <linux/err.h> 1495f25efeSWolfram Sang #include <linux/clk.h> 1566506f76SShawn Guo #include <linux/module.h> 16e149860dSRichard Zhu #include <linux/slab.h> 1795f25efeSWolfram Sang #include <linux/mmc/host.h> 1858ac8177SRichard Zhu #include <linux/mmc/mmc.h> 1958ac8177SRichard Zhu #include <linux/mmc/sdio.h> 20fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 21abfafc2dSShawn Guo #include <linux/of.h> 22abfafc2dSShawn Guo #include <linux/of_device.h> 23e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2482906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 2589d7e5c1SDong Aisheng #include <linux/pm_runtime.h> 2695f25efeSWolfram Sang #include "sdhci-pltfm.h" 2795f25efeSWolfram Sang #include "sdhci-esdhc.h" 2895f25efeSWolfram Sang 29a215186dSHaibo Chen #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f 3060bf6396SShawn Guo #define ESDHC_CTRL_D3CD 0x08 31fd44954eSHaibo Chen #define ESDHC_BURST_LEN_EN_INCR (1 << 27) 3258ac8177SRichard Zhu /* VENDOR SPEC register */ 3360bf6396SShawn Guo #define ESDHC_VENDOR_SPEC 0xc0 3460bf6396SShawn Guo #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 350322191eSDong Aisheng #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 36fed2f6e2SDong Aisheng #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 3760bf6396SShawn Guo #define ESDHC_WTMK_LVL 0x44 38cc17e129SDong Aisheng #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 393fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF 403fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0 413fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000 423fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16 433fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WML_VAL_DEF 64 443fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WML_VAL_MAX 128 4560bf6396SShawn Guo #define ESDHC_MIX_CTRL 0x48 46de5bdbffSDong Aisheng #define ESDHC_MIX_CTRL_DDREN (1 << 3) 472a15f981SShawn Guo #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 480322191eSDong Aisheng #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 490322191eSDong Aisheng #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 500b330e38SDong Aisheng #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) 510322191eSDong Aisheng #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 5228b07674SHaibo Chen #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 532a15f981SShawn Guo /* Bits 3 and 6 are not SDHCI standard definitions */ 542a15f981SShawn Guo #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 55d131a71cSDong Aisheng /* Tuning bits */ 56d131a71cSDong Aisheng #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 5758ac8177SRichard Zhu 58602519b2SDong Aisheng /* dll control register */ 59602519b2SDong Aisheng #define ESDHC_DLL_CTRL 0x60 60602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 61602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 62602519b2SDong Aisheng 630322191eSDong Aisheng /* tune control register */ 640322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STATUS 0x68 650322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STEP 1 660322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MIN 0 670322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 680322191eSDong Aisheng 6928b07674SHaibo Chen /* strobe dll register */ 7028b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL 0x70 7128b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) 7228b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) 7328b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 7428b07674SHaibo Chen 7528b07674SHaibo Chen #define ESDHC_STROBE_DLL_STATUS 0x74 7628b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) 7728b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 7828b07674SHaibo Chen 796e9fd28eSDong Aisheng #define ESDHC_TUNING_CTRL 0xcc 806e9fd28eSDong Aisheng #define ESDHC_STD_TUNING_EN (1 << 24) 816e9fd28eSDong Aisheng /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 82d87fc966SDong Aisheng #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 83d87fc966SDong Aisheng #define ESDHC_TUNING_START_TAP_MASK 0xff 84260ecb3cSHaibo Chen #define ESDHC_TUNING_STEP_MASK 0x00070000 85d407e30bSHaibo Chen #define ESDHC_TUNING_STEP_SHIFT 16 866e9fd28eSDong Aisheng 87ad93220dSDong Aisheng /* pinctrl state */ 88ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 89ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 90ad93220dSDong Aisheng 9158ac8177SRichard Zhu /* 92af51079eSSascha Hauer * Our interpretation of the SDHCI_HOST_CONTROL register 93af51079eSSascha Hauer */ 94af51079eSSascha Hauer #define ESDHC_CTRL_4BITBUS (0x1 << 1) 95af51079eSSascha Hauer #define ESDHC_CTRL_8BITBUS (0x2 << 1) 96af51079eSSascha Hauer #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 97af51079eSSascha Hauer 98af51079eSSascha Hauer /* 99d04f8d5bSBenoît Thébaudeau * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC: 10097e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 10197e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 10297e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 10397e4ba6aSRichard Zhu */ 10460bf6396SShawn Guo #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 10597e4ba6aSRichard Zhu 10697e4ba6aSRichard Zhu /* 10758ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 10858ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 10958ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 11058ac8177SRichard Zhu * be generated. 11158ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 11258ac8177SRichard Zhu * operations automatically as required at the end of the 11358ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 11458ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 115d04f8d5bSBenoît Thébaudeau * exception. Bit1 of Vendor Spec register is used to fix it. 11658ac8177SRichard Zhu */ 11731fbb301SShawn Guo #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 11831fbb301SShawn Guo /* 1199d61c009SShawn Guo * The flag tells that the ESDHC controller is an USDHC block that is 1209d61c009SShawn Guo * integrated on the i.MX6 series. 1219d61c009SShawn Guo */ 1229d61c009SShawn Guo #define ESDHC_FLAG_USDHC BIT(3) 1236e9fd28eSDong Aisheng /* The IP supports manual tuning process */ 1246e9fd28eSDong Aisheng #define ESDHC_FLAG_MAN_TUNING BIT(4) 1256e9fd28eSDong Aisheng /* The IP supports standard tuning process */ 1266e9fd28eSDong Aisheng #define ESDHC_FLAG_STD_TUNING BIT(5) 1276e9fd28eSDong Aisheng /* The IP has SDHCI_CAPABILITIES_1 register */ 1286e9fd28eSDong Aisheng #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 12918094430SDong Aisheng /* 130d04f8d5bSBenoît Thébaudeau * The IP has erratum ERR004536 13118094430SDong Aisheng * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 13218094430SDong Aisheng * when reading data from the card 133667123f6SBenoît Thébaudeau * This flag is also set for i.MX25 and i.MX35 in order to get 134667123f6SBenoît Thébaudeau * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits). 13518094430SDong Aisheng */ 13618094430SDong Aisheng #define ESDHC_FLAG_ERR004536 BIT(7) 1374245afffSDong Aisheng /* The IP supports HS200 mode */ 1384245afffSDong Aisheng #define ESDHC_FLAG_HS200 BIT(8) 13928b07674SHaibo Chen /* The IP supports HS400 mode */ 14028b07674SHaibo Chen #define ESDHC_FLAG_HS400 BIT(9) 14128b07674SHaibo Chen 142d04f8d5bSBenoît Thébaudeau /* A clock frequency higher than this rate requires strobe dll control */ 14328b07674SHaibo Chen #define ESDHC_STROBE_DLL_CLK_FREQ 100000000 144e149860dSRichard Zhu 145f47c4bbfSShawn Guo struct esdhc_soc_data { 146f47c4bbfSShawn Guo u32 flags; 147f47c4bbfSShawn Guo }; 148f47c4bbfSShawn Guo 1494f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx25_data = { 150667123f6SBenoît Thébaudeau .flags = ESDHC_FLAG_ERR004536, 151f47c4bbfSShawn Guo }; 152f47c4bbfSShawn Guo 1534f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx35_data = { 154667123f6SBenoît Thébaudeau .flags = ESDHC_FLAG_ERR004536, 155f47c4bbfSShawn Guo }; 156f47c4bbfSShawn Guo 1574f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx51_data = { 158f47c4bbfSShawn Guo .flags = 0, 159f47c4bbfSShawn Guo }; 160f47c4bbfSShawn Guo 1614f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx53_data = { 162f47c4bbfSShawn Guo .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 163f47c4bbfSShawn Guo }; 164f47c4bbfSShawn Guo 1654f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx6q_data = { 1666e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, 1676e9fd28eSDong Aisheng }; 1686e9fd28eSDong Aisheng 1694f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx6sl_data = { 1706e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1714245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 1724245afffSDong Aisheng | ESDHC_FLAG_HS200, 17357ed3314SShawn Guo }; 17457ed3314SShawn Guo 1754f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx6sx_data = { 176913d4951SDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1774245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, 178913d4951SDong Aisheng }; 179913d4951SDong Aisheng 1804f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx7d_data = { 18128b07674SHaibo Chen .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 18228b07674SHaibo Chen | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 18328b07674SHaibo Chen | ESDHC_FLAG_HS400, 18428b07674SHaibo Chen }; 18528b07674SHaibo Chen 186e149860dSRichard Zhu struct pltfm_imx_data { 187e149860dSRichard Zhu u32 scratchpad; 188e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 189ad93220dSDong Aisheng struct pinctrl_state *pins_default; 190ad93220dSDong Aisheng struct pinctrl_state *pins_100mhz; 191ad93220dSDong Aisheng struct pinctrl_state *pins_200mhz; 192f47c4bbfSShawn Guo const struct esdhc_soc_data *socdata; 193842afc02SShawn Guo struct esdhc_platform_data boarddata; 19452dac615SSascha Hauer struct clk *clk_ipg; 19552dac615SSascha Hauer struct clk *clk_ahb; 19652dac615SSascha Hauer struct clk *clk_per; 1973602785bSMichael Trimarchi unsigned int actual_clock; 198361b8482SLucas Stach enum { 199361b8482SLucas Stach NO_CMD_PENDING, /* no multiblock command pending */ 200361b8482SLucas Stach MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 201361b8482SLucas Stach WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 202361b8482SLucas Stach } multiblock_status; 203de5bdbffSDong Aisheng u32 is_ddr; 204e149860dSRichard Zhu }; 205e149860dSRichard Zhu 206f8cbf461SKrzysztof Kozlowski static const struct platform_device_id imx_esdhc_devtype[] = { 20757ed3314SShawn Guo { 20857ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 209f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 21057ed3314SShawn Guo }, { 21157ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 212f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 21357ed3314SShawn Guo }, { 21457ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 215f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 21657ed3314SShawn Guo }, { 21757ed3314SShawn Guo /* sentinel */ 21857ed3314SShawn Guo } 21957ed3314SShawn Guo }; 22057ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 22157ed3314SShawn Guo 222abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 223f47c4bbfSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 224f47c4bbfSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 225f47c4bbfSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 226f47c4bbfSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 227913d4951SDong Aisheng { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 2286e9fd28eSDong Aisheng { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 229f47c4bbfSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 23028b07674SHaibo Chen { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, 231abfafc2dSShawn Guo { /* sentinel */ } 232abfafc2dSShawn Guo }; 233abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 234abfafc2dSShawn Guo 23557ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 23657ed3314SShawn Guo { 237f47c4bbfSShawn Guo return data->socdata == &esdhc_imx25_data; 23857ed3314SShawn Guo } 23957ed3314SShawn Guo 24057ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 24157ed3314SShawn Guo { 242f47c4bbfSShawn Guo return data->socdata == &esdhc_imx53_data; 24357ed3314SShawn Guo } 24457ed3314SShawn Guo 24595a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 24695a2482aSShawn Guo { 247f47c4bbfSShawn Guo return data->socdata == &usdhc_imx6q_data; 24895a2482aSShawn Guo } 24995a2482aSShawn Guo 2509d61c009SShawn Guo static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 2519d61c009SShawn Guo { 252f47c4bbfSShawn Guo return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 2539d61c009SShawn Guo } 2549d61c009SShawn Guo 25595f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 25695f25efeSWolfram Sang { 25795f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 25895f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 25995f25efeSWolfram Sang 26095f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 26195f25efeSWolfram Sang } 26295f25efeSWolfram Sang 2637e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 2647e29c306SWolfram Sang { 265361b8482SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 266070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 267913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 268913413c3SShawn Guo 2690322191eSDong Aisheng if (unlikely(reg == SDHCI_PRESENT_STATE)) { 2700322191eSDong Aisheng u32 fsl_prss = val; 2710322191eSDong Aisheng /* save the least 20 bits */ 2720322191eSDong Aisheng val = fsl_prss & 0x000FFFFF; 2730322191eSDong Aisheng /* move dat[0-3] bits */ 2740322191eSDong Aisheng val |= (fsl_prss & 0x0F000000) >> 4; 2750322191eSDong Aisheng /* move cmd line bit */ 2760322191eSDong Aisheng val |= (fsl_prss & 0x00800000) << 1; 2770322191eSDong Aisheng } 2780322191eSDong Aisheng 27997e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 2806b4fb671SDong Aisheng /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 2816b4fb671SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 2826b4fb671SDong Aisheng val &= 0xffff0000; 2836b4fb671SDong Aisheng 28497e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 28597e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 28697e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 28797e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 288d04f8d5bSBenoît Thébaudeau * quirk on MX25/35 platforms. 28997e4ba6aSRichard Zhu */ 29097e4ba6aSRichard Zhu 29197e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 29297e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 29397e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 29497e4ba6aSRichard Zhu } 29597e4ba6aSRichard Zhu } 29697e4ba6aSRichard Zhu 2976e9fd28eSDong Aisheng if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 2986e9fd28eSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 2996e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 3006e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 3016e9fd28eSDong Aisheng else 3026e9fd28eSDong Aisheng /* imx6q/dl does not have cap_1 register, fake one */ 3030322191eSDong Aisheng val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 304888824bbSDong Aisheng | SDHCI_SUPPORT_SDR50 305da0295ffSDong Aisheng | SDHCI_USE_SDR50_TUNING 306da0295ffSDong Aisheng | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT); 30728b07674SHaibo Chen 30828b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 30928b07674SHaibo Chen val |= SDHCI_SUPPORT_HS400; 31092748beaSStefan Agner 31192748beaSStefan Agner /* 31292748beaSStefan Agner * Do not advertise faster UHS modes if there are no 31392748beaSStefan Agner * pinctrl states for 100MHz/200MHz. 31492748beaSStefan Agner */ 31592748beaSStefan Agner if (IS_ERR_OR_NULL(imx_data->pins_100mhz) || 31692748beaSStefan Agner IS_ERR_OR_NULL(imx_data->pins_200mhz)) 31792748beaSStefan Agner val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50 31892748beaSStefan Agner | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400); 3196e9fd28eSDong Aisheng } 3206e9fd28eSDong Aisheng } 3210322191eSDong Aisheng 3229d61c009SShawn Guo if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 3230322191eSDong Aisheng val = 0; 3240322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 3250322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 3260322191eSDong Aisheng val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 3270322191eSDong Aisheng } 3280322191eSDong Aisheng 32997e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 33060bf6396SShawn Guo if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 33160bf6396SShawn Guo val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 33297e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 33397e4ba6aSRichard Zhu } 334361b8482SLucas Stach 335361b8482SLucas Stach /* 336361b8482SLucas Stach * mask off the interrupt we get in response to the manually 337361b8482SLucas Stach * sent CMD12 338361b8482SLucas Stach */ 339361b8482SLucas Stach if ((imx_data->multiblock_status == WAIT_FOR_INT) && 340361b8482SLucas Stach ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 341361b8482SLucas Stach val &= ~SDHCI_INT_RESPONSE; 342361b8482SLucas Stach writel(SDHCI_INT_RESPONSE, host->ioaddr + 343361b8482SLucas Stach SDHCI_INT_STATUS); 344361b8482SLucas Stach imx_data->multiblock_status = NO_CMD_PENDING; 345361b8482SLucas Stach } 34697e4ba6aSRichard Zhu } 34797e4ba6aSRichard Zhu 3487e29c306SWolfram Sang return val; 3497e29c306SWolfram Sang } 3507e29c306SWolfram Sang 3517e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 3527e29c306SWolfram Sang { 353e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 354070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 3550d58864bSTony Lin u32 data; 356e149860dSRichard Zhu 35777da3da0SAaron Brice if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || 35877da3da0SAaron Brice reg == SDHCI_INT_STATUS)) { 359b7321042SDong Aisheng if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 3600d58864bSTony Lin /* 3610d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 362d04f8d5bSBenoît Thébaudeau * card interrupt. This is an eSDHC controller problem 3630d58864bSTony Lin * so we need to apply the following workaround: clear 3640d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 3650d58864bSTony Lin * interrupt. In case a card interrupt was lost, 3660d58864bSTony Lin * re-sample it by the following steps. 3670d58864bSTony Lin */ 3680d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 36960bf6396SShawn Guo data &= ~ESDHC_CTRL_D3CD; 3700d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 37160bf6396SShawn Guo data |= ESDHC_CTRL_D3CD; 3720d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 3730d58864bSTony Lin } 374915be485SDong Aisheng 375915be485SDong Aisheng if (val & SDHCI_INT_ADMA_ERROR) { 376915be485SDong Aisheng val &= ~SDHCI_INT_ADMA_ERROR; 377915be485SDong Aisheng val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 378915be485SDong Aisheng } 3790d58864bSTony Lin } 3800d58864bSTony Lin 381f47c4bbfSShawn Guo if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 38258ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 38358ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 38458ac8177SRichard Zhu u32 v; 38560bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 38660bf6396SShawn Guo v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 38760bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 388361b8482SLucas Stach 389361b8482SLucas Stach if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 390361b8482SLucas Stach { 391361b8482SLucas Stach /* send a manual CMD12 with RESPTYP=none */ 392361b8482SLucas Stach data = MMC_STOP_TRANSMISSION << 24 | 393361b8482SLucas Stach SDHCI_CMD_ABORTCMD << 16; 394361b8482SLucas Stach writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 395361b8482SLucas Stach imx_data->multiblock_status = WAIT_FOR_INT; 396361b8482SLucas Stach } 39758ac8177SRichard Zhu } 39858ac8177SRichard Zhu 3997e29c306SWolfram Sang writel(val, host->ioaddr + reg); 4007e29c306SWolfram Sang } 4017e29c306SWolfram Sang 40295f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 40395f25efeSWolfram Sang { 404ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 405070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 4060322191eSDong Aisheng u16 ret = 0; 4070322191eSDong Aisheng u32 val; 408ef4d0888SShawn Guo 40995a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 410ef4d0888SShawn Guo reg ^= 2; 4119d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 41295a2482aSShawn Guo /* 413ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 414ef4d0888SShawn Guo * Correct it here. 41595a2482aSShawn Guo */ 416ef4d0888SShawn Guo return SDHCI_SPEC_300; 417ef4d0888SShawn Guo } 41895a2482aSShawn Guo } 41995f25efeSWolfram Sang 4200322191eSDong Aisheng if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 4210322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4220322191eSDong Aisheng if (val & ESDHC_VENDOR_SPEC_VSELECT) 4230322191eSDong Aisheng ret |= SDHCI_CTRL_VDD_180; 4240322191eSDong Aisheng 4259d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 4266e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 4270322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_MIX_CTRL); 4286e9fd28eSDong Aisheng else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 4296e9fd28eSDong Aisheng /* the std tuning bits is in ACMD12_ERR for imx6sl */ 430869f8a69SAdrian Hunter val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 4316e9fd28eSDong Aisheng } 4326e9fd28eSDong Aisheng 4330322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_EXE_TUNE) 4340322191eSDong Aisheng ret |= SDHCI_CTRL_EXEC_TUNING; 4350322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 4360322191eSDong Aisheng ret |= SDHCI_CTRL_TUNED_CLK; 4370322191eSDong Aisheng 4380322191eSDong Aisheng ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 4390322191eSDong Aisheng 4400322191eSDong Aisheng return ret; 4410322191eSDong Aisheng } 4420322191eSDong Aisheng 4437dd109efSDong Aisheng if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 4447dd109efSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 4457dd109efSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4467dd109efSDong Aisheng ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 4477dd109efSDong Aisheng /* Swap AC23 bit */ 4487dd109efSDong Aisheng if (m & ESDHC_MIX_CTRL_AC23EN) { 4497dd109efSDong Aisheng ret &= ~ESDHC_MIX_CTRL_AC23EN; 4507dd109efSDong Aisheng ret |= SDHCI_TRNS_AUTO_CMD23; 4517dd109efSDong Aisheng } 4527dd109efSDong Aisheng } else { 4537dd109efSDong Aisheng ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 4547dd109efSDong Aisheng } 4557dd109efSDong Aisheng 4567dd109efSDong Aisheng return ret; 4577dd109efSDong Aisheng } 4587dd109efSDong Aisheng 45995f25efeSWolfram Sang return readw(host->ioaddr + reg); 46095f25efeSWolfram Sang } 46195f25efeSWolfram Sang 46295f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 46395f25efeSWolfram Sang { 46495f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 465070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 4660322191eSDong Aisheng u32 new_val = 0; 46795f25efeSWolfram Sang 46895f25efeSWolfram Sang switch (reg) { 4690322191eSDong Aisheng case SDHCI_CLOCK_CONTROL: 4700322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4710322191eSDong Aisheng if (val & SDHCI_CLOCK_CARD_EN) 4720322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4730322191eSDong Aisheng else 4740322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 4750322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4760322191eSDong Aisheng return; 4770322191eSDong Aisheng case SDHCI_HOST_CONTROL2: 4780322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 4790322191eSDong Aisheng if (val & SDHCI_CTRL_VDD_180) 4800322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_VSELECT; 4810322191eSDong Aisheng else 4820322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 4830322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 4846e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 4850322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 486da0295ffSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 4870322191eSDong Aisheng new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 488da0295ffSDong Aisheng new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 489da0295ffSDong Aisheng } else { 4900322191eSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 491da0295ffSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 492da0295ffSDong Aisheng } 4930322191eSDong Aisheng writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 4946e9fd28eSDong Aisheng } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 495869f8a69SAdrian Hunter u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 4966e9fd28eSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 4978b2bb0adSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 4988b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 4996e9fd28eSDong Aisheng } else { 5008b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 5016e9fd28eSDong Aisheng m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 5020b330e38SDong Aisheng m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 5036e9fd28eSDong Aisheng } 5046e9fd28eSDong Aisheng 5058b2bb0adSDong Aisheng if (val & SDHCI_CTRL_EXEC_TUNING) { 5068b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_EXE_TUNE; 5078b2bb0adSDong Aisheng m |= ESDHC_MIX_CTRL_FBCLK_SEL; 5080b330e38SDong Aisheng m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 5098b2bb0adSDong Aisheng } else { 5108b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 5118b2bb0adSDong Aisheng } 5126e9fd28eSDong Aisheng 513869f8a69SAdrian Hunter writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 5146e9fd28eSDong Aisheng writel(m, host->ioaddr + ESDHC_MIX_CTRL); 5156e9fd28eSDong Aisheng } 5160322191eSDong Aisheng return; 51795f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 518f47c4bbfSShawn Guo if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 51958ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 52058ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 52158ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 52258ac8177SRichard Zhu u32 v; 52360bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 52460bf6396SShawn Guo v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 52560bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 52658ac8177SRichard Zhu } 52769f54698SShawn Guo 5289d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 5293fbd4322SAndrew Gabbasov u32 wml; 53069f54698SShawn Guo u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 5312a15f981SShawn Guo /* Swap AC23 bit */ 5322a15f981SShawn Guo if (val & SDHCI_TRNS_AUTO_CMD23) { 5332a15f981SShawn Guo val &= ~SDHCI_TRNS_AUTO_CMD23; 5342a15f981SShawn Guo val |= ESDHC_MIX_CTRL_AC23EN; 5352a15f981SShawn Guo } 5362a15f981SShawn Guo m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 53769f54698SShawn Guo writel(m, host->ioaddr + ESDHC_MIX_CTRL); 5383fbd4322SAndrew Gabbasov 5393fbd4322SAndrew Gabbasov /* Set watermark levels for PIO access to maximum value 5403fbd4322SAndrew Gabbasov * (128 words) to accommodate full 512 bytes buffer. 5413fbd4322SAndrew Gabbasov * For DMA access restore the levels to default value. 5423fbd4322SAndrew Gabbasov */ 5433fbd4322SAndrew Gabbasov m = readl(host->ioaddr + ESDHC_WTMK_LVL); 5443fbd4322SAndrew Gabbasov if (val & SDHCI_TRNS_DMA) 5453fbd4322SAndrew Gabbasov wml = ESDHC_WTMK_LVL_WML_VAL_DEF; 5463fbd4322SAndrew Gabbasov else 5473fbd4322SAndrew Gabbasov wml = ESDHC_WTMK_LVL_WML_VAL_MAX; 5483fbd4322SAndrew Gabbasov m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK | 5493fbd4322SAndrew Gabbasov ESDHC_WTMK_LVL_WR_WML_MASK); 5503fbd4322SAndrew Gabbasov m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) | 5513fbd4322SAndrew Gabbasov (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT); 5523fbd4322SAndrew Gabbasov writel(m, host->ioaddr + ESDHC_WTMK_LVL); 55369f54698SShawn Guo } else { 55469f54698SShawn Guo /* 55569f54698SShawn Guo * Postpone this write, we must do it together with a 55669f54698SShawn Guo * command write that is down below. 55769f54698SShawn Guo */ 558e149860dSRichard Zhu imx_data->scratchpad = val; 55969f54698SShawn Guo } 56095f25efeSWolfram Sang return; 56195f25efeSWolfram Sang case SDHCI_COMMAND: 562361b8482SLucas Stach if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 56358ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 56495a2482aSShawn Guo 565361b8482SLucas Stach if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 566f47c4bbfSShawn Guo (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 567361b8482SLucas Stach imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 568361b8482SLucas Stach 5699d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 57095a2482aSShawn Guo writel(val << 16, 57195a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 57269f54698SShawn Guo else 573e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 57495f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 57595f25efeSWolfram Sang return; 57695f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 57795f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 57895f25efeSWolfram Sang break; 57995f25efeSWolfram Sang } 58095f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 58195f25efeSWolfram Sang } 58295f25efeSWolfram Sang 58377da3da0SAaron Brice static u8 esdhc_readb_le(struct sdhci_host *host, int reg) 58477da3da0SAaron Brice { 58577da3da0SAaron Brice u8 ret; 58677da3da0SAaron Brice u32 val; 58777da3da0SAaron Brice 58877da3da0SAaron Brice switch (reg) { 58977da3da0SAaron Brice case SDHCI_HOST_CONTROL: 59077da3da0SAaron Brice val = readl(host->ioaddr + reg); 59177da3da0SAaron Brice 59277da3da0SAaron Brice ret = val & SDHCI_CTRL_LED; 59377da3da0SAaron Brice ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; 59477da3da0SAaron Brice ret |= (val & ESDHC_CTRL_4BITBUS); 59577da3da0SAaron Brice ret |= (val & ESDHC_CTRL_8BITBUS) << 3; 59677da3da0SAaron Brice return ret; 59777da3da0SAaron Brice } 59877da3da0SAaron Brice 59977da3da0SAaron Brice return readb(host->ioaddr + reg); 60077da3da0SAaron Brice } 60177da3da0SAaron Brice 60295f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 60395f25efeSWolfram Sang { 6049a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 605070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 60681a0a8bcSBenoît Thébaudeau u32 new_val = 0; 607af51079eSSascha Hauer u32 mask; 60895f25efeSWolfram Sang 60995f25efeSWolfram Sang switch (reg) { 61095f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 61195f25efeSWolfram Sang /* 61295f25efeSWolfram Sang * FSL put some DMA bits here 61395f25efeSWolfram Sang * If your board has a regulator, code should be here 61495f25efeSWolfram Sang */ 61595f25efeSWolfram Sang return; 61695f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 6176b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 618af51079eSSascha Hauer new_val = val & SDHCI_CTRL_LED; 6197122bbb0SMasanari Iida /* ensure the endianness */ 62095f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 6219a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 6229a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 62395f25efeSWolfram Sang /* DMA mode bits are shifted */ 62495f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 6259a0985b7SWilson Callan } 62695f25efeSWolfram Sang 627af51079eSSascha Hauer /* 628af51079eSSascha Hauer * Do not touch buswidth bits here. This is done in 629af51079eSSascha Hauer * esdhc_pltfm_bus_width. 630f6825748SMartin Fuzzey * Do not touch the D3CD bit either which is used for the 631d04f8d5bSBenoît Thébaudeau * SDIO interrupt erratum workaround. 632af51079eSSascha Hauer */ 633f6825748SMartin Fuzzey mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 634af51079eSSascha Hauer 635af51079eSSascha Hauer esdhc_clrset_le(host, mask, new_val, reg); 63695f25efeSWolfram Sang return; 63781a0a8bcSBenoît Thébaudeau case SDHCI_SOFTWARE_RESET: 63881a0a8bcSBenoît Thébaudeau if (val & SDHCI_RESET_DATA) 63981a0a8bcSBenoît Thébaudeau new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); 64081a0a8bcSBenoît Thébaudeau break; 64195f25efeSWolfram Sang } 64295f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 643913413c3SShawn Guo 64481a0a8bcSBenoît Thébaudeau if (reg == SDHCI_SOFTWARE_RESET) { 64581a0a8bcSBenoît Thébaudeau if (val & SDHCI_RESET_ALL) { 646913413c3SShawn Guo /* 64781a0a8bcSBenoît Thébaudeau * The esdhc has a design violation to SDHC spec which 64881a0a8bcSBenoît Thébaudeau * tells that software reset should not affect card 64981a0a8bcSBenoît Thébaudeau * detection circuit. But esdhc clears its SYSCTL 65081a0a8bcSBenoît Thébaudeau * register bits [0..2] during the software reset. This 65181a0a8bcSBenoît Thébaudeau * will stop those clocks that card detection circuit 65281a0a8bcSBenoît Thébaudeau * relies on. To work around it, we turn the clocks on 65381a0a8bcSBenoît Thébaudeau * back to keep card detection circuit functional. 654913413c3SShawn Guo */ 655913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 65658c8c4fbSShawn Guo /* 65758c8c4fbSShawn Guo * The reset on usdhc fails to clear MIX_CTRL register. 65858c8c4fbSShawn Guo * Do it manually here. 65958c8c4fbSShawn Guo */ 660de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 66181a0a8bcSBenoît Thébaudeau /* 66281a0a8bcSBenoît Thébaudeau * the tuning bits should be kept during reset 66381a0a8bcSBenoît Thébaudeau */ 664d131a71cSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 665d131a71cSDong Aisheng writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 666d131a71cSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 667de5bdbffSDong Aisheng imx_data->is_ddr = 0; 668de5bdbffSDong Aisheng } 66981a0a8bcSBenoît Thébaudeau } else if (val & SDHCI_RESET_DATA) { 67081a0a8bcSBenoît Thébaudeau /* 67181a0a8bcSBenoît Thébaudeau * The eSDHC DAT line software reset clears at least the 67281a0a8bcSBenoît Thébaudeau * data transfer width on i.MX25, so make sure that the 67381a0a8bcSBenoît Thébaudeau * Host Control register is unaffected. 67481a0a8bcSBenoît Thébaudeau */ 67581a0a8bcSBenoît Thébaudeau esdhc_clrset_le(host, 0xff, new_val, 67681a0a8bcSBenoît Thébaudeau SDHCI_HOST_CONTROL); 67781a0a8bcSBenoît Thébaudeau } 67858c8c4fbSShawn Guo } 67995f25efeSWolfram Sang } 68095f25efeSWolfram Sang 6810ddf03c9SLucas Stach static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 6820ddf03c9SLucas Stach { 6830ddf03c9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 6840ddf03c9SLucas Stach 685a974862fSDong Aisheng return pltfm_host->clock; 6860ddf03c9SLucas Stach } 6870ddf03c9SLucas Stach 68895f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 68995f25efeSWolfram Sang { 69095f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 69195f25efeSWolfram Sang 692a974862fSDong Aisheng return pltfm_host->clock / 256 / 16; 69395f25efeSWolfram Sang } 69495f25efeSWolfram Sang 6958ba9580aSLucas Stach static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 6968ba9580aSLucas Stach unsigned int clock) 6978ba9580aSLucas Stach { 6988ba9580aSLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 699070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 700a974862fSDong Aisheng unsigned int host_clock = pltfm_host->clock; 7015143c953SBenoît Thébaudeau int ddr_pre_div = imx_data->is_ddr ? 2 : 1; 7025143c953SBenoît Thébaudeau int pre_div = 1; 703d31fc00aSDong Aisheng int div = 1; 704fed2f6e2SDong Aisheng u32 temp, val; 7058ba9580aSLucas Stach 7069d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 707fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 708fed2f6e2SDong Aisheng writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 709fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 710fed2f6e2SDong Aisheng } 71173e736f8SStefan Agner 71273e736f8SStefan Agner if (clock == 0) { 71373e736f8SStefan Agner host->mmc->actual_clock = 0; 714373073efSRussell King return; 715fed2f6e2SDong Aisheng } 716d31fc00aSDong Aisheng 717499ed50fSBenoît Thébaudeau /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ 718499ed50fSBenoît Thébaudeau if (is_imx53_esdhc(imx_data)) { 719499ed50fSBenoît Thébaudeau /* 720499ed50fSBenoît Thébaudeau * According to the i.MX53 reference manual, if DLLCTRL[10] can 721499ed50fSBenoît Thébaudeau * be set, then the controller is eSDHCv3, else it is eSDHCv2. 722499ed50fSBenoît Thébaudeau */ 723499ed50fSBenoît Thébaudeau val = readl(host->ioaddr + ESDHC_DLL_CTRL); 724499ed50fSBenoît Thébaudeau writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); 725499ed50fSBenoît Thébaudeau temp = readl(host->ioaddr + ESDHC_DLL_CTRL); 726499ed50fSBenoît Thébaudeau writel(val, host->ioaddr + ESDHC_DLL_CTRL); 727499ed50fSBenoît Thébaudeau if (temp & BIT(10)) 728499ed50fSBenoît Thébaudeau pre_div = 2; 729499ed50fSBenoît Thébaudeau } 730499ed50fSBenoît Thébaudeau 731d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 732d31fc00aSDong Aisheng temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 733d31fc00aSDong Aisheng | ESDHC_CLOCK_MASK); 734d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 735d31fc00aSDong Aisheng 7365143c953SBenoît Thébaudeau while (host_clock / (16 * pre_div * ddr_pre_div) > clock && 7375143c953SBenoît Thébaudeau pre_div < 256) 738d31fc00aSDong Aisheng pre_div *= 2; 739d31fc00aSDong Aisheng 7405143c953SBenoît Thébaudeau while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16) 741d31fc00aSDong Aisheng div++; 742d31fc00aSDong Aisheng 7435143c953SBenoît Thébaudeau host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); 744d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 745e76b8559SDong Aisheng clock, host->mmc->actual_clock); 746d31fc00aSDong Aisheng 747d31fc00aSDong Aisheng pre_div >>= 1; 748d31fc00aSDong Aisheng div--; 749d31fc00aSDong Aisheng 750d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 751d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 752d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 753d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 754d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 755fed2f6e2SDong Aisheng 7569d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 757fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 758fed2f6e2SDong Aisheng writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 759fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 760fed2f6e2SDong Aisheng } 761fed2f6e2SDong Aisheng 762d31fc00aSDong Aisheng mdelay(1); 7638ba9580aSLucas Stach } 7648ba9580aSLucas Stach 765913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 766913413c3SShawn Guo { 767842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 768070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 769842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 770913413c3SShawn Guo 771913413c3SShawn Guo switch (boarddata->wp_type) { 772913413c3SShawn Guo case ESDHC_WP_GPIO: 773fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 774913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 775913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 776913413c3SShawn Guo SDHCI_WRITE_PROTECT); 777913413c3SShawn Guo case ESDHC_WP_NONE: 778913413c3SShawn Guo break; 779913413c3SShawn Guo } 780913413c3SShawn Guo 781913413c3SShawn Guo return -ENOSYS; 782913413c3SShawn Guo } 783913413c3SShawn Guo 7842317f56cSRussell King static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 785af51079eSSascha Hauer { 786af51079eSSascha Hauer u32 ctrl; 787af51079eSSascha Hauer 788af51079eSSascha Hauer switch (width) { 789af51079eSSascha Hauer case MMC_BUS_WIDTH_8: 790af51079eSSascha Hauer ctrl = ESDHC_CTRL_8BITBUS; 791af51079eSSascha Hauer break; 792af51079eSSascha Hauer case MMC_BUS_WIDTH_4: 793af51079eSSascha Hauer ctrl = ESDHC_CTRL_4BITBUS; 794af51079eSSascha Hauer break; 795af51079eSSascha Hauer default: 796af51079eSSascha Hauer ctrl = 0; 797af51079eSSascha Hauer break; 798af51079eSSascha Hauer } 799af51079eSSascha Hauer 800af51079eSSascha Hauer esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 801af51079eSSascha Hauer SDHCI_HOST_CONTROL); 802af51079eSSascha Hauer } 803af51079eSSascha Hauer 804de3e1dd0SBOUGH CHEN static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 805de3e1dd0SBOUGH CHEN { 806de3e1dd0SBOUGH CHEN struct sdhci_host *host = mmc_priv(mmc); 807de3e1dd0SBOUGH CHEN 808de3e1dd0SBOUGH CHEN /* 809de3e1dd0SBOUGH CHEN * i.MX uSDHC internally already uses a fixed optimized timing for 810de3e1dd0SBOUGH CHEN * DDR50, normally does not require tuning for DDR50 mode. 811de3e1dd0SBOUGH CHEN */ 812de3e1dd0SBOUGH CHEN if (host->timing == MMC_TIMING_UHS_DDR50) 813de3e1dd0SBOUGH CHEN return 0; 814de3e1dd0SBOUGH CHEN 815de3e1dd0SBOUGH CHEN return sdhci_execute_tuning(mmc, opcode); 816de3e1dd0SBOUGH CHEN } 817de3e1dd0SBOUGH CHEN 8180322191eSDong Aisheng static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 8190322191eSDong Aisheng { 8200322191eSDong Aisheng u32 reg; 8210322191eSDong Aisheng 8220322191eSDong Aisheng /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 8230322191eSDong Aisheng mdelay(1); 8240322191eSDong Aisheng 8250322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 8260322191eSDong Aisheng reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 8270322191eSDong Aisheng ESDHC_MIX_CTRL_FBCLK_SEL; 8280322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 8290322191eSDong Aisheng writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 8300322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), 831d04f8d5bSBenoît Thébaudeau "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 8320322191eSDong Aisheng val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 8330322191eSDong Aisheng } 8340322191eSDong Aisheng 8350322191eSDong Aisheng static void esdhc_post_tuning(struct sdhci_host *host) 8360322191eSDong Aisheng { 8370322191eSDong Aisheng u32 reg; 8380322191eSDong Aisheng 8390322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 8400322191eSDong Aisheng reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 841da0295ffSDong Aisheng reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 8420322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 8430322191eSDong Aisheng } 8440322191eSDong Aisheng 8450322191eSDong Aisheng static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 8460322191eSDong Aisheng { 8470322191eSDong Aisheng int min, max, avg, ret; 8480322191eSDong Aisheng 8490322191eSDong Aisheng /* find the mininum delay first which can pass tuning */ 8500322191eSDong Aisheng min = ESDHC_TUNE_CTRL_MIN; 8510322191eSDong Aisheng while (min < ESDHC_TUNE_CTRL_MAX) { 8520322191eSDong Aisheng esdhc_prepare_tuning(host, min); 8539979dbe5SChaotian Jing if (!mmc_send_tuning(host->mmc, opcode, NULL)) 8540322191eSDong Aisheng break; 8550322191eSDong Aisheng min += ESDHC_TUNE_CTRL_STEP; 8560322191eSDong Aisheng } 8570322191eSDong Aisheng 8580322191eSDong Aisheng /* find the maxinum delay which can not pass tuning */ 8590322191eSDong Aisheng max = min + ESDHC_TUNE_CTRL_STEP; 8600322191eSDong Aisheng while (max < ESDHC_TUNE_CTRL_MAX) { 8610322191eSDong Aisheng esdhc_prepare_tuning(host, max); 8629979dbe5SChaotian Jing if (mmc_send_tuning(host->mmc, opcode, NULL)) { 8630322191eSDong Aisheng max -= ESDHC_TUNE_CTRL_STEP; 8640322191eSDong Aisheng break; 8650322191eSDong Aisheng } 8660322191eSDong Aisheng max += ESDHC_TUNE_CTRL_STEP; 8670322191eSDong Aisheng } 8680322191eSDong Aisheng 8690322191eSDong Aisheng /* use average delay to get the best timing */ 8700322191eSDong Aisheng avg = (min + max) / 2; 8710322191eSDong Aisheng esdhc_prepare_tuning(host, avg); 8729979dbe5SChaotian Jing ret = mmc_send_tuning(host->mmc, opcode, NULL); 8730322191eSDong Aisheng esdhc_post_tuning(host); 8740322191eSDong Aisheng 875d04f8d5bSBenoît Thébaudeau dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 8760322191eSDong Aisheng ret ? "failed" : "passed", avg, ret); 8770322191eSDong Aisheng 8780322191eSDong Aisheng return ret; 8790322191eSDong Aisheng } 8800322191eSDong Aisheng 881ad93220dSDong Aisheng static int esdhc_change_pinstate(struct sdhci_host *host, 882ad93220dSDong Aisheng unsigned int uhs) 883ad93220dSDong Aisheng { 884ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 885070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 886ad93220dSDong Aisheng struct pinctrl_state *pinctrl; 887ad93220dSDong Aisheng 888ad93220dSDong Aisheng dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 889ad93220dSDong Aisheng 890ad93220dSDong Aisheng if (IS_ERR(imx_data->pinctrl) || 891ad93220dSDong Aisheng IS_ERR(imx_data->pins_default) || 892ad93220dSDong Aisheng IS_ERR(imx_data->pins_100mhz) || 893ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) 894ad93220dSDong Aisheng return -EINVAL; 895ad93220dSDong Aisheng 896ad93220dSDong Aisheng switch (uhs) { 897ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 8989f327845SHaibo Chen case MMC_TIMING_UHS_DDR50: 899ad93220dSDong Aisheng pinctrl = imx_data->pins_100mhz; 900ad93220dSDong Aisheng break; 901ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 902429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 90328b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 904ad93220dSDong Aisheng pinctrl = imx_data->pins_200mhz; 905ad93220dSDong Aisheng break; 906ad93220dSDong Aisheng default: 907ad93220dSDong Aisheng /* back to default state for other legacy timing */ 908ad93220dSDong Aisheng pinctrl = imx_data->pins_default; 909ad93220dSDong Aisheng } 910ad93220dSDong Aisheng 911ad93220dSDong Aisheng return pinctrl_select_state(imx_data->pinctrl, pinctrl); 912ad93220dSDong Aisheng } 913ad93220dSDong Aisheng 91428b07674SHaibo Chen /* 915d04f8d5bSBenoît Thébaudeau * For HS400 eMMC, there is a data_strobe line. This signal is generated 91628b07674SHaibo Chen * by the device and used for data output and CRC status response output 91728b07674SHaibo Chen * in HS400 mode. The frequency of this signal follows the frequency of 918d04f8d5bSBenoît Thébaudeau * CLK generated by host. The host receives the data which is aligned to the 91928b07674SHaibo Chen * edge of data_strobe line. Due to the time delay between CLK line and 92028b07674SHaibo Chen * data_strobe line, if the delay time is larger than one clock cycle, 921d04f8d5bSBenoît Thébaudeau * then CLK and data_strobe line will be misaligned, read error shows up. 92228b07674SHaibo Chen * So when the CLK is higher than 100MHz, each clock cycle is short enough, 923d04f8d5bSBenoît Thébaudeau * host should configure the delay target. 92428b07674SHaibo Chen */ 92528b07674SHaibo Chen static void esdhc_set_strobe_dll(struct sdhci_host *host) 92628b07674SHaibo Chen { 92728b07674SHaibo Chen u32 v; 92828b07674SHaibo Chen 92928b07674SHaibo Chen if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) { 9307ac6da26SDong Aisheng /* disable clock before enabling strobe dll */ 9317ac6da26SDong Aisheng writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & 9327ac6da26SDong Aisheng ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 9337ac6da26SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 9347ac6da26SDong Aisheng 93528b07674SHaibo Chen /* force a reset on strobe dll */ 93628b07674SHaibo Chen writel(ESDHC_STROBE_DLL_CTRL_RESET, 93728b07674SHaibo Chen host->ioaddr + ESDHC_STROBE_DLL_CTRL); 93828b07674SHaibo Chen /* 93928b07674SHaibo Chen * enable strobe dll ctrl and adjust the delay target 94028b07674SHaibo Chen * for the uSDHC loopback read clock 94128b07674SHaibo Chen */ 94228b07674SHaibo Chen v = ESDHC_STROBE_DLL_CTRL_ENABLE | 94328b07674SHaibo Chen (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 94428b07674SHaibo Chen writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 94528b07674SHaibo Chen /* wait 1us to make sure strobe dll status register stable */ 94628b07674SHaibo Chen udelay(1); 94728b07674SHaibo Chen v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS); 94828b07674SHaibo Chen if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK)) 94928b07674SHaibo Chen dev_warn(mmc_dev(host->mmc), 95028b07674SHaibo Chen "warning! HS400 strobe DLL status REF not lock!\n"); 95128b07674SHaibo Chen if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK)) 95228b07674SHaibo Chen dev_warn(mmc_dev(host->mmc), 95328b07674SHaibo Chen "warning! HS400 strobe DLL status SLV not lock!\n"); 95428b07674SHaibo Chen } 95528b07674SHaibo Chen } 95628b07674SHaibo Chen 957d9370424SHaibo Chen static void esdhc_reset_tuning(struct sdhci_host *host) 958d9370424SHaibo Chen { 959d9370424SHaibo Chen struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 960d9370424SHaibo Chen struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 961d9370424SHaibo Chen u32 ctrl; 962d9370424SHaibo Chen 963d04f8d5bSBenoît Thébaudeau /* Reset the tuning circuit */ 964d9370424SHaibo Chen if (esdhc_is_usdhc(imx_data)) { 965d9370424SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 966d9370424SHaibo Chen ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); 967d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 968d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 969d9370424SHaibo Chen writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 970d9370424SHaibo Chen writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 971d9370424SHaibo Chen } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 972869f8a69SAdrian Hunter ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 973d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 974869f8a69SAdrian Hunter writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 975d9370424SHaibo Chen } 976d9370424SHaibo Chen } 977d9370424SHaibo Chen } 978d9370424SHaibo Chen 979850a29b8SRussell King static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 980ad93220dSDong Aisheng { 98128b07674SHaibo Chen u32 m; 982ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 983070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 984602519b2SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 985ad93220dSDong Aisheng 98628b07674SHaibo Chen /* disable ddr mode and disable HS400 mode */ 98728b07674SHaibo Chen m = readl(host->ioaddr + ESDHC_MIX_CTRL); 98828b07674SHaibo Chen m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); 98928b07674SHaibo Chen imx_data->is_ddr = 0; 99028b07674SHaibo Chen 991850a29b8SRussell King switch (timing) { 992ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR12: 993ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR25: 994ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 995ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 996de0a0decSBOUGH CHEN case MMC_TIMING_MMC_HS: 997429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 99828b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 999ad93220dSDong Aisheng break; 1000ad93220dSDong Aisheng case MMC_TIMING_UHS_DDR50: 100169f5bf38SAisheng Dong case MMC_TIMING_MMC_DDR52: 100228b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN; 100328b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1004de5bdbffSDong Aisheng imx_data->is_ddr = 1; 1005602519b2SDong Aisheng if (boarddata->delay_line) { 1006602519b2SDong Aisheng u32 v; 1007602519b2SDong Aisheng v = boarddata->delay_line << 1008602519b2SDong Aisheng ESDHC_DLL_OVERRIDE_VAL_SHIFT | 1009602519b2SDong Aisheng (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 1010602519b2SDong Aisheng if (is_imx53_esdhc(imx_data)) 1011602519b2SDong Aisheng v <<= 1; 1012602519b2SDong Aisheng writel(v, host->ioaddr + ESDHC_DLL_CTRL); 1013602519b2SDong Aisheng } 1014ad93220dSDong Aisheng break; 101528b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 101628b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 101728b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 101828b07674SHaibo Chen imx_data->is_ddr = 1; 10197ac6da26SDong Aisheng /* update clock after enable DDR for strobe DLL lock */ 10207ac6da26SDong Aisheng host->ops->set_clock(host, host->clock); 102128b07674SHaibo Chen esdhc_set_strobe_dll(host); 102228b07674SHaibo Chen break; 1023d9370424SHaibo Chen case MMC_TIMING_LEGACY: 1024d9370424SHaibo Chen default: 1025d9370424SHaibo Chen esdhc_reset_tuning(host); 1026d9370424SHaibo Chen break; 1027ad93220dSDong Aisheng } 1028ad93220dSDong Aisheng 1029850a29b8SRussell King esdhc_change_pinstate(host, timing); 1030ad93220dSDong Aisheng } 1031ad93220dSDong Aisheng 10320718e59aSRussell King static void esdhc_reset(struct sdhci_host *host, u8 mask) 10330718e59aSRussell King { 10340718e59aSRussell King sdhci_reset(host, mask); 10350718e59aSRussell King 10360718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 10370718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 10380718e59aSRussell King } 10390718e59aSRussell King 104010fd0ad9SAisheng Dong static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 104110fd0ad9SAisheng Dong { 104210fd0ad9SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1043070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 104410fd0ad9SAisheng Dong 1045d04f8d5bSBenoît Thébaudeau /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */ 10462fb0b02bSHaibo Chen return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27; 104710fd0ad9SAisheng Dong } 104810fd0ad9SAisheng Dong 1049e33eb8e2SAisheng Dong static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 1050e33eb8e2SAisheng Dong { 1051e33eb8e2SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1052070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1053e33eb8e2SAisheng Dong 1054e33eb8e2SAisheng Dong /* use maximum timeout counter */ 1055a215186dSHaibo Chen esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, 1056a215186dSHaibo Chen esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 1057e33eb8e2SAisheng Dong SDHCI_TIMEOUT_CONTROL); 1058e33eb8e2SAisheng Dong } 1059e33eb8e2SAisheng Dong 10606e9fd28eSDong Aisheng static struct sdhci_ops sdhci_esdhc_ops = { 1061e149860dSRichard Zhu .read_l = esdhc_readl_le, 10620c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 106377da3da0SAaron Brice .read_b = esdhc_readb_le, 1064e149860dSRichard Zhu .write_l = esdhc_writel_le, 10650c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 10660c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 10678ba9580aSLucas Stach .set_clock = esdhc_pltfm_set_clock, 10680ddf03c9SLucas Stach .get_max_clock = esdhc_pltfm_get_max_clock, 10690c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 107010fd0ad9SAisheng Dong .get_max_timeout_count = esdhc_get_max_timeout_count, 1071913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 1072e33eb8e2SAisheng Dong .set_timeout = esdhc_set_timeout, 10732317f56cSRussell King .set_bus_width = esdhc_pltfm_set_bus_width, 1074ad93220dSDong Aisheng .set_uhs_signaling = esdhc_set_uhs_signaling, 10750718e59aSRussell King .reset = esdhc_reset, 10760c6d49ceSWolfram Sang }; 10770c6d49ceSWolfram Sang 10781db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 107997e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 108097e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 108197e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 108285d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 108385d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 108485d6509dSShawn Guo }; 108585d6509dSShawn Guo 1086f3f5cf3dSDong Aisheng static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) 1087f3f5cf3dSDong Aisheng { 1088f3f5cf3dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1089f3f5cf3dSDong Aisheng struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 10902b16cf32SDong Aisheng int tmp; 1091f3f5cf3dSDong Aisheng 1092f3f5cf3dSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 1093f3f5cf3dSDong Aisheng /* 1094f3f5cf3dSDong Aisheng * The imx6q ROM code will change the default watermark 1095f3f5cf3dSDong Aisheng * level setting to something insane. Change it back here. 1096f3f5cf3dSDong Aisheng */ 1097f3f5cf3dSDong Aisheng writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); 1098f3f5cf3dSDong Aisheng 1099f3f5cf3dSDong Aisheng /* 1100f3f5cf3dSDong Aisheng * ROM code will change the bit burst_length_enable setting 1101d04f8d5bSBenoît Thébaudeau * to zero if this usdhc is chosen to boot system. Change 1102f3f5cf3dSDong Aisheng * it back here, otherwise it will impact the performance a 1103f3f5cf3dSDong Aisheng * lot. This bit is used to enable/disable the burst length 1104d04f8d5bSBenoît Thébaudeau * for the external AHB2AXI bridge. It's useful especially 1105f3f5cf3dSDong Aisheng * for INCR transfer because without burst length indicator, 1106f3f5cf3dSDong Aisheng * the AHB2AXI bridge does not know the burst length in 1107f3f5cf3dSDong Aisheng * advance. And without burst length indicator, AHB INCR 1108f3f5cf3dSDong Aisheng * transfer can only be converted to singles on the AXI side. 1109f3f5cf3dSDong Aisheng */ 1110f3f5cf3dSDong Aisheng writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) 1111f3f5cf3dSDong Aisheng | ESDHC_BURST_LEN_EN_INCR, 1112f3f5cf3dSDong Aisheng host->ioaddr + SDHCI_HOST_CONTROL); 1113f3f5cf3dSDong Aisheng /* 1114d04f8d5bSBenoît Thébaudeau * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 1115f3f5cf3dSDong Aisheng * TO1.1, it's harmless for MX6SL 1116f3f5cf3dSDong Aisheng */ 1117f3f5cf3dSDong Aisheng writel(readl(host->ioaddr + 0x6c) | BIT(7), 1118f3f5cf3dSDong Aisheng host->ioaddr + 0x6c); 1119f3f5cf3dSDong Aisheng 1120f3f5cf3dSDong Aisheng /* disable DLL_CTRL delay line settings */ 1121f3f5cf3dSDong Aisheng writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); 11222b16cf32SDong Aisheng 11232b16cf32SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 11242b16cf32SDong Aisheng tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 11252b16cf32SDong Aisheng tmp |= ESDHC_STD_TUNING_EN | 11262b16cf32SDong Aisheng ESDHC_TUNING_START_TAP_DEFAULT; 11272b16cf32SDong Aisheng if (imx_data->boarddata.tuning_start_tap) { 11282b16cf32SDong Aisheng tmp &= ~ESDHC_TUNING_START_TAP_MASK; 11292b16cf32SDong Aisheng tmp |= imx_data->boarddata.tuning_start_tap; 11302b16cf32SDong Aisheng } 11312b16cf32SDong Aisheng 11322b16cf32SDong Aisheng if (imx_data->boarddata.tuning_step) { 11332b16cf32SDong Aisheng tmp &= ~ESDHC_TUNING_STEP_MASK; 11342b16cf32SDong Aisheng tmp |= imx_data->boarddata.tuning_step 11352b16cf32SDong Aisheng << ESDHC_TUNING_STEP_SHIFT; 11362b16cf32SDong Aisheng } 11372b16cf32SDong Aisheng writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1138a98c557eSBOUGH CHEN } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1139a98c557eSBOUGH CHEN /* 1140a98c557eSBOUGH CHEN * ESDHC_STD_TUNING_EN may be configed in bootloader 1141a98c557eSBOUGH CHEN * or ROM code, so clear this bit here to make sure 1142a98c557eSBOUGH CHEN * the manual tuning can work. 1143a98c557eSBOUGH CHEN */ 1144a98c557eSBOUGH CHEN tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1145a98c557eSBOUGH CHEN tmp &= ~ESDHC_STD_TUNING_EN; 1146a98c557eSBOUGH CHEN writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 11472b16cf32SDong Aisheng } 1148f3f5cf3dSDong Aisheng } 1149f3f5cf3dSDong Aisheng } 1150f3f5cf3dSDong Aisheng 1151abfafc2dSShawn Guo #ifdef CONFIG_OF 1152c3be1efdSBill Pemberton static int 1153abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 115407bf2b54SSascha Hauer struct sdhci_host *host, 115591fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1156abfafc2dSShawn Guo { 1157abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 115891fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 11594800e87aSDong Aisheng int ret; 1160abfafc2dSShawn Guo 1161abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 1162abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 1163abfafc2dSShawn Guo 116474ff81e1SLinus Walleij /* 116574ff81e1SLinus Walleij * If we have this property, then activate WP check. 116674ff81e1SLinus Walleij * Retrieveing and requesting the actual WP GPIO will happen 116774ff81e1SLinus Walleij * in the call to mmc_of_parse(). 116874ff81e1SLinus Walleij */ 116974ff81e1SLinus Walleij if (of_property_read_bool(np, "wp-gpios")) 1170abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 1171abfafc2dSShawn Guo 1172d407e30bSHaibo Chen of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 1173d87fc966SDong Aisheng of_property_read_u32(np, "fsl,tuning-start-tap", 1174d87fc966SDong Aisheng &boarddata->tuning_start_tap); 1175d407e30bSHaibo Chen 1176ad93220dSDong Aisheng if (of_find_property(np, "no-1-8-v", NULL)) 117786f495c5SStefan Agner host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1178ad93220dSDong Aisheng 1179602519b2SDong Aisheng if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 1180602519b2SDong Aisheng boarddata->delay_line = 0; 1181602519b2SDong Aisheng 118207bf2b54SSascha Hauer mmc_of_parse_voltage(np, &host->ocr_mask); 118307bf2b54SSascha Hauer 118486f495c5SStefan Agner if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pins_default)) { 118591fa4252SDong Aisheng imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 118691fa4252SDong Aisheng ESDHC_PINCTRL_STATE_100MHZ); 118791fa4252SDong Aisheng imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 118891fa4252SDong Aisheng ESDHC_PINCTRL_STATE_200MHZ); 118991fa4252SDong Aisheng } 119091fa4252SDong Aisheng 119115064119SFabio Estevam /* call to generic mmc_of_parse to support additional capabilities */ 11924800e87aSDong Aisheng ret = mmc_of_parse(host->mmc); 11934800e87aSDong Aisheng if (ret) 11944800e87aSDong Aisheng return ret; 11954800e87aSDong Aisheng 1196287980e4SArnd Bergmann if (mmc_gpio_get_cd(host->mmc) >= 0) 11974800e87aSDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 11984800e87aSDong Aisheng 11994800e87aSDong Aisheng return 0; 1200abfafc2dSShawn Guo } 1201abfafc2dSShawn Guo #else 1202abfafc2dSShawn Guo static inline int 1203abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 120407bf2b54SSascha Hauer struct sdhci_host *host, 120591fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1206abfafc2dSShawn Guo { 1207abfafc2dSShawn Guo return -ENODEV; 1208abfafc2dSShawn Guo } 1209abfafc2dSShawn Guo #endif 1210abfafc2dSShawn Guo 121191fa4252SDong Aisheng static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev, 121291fa4252SDong Aisheng struct sdhci_host *host, 121391fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 121491fa4252SDong Aisheng { 121591fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 121691fa4252SDong Aisheng int err; 121791fa4252SDong Aisheng 121891fa4252SDong Aisheng if (!host->mmc->parent->platform_data) { 121991fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), "no board data!\n"); 122091fa4252SDong Aisheng return -EINVAL; 122191fa4252SDong Aisheng } 122291fa4252SDong Aisheng 122391fa4252SDong Aisheng imx_data->boarddata = *((struct esdhc_platform_data *) 122491fa4252SDong Aisheng host->mmc->parent->platform_data); 122591fa4252SDong Aisheng /* write_protect */ 122691fa4252SDong Aisheng if (boarddata->wp_type == ESDHC_WP_GPIO) { 122774ff81e1SLinus Walleij err = mmc_gpiod_request_ro(host->mmc, "wp", 0, false, 0, NULL); 122891fa4252SDong Aisheng if (err) { 122991fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 123091fa4252SDong Aisheng "failed to request write-protect gpio!\n"); 123191fa4252SDong Aisheng return err; 123291fa4252SDong Aisheng } 123391fa4252SDong Aisheng host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 123491fa4252SDong Aisheng } 123591fa4252SDong Aisheng 123691fa4252SDong Aisheng /* card_detect */ 123791fa4252SDong Aisheng switch (boarddata->cd_type) { 123891fa4252SDong Aisheng case ESDHC_CD_GPIO: 123974ff81e1SLinus Walleij err = mmc_gpiod_request_cd(host->mmc, "cd", 0, false, 0, NULL); 124091fa4252SDong Aisheng if (err) { 124191fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 124291fa4252SDong Aisheng "failed to request card-detect gpio!\n"); 124391fa4252SDong Aisheng return err; 124491fa4252SDong Aisheng } 124591fa4252SDong Aisheng /* fall through */ 124691fa4252SDong Aisheng 124791fa4252SDong Aisheng case ESDHC_CD_CONTROLLER: 124891fa4252SDong Aisheng /* we have a working card_detect back */ 124991fa4252SDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 125091fa4252SDong Aisheng break; 125191fa4252SDong Aisheng 125291fa4252SDong Aisheng case ESDHC_CD_PERMANENT: 125391fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_NONREMOVABLE; 125491fa4252SDong Aisheng break; 125591fa4252SDong Aisheng 125691fa4252SDong Aisheng case ESDHC_CD_NONE: 125791fa4252SDong Aisheng break; 125891fa4252SDong Aisheng } 125991fa4252SDong Aisheng 126091fa4252SDong Aisheng switch (boarddata->max_bus_width) { 126191fa4252SDong Aisheng case 8: 126291fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 126391fa4252SDong Aisheng break; 126491fa4252SDong Aisheng case 4: 126591fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_4_BIT_DATA; 126691fa4252SDong Aisheng break; 126791fa4252SDong Aisheng case 1: 126891fa4252SDong Aisheng default: 126991fa4252SDong Aisheng host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 127091fa4252SDong Aisheng break; 127191fa4252SDong Aisheng } 127291fa4252SDong Aisheng 127391fa4252SDong Aisheng return 0; 127491fa4252SDong Aisheng } 127591fa4252SDong Aisheng 1276c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 127795f25efeSWolfram Sang { 1278abfafc2dSShawn Guo const struct of_device_id *of_id = 1279abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 128085d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 128185d6509dSShawn Guo struct sdhci_host *host; 12820c6d49ceSWolfram Sang int err; 1283e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 128495f25efeSWolfram Sang 1285070e6d3fSJisheng Zhang host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 1286070e6d3fSJisheng Zhang sizeof(*imx_data)); 128785d6509dSShawn Guo if (IS_ERR(host)) 128885d6509dSShawn Guo return PTR_ERR(host); 128985d6509dSShawn Guo 129085d6509dSShawn Guo pltfm_host = sdhci_priv(host); 129185d6509dSShawn Guo 1292070e6d3fSJisheng Zhang imx_data = sdhci_pltfm_priv(pltfm_host); 129357ed3314SShawn Guo 1294f47c4bbfSShawn Guo imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 12953770ee8fSShawn Guo pdev->id_entry->driver_data; 129685d6509dSShawn Guo 129752dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 129852dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 129952dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 1300e3af31c6SShawn Guo goto free_sdhci; 130195f25efeSWolfram Sang } 130252dac615SSascha Hauer 130352dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 130452dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 130552dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 1306e3af31c6SShawn Guo goto free_sdhci; 130752dac615SSascha Hauer } 130852dac615SSascha Hauer 130952dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 131052dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 131152dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 1312e3af31c6SShawn Guo goto free_sdhci; 131352dac615SSascha Hauer } 131452dac615SSascha Hauer 131552dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 1316a974862fSDong Aisheng pltfm_host->clock = clk_get_rate(pltfm_host->clk); 131717b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_per); 131817b1eb7fSFabio Estevam if (err) 131917b1eb7fSFabio Estevam goto free_sdhci; 132017b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ipg); 132117b1eb7fSFabio Estevam if (err) 132217b1eb7fSFabio Estevam goto disable_per_clk; 132317b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ahb); 132417b1eb7fSFabio Estevam if (err) 132517b1eb7fSFabio Estevam goto disable_ipg_clk; 132695f25efeSWolfram Sang 1327ad93220dSDong Aisheng imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1328e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 1329e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 133017b1eb7fSFabio Estevam goto disable_ahb_clk; 1331e62d8b8fSDong Aisheng } 1332e62d8b8fSDong Aisheng 1333ad93220dSDong Aisheng imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, 1334ad93220dSDong Aisheng PINCTRL_STATE_DEFAULT); 1335cd529af7SDirk Behme if (IS_ERR(imx_data->pins_default)) 1336cd529af7SDirk Behme dev_warn(mmc_dev(host->mmc), "could not get default state\n"); 1337ad93220dSDong Aisheng 133869ed60e0SDong Aisheng if (esdhc_is_usdhc(imx_data)) { 133969ed60e0SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 134009c8192bSStefan Agner host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; 13414245afffSDong Aisheng if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 13424245afffSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 1343a75dcbf4SDong Aisheng 1344a75dcbf4SDong Aisheng /* clear tuning bits in case ROM has set it already */ 1345a75dcbf4SDong Aisheng writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); 1346869f8a69SAdrian Hunter writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1347a75dcbf4SDong Aisheng writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1348de3e1dd0SBOUGH CHEN 1349de3e1dd0SBOUGH CHEN /* 1350de3e1dd0SBOUGH CHEN * Link usdhc specific mmc_host_ops execute_tuning function, 1351de3e1dd0SBOUGH CHEN * to replace the standard one in sdhci_ops. 1352de3e1dd0SBOUGH CHEN */ 1353de3e1dd0SBOUGH CHEN host->mmc_host_ops.execute_tuning = usdhc_execute_tuning; 135469ed60e0SDong Aisheng } 1355f750ba9bSShawn Guo 13566e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 13576e9fd28eSDong Aisheng sdhci_esdhc_ops.platform_execute_tuning = 13586e9fd28eSDong Aisheng esdhc_executing_tuning; 13598b2bb0adSDong Aisheng 136018094430SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 136118094430SDong Aisheng host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 136218094430SDong Aisheng 136328b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 136428b07674SHaibo Chen host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; 136528b07674SHaibo Chen 136691fa4252SDong Aisheng if (of_id) 136791fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 136891fa4252SDong Aisheng else 136991fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data); 137091fa4252SDong Aisheng if (err) 137117b1eb7fSFabio Estevam goto disable_ahb_clk; 1372ad93220dSDong Aisheng 1373f3f5cf3dSDong Aisheng sdhci_esdhc_imx_hwinit(host); 1374f3f5cf3dSDong Aisheng 137585d6509dSShawn Guo err = sdhci_add_host(host); 137685d6509dSShawn Guo if (err) 137717b1eb7fSFabio Estevam goto disable_ahb_clk; 137885d6509dSShawn Guo 137989d7e5c1SDong Aisheng pm_runtime_set_active(&pdev->dev); 138089d7e5c1SDong Aisheng pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 138189d7e5c1SDong Aisheng pm_runtime_use_autosuspend(&pdev->dev); 138289d7e5c1SDong Aisheng pm_suspend_ignore_children(&pdev->dev, 1); 138377903c01SUlf Hansson pm_runtime_enable(&pdev->dev); 138489d7e5c1SDong Aisheng 13857e29c306SWolfram Sang return 0; 13867e29c306SWolfram Sang 138717b1eb7fSFabio Estevam disable_ahb_clk: 138852dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 138917b1eb7fSFabio Estevam disable_ipg_clk: 139017b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_ipg); 139117b1eb7fSFabio Estevam disable_per_clk: 139217b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_per); 1393e3af31c6SShawn Guo free_sdhci: 139485d6509dSShawn Guo sdhci_pltfm_free(pdev); 139585d6509dSShawn Guo return err; 139695f25efeSWolfram Sang } 139795f25efeSWolfram Sang 13986e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 139995f25efeSWolfram Sang { 140085d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 140195f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1402070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 140385d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 140485d6509dSShawn Guo 14050b414368SUlf Hansson pm_runtime_get_sync(&pdev->dev); 14060b414368SUlf Hansson pm_runtime_disable(&pdev->dev); 14070b414368SUlf Hansson pm_runtime_put_noidle(&pdev->dev); 14080b414368SUlf Hansson 140985d6509dSShawn Guo sdhci_remove_host(host, dead); 14100c6d49ceSWolfram Sang 141152dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 141252dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 141352dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 141452dac615SSascha Hauer 141585d6509dSShawn Guo sdhci_pltfm_free(pdev); 141685d6509dSShawn Guo 141785d6509dSShawn Guo return 0; 141895f25efeSWolfram Sang } 141995f25efeSWolfram Sang 14202788ed42SUlf Hansson #ifdef CONFIG_PM_SLEEP 142104143fbaSDong Aisheng static int sdhci_esdhc_suspend(struct device *dev) 142204143fbaSDong Aisheng { 14233e3274abSUlf Hansson struct sdhci_host *host = dev_get_drvdata(dev); 14243e3274abSUlf Hansson 1425d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1426d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 1427d38dcad4SAdrian Hunter 14283e3274abSUlf Hansson return sdhci_suspend_host(host); 142904143fbaSDong Aisheng } 143004143fbaSDong Aisheng 143104143fbaSDong Aisheng static int sdhci_esdhc_resume(struct device *dev) 143204143fbaSDong Aisheng { 1433cc17e129SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 1434cc17e129SDong Aisheng 143519dbfdd3SDong Aisheng /* re-initialize hw state in case it's lost in low power mode */ 143619dbfdd3SDong Aisheng sdhci_esdhc_imx_hwinit(host); 1437cc17e129SDong Aisheng 14383e3274abSUlf Hansson return sdhci_resume_host(host); 143904143fbaSDong Aisheng } 14402788ed42SUlf Hansson #endif 144104143fbaSDong Aisheng 14422788ed42SUlf Hansson #ifdef CONFIG_PM 144389d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_suspend(struct device *dev) 144489d7e5c1SDong Aisheng { 144589d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 144689d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1447070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 144889d7e5c1SDong Aisheng int ret; 144989d7e5c1SDong Aisheng 145089d7e5c1SDong Aisheng ret = sdhci_runtime_suspend_host(host); 1451371d39faSMichael Trimarchi if (ret) 1452371d39faSMichael Trimarchi return ret; 145389d7e5c1SDong Aisheng 1454d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1455d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 1456d38dcad4SAdrian Hunter 1457be138554SRussell King if (!sdhci_sdio_irq_enabled(host)) { 14583602785bSMichael Trimarchi imx_data->actual_clock = host->mmc->actual_clock; 14593602785bSMichael Trimarchi esdhc_pltfm_set_clock(host, 0); 146089d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_per); 146189d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ipg); 1462be138554SRussell King } 146389d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ahb); 146489d7e5c1SDong Aisheng 146589d7e5c1SDong Aisheng return ret; 146689d7e5c1SDong Aisheng } 146789d7e5c1SDong Aisheng 146889d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_resume(struct device *dev) 146989d7e5c1SDong Aisheng { 147089d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 147189d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1472070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 147317b1eb7fSFabio Estevam int err; 147489d7e5c1SDong Aisheng 1475a0ad3087SMichael Trimarchi err = clk_prepare_enable(imx_data->clk_ahb); 1476a0ad3087SMichael Trimarchi if (err) 1477a0ad3087SMichael Trimarchi return err; 1478a0ad3087SMichael Trimarchi 1479be138554SRussell King if (!sdhci_sdio_irq_enabled(host)) { 148017b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_per); 148117b1eb7fSFabio Estevam if (err) 1482a0ad3087SMichael Trimarchi goto disable_ahb_clk; 148317b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ipg); 148417b1eb7fSFabio Estevam if (err) 148517b1eb7fSFabio Estevam goto disable_per_clk; 14863602785bSMichael Trimarchi esdhc_pltfm_set_clock(host, imx_data->actual_clock); 1487be138554SRussell King } 1488a0ad3087SMichael Trimarchi 148917b1eb7fSFabio Estevam err = sdhci_runtime_resume_host(host); 149017b1eb7fSFabio Estevam if (err) 1491a0ad3087SMichael Trimarchi goto disable_ipg_clk; 149289d7e5c1SDong Aisheng 149317b1eb7fSFabio Estevam return 0; 149417b1eb7fSFabio Estevam 149517b1eb7fSFabio Estevam disable_ipg_clk: 149617b1eb7fSFabio Estevam if (!sdhci_sdio_irq_enabled(host)) 149717b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_ipg); 149817b1eb7fSFabio Estevam disable_per_clk: 149917b1eb7fSFabio Estevam if (!sdhci_sdio_irq_enabled(host)) 150017b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_per); 1501a0ad3087SMichael Trimarchi disable_ahb_clk: 1502a0ad3087SMichael Trimarchi clk_disable_unprepare(imx_data->clk_ahb); 150317b1eb7fSFabio Estevam return err; 150489d7e5c1SDong Aisheng } 150589d7e5c1SDong Aisheng #endif 150689d7e5c1SDong Aisheng 150789d7e5c1SDong Aisheng static const struct dev_pm_ops sdhci_esdhc_pmops = { 150804143fbaSDong Aisheng SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) 150989d7e5c1SDong Aisheng SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 151089d7e5c1SDong Aisheng sdhci_esdhc_runtime_resume, NULL) 151189d7e5c1SDong Aisheng }; 151289d7e5c1SDong Aisheng 151385d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 151485d6509dSShawn Guo .driver = { 151585d6509dSShawn Guo .name = "sdhci-esdhc-imx", 1516abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 151789d7e5c1SDong Aisheng .pm = &sdhci_esdhc_pmops, 151885d6509dSShawn Guo }, 151957ed3314SShawn Guo .id_table = imx_esdhc_devtype, 152085d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 15210433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 152295f25efeSWolfram Sang }; 152385d6509dSShawn Guo 1524d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 152585d6509dSShawn Guo 152685d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1527035ff831SWolfram Sang MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 152885d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1529